June 2012 - U-Boot

[U-Boot] [PATCH - resend due to bounce] libfdt: Add fdt functionality for more intuitive
by Peter Feuerer 16 Oct '12

16 Oct '12

libfdt: Add fdt functionality for more intuitive fdt handling New functions: fdt_read - retrieve the value of a property by full path fdt_write - create or change a property with full path and create subnodes if needed fdt_create_path - create subnode path with parents Signed-off-by: Peter Feuerer <peter.feuerer(a)sysgo.com> CC: David Gibson <david(a)gibson.dropbear.id.au> CC: Gerald Van Baren <gvb(a)unssw.com> --- include/libfdt.h | 93 ++++++++++++++++++++++++++++++++++++++++ lib/libfdt/fdt_ro.c | 30 +++++++++++++ lib/libfdt/fdt_rw.c | 97 ++++++++++++++++++++++++++++++++++++++++++ lib/libfdt/libfdt_internal.h | 4 ++ 4 files changed, 224 insertions(+), 0 deletions(-) diff --git a/include/libfdt.h b/include/libfdt.h index de82ed5..822ab18 100644 --- a/include/libfdt.h +++ b/include/libfdt.h @@ -548,6 +548,37 @@ static inline void *fdt_getprop_w(void *fdt, int nodeoffset, } /** + * fdt_read - retrieve the value of a property by full path + * @fdt: pointer to the device tree blob + * @path: string containing the absolute path of the property + * @name: name of the property + * @lenp: pointer to an integer variable (will be overwritten) or NULL + * + * fdt_getprop() retrieves a pointer to the value of the property + * named 'name' of the node at offset nodeoffset (this will be a + * pointer to within the device blob itself, not a copy of the value). + * If lenp is non-NULL, the length of the property value is also + * returned, in the integer pointed to by lenp. + * + * returns: + * pointer to the property's value + * if lenp is non-NULL, *lenp contains the length of the property + * value (>=0) + * NULL, on error + * if lenp is non-NULL, *lenp contains an error code (<0): + * -FDT_ERR_NOTFOUND, node does not have named property + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings + */ +const void *fdt_read(const void *fdt, const char *path, + const char *name, int *lenp); + +/** * fdt_get_phandle - retrieve the phandle of a given node * @fdt: pointer to the device tree blob * @nodeoffset: structure block offset of the node @@ -1066,6 +1097,38 @@ int fdt_set_name(void *fdt, int nodeoffset, const char *name); */ int fdt_setprop(void *fdt, int nodeoffset, const char *name, const void *val, int len); +/** + * fdt_write - create or change a property with full path and create + * all subnodes to the property if needed + * @fdt: pointer to the device tree blob + * @path: string containing the absolute path of the property + * @name: name of the property to change + * @val: pointer to data to set the property value to + * @len: length of the property value + * + * fdt_write() sets the value of the named property in the given + * node to the given value and length, creating the property if it + * does not already exist. Additionally it creates all parent nodes if + * not yet existing. + * + * This function may insert or delete data from the blob, and will + * therefore change the offsets of some existing nodes. + * + * returns: + * 0, on success + * -FDT_ERR_NOSPACE, there is insufficient free space in the blob to + * contain the new property value + * -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_TRUNCATED, standard meanings + */ +int fdt_write(void *fdt, const char *path, const char *name, + const void *val, int len); /** * fdt_setprop_cell - set a property to a single cell value @@ -1204,6 +1267,36 @@ int fdt_add_subnode_namelen(void *fdt, int parentoffset, int fdt_add_subnode(void *fdt, int parentoffset, const char *name); /** + * fdt_create_path - create subnode path with parents + * @fdt: pointer to the device tree blob + * @path: absolute path of subnodes to create + * + * fdt_create_path() creates absolute subnode path with all needed + * parents, if they don't exist. + * + * This function will insert data into the blob, and will therefore + * change the offsets of some existing nodes. + * + * returns: + * structure block offset of the created nodeequested subnode (>=0), on success + * -FDT_ERR_NOTFOUND, if the requested subnode does not exist + * -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag + * -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of + * the given name + * -FDT_ERR_NOSPACE, if there is insufficient free space in the + * blob to contain the new node + * -FDT_ERR_NOSPACE, + * -FDT_ERR_BADPATH, + * -FDT_ERR_BADLAYOUT, + * -FDT_ERR_BADMAGIC, + * -FDT_ERR_BADVERSION, + * -FDT_ERR_BADSTATE, + * -FDT_ERR_BADSTRUCTURE, + * -FDT_ERR_TRUNCATED, standard meanings. + */ +int fdt_create_path(struct fdt_header *fdt, const char *path); + +/** * fdt_del_node - delete a node (subtree) * @fdt: pointer to the device tree blob * @nodeoffset: offset of the node to nop diff --git a/lib/libfdt/fdt_ro.c b/lib/libfdt/fdt_ro.c index 1933010..9a08200 100644 --- a/lib/libfdt/fdt_ro.c +++ b/lib/libfdt/fdt_ro.c @@ -324,6 +324,36 @@ const void *fdt_getprop(const void *fdt, int nodeoffset, return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp); } +const void *fdt_read(const void *fdt, const char *path, + const char *name, int *lenp) +{ + int nodeoffset; + int len; + const void *nodep ; + + if (fdt_check_header(fdt) != 0) { + if (lenp) + *lenp = -FDT_ERR_BADSTRUCTURE; + return NULL; + } + + nodeoffset = fdt_path_offset(fdt, path); + + if (nodeoffset < 0) { + if (lenp) + *lenp = -FDT_ERR_BADPATH; + return NULL; + } else { + nodep = fdt_getprop(fdt, nodeoffset, name, &len); + if (len <= 0) + return NULL; + if (lenp) + *lenp = len; + } + return nodep; +} + + uint32_t fdt_get_phandle(const void *fdt, int nodeoffset) { const uint32_t *php; diff --git a/lib/libfdt/fdt_rw.c b/lib/libfdt/fdt_rw.c index 5c27a67..ccebafb 100644 --- a/lib/libfdt/fdt_rw.c +++ b/lib/libfdt/fdt_rw.c @@ -293,6 +293,21 @@ int fdt_setprop(void *fdt, int nodeoffset, const char *name, return 0; } +int fdt_write(void *fdt, const char *path, const char *name, + const void *val, int len) +{ + int nodeoffset; + + FDT_CHECK_HEADER(fdt); + + nodeoffset = fdt_create_path(fdt, path); + + if (nodeoffset < 0) + return nodeoffset; + + return fdt_setprop(fdt, nodeoffset, name, val, len); +} + int fdt_delprop(void *fdt, int nodeoffset, const char *name) { struct fdt_property *prop; @@ -354,6 +369,88 @@ int fdt_add_subnode(void *fdt, int parentoffset, const char *name) return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name)); } +int fdt_create_path_internal(struct fdt_header *fdt, char *path) +{ + int offset = 0; + char *p = NULL; + char *last_slash = NULL; + char *path2 = path; + int ret = 0; + + /* search for last slash */ + for (p = path; *p != 0; ++p) + if (*p == '/') + last_slash = p; + + /* if path ends with "/" then, error */ + if (*(last_slash + 1) == 0) + return -FDT_ERR_BADPATH; + + /* + * if last_slash is root, use "/" instead of string + * otherwise terminate string at slash + */ + if (last_slash == path) + path2 = "/"; + else + *last_slash = 0; + + /* + * test if the parent path is valid, if not valid, + * recursively add paths + */ + offset = fdt_path_offset(fdt, path2); + if (offset == -FDT_ERR_NOTFOUND) + offset = fdt_create_path_internal(fdt, path2); + + if (offset < 0) + return offset; + + /* path valid, create subnode */ + ret = fdt_add_subnode(fdt, offset, last_slash + 1); + + /* undo termination */ + if (last_slash && last_slash != path) + *last_slash = '/'; + + return ret; +} + +int fdt_create_path(struct fdt_header *fdt, const char *path) +{ + int offset = 0; + int ret = 0; + int size = 0; +#ifndef FDT_USE_MALLOC + char path_mem[FDT_MAX_PATHLEN] = {0}; + size = FDT_MAX_PATHLEN; +#else + char *path_mem; + size = strlen(path); + path_mem = calloc(size, 1); + if (!path_mem) + return -FDT_ERR_NOSPACE; +#endif + + /* if full path already exists, return the offset */ + offset = fdt_path_offset(fdt, path); + if (offset >= 0) { + ret = offset; + goto end; + } + + /* copy path to local path variable, so that we can modify it */ + strncpy(path_mem, path, size - 1); + + ret = fdt_create_path_internal(fdt, path_mem); +end: +#ifdef FDT_USE_MALLOC + free(path_mem); +#endif + return ret; + +} + int fdt_del_node(void *fdt, int nodeoffset) { int endoffset; diff --git a/lib/libfdt/libfdt_internal.h b/lib/libfdt/libfdt_internal.h index 381133b..786a052 100644 --- a/lib/libfdt/libfdt_internal.h +++ b/lib/libfdt/libfdt_internal.h @@ -55,6 +55,10 @@ #define FDT_ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) #define FDT_TAGALIGN(x) (FDT_ALIGN((x), FDT_TAGSIZE)) +#ifndef FDT_USE_MALLOC +#define FDT_MAX_PATHLEN 2048 +#endif + #define FDT_CHECK_HEADER(fdt) \ { \ int err; \ -- 1.7.3

2 1

[U-Boot] [PATCH v2] Add support for MMC to fw_printenv/setenv
by Christian Daudt 16 Oct '12

16 Oct '12

Changes from previous: - Changed // to /* */ - Ran through checkpatch.pl, cleaned up a number of line-too-big and extra space in the code that was shifted due to being in the new 'if'. Thanks, csd Subject: [PATCH] Add support for MMC to fw_printenv/setenv This patch checks if the fd is MTD and if not (using an MTD-specific IOCTL) and skips the flash unlock/erase/lock sequence if it is not MTD. - fd_is_mtd function added to determine MTD/MMC - flash_write_block made to not try MTD operations if mtd_type == MTD_ABSENT - flash_read works with MMC devices now. Signed-off-by: Christian Daudt <csd(a)broadcom.com> --- tools/env/fw_env.c | 103 ++++++++++++++++++++++++++++++++++++---------------- 1 files changed, 71 insertions(+), 32 deletions(-) diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c index 996682e..c760429 100644 --- a/tools/env/fw_env.c +++ b/tools/env/fw_env.c @@ -211,6 +211,27 @@ static int flash_io (int mode); static char *envmatch (char * s1, char * s2); static int parse_config (void); + +/* + * Returns 1 if it is MTD and 0 if it is not MTD + */ +static int fd_is_mtd(int fd) +{ + struct mtd_info_user mtdinfo; + int rc; + + rc = ioctl(fd, MEMGETINFO, &mtdinfo); + if (rc < 0) { + /* Failed MEMGETINFO, not MTD */ + return 0; + } else { + /* Succeeded, MTD */ + return 1; + } +} + + + #if defined(CONFIG_FILE) static int get_config (char *); #endif @@ -836,31 +857,35 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, /* This only runs once on NOR flash and SPI-dataflash */ while (processed < write_total) { - rc = flash_bad_block (fd, mtd_type, &blockstart); - if (rc < 0) /* block test failed */ - return rc; + if (mtd_type != MTD_ABSENT) { + rc = flash_bad_block(fd, mtd_type, &blockstart); + if (rc < 0) /* block test failed */ + return rc; - if (blockstart + erasesize > top_of_range) { - fprintf (stderr, "End of range reached, aborting\n"); - return -1; - } + if (blockstart + erasesize > top_of_range) { + fprintf(stderr, + "End of range reached, aborting\n"); + return -1; + } - if (rc) { /* block is bad */ - blockstart += blocklen; - continue; - } + if (rc) { /* block is bad */ + blockstart += blocklen; + continue; + } - erase.start = blockstart; - ioctl (fd, MEMUNLOCK, &erase); + erase.start = blockstart; + ioctl(fd, MEMUNLOCK, &erase); - /* Dataflash does not need an explicit erase cycle */ - if (mtd_type != MTD_DATAFLASH) - if (ioctl (fd, MEMERASE, &erase) != 0) { - fprintf (stderr, "MTD erase error on %s: %s\n", - DEVNAME (dev), - strerror (errno)); - return -1; - } + /* Dataflash does not need an explicit erase cycle */ + if (mtd_type != MTD_DATAFLASH) + if (ioctl(fd, MEMERASE, &erase) != 0) { + fprintf(stderr, + "MTD erase error on %s: %s\n", + DEVNAME(dev), + strerror(errno)); + return -1; + } + } if (lseek (fd, blockstart, SEEK_SET) == -1) { fprintf (stderr, @@ -878,7 +903,8 @@ static int flash_write_buf (int dev, int fd, void *buf, size_t count, return -1; } - ioctl (fd, MEMLOCK, &erase); + if (mtd_type != MTD_ABSENT) + ioctl(fd, MEMLOCK, &erase); processed += blocklen; block_seek = 0; @@ -964,18 +990,31 @@ static int flash_read (int fd) { struct mtd_info_user mtdinfo; int rc; + int is_mtd; - rc = ioctl (fd, MEMGETINFO, &mtdinfo); - if (rc < 0) { - perror ("Cannot get MTD information"); - return -1; - } + is_mtd = fd_is_mtd(fd); - if (mtdinfo.type != MTD_NORFLASH && - mtdinfo.type != MTD_NANDFLASH && - mtdinfo.type != MTD_DATAFLASH) { - fprintf (stderr, "Unsupported flash type %u\n", mtdinfo.type); - return -1; + if (is_mtd) { + rc = ioctl(fd, MEMGETINFO, &mtdinfo); + if (rc < 0) { + perror("Cannot get MTD information"); + return -1; + } + + if (mtdinfo.type != MTD_NORFLASH && + mtdinfo.type != MTD_NANDFLASH && + mtdinfo.type != MTD_DATAFLASH) { + fprintf(stderr, "Unsupported flash type %u\n", + mtdinfo.type); + return -1; + } + } else { + /* + * Kinda hacky assuming !MTD means == MMC + * but seems to be the easiest way to + * determine that. + */ + mtdinfo.type = MTD_ABSENT; } DEVTYPE(dev_current) = mtdinfo.type; -- 1.7.1

3 3

[U-Boot] [PATCH] config.mk:Update DBGFLAGS with dwarf information
by Prabhakar Kushwaha 16 Oct '12

16 Oct '12

Built u-boot elf file does not contain any dwarf informations by default. This information is required for debugging. Add dwarf ver 2 flag in DBGFLAGS. Signed-off-by: Radu Lazarescu <radu.lazarescu(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Applies on http://git.denx.de/u-boot.git branch master config.mk | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/config.mk b/config.mk index ddaa477..11bc20d 100644 --- a/config.mk +++ b/config.mk @@ -178,7 +178,7 @@ endif # who are porting old code to latest mainline but not updating $(AR). ARFLAGS = $(error update your Makefile to use cmd_link_o_target and not AR) RELFLAGS= $(PLATFORM_RELFLAGS) -DBGFLAGS= -g # -DDEBUG +DBGFLAGS= -g -gdwarf-2 # -DDEBUG OPTFLAGS= -Os #-fomit-frame-pointer OBJCFLAGS += --gap-fill=0xff -- 1.7.5.4

4 5

[U-Boot] [PATCH] fix IDE_BUS(dev) macro
by Luka Perkov 08 Oct '12

08 Oct '12

IDE_BUS assumes that each bus has two devices and thus returns the first bus even when the second one should be probed. Signed-off-by: Simon Baatz <gmbnomis(a)gmail.com> Tested-by: Luka Perkov <uboot(a)lukaperkov.net> --- Simon discovered this while adding support for new board IB NAS6210. More info can be found here: http://lists.denx.de/pipermail/u-boot/2012-April/122525.html When this is commited I will do a coding style cleanup. There are tabs after few "#define" parts in include/ide.h. include/ide.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/ide.h b/include/ide.h index 8ecc9dd..385e909 100644 --- a/include/ide.h +++ b/include/ide.h @@ -24,7 +24,7 @@ #ifndef _IDE_H #define _IDE_H -#define IDE_BUS(dev) (dev >> 1) +#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS)) #define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])

11 23

[U-Boot] [PATCH v3 0/23] tegra: warmboot (suspend / resume) support
by Simon Glass 06 Oct '12

06 Oct '12

This series adds support for warm boot, allowing the device to suspend and resume. U-Boot sets up some 'warm boot' code in a special area such that the SOC can find it on a resume. This code is responsible for setting up memory and clocked and then allowing the OS to continue where it left off. Also included here is support for the EMC, which allows setting the memory timings correctly in U-Boot for maximum speed operation. Note: sign-offs are needed from Jimmy Zhang, Wei Ni and Yen Lin. Changes in v2: - Add check of undocumented values in hidrev register - Add debug() output to EMC - Add new fdtdec_locate_array() function - Add patch to find DVC bus number - Check error return from pmu_set_nominal() in debug mode - Move EMC tables to device tree - Move structs shared between A9 and AVP into warmboot.h header file - New patch to add low-level clock functions - Rely on compiler to optimise out debug_print_vector() - Remove unused crypto code - Remove unused crypto code from crypto.c - Removed check for nominal voltage (not needed as it is done just before) - Split PMU code into separate TPS6586X driver - Tidy SDRAM range check in warmboot_prepare_code() - Tidy whitespace problems - Use const for sbox arrays - Use low-level clock functions in warmboot code instead of register access Changes in v3: - Add apb_misc.h header file in new patch - Add better error reporting when EMC setup fails - Add new fdtdec_next_compatible_subnode() patch - Add new patch to put abs() in common.h - Fix CONFIG_TEGRA_I2C define - Move abs() macro into common.h - Support nvidia,use-ram-code binding option for EMC - Try to return a useful error code when EMC config fails Jimmy Zhang (3): tegra: Add EMC support for optimal memory timings tegra: Add PMU to manage power supplies tegra: Add EMC settings for Seaboard Simon Glass (14): fdt: Add function to locate an array in the device tree fdt: Add function to return next compatible subnode Add abs() macro to return absolute value i2c: Add TPS6586X driver tegra: Move ap20.h header into arch location tegra: Add functions to access low-level Osc/PLL details tegra: Add tegra_get_chip_type() to detect SKU tegra: Add header file for APB_MISC register tegra: Set up PMU for Nvidia boards tegra: Set up warmboot code on Nvidia boards fdt: tegra: Add EMC node to device tree tegra: i2c: Add function to find DVC bus tegra: fdt: Add EMC data for Tegra2 Seaboard tegra: Enable LP0 on Seaboard Wei Ni (1): tegra: Turn off power detect in board init Yen Lin (5): Add AES crypto library tegra: Add crypto library for warmboot code tegra: Add flow, gp_padctl, fuse, sdram headers tegra: Add warmboot implementation tegra: Setup PMC scratch info from ap20 setup arch/arm/cpu/armv7/tegra2/Makefile | 4 + arch/arm/cpu/armv7/tegra2/ap20.c | 44 ++- arch/arm/cpu/armv7/tegra2/board.c | 4 +- arch/arm/cpu/armv7/tegra2/clock.c | 32 + arch/arm/cpu/armv7/tegra2/crypto.c | 230 ++++++++ arch/arm/cpu/armv7/tegra2/crypto.h | 36 ++ arch/arm/cpu/armv7/tegra2/emc.c | 286 ++++++++++ arch/arm/cpu/armv7/tegra2/pmu.c | 70 +++ arch/arm/cpu/armv7/tegra2/warmboot.c | 382 +++++++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.c | 250 ++++++++ arch/arm/cpu/armv7/tegra2/warmboot_avp.h | 81 +++ arch/arm/dts/tegra20.dtsi | 7 + .../tegra2 => include/asm/arch-tegra2}/ap20.h | 7 + arch/arm/include/asm/arch-tegra2/apb_misc.h | 36 ++ arch/arm/include/asm/arch-tegra2/clk_rst.h | 3 + arch/arm/include/asm/arch-tegra2/clock.h | 22 + arch/arm/include/asm/arch-tegra2/emc.h | 113 ++++ arch/arm/include/asm/arch-tegra2/flow.h | 36 ++ arch/arm/include/asm/arch-tegra2/fuse.h | 39 ++ arch/arm/include/asm/arch-tegra2/gp_padctrl.h | 73 +++ arch/arm/include/asm/arch-tegra2/pmu.h | 30 + arch/arm/include/asm/arch-tegra2/sdram_param.h | 148 +++++ arch/arm/include/asm/arch-tegra2/tegra2.h | 25 + arch/arm/include/asm/arch-tegra2/tegra_i2c.h | 7 + arch/arm/include/asm/arch-tegra2/warmboot.h | 150 +++++ board/nvidia/common/Makefile | 1 + board/nvidia/common/board.c | 41 ++- board/nvidia/common/emc.c | 53 ++ board/nvidia/common/emc.h | 29 + board/nvidia/dts/tegra2-seaboard.dts | 72 +++ drivers/i2c/tegra_i2c.c | 14 + drivers/power/Makefile | 1 + drivers/power/tps6586x.c | 280 +++++++++ include/aes.h | 70 +++ include/common.h | 13 + include/configs/seaboard.h | 8 + include/configs/tegra2-common.h | 17 + include/fdtdec.h | 38 ++ include/tps6586x.h | 68 +++ lib/Makefile | 1 + lib/aes.c | 598 ++++++++++++++++++++ lib/fdtdec.c | 28 + 42 files changed, 3443 insertions(+), 4 deletions(-) create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.c create mode 100644 arch/arm/cpu/armv7/tegra2/crypto.h create mode 100644 arch/arm/cpu/armv7/tegra2/emc.c create mode 100644 arch/arm/cpu/armv7/tegra2/pmu.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.c create mode 100644 arch/arm/cpu/armv7/tegra2/warmboot_avp.h rename arch/arm/{cpu/armv7/tegra2 => include/asm/arch-tegra2}/ap20.h (96%) create mode 100644 arch/arm/include/asm/arch-tegra2/apb_misc.h create mode 100644 arch/arm/include/asm/arch-tegra2/emc.h create mode 100644 arch/arm/include/asm/arch-tegra2/flow.h create mode 100644 arch/arm/include/asm/arch-tegra2/fuse.h create mode 100644 arch/arm/include/asm/arch-tegra2/gp_padctrl.h create mode 100644 arch/arm/include/asm/arch-tegra2/pmu.h create mode 100644 arch/arm/include/asm/arch-tegra2/sdram_param.h create mode 100644 arch/arm/include/asm/arch-tegra2/warmboot.h create mode 100644 board/nvidia/common/emc.c create mode 100644 board/nvidia/common/emc.h create mode 100644 drivers/power/tps6586x.c create mode 100644 include/aes.h create mode 100644 include/tps6586x.h create mode 100644 lib/aes.c -- 1.7.7.3

8 53

[U-Boot] [PATCH] arm: rmobile: kzm9g: Adjust hardware setting in lowlevel_init.S
by Tetsuyuki Kobayashi 05 Oct '12

05 Oct '12

This patch depends on Nobuhiro Iwamatsu's arm: rmobile: Add supoprt for KMC KZM-A9-GT board Tetsuyuki Kobayashi's arm: rmobile: kzm9g: Modify sdram area Adjust hardware setting in lowlevel_init.S. After this patch U-boot can boot Linux kernel (without DTB) on KZM-A9-GT board successfully. Signed-off-by: Tetsuyuki Kobayashi <koba(a)kmckk.co.jp> --- arch/arm/include/asm/arch-rmobile/sh73a0.h | 1 + board/kmc/kzm/lowlevel_init.S | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/arm/include/asm/arch-rmobile/sh73a0.h b/arch/arm/include/asm/arch-rmobile/sh73a0.h index 07824ab..bb66d20 100644 --- a/arch/arm/include/asm/arch-rmobile/sh73a0.h +++ b/arch/arm/include/asm/arch-rmobile/sh73a0.h @@ -191,6 +191,7 @@ #define SMSTPCR3 (CPG_BASE + 0x013C) #define SMSTPCR4 (CPG_BASE + 0x0140) #define SMSTPCR5 (CPG_BASE + 0x0144) +#define CPGXXCR4 (CPG_BASE + 0x0150) #define SRCR0 (CPG_BASE + 0x80A0) #define SRCR1 (CPG_BASE + 0x80A8) #define SRCR2 (CPG_BASE + 0x80B0) diff --git a/board/kmc/kzm/lowlevel_init.S b/board/kmc/kzm/lowlevel_init.S index 5221611..be3d203 100644 --- a/board/kmc/kzm/lowlevel_init.S +++ b/board/kmc/kzm/lowlevel_init.S @@ -111,6 +111,7 @@ loop0: and_write32 LIFEC_SEC_SRC, 0xFFFFFFE7 + and_write32 SMSTPCR3,0xFFFF7FFF and_write32 SRCR3, 0xFFFF7FFF and_write32 SMSTPCR2,0xFFFBFFFF and_write32 SRCR2, 0xFFFBFFFF @@ -302,6 +303,8 @@ loop0: write32 FRQCRD, 0x00000B0B cmp_loop FRQCRD, 0x80000000, 0x00000000 + write32 CPGXXCR4, 0xfffffffc + bx lr .pool -- 1.7.9.5

6 45

[U-Boot] [PATCH 2/2] ARM: increase lmb stack space reservation to 4KB
by Rob Herring 04 Oct '12

04 Oct '12

From: Rob Herring <rob.herring(a)calxeda.com> The bootm initrd image copy to ram can collide with the stack in cases where the print buffer size is large (i.e. 1K). The result is intermittent initrd decompression errors depending on the initrd size MOD 4KB since the initrd start address is 4KB aligned. Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Signed-off-by: Rob Herring <rob.herring(a)calxeda.com> --- arch/arm/lib/bootm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c index 599547d..999f201 100644 --- a/arch/arm/lib/bootm.c +++ b/arch/arm/lib/bootm.c @@ -69,8 +69,8 @@ void arch_lmb_reserve(struct lmb *lmb) sp = get_sp(); debug("## Current stack ends at 0x%08lx ", sp); - /* adjust sp by 1K to be safe */ - sp -= 1024; + /* adjust sp by 4K to be safe */ + sp -= 4096; lmb_reserve(lmb, sp, gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size - sp); } -- 1.7.9.5

2 2

[U-Boot] [PATCH v2] ARM: Add X600 board support (SPEAr600 based)
by Stefan Roese 04 Oct '12

04 Oct '12

This patch adds support for the X600 SPEAr600 based board. Its also the first SPEAr600 board that uses the newly introduced SPEAr600 SPL support. Xloader is not necessary any more. By using the new "u-boot.spr" make target, one image will generated containing both, U-Boot SPL (with mkimage header as needed by the SPEAr BootROM, and the main U-Boot with mkimage header. Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Amit Virdi <amit.virdi(a)st.com> Cc: Vipin Kumar <vipin.kumar(a)st.com> --- v2: - Add hush support - Add bootcount & altbootcmd support MAINTAINERS | 2 + board/spear/x600/Makefile | 47 +++++++ board/spear/x600/fpga.c | 280 +++++++++++++++++++++++++++++++++++++ board/spear/x600/fpga.h | 23 +++ board/spear/x600/x600.c | 124 +++++++++++++++++ boards.cfg | 1 + include/configs/x600.h | 339 +++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 816 insertions(+) create mode 100644 board/spear/x600/Makefile create mode 100644 board/spear/x600/fpga.c create mode 100644 board/spear/x600/fpga.h create mode 100644 board/spear/x600/x600.c create mode 100644 include/configs/x600.h diff --git a/MAINTAINERS b/MAINTAINERS index f796872..c55faff 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -828,6 +828,8 @@ John Rigby <jcrigby(a)gmail.com> Stefan Roese <sr(a)denx.de> + x600 ARM926EJS (spear600 Soc) + pdnb3 xscale/ixp scpu xscale/ixp diff --git a/board/spear/x600/Makefile b/board/spear/x600/Makefile new file mode 100644 index 0000000..8c4e7e2 --- /dev/null +++ b/board/spear/x600/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2004 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifndef CONFIG_SPL_BUILD +COBJS := fpga.o $(BOARD).o +endif +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/spear/x600/fpga.c b/board/spear/x600/fpga.c new file mode 100644 index 0000000..85eb31b --- /dev/null +++ b/board/spear/x600/fpga.c @@ -0,0 +1,280 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <spartan3.h> +#include <command.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_misc.h> +#include <asm/arch/spr_ssp.h> + +/* + * FPGA program pin configuration on X600: + * + * Only PROG and DONE are connected to GPIOs. INIT is not connected to the + * SoC at all. And CLOCK and DATA are connected to the SSP2 port. We use + * 16bit serial writes via this SSP port to write the data bits into the + * FPGA. + */ +#define CONFIG_SYS_FPGA_PROG 2 +#define CONFIG_SYS_FPGA_DONE 3 + +/* + * Set the active-low FPGA reset signal. + */ +static void fpga_reset(int assert) +{ + /* + * On x600 we have no means to toggle the FPGA reset signal + */ + debug("%s:%d: RESET (%d)\n", __func__, __LINE__, assert); +} + +/* + * Set the FPGA's active-low SelectMap program line to the specified level + */ +static int fpga_pgm_fn(int assert, int flush, int cookie) +{ + debug("%s:%d: FPGA PROG (%d)\n", __func__, __LINE__, assert); + + gpio_set_value(CONFIG_SYS_FPGA_PROG, assert); + + return assert; +} + +/* + * Test the state of the active-low FPGA INIT line. Return 1 on INIT + * asserted (low). + */ +static int fpga_init_fn(int cookie) +{ + static int state; + + debug("%s:%d: init (state=%d)\n", __func__, __LINE__, state); + + /* + * On x600, the FPGA INIT signal is not connected to the SoC. + * We can't read the INIT status. Let's return the "correct" + * INIT signal state generated via a local state-machine. + */ + if (++state == 1) { + return 1; + } else { + state = 0; + return 0; + } +} + +/* + * Test the state of the active-high FPGA DONE pin + */ +static int fpga_done_fn(int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + + /* + * Wait for Tx-FIFO to become empty before looking for DONE + */ + while (!(readl(&ssp->sspsr) & SSPSR_TFE)) + ; + + if (gpio_get_value(CONFIG_SYS_FPGA_DONE)) + return 1; + else + return 0; +} + +/* + * FPGA pre-configuration function. Just make sure that + * FPGA reset is asserted to keep the FPGA from starting up after + * configuration. + */ +static int fpga_pre_config_fn(int cookie) +{ + debug("%s:%d: FPGA pre-configuration\n", __func__, __LINE__); + fpga_reset(TRUE); + + return 0; +} + +/* + * FPGA post configuration function. Blip the FPGA reset line and then see if + * the FPGA appears to be running. + */ +static int fpga_post_config_fn(int cookie) +{ + int rc = 0; + + debug("%s:%d: FPGA post configuration\n", __func__, __LINE__); + + fpga_reset(TRUE); + udelay(100); + fpga_reset(FALSE); + udelay(100); + + return rc; +} + +static int fpga_clk_fn(int assert_clk, int flush, int cookie) +{ + /* + * No dedicated clock signal on x600 (data & clock generated) + * in SSP interface. So we don't have to do anything here. + */ + return assert_clk; +} + +static int fpga_wr_fn(int assert_write, int flush, int cookie) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + static int count; + static u16 data; + + /* + * First collect 16 bits of data + */ + data = data << 1; + if (assert_write) + data |= 1; + + /* + * If 16 bits are not available, return for more bits + */ + count++; + if (count != 16) + return assert_write; + + count = 0; + + /* + * Wait for Tx-FIFO to become ready + */ + while (!(readl(&ssp->sspsr) & SSPSR_TNF)) + ; + + /* Send 16 bits to FPGA via SSP bus */ + writel(data, &ssp->sspdr); + + return assert_write; +} + +static Xilinx_Spartan3_Slave_Serial_fns x600_fpga_fns = { + fpga_pre_config_fn, + fpga_pgm_fn, + fpga_clk_fn, + fpga_init_fn, + fpga_done_fn, + fpga_wr_fn, + fpga_post_config_fn, +}; + +static Xilinx_desc fpga[CONFIG_FPGA_COUNT] = { + XILINX_XC3S1200E_DESC(slave_serial, &x600_fpga_fns, 0) +}; + +/* + * Initialize the SelectMap interface. We assume that the mode and the + * initial state of all of the port pins have already been set! + */ +static void fpga_serialslave_init(void) +{ + debug("%s:%d: Initialize serial slave interface\n", __func__, __LINE__); + fpga_pgm_fn(FALSE, FALSE, 0); /* make sure program pin is inactive */ +} + +static int expi_setup(int freq) +{ + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + int pll2_m, pll2_n, pll2_p, expi_x, expi_y; + + pll2_m = (freq * 2) / 1000; + pll2_n = 15; + pll2_p = 1; + expi_x = 1; + expi_y = 2; + + /* + * Disable reset, Low compression, Disable retiming, Enable Expi, + * Enable soft reset, DMA, PLL2, Internal + */ + writel(EXPI_CLK_CFG_LOW_COMPR | EXPI_CLK_CFG_CLK_EN | EXPI_CLK_CFG_RST | + EXPI_CLK_SYNT_EN | EXPI_CLK_CFG_SEL_PLL2 | + EXPI_CLK_CFG_INT_CLK_EN | (expi_y << 16) | (expi_x << 24), + &misc->expi_clk_cfg); + + /* + * 6 uA, Internal feedback, 1st order, Non-dithered, Sample Parameters, + * Enable PLL2, Disable reset + */ + writel((pll2_m << 24) | (pll2_p << 8) | (pll2_n), &misc->pll2_frq); + writel(PLL2_CNTL_6UA | PLL2_CNTL_SAMPLE | PLL2_CNTL_ENABLE | + PLL2_CNTL_RESETN | PLL2_CNTL_LOCK, &misc->pll2_cntl); + + /* + * Disable soft reset + */ + clrbits_le32(&misc->expi_clk_cfg, EXPI_CLK_CFG_RST); + + return 0; +} + +/* + * Initialize the fpga + */ +int x600_init_fpga(void) +{ + struct ssp_regs *ssp = (struct ssp_regs *)CONFIG_SSP2_BASE; + struct misc_regs *misc = (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + + /* Enable SSP2 clock */ + writel(readl(&misc->periph1_clken) | MISC_SSP2ENB | MISC_GPIO4ENB, + &misc->periph1_clken); + + /* Set EXPI clock to 45 MHz */ + expi_setup(45000); + + /* Configure GPIO directions */ + gpio_direction_output(CONFIG_SYS_FPGA_PROG, 0); + gpio_direction_input(CONFIG_SYS_FPGA_DONE); + + writel(SSPCR0_DSS_16BITS, &ssp->sspcr0); + writel(SSPCR1_SSE, &ssp->sspcr1); + + /* + * Set lowest prescale divisor value (CPSDVSR) of 2 for max download + * speed. + * + * Actual data clock rate is: 80MHz / (CPSDVSR * (SCR + 1)) + * With CPSDVSR at 2 and SCR at 0, the maximume clock rate is 40MHz. + */ + writel(2, &ssp->sspcpsr); + + fpga_init(); + fpga_serialslave_init(); + + debug("%s:%d: Adding fpga 0\n", __func__, __LINE__); + fpga_add(fpga_xilinx, &fpga[0]); + + return 0; +} diff --git a/board/spear/x600/fpga.h b/board/spear/x600/fpga.h new file mode 100644 index 0000000..2b18557 --- /dev/null +++ b/board/spear/x600/fpga.h @@ -0,0 +1,23 @@ +/* + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +int x600_init_fpga(void); diff --git a/board/spear/x600/x600.c b/board/spear/x600/x600.c new file mode 100644 index 0000000..96ec0ad --- /dev/null +++ b/board/spear/x600/x600.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, ST Micoelectronics, vipin.kumar(a)st.com. + * + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <nand.h> +#include <netdev.h> +#include <phy.h> +#include <rtc.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/spr_defs.h> +#include <asm/arch/spr_misc.h> +#include <linux/mtd/fsmc_nand.h> +#include "fpga.h" + +static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE]; + +int board_init(void) +{ + /* + * X600 is equipped with an M41T82 RTC. This RTC has the + * HT bit (Halt Update), which needs to be cleared upon + * power-up. Otherwise the RTC is halted. + */ + rtc_reset(); + + return spear_board_init(MACH_TYPE_SPEAR600); +} + +int board_late_init(void) +{ + /* + * Monitor and env protection on by default + */ + flash_protect(FLAG_PROTECT_SET, + CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + + CONFIG_SYS_SPL_LEN + CONFIG_SYS_MONITOR_LEN + + 2 * CONFIG_ENV_SECT_SIZE - 1, + &flash_info[0]); + + /* Init FPGA subsystem */ + x600_init_fpga(); + + return 0; +} + +/* + * board_nand_init - Board specific NAND initialization + * @nand: mtd private chip structure + * + * Called by nand_init_chip to initialize the board specific functions + */ + +void board_nand_init(void) +{ + struct misc_regs *const misc_regs_p = + (struct misc_regs *)CONFIG_SPEAR_MISCBASE; + struct nand_chip *nand = &nand_chip[0]; + + if (!(readl(&misc_regs_p->auto_cfg_reg) & MISC_NANDDIS)) + fsmc_nand_init(nand); +} + +int designware_board_phy_init(struct eth_device *dev, int phy_addr, + int (*mii_write)(struct eth_device *, u8, u8, u16), + int dw_reset_phy(struct eth_device *)) +{ + /* Extended PHY control 1, select GMII */ + mii_write(dev, phy_addr, 23, 0x0020); + + /* Software reset necessary after GMII mode selction */ + dw_reset_phy(dev); + + /* Enable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0001); + + /* 17e: Enhanced LED behavior, needs to be written twice */ + mii_write(dev, phy_addr, 17, 0x09ff); + mii_write(dev, phy_addr, 17, 0x09ff); + + /* 16e: Enhanced LED method select */ + mii_write(dev, phy_addr, 16, 0xe0ea); + + /* Disable extended page register access */ + mii_write(dev, phy_addr, 31, 0x0000); + + /* Enable clock output pin */ + mii_write(dev, phy_addr, 18, 0x0049); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + int ret = 0; + + if (designware_initialize(0, CONFIG_SPEAR_ETHBASE, CONFIG_PHY_ADDR, + PHY_INTERFACE_MODE_GMII) >= 0) + ret++; + + return ret; +} diff --git a/boards.cfg b/boards.cfg index 2a75880..89984d0 100644 --- a/boards.cfg +++ b/boards.cfg @@ -193,6 +193,7 @@ spear600 arm arm926ejs spear600 spear spear600_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,nand spear600_usbtty arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty spear600_usbtty_nand arm arm926ejs spear600 spear spear spear6xx_evb:spear600,usbtty,nand +x600 arm arm926ejs - spear spear x600 versatileab arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_AB versatilepb arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_PB versatileqemu arm arm926ejs versatile armltd versatile versatile:ARCH_VERSATILE_QEMU,ARCH_VERSATILE_PB diff --git a/include/configs/x600.h b/include/configs/x600.h new file mode 100644 index 0000000..3082aaa --- /dev/null +++ b/include/configs/x600.h @@ -0,0 +1,339 @@ +/* + * (C) Copyright 2009 + * Vipin Kumar, STMicroelectronics, <vipin.kumar(a)st.com> + * + * Copyright (C) 2012 Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_SPEAR600 /* SPEAr600 SoC */ +#define CONFIG_X600 /* on X600 board */ + +#include <asm/arch/hardware.h> + +/* Timer, HZ specific defines */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK 8300000 + +#define CONFIG_SYS_TEXT_BASE 0x00800040 +#define CONFIG_SYS_FLASH_BASE 0xf8000000 +/* Reserve 8KiB for SPL */ +#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */ +#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO +#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ + CONFIG_SYS_SPL_LEN) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN 0x60000 + +#define CONFIG_ENV_IS_IN_FLASH + +/* Serial Configuration (PL011) */ +#define CONFIG_SYS_SERIAL0 0xD0000000 +#define CONFIG_SYS_SERIAL1 0xD0080000 +#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \ + (void *)CONFIG_SYS_SERIAL1 } +#define CONFIG_PL011_SERIAL +#define CONFIG_PL011_CLOCK (48 * 1000 * 1000) +#define CONFIG_CONS_INDEX 0 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \ + 57600, 115200 } +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* NOR FLASH config options */ +#define CONFIG_ST_SMI +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000 +#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ) + +/* NAND FLASH config options */ +#define CONFIG_NAND_FSMC +#define CONFIG_SYS_NAND_SELF_INIT +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE +#define CONFIG_MTD_ECC_SOFT +#define CONFIG_SYS_FSMC_NAND_8BIT +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* UBI/UBI config options */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_RBTREE + +/* Ethernet config options */ +#define CONFIG_MII +#define CONFIG_DESIGNWARE_ETH +#define CONFIG_DW_SEARCH_PHY +#define CONFIG_NET_MULTI +#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */ +#define CONFIG_DW_AUTONEG +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#define CONFIG_SPEAR_GPIO + +/* I2C config options */ +#define CONFIG_HARD_I2C +#define CONFIG_DW_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x02 +#define CONFIG_I2C_CHIPADDRESS 0x50 + +#define CONFIG_RTC_M41T62 1 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* FPGA config options */ +#define CONFIG_FPGA +#define CONFIG_FPGA_XILINX +#define CONFIG_FPGA_SPARTAN3 +#define CONFIG_FPGA_COUNT 1 + +/* + * Command support defines + */ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_FPGA +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_MII +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_RUN +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_LZO + +/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <config_cmd_default.h> + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * U-Boot Environment placing definitions. + */ +#define CONFIG_ENV_SECT_SIZE 0x00010000 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SIZE 0x02000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +/* Miscellaneous configurable options */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_BOOT_PARAMS_ADDR 0x00000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_OF_LIBFDT /* enable passing of devicetree */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_MISC_INIT_R +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_LOOPW /* enable loopw command */ +#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_STOP_STR " " +#define CONFIG_AUTOBOOT_PROMPT \ + "Hit SPACE in %d seconds to stop autoboot.\n", bootdelay + +#define CONFIG_SYS_MEMTEST_START 0x00800000 +#define CONFIG_SYS_MEMTEST_END 0x04000000 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) +#define CONFIG_IDENT_STRING "-SPEAr" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "X600> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x00800000 +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_64BIT_VSPRINTF + +/* Use last 2 lwords in internal SRAM for bootcounter */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR 0xd2801ff8 + +#define CONFIG_HOSTNAME x600 +#define CONFIG_UBI_PART ubi0 +#define CONFIG_UBIFS_VOLUME rootfs + +#define xstr(s) str(s) +#define str(s) #s + +#define MTDIDS_DEFAULT "nand0=nand" +#define MTDPARTS_DEFAULT "mtdparts=nand:64M(ubi0),64M(ubi1)" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "u-boot_addr=1000000\0" \ + "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.spr\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};"\ + "erase " xstr(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \ + "cp.b ${u-boot_addr} " xstr(CONFIG_SYS_MONITOR_BASE) \ + " ${filesize};" \ + "protect on " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize}\0" \ + "upd=run load update\0" \ + "ubifs=" xstr(CONFIG_HOSTNAME) "/ubifs.img\0" \ + "part=" xstr(CONFIG_UBI_PART) "\0" \ + "vol=" xstr(CONFIG_UBIFS_VOLUME) "\0" \ + "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \ + "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \ + " ${filesize}\0" \ + "upd_ubifs=run load_ubifs update_ubifs\0" \ + "init_ubifs=nand erase.part ubi0;ubi part ${part};" \ + "ubi create ${vol} 4000000\0" \ + "netdev=eth0\0" \ + "rootpath=/opt/eldk-4.2/arm\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "boot_part=0\0" \ + "altbootcmd=if test $boot_part -eq 0;then " \ + "echo Switching to partition 1!;" \ + "setenv boot_part 1;" \ + "else; " \ + "echo Switching to partition 0!;" \ + "setenv boot_part 0;" \ + "fi;" \ + "saveenv;boot\0" \ + "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \ + "root=ubi0:rootfs rootfstype=ubifs\0" \ + "kernel=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ + "kernel_fs=/boot/uImage \0" \ + "kernel_addr=1000000\0" \ + "dtb=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_fs=/boot/" xstr(CONFIG_HOSTNAME) ".dtb\0" \ + "dtb_addr=1800000\0" \ + "load_kernel=tftp ${kernel_addr} ${kernel}\0" \ + "load_dtb=tftp ${dtb_addr} ${dtb}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \ + "${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "net_nfs=run load_dtb load_kernel; " \ + "run nfsargs addip addcon addmtd addmisc;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \ + " addcon addmisc addmtd;" \ + "bootm ${kernel_addr} - ${dtb_addr}\0" \ + "ubifs_mount=ubi part ubi${boot_part};ubifsmount rootfs\0" \ + "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \ + "ubifsload ${dtb_addr} ${dtb_fs};\0" \ + "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \ + "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \ + "bootcmd=run nand_ubifs\0" \ + "\0" + +/* Stack sizes */ +#define CONFIG_STACKSIZE (512 * 1024) + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_MAXSIZE 0x40000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xD2800000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* + * SPL related defines + */ +#define CONFIG_SPL +#define CONFIG_SPL_TEXT_BASE 0xd2800b00 +#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear" +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/arm926ejs/spear/u-boot-spl.lds" + +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */ +#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */ +#define CONFIG_SPL_NO_PRINTF + +/* + * Please select/define only one of the following + * Each definition corresponds to a supported DDR chip. + * DDR configuration is based on the following selection + */ +#define CONFIG_DDR_MT47H64M16 1 +#define CONFIG_DDR_MT47H32M16 0 +#define CONFIG_DDR_MT47H128M8 0 + +/* + * Synchronous/Asynchronous operation of DDR + * + * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation + * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation + * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation + */ +#define CONFIG_DDR_2HCLK 1 +#define CONFIG_DDR_HCLK 0 +#define CONFIG_DDR_PLL2 0 + +/* + * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported + * or not. Modify/Add to only these macros to define new boot types + */ +#define USB_BOOT_SUPPORTED 0 +#define PCIE_BOOT_SUPPORTED 0 +#define SNOR_BOOT_SUPPORTED 1 +#define NAND_BOOT_SUPPORTED 1 +#define PNOR_BOOT_SUPPORTED 0 +#define TFTP_BOOT_SUPPORTED 0 +#define UART_BOOT_SUPPORTED 0 +#define SPI_BOOT_SUPPORTED 0 +#define I2C_BOOT_SUPPORTED 0 +#define MMC_BOOT_SUPPORTED 0 + +#endif /* __CONFIG_H */ -- 1.7.10.3

4 5

[U-Boot] [PATCH 0/2] Add support for MINI2440 (s3c2440)
by Gabriel Huau 03 Oct '12

03 Oct '12

>From the last time, I removed the patch about the PLL initialization because it's board specific. I added a new patch for s3c440 gpio driver. Now in the board file we have no more magic bloat. >> +/* >> + * When booting from NAND, it is impossible to access the lowest addresses >> + * due to the SteppingStone being in the way. Luckily the NOR doesn't really >> + * care about the highest 16 bits of address, so we set the controlers >> + * registers to go and poke over there, instead. >> + */ >> +#define PHYS_FLASH_1 0x0 >> +#define CONFIG_SYS_FLASH_BASE 0x0 > >Urghh... this sounds very much like a serious design issue? About this point, I ported it from the old version uboot as well. It may need some investigation, but I remember it was a big problem with this board. In the case of a NAND boot, we don't have access to NOR because the SteppingStone (SRAM) is mapped at the same range. Gabriel Huau (2): Add GPIO Driver and IOMUX definition for S3C2440 Add support for MINI2440 (s3c2440). MAINTAINERS | 4 + arch/arm/include/asm/arch-s3c24x0/gpio.h | 183 +++++++++++++++++++++++++ arch/arm/include/asm/arch-s3c24x0/iomux.h | 197 +++++++++++++++++++++++++++ board/friendlyarm/mini2440/Makefile | 44 ++++++ board/friendlyarm/mini2440/mini2440.c | 135 +++++++++++++++++++ board/friendlyarm/mini2440/mini2440.h | 144 ++++++++++++++++++++ boards.cfg | 1 + doc/README.mini2440 | 28 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/s3c2440_gpio.c | 74 ++++++++++ include/configs/mini2440.h | 209 +++++++++++++++++++++++++++++ 11 files changed, 1020 insertions(+) create mode 100644 arch/arm/include/asm/arch-s3c24x0/gpio.h create mode 100644 arch/arm/include/asm/arch-s3c24x0/iomux.h create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 board/friendlyarm/mini2440/mini2440.h create mode 100644 doc/README.mini2440 create mode 100644 drivers/gpio/s3c2440_gpio.c create mode 100644 include/configs/mini2440.h -- 1.7.9.5

6 48

[U-Boot] [PATCH 5/5] msm7x30: Add support for msm7630_surf board
by mohamed.haneef＠lntinfotech.com 03 Oct '12

03 Oct '12

From: Mohamed Haneef <mohamed.haneef(a)lntinfotech.com> *Support for msm7630_surf board Signed-off-by: Mohamed Haneef <mohamed.haneef(a)lntinfotech.com> --- board/qcom/msm7630_surf/Makefile | 55 +++++++++++ board/qcom/msm7630_surf/msm7630_surf.c | 155 ++++++++++++++++++++++++++++++++ board/qcom/msm7630_surf/msm7630_surf.h | 30 ++++++ boards.cfg | 1 + include/configs/msm7630_surf.h | 131 +++++++++++++++++++++++++++ 5 files changed, 372 insertions(+), 0 deletions(-) create mode 100644 board/qcom/msm7630_surf/Makefile create mode 100644 board/qcom/msm7630_surf/msm7630_surf.c create mode 100644 board/qcom/msm7630_surf/msm7630_surf.h create mode 100644 include/configs/msm7630_surf.h diff --git a/board/qcom/msm7630_surf/Makefile b/board/qcom/msm7630_surf/Makefile new file mode 100644 index 0000000..f9dec32 --- /dev/null +++ b/board/qcom/msm7630_surf/Makefile @@ -0,0 +1,55 @@ +# +# (C) Copyright 2012 +# LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com> +# +# (C) Copyright 2010,2011 +# NVIDIA Corporation <www.nvidia.com> +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)../../qcom/msm7630_surf/) +endif + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/qcom/msm7630_surf/msm7630_surf.c b/board/qcom/msm7630_surf/msm7630_surf.c new file mode 100644 index 0000000..eb941c7 --- /dev/null +++ b/board/qcom/msm7630_surf/msm7630_surf.c @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2012 + * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/iomap.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> +#include <malloc.h> +#include <asm/arch/mmc.h> +#include <linux/string.h> +#include <asm/mach-types.h> +#include <asm/arch/proc_comm.h> +#include "msm7630_surf.h" + +static struct msm_gpio uart2_gpio_table[] = { + { + .gpio_cfg = GPIO_CFG(49, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), + .label = NULL, + }, + { + .gpio_cfg = GPIO_CFG(50, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), + .label = NULL, + }, + { + .gpio_cfg = GPIO_CFG(51, 2, GPIO_INPUT, GPIO_PULL_DOWN, GPIO_2MA), + .label = NULL, + }, + { + .gpio_cfg = GPIO_CFG(52, 2, GPIO_OUTPUT, GPIO_PULL_DOWN, GPIO_2MA), + .label = NULL, + }, +}; + + + +DECLARE_GLOBAL_DATA_PTR; + +void uart2_mux_init(void) +{ + platform_gpios_enable(uart2_gpio_table, ARRAY_SIZE(uart2_gpio_table)); +} + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f() +{ + uart2_mux_init(); + uart2_clock_init(); + return 0; +} +#endif +int board_init() +{ + unsigned long new_addr; + unsigned long offset; + offset = gd->relocaddr - CONFIG_SYS_TEXT_BASE; + new_addr = CONFIG_SYS_TEXT_BASE + offset; + set_vector_base(new_addr); + bd_t *bd = gd->bd; + bd->bi_arch_number = MACH_TYPE_MSM7X30_SURF; + acpu_clock_init(); + adm_enable_clock(); + return 0; +} + +#ifdef CONFIG_QC_MMC + +/* called during the scan of each mmc device */ +int qc_board_mmc_init(struct mmc *mmc) +{ + + struct mmc_priv *sd = (struct mmc_priv *)mmc->priv; + u32 smem_val; + do { + smem_val = 0; + smem_val = readl(MSM_SHARED_BASE + 0x14); + } while (smem_val != 1); + + if (sd->instance == 2 || sd->instance == 4) { + mmc_boot_main(mmc); + return 0; + } else + /* this board does not have an sd/mmc card on this interface. */ + return 1; + } +int board_mmc_init(bd_t *bis) +{ +#ifdef QC_SD + struct mmc *mmc_4; + struct mmc_priv *sdcc_4; + mmc_4 = (struct mmc *) malloc(sizeof(struct mmc)); + if (!mmc_4) + return 1; + sdcc_4 = (struct mmc_priv *) malloc(sizeof(struct mmc_priv)); + if (!sdcc_4) { + free(mmc_4); + return 1; + } + sdcc_4->instance = 4; + sdcc_4->base = MSM_SDC4_BASE; + mmc_4->priv = sdcc_4; + mmc_4->send_cmd = mmc_boot_send_command_map; + mmc_4->set_ios = mmc_boot_set_ios; + mmc_4->init = qc_board_mmc_init; + mmc_4->voltages = MMC_VDD_29_30|MMC_VDD_165_195; + mmc_4->host_caps = MMC_MODE_4BIT|MMC_MODE_HS; + mmc_4->f_min = MMC_CLK_400KHZ; + mmc_4->f_max = MMC_CLK_48MHZ; + sprintf(mmc_4->name, "External_Card"); + mmc_register(mmc_4); +#else + struct mmc *mmc_2; + struct mmc_priv *sdcc_2; + mmc_2 = (struct mmc *) malloc(sizeof(struct mmc)); + if (!mmc_2) + return 1; + sdcc_2 = (struct mmc_priv *) malloc(sizeof(struct mmc_priv)); + if (!sdcc_2) { + free(mmc_2); + return 1; + } + sdcc_2->instance = 2; + sdcc_2->base = MSM_SDC2_BASE; + mmc_2->priv = sdcc_2; + mmc_2->send_cmd = mmc_boot_send_command_map; + mmc_2->set_ios = mmc_boot_set_ios; + mmc_2->init = qc_board_mmc_init; + mmc_2->voltages = MMC_VDD_29_30|MMC_VDD_165_195; + mmc_2->host_caps = MMC_MODE_4BIT|MMC_MODE_HS|MMC_MODE_8BIT| + MMC_MODE_HS_52MHz; + mmc_2->f_min = MMC_CLK_400KHZ; + mmc_2->f_max = MMC_CLK_48MHZ; + sprintf(mmc_2->name, "Internal_Card"); + mmc_register(mmc_2); +#endif + return 0; +} +#endif diff --git a/board/qcom/msm7630_surf/msm7630_surf.h b/board/qcom/msm7630_surf/msm7630_surf.h new file mode 100644 index 0000000..a3d4bde --- /dev/null +++ b/board/qcom/msm7630_surf/msm7630_surf.h @@ -0,0 +1,30 @@ +/* + * (C) Copyright 2012 + * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MSM7630_SURF_H_ +#define __MSM7630_SURF_H_ +#include <asm/arch/gpio_hw.h> + +extern void set_vector_base(unsigned long); +extern void adm_enable_clock(void); +extern void acpu_clock_init(void); +extern void uart2_clock_init(void); +extern int platform_gpios_enable(const struct msm_gpio *table, int size); +#endif diff --git a/boards.cfg b/boards.cfg index bf71a66..4ab9330 100644 --- a/boards.cfg +++ b/boards.cfg @@ -190,6 +190,7 @@ integratorcp_cm946es arm arm946es integrator armltd ca9x4_ct_vxp arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx highbank arm armv7 highbank - highbank +msm7630_surf arm armv7 msm7630_surf qcom msm7630 efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg diff --git a/include/configs/msm7630_surf.h b/include/configs/msm7630_surf.h new file mode 100644 index 0000000..3356611 --- /dev/null +++ b/include/configs/msm7630_surf.h @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2012 + * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/sizes.h> +#define PLATFORM_MSM7X30 1 +#define CONFIG_MSM_UART +#define CONFIG_SYS_NO_FLASH +#define CONFIG_L2_OFF +#define CONFIG_SKIP_LOWLEVEL_INIT +/* Environment */ +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */ +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MSM_PCOMM +#define CONFIG_ARCH_CPU_INIT +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024) /* 4KB */ +#define CONFIG_MSM7630 + +/* + * select serial console configuration + */ +#define CONFIG_CONS_INDEX 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +#include <config_cmd_default.h> + +/* remove unused commands */ +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration support */ +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_NFS /* NFS support */ +#undef CONFIG_CMD_NET /* network support */ +#undef CONFIG_SYS_MAX_FLASH_SECT +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttyS0,115200n8\0" \ + +#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define V_PROMPT "(MSM 7x30) # " +#define CONFIG_SYS_PROMPT V_PROMPT +/* + * Increasing the size of the IO buffer as default nfsargs size is more + * than 256 and so it is not possible to edit it + */ +#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_LOAD_ADDR 0x00208000 +#define CONFIG_SYS_MEMTEST_START 0x08008000 +#define CONFIG_SYS_MEMTEST_END 0x08008001 + +#define CONFIG_DOS_PARTITION +#define CONFIG_MMC +#define CONFIG_CMD_MMC + +#define CONFIG_GENERIC_MMC +#define CONFIG_QC_MMC + +/*--------------------------------------------------------------------- + * IRQ Settings + */ + +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ + + +#define CONFIG_NR_DRAM_BANKS 2 + +#define PHYS_SDRAM_1 0x00200000 +#define PHYS_SDRAM_1_SIZE (60*1024*1024) /* 512M */ + + +#define PHYS_SDRAM_2 0x07A00000 +#define PHYS_SDRAM_2_SIZE (134*1024*1024) + +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00100000 + + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#endif -- 1.7.1 The contents of this e-mail and any attachment(s) may contain confidential or privileged information for the intended recipient(s). Unintended recipients are prohibited from taking action on the basis of information in this e-mail and using or disseminating the information, and must notify the sender and delete it from their system. L&T Infotech will not accept responsibility or liability for the accuracy or completeness of, or the presence of any virus or disabling code in this e-mail"

2 1