June 2012 - U-Boot

[U-Boot] Add new NAND flash
by Matthias Weißer 05 Mar '13

05 Mar '13

Hi I would like to add a new NAND flash type to u-boot and have some problems with it. The type is MT29F16G08CBABA – Page size x8: 4320 bytes (4096 + 224 bytes) – Block size: 256 pages (1024K + 56K bytes) – Plane size: 2 planes x 1024 blocks per plane – Device size: 16Gb: 2048 blocks The NAND subsystem is configured as follows #define CONFIG_NAND_MXC #define CONFIG_NAND_MXC_V1_1 #define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (0xBB000000) #define CONFIG_MXC_NAND_HWECC #define CONFIG_SYS_NAND_LARGEPAGE The NAND is connected (8 bit wide) to an iMX25 which is booting from NOR. So the NAND is only a mass storage device. I am able to read the ID of the chip. 2Ch 48h 04h 46h 85h I then added the following entry to the nand_flash_ids[] table {"NAND 2GiB 3,3V 8-bit", 0x48, 0, 2048, 0, LP_OPTIONS}, Before getting to the u-boot prompt I get the following message: NAND: NAND device: Manufacturer ID: 0x2c, Chip ID: 0x48 (Micron NAND 2GiB 3,3V 8-bit) NAND bus width 8 instead 16 bit This is caused by bit 6 in id byte 4 which tells that the device is 16 bit wide organized and the iMX specific part of the NAND system which tells the generic system that the device is connected via a 8 bit bus which is obviously correct as the flash chip only has 8 data lines. Is there anything I am doing wrong here? Thanks, Matthias

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[U-Boot] [PATCH] ARM: Fix malloc area size for versatile and integrator
by Marek Vasut 03 Feb '13

03 Feb '13

These boards couldn't save their environment because they couldn't malloc() the whole size of the sector. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Linus Walleij <linus.walleij(a)linaro.org> --- include/configs/integratorcp.h | 2 +- include/configs/versatile.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 57610a6..511fa1f 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -56,7 +56,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128*1024) /* * Hardware drivers diff --git a/include/configs/versatile.h b/include/configs/versatile.h index bb835e0..6a9aa30 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -71,7 +71,7 @@ * Size of malloc() pool */ #define CONFIG_ENV_SIZE 8192 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128 * 1024) /* * Hardware drivers -- 1.7.9

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Re: [U-Boot] Nand flash R/W,saveenv issue..
by Marek Vasut 25 Jan '13

25 Jan '13

Dear Manukumar, > Hello, CCing someone who might actually help you, CCing the uboot mailing list, please keep it that way. > i can able to detect nand flash. > but i had an issue that i could not do operation(Read/write) > on nand flash. > i tried to erase the nand flash i got the error as below: > > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > > even if i try to saveenv then also is not saving the envionment > variables > > processor used: P1012 > nand flash: samsung K9F5608U0D > > please reply ASAP. > > manukumar > signal-networks Best regards, Marek Vasut

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[U-Boot] [PATCH v4] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Jan '13

25 Jan '13

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code drivers/net/Makefile | 1 + drivers/net/mv88e61xx.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mv88e61xx.h | 73 ++++++++++++ 3 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 drivers/net/mv88e61xx.c create mode 100644 drivers/net/mv88e61xx.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..7d397d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index 0000000..713e728 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include "mv88e61xx.h" + +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +#ifndef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define mv88e61xx_wr_phy miiphy_write +#define mv88e61xx_rd_phy miiphy_read +#else + +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_vlaninit(struct mv88f61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + reg); + } + /* Set CPU port VID to 0x1 */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xfff; + reg |= 0x1; + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xc000; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + /* + * Set Vlan map table for all ports to send only to + * cpu_port + */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + mv88e61xx_rd_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv_switch_88e61xx_init(struct mv88f61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->mode != MV88F61XX_MODE_SW_MANAGEED) { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + swconfig->ports_enabled &= 0x023; /* ports 2,3,4 no available */ + } + + /* Init vlan */ + mv88e61xx_vlaninit(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + + if (swconfig->rgmii_delay == MV88F61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/mv88e61xx.h b/drivers/net/mv88e61xx.h new file mode 100644 index 0000000..f1c86a6 --- /dev/null +++ b/drivers/net/mv88e61xx.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88f61xx_cfg_mode { + MV88F61XX_MODE_SW_MANAGEED, + MV88F61XX_MODE_SW_UNMANAGEED +}; + +enum mv88f61xx_cfg_rgmiid { + MV88F61XX_RGMII_DELAY_DIS, + MV88F61XX_RGMII_DELAY_EN +}; + +enum mv88f61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88f61xx_config { + char *name; + enum mv88f61xx_cfg_mode mode; + enum mv88f61xx_cfg_rgmiid rgmii_delay; + enum mv88f61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#endif /* _MV88E61XX_H */ -- 1.5.3.3

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[U-Boot] Read-only env variables
by Joe Hershberger 15 Jan '13

15 Jan '13

Hi u-boot, I see u-boot supports readonly serial# and ethaddr, but I have a few other variables that I need to be read-only. I'm planning to implement a generic list of variables that cannot be changed or deleted. I'm interested to know what sort of specification people would find most appropriate. My current thought is to follow the same delimiter as the env itself, i.e. null separated list with double null terminator. This list would then be defined in the board config header. It also seems that you should be able to specify simple access rules for each variable name perhaps using "=<val>" after each var name where <val> could have constants (probably numbers for performance, but could be string literals) to define modes. Right now I'm thinking read-only, create-only, change-default, and change-only (i.e no delete) are the modes that make sense. I'm also interested if anyone would be opposed to simply using this new specification of readonly vars to implement the serial# and ethaddr protection. The CONFIG_HAS_UID is a bit odd... should that be available in general for read-only vars? Comments? Thanks, -Joe

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[U-Boot] [PATCH v3] davinci: cleanup davinci_sync_env_enetaddr() fucntion
by Manjunath Hadli 14 Jan '13

14 Jan '13

check for the return status for eth_getenv_enetaddr_by_index() and eth_setenv_enetaddr() functions and print appropriate message on failure. Signed-off-by: Manjunath Hadli <manjunath.hadli(a)ti.com> Cc: Tom Rini <trini(a)ti.com> Cc: Mike Frysinger <vapier(a)gentoo.org> Cc: Wolfgang Denk <wd(a)denx.de> --- Changes for v3: undo conversion of debug statement to printf(). Changes for v2: Removed additional check of comparing ethernet address is all zeros, As the core code already calls is_valid_ether_addr() and one of the checks in there is for all zeros. arch/arm/cpu/arm926ejs/davinci/misc.c | 9 ++++++--- 1 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/davinci/misc.c b/arch/arm/cpu/arm926ejs/davinci/misc.c index 5f510b6..c310c69 100644 --- a/arch/arm/cpu/arm926ejs/davinci/misc.c +++ b/arch/arm/cpu/arm926ejs/davinci/misc.c @@ -101,9 +101,10 @@ void davinci_emac_mii_mode_sel(int mode_sel) void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) { uint8_t env_enetaddr[6]; + int ret; - eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); - if (!memcmp(env_enetaddr, "\0\0\0\0\0\0", 6)) { + ret = eth_getenv_enetaddr_by_index("eth", 0, env_enetaddr); + if (ret) { /* * There is no MAC address in the environment, so we * initialize it from the value in the EEPROM. @@ -111,8 +112,10 @@ void davinci_sync_env_enetaddr(uint8_t *rom_enetaddr) debug("### Setting environment from EEPROM MAC address = " "\"%pM\"\n", env_enetaddr); - eth_setenv_enetaddr("ethaddr", rom_enetaddr); + ret = !eth_setenv_enetaddr("ethaddr", rom_enetaddr); } + if (!ret) + printf("Failed to set mac address from EEPROM\n"); } #endif /* CONFIG_DRIVER_TI_EMAC */ -- 1.6.2.4

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[U-Boot] Pull request for u-boot-marvell.git
by Prafulla Wadaskar 10 Jan '13

10 Jan '13

Dear Albert Please kindly pull The following changes since commit ca849aa4b86b282f837c58a0b129460ebfad2239: David MÃ¼ller (ELSOFT AG) (1): ARM: activate DISPLAY_CPUINFO for VCMA9 + SMDK2410 board are available in the git repository at: u-boot-marvell.git master branch. Albert ARIBAUD (5): edminiv2: add hush parser, cmdline editing and long help Rename ehci-kirkwood as ehci-marvell Remove kirkwood-specifics from marvell EHCI driver orion5x: add USB host ehci-marvell support edminiv2: add USB host support Holger Brunck (2): arm/km: speed up i2c access for keymile boards arm/km: checkpatch cleanup Ian Campbell (1): kirkwood_spi: correct access to irq_mask register Michael Walle (1): arm, arm-kirkwood: disable l2c before linux boot Prafulla Wadaskar (1): bugfix: all Marvell specific build fails due to undefined reference to `get_ticks' Stefan (1): kirkwood: add support for D-Link DNS-325 MAINTAINERS | 4 + arch/arm/cpu/arm926ejs/armada100/timer.c | 18 ++ arch/arm/cpu/arm926ejs/cache.c | 9 + arch/arm/cpu/arm926ejs/cpu.c | 2 + arch/arm/cpu/arm926ejs/kirkwood/Makefile | 1 + arch/arm/cpu/arm926ejs/kirkwood/cache.c | 34 ++++ arch/arm/cpu/arm926ejs/kirkwood/timer.c | 18 ++ arch/arm/cpu/arm926ejs/orion5x/timer.c | 18 ++ arch/arm/cpu/arm926ejs/pantheon/timer.c | 18 ++ arch/arm/include/asm/arch-kirkwood/config.h | 2 +- arch/arm/include/asm/arch-kirkwood/kirkwood.h | 12 ++ arch/arm/include/asm/arch-orion5x/orion5x.h | 12 ++ board/d-link/dns325/Makefile | 49 +++++ board/d-link/dns325/dns325.c | 148 ++++++++++++++ board/d-link/dns325/dns325.h | 48 +++++ board/d-link/dns325/kwbimage.cfg | 208 ++++++++++++++++++++ board/keymile/km_arm/km_arm.c | 23 +-- boards.cfg | 1 + drivers/spi/kirkwood_spi.c | 2 +- drivers/usb/host/Makefile | 2 +- .../usb/host/{ehci-kirkwood.c => ehci-marvell.c} | 36 ++-- include/configs/dns325.h | 188 ++++++++++++++++++ include/configs/edminiv2.h | 24 +++ include/configs/km/km_arm.h | 2 +- 24 files changed, 849 insertions(+), 30 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/kirkwood/cache.c create mode 100644 board/d-link/dns325/Makefile create mode 100644 board/d-link/dns325/dns325.c create mode 100644 board/d-link/dns325/dns325.h create mode 100644 board/d-link/dns325/kwbimage.cfg rename drivers/usb/host/{ehci-kirkwood.c => ehci-marvell.c} (73%) create mode 100644 include/configs/dns325.h Regards.. Prafulla . . .

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[U-Boot] Secure update of uboot devices?
by Andreas Bäck 08 Jan '13

08 Jan '13

With the new threats like Stuxnet and Duqu one need to improve on how new updates to software is distrubuted to devcies so one can be sure that it's not a hacked or modified software that runs in the device. We use uboot + usb stick to update the software in our devices. Have anyone been trying out to add e.g cryptated,certificates or rsa keys to uboot?

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[U-Boot] [PATCH] arm: bugfix: Move vector table before jumping relocated code
by Tetsuyuki Kobayashi 26 Dec '12

26 Dec '12

Interrupts and exceptions doesn't work in relocated code. It badly use IRQ_STACK_START_IN in rom area as interrupt stack. It is because the vecotr table is not moved to ram area. This patch moves vector table before jumping relocated code. Signed-off-by: Tetsuyuki Kobayashi <koba(a)kmckk.co.jp> --- arch/arm/cpu/armv7/start.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 52f7f6e..5098f7b 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -277,6 +277,18 @@ jump_2_ram: mcr p15, 0, r0, c7, c10, 4 @ DSB mcr p15, 0, r0, c7, c5, 4 @ ISB #endif +/* + * Move vector table + */ +#if !defined(CONFIG_TEGRA2) +#if !(defined(CONFIG_OMAP44XX) && defined(CONFIG_SPL_BUILD)) + /* Set vector address in CP15 VBAR register */ + ldr r0, =_start + add r0, r0, r9 + mcr p15, 0, r0, c12, c0, 0 @Set VBAR +#endif +#endif /* !Tegra2 */ + ldr r0, _board_init_r_ofs adr r1, _start add lr, r0, r1 -- 1.7.9.5

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[U-Boot] [PATCH 0/5] Various x86 patches
by Graeme Russ 28 Nov '12

28 Nov '12

These have been floating around for a while waiting for 2012.04 The first patch touches on the common makefiles, but it is only examples/standalone/Makefile that really needs to be checked for cross-platform issues Graeme Russ (5): x86: Fix compilation on 64-built built machines x86: Forward declate gd_t x86: Put global data on the stack x86: Remove duplicate PCI init x86: Add ilog2 to bitops Makefile | 1 + arch/x86/cpu/config.mk | 3 +- arch/x86/cpu/cpu.c | 6 --- arch/x86/cpu/start.S | 67 +++++++++++++++++++++++++++++++---- arch/x86/include/asm/bitops.h | 5 +++ arch/x86/include/asm/global_data.h | 5 ++- arch/x86/include/asm/init_helpers.h | 1 - arch/x86/include/asm/processor.h | 1 + arch/x86/lib/board.c | 5 +-- arch/x86/lib/init_helpers.c | 37 +------------------- examples/standalone/Makefile | 2 +- include/configs/eNET.h | 6 --- 12 files changed, 75 insertions(+), 64 deletions(-) -- 1.7.7.6

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