June 2012 - U-Boot

[U-Boot] [PATCH] Kirkwood: Add support for Ka-Ro TK71
by Marek Vasut 04 Jun '12

04 Jun '12

Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Prafulla Wadaskar <prafulla(a)marvell.com> Cc: Wolfgang Denk <wd(a)denx.de> --- board/karo/tk71/Makefile | 45 ++++++++++ board/karo/tk71/kwbimage-256.cfg | 174 ++++++++++++++++++++++++++++++++++++++ board/karo/tk71/kwbimage-512.cfg | 174 ++++++++++++++++++++++++++++++++++++++ board/karo/tk71/tk71.c | 165 ++++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/tk71.h | 128 ++++++++++++++++++++++++++++ 6 files changed, 688 insertions(+) create mode 100644 board/karo/tk71/Makefile create mode 100644 board/karo/tk71/kwbimage-256.cfg create mode 100644 board/karo/tk71/kwbimage-512.cfg create mode 100644 board/karo/tk71/tk71.c create mode 100644 include/configs/tk71.h diff --git a/board/karo/tk71/Makefile b/board/karo/tk71/Makefile new file mode 100644 index 0000000..934e391 --- /dev/null +++ b/board/karo/tk71/Makefile @@ -0,0 +1,45 @@ +# +# Copyright (C) 2012 Marek Vasut <marex(a)denx.de> +# on behalf of DENX Software Engineering GmbH +# +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tk71.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tk71/kwbimage-256.cfg b/board/karo/tk71/kwbimage-256.cfg new file mode 100644 index 0000000..83145e9 --- /dev/null +++ b/board/karo/tk71/kwbimage-256.cfg @@ -0,0 +1,174 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# adopted to TK71 by +# Nils Faerber <nils.faerber(a)kernelconcepts.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000034 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/karo/tk71/kwbimage-512.cfg b/board/karo/tk71/kwbimage-512.cfg new file mode 100644 index 0000000..0166826 --- /dev/null +++ b/board/karo/tk71/kwbimage-512.cfg @@ -0,0 +1,174 @@ +# +# (C) Copyright 2009 +# Marvell Semiconductor <www.marvell.com> +# Written-by: Prafulla Wadaskar <prafulla(a)marvell.com> +# +# adopted to TK71 by +# Nils Faerber <nils.faerber(a)kernelconcepts.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.kwimage for more details about how-to configure +# and create kirkwood boot image +# + +# Boot Media configurations +BOOT_FROM nand +NAND_ECC_MODE default +NAND_PAGE_SIZE 0x0800 + +# SOC registers configuration using bootrom header extension +# Maximum KWBIMAGE_MAX_CONFIG configurations allowed + +# Configure RGMII-0 interface pad voltage to 1.8V +DATA 0xFFD100e0 0x1b1b1b9b + +#Dram initalization for SINGLE x16 CL=5 @ 400MHz +DATA 0xFFD01400 0x43000c30 # DDR Configuration register +# bit13-0: 0xc30 (3120 DDR2 clks refresh rate) +# bit23-14: zero +# bit24: 1= enable exit self refresh mode on DDR access +# bit25: 1 required +# bit29-26: zero +# bit31-30: 01 + +DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +# bit 4: 0=addr/cmd in smame cycle +# bit 5: 0=clk is driven during self refresh, we don't care for APX +# bit 6: 0=use recommended falling edge of clk for addr/cmd +# bit14: 0=input buffer always powered up +# bit18: 1=cpu lock transaction enabled +# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 +# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM +# bit30-28: 3 required +# bit31: 0=no additional STARTBURST delay + +DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) +# bit3-0: TRAS lsbs +# bit7-4: TRCD +# bit11- 8: TRP +# bit15-12: TWR +# bit19-16: TWTR +# bit20: TRAS msb +# bit23-21: 0x0 +# bit27-24: TRRD +# bit31-28: TRTP + +DATA 0xFFD0140C 0x00000034 # DDR Timing (High) +# bit6-0: TRFC +# bit8-7: TR2R +# bit10-9: TR2W +# bit12-11: TW2W +# bit31-13: zero required + +DATA 0xFFD01410 0x00000000 # DDR Address Control +# bit1-0: 01, Cs0width=x16 +# bit3-2: 10, Cs0size=512Mb +# bit5-4: 01, Cs1width=x16 +# bit7-6: 10, Cs1size=512Mb +# bit9-8: 00, Cs2width=nonexistent +# bit11-10: 00, Cs2size =nonexistent +# bit13-12: 00, Cs3width=nonexistent +# bit15-14: 00, Cs3size =nonexistent +# bit16: 0, Cs0AddrSel +# bit17: 0, Cs1AddrSel +# bit18: 0, Cs2AddrSel +# bit19: 0, Cs3AddrSel +# bit31-20: 0 required + +DATA 0xFFD01414 0x00000000 # DDR Open Pages Control +# bit0: 0, OpenPage enabled +# bit31-1: 0 required + +DATA 0xFFD01418 0x00000000 # DDR Operation +# bit3-0: 0x0, DDR cmd +# bit31-4: 0 required + +DATA 0xFFD0141C 0x00000652 # DDR Mode +# bit2-0: 2, BurstLen=2 required +# bit3: 0, BurstType=0 required +# bit6-4: 4, CL=5 +# bit7: 0, TestMode=0 normal +# bit8: 0, DLL reset=0 normal +# bit11-9: 6, auto-precharge write recovery ???????????? +# bit12: 0, PD must be zero +# bit31-13: 0 required + +DATA 0xFFD01420 0x00000042 # DDR Extended Mode +# bit0: 0, DDR DLL enabled +# bit1: 0, DDR drive strenght normal +# bit2: 0, DDR ODT control lsd (disabled) +# bit5-3: 000, required +# bit6: 1, DDR ODT control msb, (disabled) +# bit9-7: 000, required +# bit10: 0, differential DQS enabled +# bit11: 0, required +# bit12: 0, DDR output buffer enabled +# bit31-13: 0 required + +DATA 0xFFD01424 0x0000F17F # DDR Controller Control High +# bit2-0: 111, required +# bit3 : 1 , MBUS Burst Chop disabled +# bit6-4: 111, required +# bit7 : 0 +# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz +# bit9 : 0 , no half clock cycle addition to dataout +# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals +# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh +# bit15-12: 1111 required +# bit31-16: 0 required + +DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values) +DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values) + +DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0 +DATA 0xFFD01504 0x1FFFFFF1 # CS[0]n Size +# bit0: 1, Window enabled +# bit1: 0, Write Protect disabled +# bit3-2: 00, CS0 hit selected +# bit23-4: ones, required +# bit31-24: 0x0F, Size (i.e. 256MB) + +DATA 0xFFD01508 0x00000000 # CS[1]n Base address to 256Mb +DATA 0xFFD0150C 0x00000000 # CS[1]n Size 256Mb Window enabled for CS1 + +DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled +DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled + +DATA 0xFFD01494 0x00110000 # DDR ODT Control (Low) +# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1 +# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0 +# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1. +# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0. +DATA 0xFFD01498 0x00000000 # DDR ODT Control (High) +# bit1-0: 00, ODT0 controlled by ODT Control (low) register above +# bit3-2: 01, ODT1 active NEVER! +# bit31-4: zero, required + +DATA 0xFFD0149C 0x0000F80F # CPU ODT Control +# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3 +# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm +# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm +# bit14: 1, M_STARTBURST_IN ODT: Enabled +# bit15: 1, DDR IO ODT Unit: Use ODT block +DATA 0xFFD01480 0x00000001 # DDR Initialization Control +#bit0=1, enable DDR init upon this register write + +# End of Header extension +DATA 0x0 0x0 diff --git a/board/karo/tk71/tk71.c b/board/karo/tk71/tk71.c new file mode 100644 index 0000000..66085c3 --- /dev/null +++ b/board/karo/tk71/tk71.c @@ -0,0 +1,165 @@ +/* + * Copyright (C) 2012 Marek Vasut <marex(a)denx.de> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include <asm/arch/cpu.h> +#include <asm/arch/kirkwood.h> +#include <asm/arch/mpp.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TK71_OE_LOW (~0) +#define TK71_OE_HIGH (~0) +#define TK71_OE_VAL_LOW (0) +#define TK71_OE_VAL_HIGH (0) + +int board_early_init_f(void) +{ + /* + * default gpio configuration + * There are maximum 64 gpios controlled through 2 sets of registers + * the below configuration configures mainly initial LED status + */ + kw_config_gpio(TK71_OE_VAL_LOW, + TK71_OE_VAL_HIGH, + TK71_OE_LOW, TK71_OE_HIGH); + + /* Multi-Purpose Pins Functionality configuration */ + u32 kwmpp_config[] = { + MPP0_NF_IO2, + MPP1_NF_IO3, + MPP2_NF_IO4, + MPP3_NF_IO5, + MPP4_NF_IO6, + MPP5_NF_IO7, + MPP6_SYSRST_OUTn, + MPP7_GPO, + MPP8_TW_SDA, + MPP9_TW_SCK, + MPP10_UART0_TXD, + MPP11_UART0_RXD, + MPP12_SD_CLK, + MPP13_SD_CMD, + MPP14_SD_D0, + MPP15_SD_D1, + MPP16_SD_D2, + MPP17_SD_D3, + MPP18_NF_IO0, + MPP19_NF_IO1, + MPP20_GE1_0, + MPP21_GE1_1, + MPP22_GE1_2, + MPP23_GE1_3, + MPP24_GE1_4, + MPP25_GE1_5, + MPP26_GE1_6, + MPP27_GE1_7, + MPP28_GPIO, + MPP29_GPIO, + MPP30_GE1_10, + MPP31_GE1_11, + MPP32_GE1_12, + MPP33_GE1_13, + MPP34_GPIO, + MPP35_GPIO, + MPP36_GPIO, + MPP37_GPIO, + MPP38_GPIO, + MPP39_GPIO, + MPP40_GPIO, + MPP41_GPIO, + MPP42_GPIO, + MPP43_GPIO, + MPP44_GPIO, + MPP45_GPIO, + MPP46_GPIO, + MPP47_GPIO, + MPP48_GPIO, + MPP49_GPIO, + 0 + }; + kirkwood_mpp_conf(kwmpp_config); + + return 0; +} + +int board_init(void) +{ + /* + * arch number of board + */ + gd->bd->bi_arch_number = CONFIG_MACH_TYPE; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_NET + +#define MV88E1116_MAC_CTRL2_REG 21 +#define MV88E1116_PGADR_REG 22 +#define MV88E1116_RGMII_TXTM_CTRL (1 << 4) +#define MV88E1116_RGMII_RXTM_CTRL (1 << 5) + +static void mv_phy_88e1118_init(char *name) +{ + u16 reg; + u16 devadr; + + if (miiphy_set_current_dev(name)) + return; + + /* command to read PHY dev address */ + if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) { + printf("Err..%s could not read PHY dev address\n", + __func__); + return; + } + + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 4.7.2 of chip datasheet + */ + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2); + miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg); + reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL); + miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg); + miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0); + + /* reset the phy */ + miiphy_reset(name, devadr); + + printf("88E1118 Initialized on %s\n", name); +} + +/* Configure and enable Switch and PHY */ +void reset_phy(void) +{ + /* configure and initialize PHY */ + mv_phy_88e1118_init("egiga0"); + +} +#endif diff --git a/boards.cfg b/boards.cfg index 5f328b5..1f6f726 100644 --- a/boards.cfg +++ b/boards.cfg @@ -154,6 +154,8 @@ openrd_ultimate arm arm926ejs openrd Marvell rd6281a arm arm926ejs - Marvell kirkwood sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood +tk71_256mb arm arm926ejs tk71 karo kirkwood tk71:RAM_SIZE=256 +tk71_512mb arm arm926ejs tk71 karo kirkwood tk71:RAM_SIZE=512 jadecpu arm arm926ejs jadecpu syteco mb86r0x mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg tx25 arm arm926ejs tx25 karo mx25 diff --git a/include/configs/tk71.h b/include/configs/tk71.h new file mode 100644 index 0000000..0207803 --- /dev/null +++ b/include/configs/tk71.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2012 Marek Vasut <marex(a)denx.de> + * on behalf of DENX Software Engineering GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __CONFIG_TK71_H__ +#define __CONFIG_TK71_H__ + +/* + * Version number information + */ +#define CONFIG_IDENT_STRING "\nKa-Ro TK71" + +/* + * High Level Configuration Options (easy to change) + */ +#define CONFIG_FEROCEON_88FR131 1 /* CPU Core subversion */ +#define CONFIG_KIRKWOOD 1 /* SOC Family Name */ +#define CONFIG_KW88F6281 1 /* SOC Name */ +#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ +#define CONFIG_NR_DRAM_BANKS 1 + +#define MACH_TYPE_TK71 2399 +#define CONFIG_MACH_TYPE MACH_TYPE_TK71 + +#define CONFIG_SYS_KWD_CONFIG \ + $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage-$(CONFIG_RAM_SIZE).cfg + +/* + * Commands configuration + */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT + +#include <config_cmd_default.h> +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ENV +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB + +/* + * mv-common.h should be defined after CMD configs since it used them + * to enable certain macros + */ +#include "mv-common.h" + +/* + * NAND flash + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define CONFIG_JFFS2_NAND +#define CONFIG_JFFS2_DEV "nand0,3" +#endif + +/* + * Ethernet Driver configuration + */ +#ifdef CONFIG_CMD_NET +#define CONFIG_MVGBE_PORTS {1, 0} +#define CONFIG_PHY_BASE_ADR 0x08 +#endif + +/* + * USB/EHCI + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_KIRKWOOD +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#endif + +/* + * Environment variables configurations + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_SECT_SIZE 0x20000 +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_ENV_SIZE 0x20000 +#define CONFIG_ENV_ADDR 0x80000 +#define CONFIG_ENV_OFFSET 0x80000 + +/* + * Default environment variables + */ +#define CONFIG_BOOTCOMMAND "nand read 0x800000 kernel 0x300000; bootm;" +#define CONFIG_MTDPARTS "512K(u-boot),512K(u-boot-env),3M(kernel),-(root)" +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_uboot=dhcp u-boot.kwb; nand erase.part u-boot; nand write ${fileaddr} u-boot ${filesize}\0" \ + "update_kernel=dhcp uImage-tk71; nand erase.part kernel; nand write ${fileaddr} kernel ${filesize} \0" \ + "update_rootfs=dhcp rootfs-tk71; nand erase.part root; nand write ${fileaddr} root ${filesize}\0" \ + "update_all=run update_uboot; run update_kernel; run update_rootfs; reset\0" \ + "mtdids=nand0=orion_nand\0" \ + "mtdparts=mtdparts=orion_nand:"CONFIG_MTDPARTS"\0" \ + "bootargs=console=ttyS0,115200 mtdparts=orion_nand:"CONFIG_MTDPARTS" rootfstype=jffs2 root=/dev/mtdblock3 rw\0" +#define MTDIDS_DEFAULT "nand0=orion_nand" +#define MTDPARTS_DEFAULT "mtdparts=orion_nand:"CONFIG_MTDPARTS + +#endif /* __CONFIG_TK71_H__ */ -- 1.7.10

4 6

[U-Boot] crashed u+boot with MV88F6560
by Dawid Partyka - Safe-lock.net 04 Jun '12

04 Jun '12

hello. I deleted the u-boot witch MV88F6560. The board is ZTE-88F6560-FXXX this is modem of epon (ftth). I have the copy of the rom with mtdblock0 (~10MB). If I look with hex editor when I see information witch first 512KB is u-boot room. If I connect with rs232 (added max232) and checked bootrom dipswitch for ths board I have information: BootROM 1.34 If I send the backup rom with mtdblock0 (xmodem with hyperterminal) then hyperterminal send me information checksum error. I find with internet u-boot.bin then I send with hyperterminal then hyperterminal send witch board first 1024block (uboot have 1670block :( ). This not work. Log with good board connected with hyperterminal: BootROM 1.34 Booting from NAND flash BootROM: Image checksum verification PASSED U-Boot 2009.08 (Sep 20 2011 - 17:28:41) CPU: Feroceon (Rev 1) @ 1200Mhz - LE, L2 @ 400Mhz DDR3 @ 400Mhz, TClock @ 200Mhz, P/V ID=7/15 DRAM: 128 MB CS 0: base 0x00000000 size 128 MB Addresses 26M - 0M are saved for the U-Boot usage. NAND: 1bit HM ECC, Size: 32 MiB Modules Detected: GPON module detected. TDM module. Ethernet Switch on MAC0. 3xFE PHY Module. GE-PHY on Switch port #0. Net: egiga0 [PRIME], egiga1 Hit 1 to upgrade softwate version Hit enter to stop autoboot: 0 select=0x0 NAND read: device 0 offset 0x1980000, size 0x100 256 bytes read: OK select=0x0 search=0x2 NAND read: device 0 offset 0x80000, size 0x937110 9662736 bytes read: OK NAND read: device 0 offset 0x30000, size 0x30000 196608 bytes read: OK ## Booting kernel from Legacy Image at 02000100 ... Image Name: Linux Kernel Image Image Type: ARM Linux Kernel Image (lzma compressed) Data Size: 9662403 Bytes = 9.2 MB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK Uncompressing (lzma) Kernel Image ... OK ---------------------- |-->setup start tag... ---------------------- |-->setup memory tag... ---------------------- |-->setup cmdline tag... ---------------------- |-->setup marvell tag... ---------------------- |-->setup versioninfo tag... ---------------------- |-->setup end tag... ---------------------- Starting kernel ... Linux version 2.6.21.5 (wangkai(a)localhost.localdomain) (gcc version 4.3.4 (Build root 2010.05) ) #44 Tue Sep 20 17:53:59 CST 2011 CPU: ARM926EJ-S [56251311] revision 1 (ARMv5TE), cr=00053977 Machine: Feroceon-KW2 Using UBoot passing parameters structure Memory policy: ECC disabled, Data cache writeback <7>On node 0 totalpages: 32512 <7> Normal zone: 0 pages used for memmap CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets CPU0: D cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets Built 1 zonelists. Total pages: 32258 Kernel command line: console=ttyS0,115200 root=/dev/ram0 rw load_ramdisk=1 rdini t=/sbin/init mv_net_config=0 mem=127M PID hash table entries: 512 (order: 9, 2048 bytes) Console: colour dummy device 80x30 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 127MB = 127MB total Memory: 116352KB available (3536K code, 714K data, 8168K init) Mount-cache hash table entries: 512 <6>CPU: Testing write buffer coherency: ok pdt_cspkernel_init NET: Registered protocol family 16 CPU Interface ------------- SDRAM_CS0 ....base 00000000, size 128MB SDRAM_CS1 ....no such SDRAM_CS2 ....no such SDRAM_CS3 ....no such DEVICE_CS0 ....no such DEVICE_CS1 ....no such DEVICE_CS2 ....no such DEVICE_CS3 ....no such PEX0_MEM ....base f3000000, size 16MB PEX0_IO ....base f2000000, size 1MB PEX1_MEM ....base f4000000, size 16MB PEX1_IO ....base f2100000, size 1MB INTER_REGS ....base f1000000, size 1MB NAND_NOR_CS ....base f8000000, size 2MB SPI_CS0 ....base f0000000, size 16MB SPI_CS1 ....no such SPI_CS2 ....no such SPI_CS3 ....no such <4>SPI_CS4 ....no such SPI_CS5 ....no such SPI_CS6 ....no such SPI_CS7 ....no such SPI_B_CS0 ....no such BOOT_ROM_CS ....no such <4>DEV_BOOTCS ....no such CRYPT1_ENG ....no such CRYPT2_ENG ....no such PNC_BM ....base f5000000, size 1MB ETH_CTRL ....base f5100000, size 1MB PON_CTRL ....base f5200000, size 1MB NFC_CTRL ....no such Marvell Development Board (LSP Version KW2_LSP_1.0.4_p26_KERNEL_2.6.21.5_NQ)-- ZTE-88F6560-FXXX Soc: MV88F6560 Rev 2 LE Detected Tclk 200000000 and SysClk 400000000 g_pdwWdRsvMemBase is c8000000 g_dwWdRsvMemLen is 40052 magic has been changed! g_pdwWdRegTableBase = c800000c : success register character device for /dev/watchdog Marvell USB EHCI Host controller #0: c0d75600 <4>PEX0 interface detected no Link. PEX1 interface detected Link X4 PCI: bus0: Fast back to back transfers enabled PCI: bus1: Fast back to back transfers disabled SCSI subsystem initialized Time: kw_clocksource clocksource has been installed. NET: Registered protocol family 2 ip_rt_init() start call CSP_alloc_large_system_hash IP route cache hash table entries: 1024 (order: 0, 4096 bytes) ip_rt_init() call CSP_alloc_large_system_hash end TCP established hash table entries: 4096 (order: 2, 16384 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes) TCP: Hash tables configured (established 4096 bind 2048) TCP reno registered RTC has been updated!!! RTC registered cpufreq: Init kirkwood cpufreq driver NTFS driver 2.1.28 [Flags: R/W]. JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. <4>fuse init (API version 7.8) <6>io scheduler noop registered <6>io scheduler anticipatory registered (default) Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A serial8250.1: ttyS1 at MMIO 0xf1012100 (irq = 34) is a 16550A RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize 0 - Base 0x00000000 , Size = 0x08000000. 8 - Base 0xf3000000 , Size = 0x01000000. 9 - Base 0xf2000000 , Size = 0x00100000. 10 - Base 0xf4000000 , Size = 0x01000000. 11 - Base 0xf2100000 , Size = 0x00100000. 12 - Base 0xf1000000 , Size = 0x00100000. 13 - Base 0xf8000000 , Size = 0x00200000. 14 - Base 0xf0000000 , Size = 0x01000000. 27 - Base 0xf5000000 , Size = 0x00100000. 28 - Base 0xf5100000 , Size = 0x00100000. 29 - Base 0xf5200000 , Size = 0x00100000. mvPncVirtBase = 0xc8400000 o 3 Giga ports supported o Giga PON port is #2: - 8 TCONTs supported o NETA acceleration mode 4 o BM supported: short buffer size is 256 bytes o PnC supported o HWF supported o PMT supported o RX Queue support: 8 Queues * 512 Descriptors o TX Queue support: 8 Queues * 3072 Descriptors o Receive checksum offload supported o Transmit checksum offload supported o Driver ERROR statistics enabled o Driver INFO statistics enabled o Driver DEBUG statistics enabled o Proc tool API enabled o Switch support enabled o IGMP special processing support o Loading Switch QuarterDeck driver o Internal GE PHY Connected to Switch Port 0 Detected o Setting Switch CPU port (port #4) for 1000 Full with FC o Disable disconnected switch port (port #5) and force link down o Disable disconnected switch port (port #6) and force link down o Loading network interface(s) o Port 0 is connected to Linux netdevice o Using UBoot netconfig string net_config_str: 0 o Working in External Switch mode giga p=0: mtu=1500, mac=c0d61f72 o mii0, ifindex = 1, GbE port = 0 o Warning: GbE port 1 is not connected to PHY/RGMII/Switch, skipping initializ ation o Port 2 is connected to Linux netdevice pon p=2: mtu=1500, mac=c0d61f72 o mii1, ifindex = 2, GbE port = 2 e100: Intel(R) PRO/100 Network Driver, 3.5.17-k2-NAPI e100: Copyright(c) 1999-2006 Intel Corporation NFTL driver: nftlcore.c $Revision: 1.98 $, nftlmount.c $Revision: 1.41 $ Using Hamming 1-bit ECC for NAND device NAND device: Manufacturer ID: 0x20, Chip ID: 0x75 (ST Micro NAND 32MiB 3,3V 8-bi t) Scanning device for bad blocks Using static partition definition Creating 8 MTD partitions on "nand_mtd": 0x00000000-0x02000000 : "whole flash" 0x00000000-0x00080000 : "u-boot" 0x01a40000-0x01ac0000 : "parameter tags" 0x00080000-0x00d00000 : "kernel0" 0x01c00000-0x02000000 : "middleware" 0x01ac0000-0x01c00000 : "usercfg" 0x00d00000-0x01980000 : "kernel1" 0x01980000-0x01a40000 : "others" mice: PS/2 mouse device common for all mice Linux telephony interface: v1.00 Loading Marvell vpapi device Sorry for me english :( I'm in poland. Thansk for you help.

1 0

[U-Boot] crashed u-boot with MV88F6560
by Dawid Partyka - Safe-lock.net 04 Jun '12

04 Jun '12

hello. I deleted the u-boot witch MV88F6560. The board is ZTE-88F6560-FXXX this is modem of epon (ftth). I have the copy of the rom with mtdblock0 (~10MB). If I look with hex editor when I see information witch first 512KB is u-boot room. If I connect with rs232 (added max232) and checked bootrom dipswitch for ths board I have information: BootROM 1.34 If I send the backup rom with mtdblock0 (xmodem with hyperterminal) then hyperterminal send me information checksum error. I find with internet u-boot.bin then I send with hyperterminal then hyperterminal send witch board first 1024block (uboot have 1670block :( ). This not work. Log with good board connected with hyperterminal: BootROM 1.34 Booting from NAND flash BootROM: Image checksum verification PASSED U-Boot 2009.08 (Sep 20 2011 - 17:28:41) CPU: Feroceon (Rev 1) @ 1200Mhz - LE, L2 @ 400Mhz DDR3 @ 400Mhz, TClock @ 200Mhz, P/V ID=7/15 DRAM: 128 MB CS 0: base 0x00000000 size 128 MB Addresses 26M - 0M are saved for the U-Boot usage. NAND: 1bit HM ECC, Size: 32 MiB Modules Detected: GPON module detected. TDM module. Ethernet Switch on MAC0. 3xFE PHY Module. GE-PHY on Switch port #0. Net: egiga0 [PRIME], egiga1 Hit 1 to upgrade softwate version Hit enter to stop autoboot: 0 select=0x0 NAND read: device 0 offset 0x1980000, size 0x100 256 bytes read: OK select=0x0 search=0x2 NAND read: device 0 offset 0x80000, size 0x937110 9662736 bytes read: OK NAND read: device 0 offset 0x30000, size 0x30000 196608 bytes read: OK ## Booting kernel from Legacy Image at 02000100 ... Image Name: Linux Kernel Image Image Type: ARM Linux Kernel Image (lzma compressed) Data Size: 9662403 Bytes = 9.2 MB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK Uncompressing (lzma) Kernel Image ... OK ---------------------- |-->setup start tag... ---------------------- |-->setup memory tag... ---------------------- |-->setup cmdline tag... ---------------------- |-->setup marvell tag... ---------------------- |-->setup versioninfo tag... ---------------------- |-->setup end tag... ---------------------- Starting kernel ... Linux version 2.6.21.5 (wangkai(a)localhost.localdomain) (gcc version 4.3.4 (Build root 2010.05) ) #44 Tue Sep 20 17:53:59 CST 2011 CPU: ARM926EJ-S [56251311] revision 1 (ARMv5TE), cr=00053977 Machine: Feroceon-KW2 Using UBoot passing parameters structure Memory policy: ECC disabled, Data cache writeback <7>On node 0 totalpages: 32512 <7> Normal zone: 0 pages used for memmap CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets CPU0: D cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets Built 1 zonelists. Total pages: 32258 Kernel command line: console=ttyS0,115200 root=/dev/ram0 rw load_ramdisk=1 rdini t=/sbin/init mv_net_config=0 mem=127M PID hash table entries: 512 (order: 9, 2048 bytes) Console: colour dummy device 80x30 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 127MB = 127MB total Memory: 116352KB available (3536K code, 714K data, 8168K init) Mount-cache hash table entries: 512 <6>CPU: Testing write buffer coherency: ok pdt_cspkernel_init NET: Registered protocol family 16 CPU Interface ------------- SDRAM_CS0 ....base 00000000, size 128MB SDRAM_CS1 ....no such SDRAM_CS2 ....no such SDRAM_CS3 ....no such DEVICE_CS0 ....no such DEVICE_CS1 ....no such DEVICE_CS2 ....no such DEVICE_CS3 ....no such PEX0_MEM ....base f3000000, size 16MB PEX0_IO ....base f2000000, size 1MB PEX1_MEM ....base f4000000, size 16MB PEX1_IO ....base f2100000, size 1MB INTER_REGS ....base f1000000, size 1MB NAND_NOR_CS ....base f8000000, size 2MB SPI_CS0 ....base f0000000, size 16MB SPI_CS1 ....no such SPI_CS2 ....no such SPI_CS3 ....no such <4>SPI_CS4 ....no such SPI_CS5 ....no such SPI_CS6 ....no such SPI_CS7 ....no such SPI_B_CS0 ....no such BOOT_ROM_CS ....no such <4>DEV_BOOTCS ....no such CRYPT1_ENG ....no such CRYPT2_ENG ....no such PNC_BM ....base f5000000, size 1MB ETH_CTRL ....base f5100000, size 1MB PON_CTRL ....base f5200000, size 1MB NFC_CTRL ....no such Marvell Development Board (LSP Version KW2_LSP_1.0.4_p26_KERNEL_2.6.21.5_NQ)-- ZTE-88F6560-FXXX Soc: MV88F6560 Rev 2 LE Detected Tclk 200000000 and SysClk 400000000 g_pdwWdRsvMemBase is c8000000 g_dwWdRsvMemLen is 40052 magic has been changed! g_pdwWdRegTableBase = c800000c : success register character device for /dev/watchdog Marvell USB EHCI Host controller #0: c0d75600 <4>PEX0 interface detected no Link. PEX1 interface detected Link X4 PCI: bus0: Fast back to back transfers enabled PCI: bus1: Fast back to back transfers disabled SCSI subsystem initialized Time: kw_clocksource clocksource has been installed. NET: Registered protocol family 2 ip_rt_init() start call CSP_alloc_large_system_hash IP route cache hash table entries: 1024 (order: 0, 4096 bytes) ip_rt_init() call CSP_alloc_large_system_hash end TCP established hash table entries: 4096 (order: 2, 16384 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes) TCP: Hash tables configured (established 4096 bind 2048) TCP reno registered RTC has been updated!!! RTC registered cpufreq: Init kirkwood cpufreq driver NTFS driver 2.1.28 [Flags: R/W]. JFFS2 version 2.2. (NAND) (C) 2001-2006 Red Hat, Inc. <4>fuse init (API version 7.8) <6>io scheduler noop registered <6>io scheduler anticipatory registered (default) Serial: 8250/16550 driver $Revision: 1.90 $ 4 ports, IRQ sharing disabled serial8250.0: ttyS0 at MMIO 0xf1012000 (irq = 33) is a 16550A serial8250.1: ttyS1 at MMIO 0xf1012100 (irq = 34) is a 16550A RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize 0 - Base 0x00000000 , Size = 0x08000000. 8 - Base 0xf3000000 , Size = 0x01000000. 9 - Base 0xf2000000 , Size = 0x00100000. 10 - Base 0xf4000000 , Size = 0x01000000. 11 - Base 0xf2100000 , Size = 0x00100000. 12 - Base 0xf1000000 , Size = 0x00100000. 13 - Base 0xf8000000 , Size = 0x00200000. 14 - Base 0xf0000000 , Size = 0x01000000. 27 - Base 0xf5000000 , Size = 0x00100000. 28 - Base 0xf5100000 , Size = 0x00100000. 29 - Base 0xf5200000 , Size = 0x00100000. mvPncVirtBase = 0xc8400000 o 3 Giga ports supported o Giga PON port is #2: - 8 TCONTs supported o NETA acceleration mode 4 o BM supported: short buffer size is 256 bytes o PnC supported o HWF supported o PMT supported o RX Queue support: 8 Queues * 512 Descriptors o TX Queue support: 8 Queues * 3072 Descriptors o Receive checksum offload supported o Transmit checksum offload supported o Driver ERROR statistics enabled o Driver INFO statistics enabled o Driver DEBUG statistics enabled o Proc tool API enabled o Switch support enabled o IGMP special processing support o Loading Switch QuarterDeck driver o Internal GE PHY Connected to Switch Port 0 Detected o Setting Switch CPU port (port #4) for 1000 Full with FC o Disable disconnected switch port (port #5) and force link down o Disable disconnected switch port (port #6) and force link down o Loading network interface(s) o Port 0 is connected to Linux netdevice o Using UBoot netconfig string net_config_str: 0 o Working in External Switch mode giga p=0: mtu=1500, mac=c0d61f72 o mii0, ifindex = 1, GbE port = 0 o Warning: GbE port 1 is not connected to PHY/RGMII/Switch, skipping initializ ation o Port 2 is connected to Linux netdevice pon p=2: mtu=1500, mac=c0d61f72 o mii1, ifindex = 2, GbE port = 2 e100: Intel(R) PRO/100 Network Driver, 3.5.17-k2-NAPI e100: Copyright(c) 1999-2006 Intel Corporation NFTL driver: nftlcore.c $Revision: 1.98 $, nftlmount.c $Revision: 1.41 $ Using Hamming 1-bit ECC for NAND device NAND device: Manufacturer ID: 0x20, Chip ID: 0x75 (ST Micro NAND 32MiB 3,3V 8-bi t) Scanning device for bad blocks Using static partition definition Creating 8 MTD partitions on "nand_mtd": 0x00000000-0x02000000 : "whole flash" 0x00000000-0x00080000 : "u-boot" 0x01a40000-0x01ac0000 : "parameter tags" 0x00080000-0x00d00000 : "kernel0" 0x01c00000-0x02000000 : "middleware" 0x01ac0000-0x01c00000 : "usercfg" 0x00d00000-0x01980000 : "kernel1" 0x01980000-0x01a40000 : "others" mice: PS/2 mouse device common for all mice Linux telephony interface: v1.00 Loading Marvell vpapi device Sorry for me english :( I'm in poland. Thansk for you help.

1 0

[U-Boot] Detecting board revision that needs to be done after relocation
by Fabio Estevam 04 Jun '12

04 Jun '12

Hi, I need to provide a get_board_rev() function that depends on I2C probe of a PMIC to decide between the board revision. I2C is only available after relocation, so what is the correct way to "delay" get_board_rev, so that it gets called only at a time when I2C is ready? Thanks, Fabio Estevam

4 4

[U-Boot] [PATCH 1/2] avr32:grasshopper: fix PHY initialisation
by Andreas Bießmann 04 Jun '12

04 Jun '12

Signed-off-by: Andreas Bießmann <andreas.devel(a)googlemail.com> --- board/in-circuit/grasshopper/grasshopper.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c index 475a759..222fe43 100644 --- a/board/in-circuit/grasshopper/grasshopper.c +++ b/board/in-circuit/grasshopper/grasshopper.c @@ -72,6 +72,13 @@ int board_early_init_f(void) portmux_enable_usart0(PORTMUX_DRIVE_MIN); portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) + /* set PHY reset and pwrdown to low */ + portmux_select_gpio(PORTMUX_PORT_B, (1 << 29) | (1 << 30), + PORTMUX_DIR_OUTPUT | PORTMUX_INIT_LOW); + udelay(100); + /* release PHYs reset */ + gpio_set_value(GPIO_PIN_PB(29), 1); + portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); #endif -- 1.7.10

1 2

[U-Boot] [PATCH 2/2] P4080/PBL: add tool to support pbl image build.
by Shaohui Xie 04 Jun '12

04 Jun '12

The tool can build u-boot image which can be used by PBL, run "make P4080DS_RAMBOOT_PBL" can make all works done, the default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie <b21989(a)freescale.com> --- Makefile | 5 + board/freescale/corenet_ds/config.mk | 26 +++ board/freescale/corenet_ds/pblimage.cfg | 59 ++++++ common/image.c | 1 + doc/README.pblimage | 83 ++++++++ include/image.h | 1 + tools/Makefile | 2 + tools/mkimage.c | 5 + tools/mkimage.h | 2 + tools/pblimage.c | 329 +++++++++++++++++++++++++++++++ tools/pblimage.h | 36 ++++ 11 files changed, 549 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/config.mk create mode 100644 board/freescale/corenet_ds/pblimage.cfg create mode 100644 doc/README.pblimage create mode 100644 tools/pblimage.c create mode 100644 tools/pblimage.h diff --git a/Makefile b/Makefile index dc2e3d8..ca6078e 100644 --- a/Makefile +++ b/Makefile @@ -361,6 +361,10 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +$(obj)u-boot.pbl: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(PBL_CONFIG) -T pblimage \ + -d $< $@ + $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin @@ -1156,6 +1160,7 @@ clobber: clean $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk new file mode 100644 index 0000000..c94938f --- /dev/null +++ b/board/freescale/corenet_ds/config.mk @@ -0,0 +1,26 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +ifeq ($(CONFIG_RAMBOOT_PBL), y) +PBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/pblimage.cfg +ALL += $(obj)u-boot.pbl +endif diff --git a/board/freescale/corenet_ds/pblimage.cfg b/board/freescale/corenet_ds/pblimage.cfg new file mode 100644 index 0000000..96c55ee --- /dev/null +++ b/board/freescale/corenet_ds/pblimage.cfg @@ -0,0 +1,59 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# Written-by: Shaohui Xie<b21989(a)freescale.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +4c580000 00000000 18185218 0000cccc +40464000 3c3c2000 58000000 61000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/common/image.c b/common/image.c index f63a2ff..76e493d 100644 --- a/common/image.c +++ b/common/image.c @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, + { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { -1, "", "", }, }; diff --git a/doc/README.pblimage b/doc/README.pblimage new file mode 100644 index 0000000..e7ebea0 --- /dev/null +++ b/doc/README.pblimage @@ -0,0 +1,83 @@ +------------------------------------------------------------------ +Freescale PBL(pre-boot loader) Boot Image generation using mkimage +------------------------------------------------------------------ + +This document describes the U-Boot feature as it +is implemented for the Freescale P4080. + +The P4080 SoC's can boot directly from eSPI FLASH. + +for more details refer section 5 Pre-boot loader specifications. + +Building PBL boot image and boot steps +-------------------------------------- + +1. To build the PBL boot image for P4080DS: + make P4080DS_RAMBOOT_PBL + The default image is u-boot.pbl. + +2. Command below provided a way to re-build the PBL boot image if the +configuration file needes to be modified while the u-boot.bin does not +need to be re-build. + +Command syntax: +-------------- +./tools/mkimage -n <board specific configuration file> \ + -T pblimage -d <input_raw_binary> <output_pblboot_file> + +for ex. +./tools/mkimage -n ./board/freescale/corenet_ds/pblimage.cfg \ + -T pblimage -d u-boot.bin u-boot.pbl + + +3. pblimage support available with mkimage utility will generate Freescale PBL +boot image that can be flashed on the board eSPI flash. After flashed the +image u-boot.pbl, Change SW1[2] = off, then power on, board will boot from +eSPI flash. + +Board specific configuration file specifications: +------------------------------------------------ +1. This file must present in the $(BOARDDIR) and the name should be + pblimage.cfg (since this is used in Makefile) +2. This file can have empty lines and lines starting with "#" as first + character to put comments + +Typical example of pblimage.cfg file: +----------------------------------- + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +4c580000 00000000 18185218 0000cccc +40464000 3c3c2000 58000000 61000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 + +------------------------------------------------ +Author: Shaohui Xie<b21989(a)freescale.com> diff --git a/include/image.h b/include/image.h index 005e0d2..56b849e 100644 --- a/include/image.h +++ b/include/image.h @@ -157,6 +157,7 @@ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ #define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ #define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ +#define IH_TYPE_PBLIMAGE 11 /* Freescale PBLBoot Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 623f908..c068bc0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -83,6 +83,7 @@ OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o NOPED_OBJ_FILES-y += kwbimage.o +NOPED_OBJ_FILES-y += pblimage.o NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o @@ -181,6 +182,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)image.o \ $(obj)imximage.o \ $(obj)kwbimage.o \ + $(obj)pblimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ $(obj)os_support.o \ diff --git a/tools/mkimage.c b/tools/mkimage.c index f5859d7..a3e793a 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -149,6 +149,8 @@ main (int argc, char **argv) int retval = 0; struct image_type_params *tparams = NULL; + /* Init Freescale PBL Boot image generation/list support */ + init_pbl_image_type(); /* Init Kirkwood Boot image generation/list support */ init_kwb_image_type (); /* Init Freescale imx Boot image generation/list support */ @@ -421,6 +423,9 @@ NXTARG: ; break; } } + } else if (params.type == IH_TYPE_PBLIMAGE) { + /* the copy_file need to be re-write for PBL. */ + pbl_load_uboot(ifd, &params); } else { copy_file (ifd, params.datafile, 0); } diff --git a/tools/mkimage.h b/tools/mkimage.h index 9033a7d..597dcaf 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -139,6 +139,8 @@ void mkimage_register (struct image_type_params *tparams); * * Supported image types init functions */ +void pbl_load_uboot(int, struct mkimage_params *); +void init_pbl_image_type(void); void init_kwb_image_type (void); void init_imx_image_type (void); void init_default_image_type (void); diff --git a/tools/pblimage.c b/tools/pblimage.c new file mode 100644 index 0000000..d0c29a6 --- /dev/null +++ b/tools/pblimage.c @@ -0,0 +1,329 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "pblimage.h" + +/* + * PBL can load 64 bytes each time in MAX, so the u-boot need to be splited into + * pieces of 64 bytes, PBL needs a command for each piece, the command looks + * like 81xxxxxx, the "xxxxxx" is offset, it starts from F80000 in our case. + */ +static unsigned int uboot_label = 0x81F80000; +/* + * need to store all bytes in memory for calculating crc32, then write the + * bytes to image file for PBL boot. + */ +static unsigned char mem_buf[600000]; +static unsigned char *pmem_buf = mem_buf; +static int mem_byte_cnt; +static char *fname = "Unknown"; +static int lineno = -1; +static struct pbl_header pblimage_header; + +static union +{ + char c[4]; + unsigned char l; +} endian_test = { {'l', '?', '?', 'b'} }; + +#define ENDIANNESS ((char)endian_test.l) + +static void generate_pbl_cmd(void) +{ + unsigned int val = uboot_label; + uboot_label += 0x40; + int i; + + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (val >> (i * 8)) & 0xff; + mem_byte_cnt++; + } +} + +static void pbl_fget(size_t size, FILE *stream) +{ + unsigned char c; + while (size) { + c = (unsigned char)fgetc(stream); + *pmem_buf++ = c; + mem_byte_cnt++; + size--; + } +} + +/* load splited u-boot with PBI command 81xxxxxx. */ +static void load_uboot(FILE *fp_uboot) +{ + while (uboot_label < 0x82000000) { + generate_pbl_cmd(); + pbl_fget(64, fp_uboot); + } +} + +static void check_get_hexval(char *token) +{ + uint32_t hexval; + int i; + + if (!sscanf(token, "%x", &hexval)) { + printf("Error:%s[%d] - Invalid hex data(%s)\n", fname, + lineno, token); + exit(EXIT_FAILURE); + } + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (hexval >> (i * 8)) & 0xff; + mem_byte_cnt++; + } +} + +static void pbl_parser(char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + size_t len = 0; + + fname = name; + fd = fopen(name, "r"); + if (fd == NULL) { + printf("Error:%s - Can't open\n", fname); + exit(EXIT_FAILURE); + } + + while ((getline(&line, &len, fd)) > 0) { + lineno++; + token = strtok_r(line, "\r\n", &saveptr1); + /* drop all lines with zero tokens (= empty lines) */ + if (token == NULL) + continue; + for (line = token;; line = NULL) { + token = strtok_r(line, " \t", &saveptr2); + if (token == NULL) + break; + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + check_get_hexval(token); + } + } + if (line) + free(line); + fclose(fd); +} + +static uint32_t crc_table[256]; + +static void make_crc_table(void) +{ + uint32_t mask; + int i, j; + uint32_t poly; /* polynomial exclusive-or pattern */ + + /* + * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + * + x11 + x12 + x16 + x22 + x23 + x26 + x32. + */ + poly = 0x04c11db7; + + for (i = 0; i < 256; i++) { + mask = i << 24; + for (j = 0; j < 8; j++) { + if (mask & 0x80000000) + mask = (mask << 1) ^ poly; + else + mask <<= 1; + } + crc_table[i] = mask; + } +} + +unsigned long pbl_crc32(unsigned long crc, const char *buf, unsigned int len) +{ + unsigned int crc32_val = 0xffffffff; + unsigned int xor = 0x0; + int i; + + make_crc_table(); + + for (i = 0; i < len; i++) + crc32_val = (crc32_val << 8) ^ + crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)]; + + crc32_val = crc32_val ^ xor; + if (crc32_val < 0) { + crc32_val += 0xffffffff; + crc32_val += 1; + } + return crc32_val; +} + +static unsigned int reverse_byte(unsigned int val) +{ + unsigned int temp; + unsigned char *p1; + int j; + + temp = val; + p1 = (unsigned char *)&temp; + for (j = 3; j >= 0; j--) + *p1++ = (val >> (j * 8)) & 0xff; + return temp; +} + +/* write end command and crc command to memory. */ +static void add_end_cmd(void) +{ + unsigned int pbl_end_cmd[4] = {0x09138000, 0x00000000, + 0x091380c0, 0x00000000}; + unsigned int crc32_pbl; + int i; + unsigned char *p = (unsigned char *)&pbl_end_cmd; + + if (ENDIANNESS == 'l') { + for (i = 0; i < 4; i++) + pbl_end_cmd[i] = reverse_byte(pbl_end_cmd[i]); + } + + for (i = 0; i < 16; i++) { + *pmem_buf++ = *p++; + mem_byte_cnt++; + } + + /* Add PBI CRC command. */ + *pmem_buf++ = 0x08; + *pmem_buf++ = 0x13; + *pmem_buf++ = 0x80; + *pmem_buf++ = 0x40; + mem_byte_cnt += 4; + + /* calculated CRC32 and write it to memory. */ + crc32_pbl = pbl_crc32(0, (const char *)mem_buf, mem_byte_cnt); + *pmem_buf++ = (crc32_pbl >> 24) & 0xff; + *pmem_buf++ = (crc32_pbl >> 16) & 0xff; + *pmem_buf++ = (crc32_pbl >> 8) & 0xff; + *pmem_buf++ = (crc32_pbl) & 0xff; + mem_byte_cnt += 4; + + if (((mem_byte_cnt) % 16) != 0) { + for (i = 0; i < 8; i++) { + *pmem_buf++ = 0x0; + mem_byte_cnt++; + } + } + if ((mem_byte_cnt % 16 != 0)) { + printf("Error: Bad size of image file\n"); + exit(EXIT_FAILURE); + } + +} + +void pbl_load_uboot(int ifd, struct mkimage_params *params) +{ + FILE *fp_uboot; + int size; + + /* parse the pblimage.cfg file. */ + pbl_parser(params->imagename); + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + + load_uboot(fp_uboot); + add_end_cmd(); + fclose(fp_uboot); + lseek(ifd, 0, SEEK_SET); + + size = mem_byte_cnt; + if (write(ifd, (const void *)&mem_buf, size) != size) { + fprintf(stderr, "Write error on %s: %s\n", + params->imagefile, strerror(errno)); + exit(EXIT_FAILURE); + } +} + +static int pblimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_PBLIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int pblimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + + struct pbl_header *pbl_hdr = (struct pbl_header *) ptr; + + /* Only a few checks can be done: search for magic numbers */ + if (ENDIANNESS == 'l') { + if (pbl_hdr->preamble != reverse_byte(RCW_PREAMBLE)) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != reverse_byte(RCW_HEADER)) + return -FDT_ERR_BADSTRUCTURE; + } else { + if (pbl_hdr->preamble != RCW_PREAMBLE) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != RCW_HEADER) + return -FDT_ERR_BADSTRUCTURE; + } + + return 0; +} + +static void pblimage_print_header(const void *ptr) +{ + printf("Image Type: Freescale pbl Boot Image\n"); +} + +static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + /*nothing need to do, pbl_load_uboot takes care of whole file. */ +} + +/* + * pblimage parameters + */ +static struct image_type_params pblimage_params = { + .name = "Freescale PBL Boot Image support", + .header_size = sizeof(struct pbl_header), + .hdr = (void *)&pblimage_header, + .check_image_type = pblimage_check_image_types, + .verify_header = pblimage_verify_header, + .print_header = pblimage_print_header, + .set_header = pblimage_set_header, +}; + +void init_pbl_image_type(void) +{ + mem_byte_cnt = 0; + mkimage_register(&pblimage_params); +} diff --git a/tools/pblimage.h b/tools/pblimage.h new file mode 100644 index 0000000..887d4c9 --- /dev/null +++ b/tools/pblimage.h @@ -0,0 +1,36 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PBLIMAGE_H_ +#define _PBLIMAGE_H_ + +#define RCW_BYTES 64 +#define RCW_PREAMBLE 0xaa55aa55 +#define RCW_HEADER 0x010e0100 + +struct pbl_header { + uint32_t preamble; + uint32_t rcwheader; + uint8_t rcw_data[RCW_BYTES]; +}; + +#endif /* _PBLIMAGE_H_ */ -- 1.6.4

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[U-Boot] Support for drives larger than 2.1TB with U-Boot & Kirkwood
by David Purdy 04 Jun '12

04 Jun '12

Hello, Does anyone in the community here have experience (first-hand, preferably) & knowledge regarding the use of drives larger than 2.1TB? It is my understanding that CONFIG_EFI_PARTITION and CONFIG_SYS_64BIT_LBA both required - but is there anything else that needs to be switched on? Peculiarities when using this, especially related to ARM/Kirkwood, would be great to know about. Thanks, Dave

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[U-Boot] [PATCH v2] mmc: fix wrong timeout check in mmc_send_status()
by Jongman Heo 04 Jun '12

04 Jun '12

(!timeout) condition check in mmc_send_status() can never be met, because do-while loop ends up with negative timeout value, -1. Fix the check to handle TIMEOUT case correctly. Signed-off-by: Jongman Heo <jongman.heo(a)gmail.com> --- drivers/mmc/mmc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..d3cca6c 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -238,7 +238,7 @@ int mmc_send_status(struct mmc *mmc, int timeout) status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; printf("CURR STATE:%d\n", status); #endif - if (!timeout) { + if (timeout <= 0) { printf("Timeout waiting card ready\n"); return TIMEOUT; } -- 1.7.7.6

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[U-Boot] [PATCH] mmc: fix wrong timeout check in mmc_send_status()
by Jongman Heo 04 Jun '12

04 Jun '12

(!timeout) condition check in mmc_send_status() can never be met, because do-while loop ends up with negative timeout value, -1. Fix it by using pre-decrement. Signed-off-by: Jongman Heo <jongman.heo(a)gmail.com> --- drivers/mmc/mmc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index aebe578..de19d4e 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -232,7 +232,7 @@ int mmc_send_status(struct mmc *mmc, int timeout) udelay(1000); - } while (timeout--); + } while (--timeout); #ifdef CONFIG_MMC_TRACE status = (cmd.response[0] & MMC_STATUS_CURR_STATE) >> 9; -- 1.7.7.6

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[U-Boot] [PATCH] MIPS: board.c: move extern declarations to u-boot-mips.h
by Daniel Schwierzeck 04 Jun '12

04 Jun '12

This fixes some remaining checkpatch.pl warnings. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck(a)googlemail.com> --- arch/mips/include/asm/u-boot-mips.h | 11 +++++++++++ arch/mips/lib/board.c | 7 ------- include/common.h | 3 +++ 3 files changed, 14 insertions(+), 7 deletions(-) create mode 100644 arch/mips/include/asm/u-boot-mips.h diff --git a/arch/mips/include/asm/u-boot-mips.h b/arch/mips/include/asm/u-boot-mips.h new file mode 100644 index 0000000..6f26dfa --- /dev/null +++ b/arch/mips/include/asm/u-boot-mips.h @@ -0,0 +1,11 @@ +/* + * This file is released under the terms of GPL v2 and any later version. + * See the file COPYING in the root directory of the source tree for details. + * + * Copyright (C) 2003 Wolfgang Denk, DENX Software Engineering, wd(a)denx.de + */ + +extern ulong uboot_end_data; +extern ulong uboot_end; + +extern int incaip_set_cpuclk(void); diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index 59a8001..62d47a8 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -38,13 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -extern int timer_init(void); - -extern int incaip_set_cpuclk(void); - -extern ulong uboot_end_data; -extern ulong uboot_end; - ulong monitor_flash_len; static char *failed = "*** failed ***\n"; diff --git a/include/common.h b/include/common.h index 8564a65..ecfa6c4 100644 --- a/include/common.h +++ b/include/common.h @@ -355,6 +355,9 @@ int setenv_addr(const char *varname, const void *addr); # include <asm/mach-types.h> # include <asm/u-boot-nds32.h> #endif /* CONFIG_NDS32 */ +#ifdef CONFIG_MIPS +# include <asm/u-boot-mips.h> +#endif /* CONFIG_MIPS */ #ifdef CONFIG_AUTO_COMPLETE int env_complete(char *var, int maxv, char *cmdv[], int maxsz, char *buf); -- 1.7.10

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