June 2012 - U-Boot

[U-Boot] [PATCH 0/6] updates for keymile powerpc83xx boards
by Holger Brunck 15 Jun '12

15 Jun '12

- board support for the new kmcoge5ne board was added - other headerfiles are reworked and simplified - new feature for boards with two different flashtypes are added to km common code The patch for km/common changes also some lines in km_arm.h but because of some interdependencies it should go through the powepc83xx tree if possible. Andreas Huber (1): km/common: add support for second flash Christian Herzig (1): powerpc83xx/km: lock the window size to 2GiB befor fixing sdram size Holger Brunck (4): powerpc/83xx/km: use tuxx1.h for kmsupx5 target powerpc83xx/km: remove unneeded CONFIG_PCI for kmeter1 powerpc/83xx: add kmcoge5ne board support MAINTAINERS: cleanup for keymile boards MAINTAINERS | 12 +- board/keymile/km83xx/km83xx.c | 4 +- boards.cfg | 11 +- include/configs/km/keymile-common.h | 34 +++- include/configs/km/km83xx-common.h | 13 ++- include/configs/km/km_arm.h | 15 +- include/configs/km8360.h | 281 +++++++++++++++++++++++++++++++++++ include/configs/kmeter1.h | 187 ----------------------- include/configs/kmsupx5.h | 91 ----------- include/configs/tuxx1.h | 22 ++- 10 files changed, 353 insertions(+), 317 deletions(-) create mode 100644 include/configs/km8360.h delete mode 100644 include/configs/kmeter1.h delete mode 100644 include/configs/kmsupx5.h

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[U-Boot] [PATCH] powerpc/83xx: increment malloc heap size for the MPC832x MDS boards
by Timur Tabi 15 Jun '12

15 Jun '12

The malloc buffer is not large enough to hold a flash sector (0x20000 bytes) in addition to whatever else it normally holds, so double its size. This fixes a failure trying to save the environment: => save Saving Environment to Flash... Unable to save the rest of sector (122880) . done Protected 1 sectors This problem probably surfaced from some other change that significantly increased the normal memory usage, thereby not leaving enough room for the saveenv command. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- include/configs/MPC832XEMDS.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4ed5a97..6f8622c 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -181,7 +181,7 @@ /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup -- 1.7.4.4

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[U-Boot] [PATCH v2] tx25: Use generic gpio_* calls
by Vikram Narayanan 15 Jun '12

15 Jun '12

Changes from v1: Used appropriate gpio_* lib calls. --- Instead of manipulating gpio registers directly, use the calls from the gpio library. Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Cc: Fabio Estevam <fabio.estevam(a)freescale.com> Cc: John Rigby <jcrigby(a)gmail.com> Cc: Stefano Babic <sbabic(a)denx.de> --- board/karo/tx25/tx25.c | 25 +++++++++---------------- 1 files changed, 9 insertions(+), 16 deletions(-) diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 2a29943..ff2de38 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -34,14 +34,13 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_FEC_MXC +#define GPIO_FEC_RESET_B MXC_GPIO_PORT_TO_NUM(4, 7) +#define GPIO_FEC_ENABLE_B MXC_GPIO_PORT_TO_NUM(4, 9) void tx25_fec_init(void) { struct iomuxc_mux_ctl *muxctl; struct iomuxc_pad_ctl *padctl; - u32 val; u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); - struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; - struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; u32 saved_rdata0_mode, saved_rdata1_mode, saved_rx_dv_mode; debug("tx25_fec_init\n"); @@ -66,18 +65,15 @@ void tx25_fec_init(void) writel(0x0, &padctl->pad_d11); /* drop PHY power and assert reset (low) */ - val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9)); - writel(val, &gpio4->gpio_dr); - val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9); - writel(val, &gpio4->gpio_dir); + gpio_direction_output(GPIO_FEC_RESET_B, 0); + gpio_direction_output(GPIO_FEC_ENABLE_B, 0); mdelay(5); debug("resetting phy\n"); /* turn on PHY power leaving reset asserted */ - val = readl(&gpio4->gpio_dr) | 1 << 9; - writel(val, &gpio4->gpio_dr); + gpio_direction_output(GPIO_FEC_ENABLE_B, 1); mdelay(10); @@ -107,19 +103,16 @@ void tx25_fec_init(void) /* * set each to 1 and make each an output */ - val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->gpio_dr); - val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->gpio_dir); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 10), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 11), 1); + gpio_direction_output(MXC_GPIO_PORT_TO_NUM(3, 12), 1); mdelay(22); /* this value came from RedBoot */ /* * deassert PHY reset */ - val = readl(&gpio4->gpio_dr) | 1 << 7; - writel(val, &gpio4->gpio_dr); - writel(val, &gpio4->gpio_dr); + gpio_set_value(GPIO_FEC_RESET_B, 1); mdelay(5); -- 1.7.4.1

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[U-Boot] imx: gpio cleanups
by Vikram Narayanan 15 Jun '12

15 Jun '12

This patchset cleanups up the gpio related stuff on imx boards. Define a common header for gpio and remove the same struct defines in all the include directories. Vikram Narayanan (3): imx25: Move MXC_GPIO_PORT_TO_NUM to imx-regs.h tx25: Use generic gpio_* calls imx: Define a common header file for gpio.h arch/arm/include/asm/arch-mx25/gpio.h | 45 -------------------- arch/arm/include/asm/arch-mx25/imx-regs.h | 6 +++ arch/arm/include/asm/arch-mx31/gpio.h | 35 --------------- arch/arm/include/asm/arch-mx35/gpio.h | 40 ----------------- arch/arm/include/asm/arch-mx5/gpio.h | 35 --------------- board/CarMediaLab/flea3/flea3.c | 2 +- board/davedenx/qong/fpga.c | 2 +- board/davedenx/qong/qong.c | 2 +- board/denx/m28evk/m28evk.c | 2 +- board/efikamx/efikamx-usb.c | 2 +- board/efikamx/efikamx.c | 2 +- board/esg/ima3-mx53/ima3-mx53.c | 2 +- board/freescale/mx28evk/mx28evk.c | 2 +- board/freescale/mx35pdk/mx35pdk.c | 2 +- board/freescale/mx51evk/mx51evk.c | 2 +- board/freescale/mx53ard/mx53ard.c | 2 +- board/freescale/mx53evk/mx53evk.c | 2 +- board/freescale/mx53loco/mx53loco.c | 2 +- board/freescale/mx53smd/mx53smd.c | 2 +- board/freescale/mx6qarm2/mx6qarm2.c | 2 +- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 2 +- board/karo/tx25/tx25.c | 30 ++++++------- board/syteco/zmx25/zmx25.c | 2 +- board/ttcontrol/vision2/vision2.c | 2 +- common/cmd_gpio.c | 2 +- drivers/gpio/mxc_gpio.c | 2 +- .../asm/arch-mx6/gpio.h => drivers/gpio/mxc_gpio.h | 12 +++--- drivers/spi/mxc_spi.c | 2 +- 28 files changed, 46 insertions(+), 199 deletions(-) delete mode 100644 arch/arm/include/asm/arch-mx25/gpio.h delete mode 100644 arch/arm/include/asm/arch-mx31/gpio.h delete mode 100644 arch/arm/include/asm/arch-mx35/gpio.h delete mode 100644 arch/arm/include/asm/arch-mx5/gpio.h rename arch/arm/include/asm/arch-mx6/gpio.h => drivers/gpio/mxc_gpio.h (85%) -- 1.7.4.1

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[U-Boot] [PATCH 1/1] tegra: usb: Fix device enumeration problem of USB1
by Jim Lin 15 Jun '12

15 Jun '12

For some reason, bit 1 (connect status change) of PORTSC will be set after issuing Port Reset (like "usb reset" in u-boot command line). This will be treated as an error and stops later device enumeration. Therefore we add a definition in header file to ignore checking of that bit after Port Reset. CONFIG_USB_RESET_IGNORE_CONNECT_CHANGE Signed-off-by: Jim Lin <jilin(a)nvidia.com> --- To reproduce this issue, you can modify board .dts file to set as the following to build u-boot binary. " usb0 = "/usb@c5000000"; usb1 = "/usb@c5008000"; " Install device on USB1 port (address at 0xc5000000). And run "usb reset" in u-boot console to enumerate device. common/usb_hub.c | 4 ++++ include/configs/tegra2-common.h | 7 +++++++ 2 files changed, 11 insertions(+), 0 deletions(-) diff --git a/common/usb_hub.c b/common/usb_hub.c index e0edaad..8e6bdd8 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -180,8 +180,12 @@ int hub_port_reset(struct usb_device *dev, int port, (portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0, (portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0); +#ifdef CONFIG_USB_RESET_IGNORE_CONNECT_CHANGE + if (!(portstatus & USB_PORT_STAT_CONNECTION)) +#else if ((portchange & USB_PORT_STAT_C_CONNECTION) || !(portstatus & USB_PORT_STAT_CONNECTION)) +#endif return -1; if (portstatus & USB_PORT_STAT_ENABLE) diff --git a/include/configs/tegra2-common.h b/include/configs/tegra2-common.h index 1931179..904c17e 100644 --- a/include/configs/tegra2-common.h +++ b/include/configs/tegra2-common.h @@ -111,6 +111,13 @@ #define CONFIG_EHCI_IS_TDI #define CONFIG_EHCI_DCACHE +/* + * For some reason, bit 1 (Connect Status Change) of PORTSC register will be + * set after issuing Port Reset. This setting is to ignore checking of that + * bit after reset. + */ +#define CONFIG_USB_RESET_IGNORE_CONNECT_CHANGE + /* Total I2C ports on Tegra2 */ #define TEGRA_I2C_NUM_CONTROLLERS 4 -- 1.7.3 nvpublic

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[U-Boot] am35xx, twister: could not write nand flash
by Heiko Schocher 15 Jun '12

15 Jun '12

Hello Scott, I currently tried current U-Boot HEAD commit fedab338f3459315cb69627fcf46032ec8df1753 Merge: 74b5b5d f6b690e Author: Wolfgang Denk <wd(a)denx.de> Date: Thu Jun 7 23:42:17 2012 +0200 Merge branch 'master' of git://git.denx.de/u-boot-video on the twister board, and detected that a "run update" fails with: twister => run update SW ECC selected NAND erase: device 0 offset 0x80000, size 0x100000 Erasing at 0x160000 -- 100% complete. OK NAND write: (board hangs ...) Environment var: update=nandecc sw;nand erase ${uboot_addr} 100000;nand write ${loadaddr} ${uboot_addr} 80000 So I started "git bisection": [hs@pollux u-boot]$ git bisect start [hs@pollux u-boot]$ git bisect bad [hs@pollux u-boot]$ git bisect good 415d386877df49eb051b85ef74fa59a16dc17c7d Bisecting: 211 revisions left to test after this (roughly 8 steps) [...] [hs@pollux u-boot]$ git bisect bad 418396e212b59bf907dbccad997ff50f7eb61b16 is the first bad commit commit 418396e212b59bf907dbccad997ff50f7eb61b16 Author: Scott Wood <scottwood(a)freescale.com> Date: Fri Mar 2 14:01:57 2012 -0600 nand: extend .raw accesses to work on multiple pages A use for this is to read, modify, erase, and write an entire block as a single unit, as a replacement for the biterr command. This way gives more flexibility in that you can also test multiple bit errors, errors in the ECC, etc. Signed-off-by: Scott Wood <scottwood(a)freescale.com> :040000 040000 ad5ce55a0fdf3a40e1aaae0546aae68bf7a0b480 f57e87a8630715e37170b5bb3a109a58b6b89333 M common :040000 040000 83834ae80a73f20357132875078f643b4064f9dd ed0004e44b4da8b2734168a3950733afba0a0b64 M doc [hs@pollux u-boot]$ following patch helps: diff --git a/common/cmd_nand.c b/common/cmd_nand.c index fa44295..edeb093 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -617,7 +617,7 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) s = strchr(cmd, '.'); - if (!strcmp(s, ".raw")) { + if ((s != NULL) && (!strcmp(s, ".raw"))) { raw = 1; if (arg_off(argv[3], &dev, &off, &size)) What do you think? Is this a correct fix, and I should sent this as a real patch, or did I overlook something? bye, Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] [PATCH 1/6] imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition
by Fabio Estevam 15 Jun '12

15 Jun '12

From: Fabio Estevam <fabio.estevam(a)freescale.com> According to include/i2c.h: "/* * Many boards/controllers/drivers don't support an I2C slave interface so * provide a default slave address for them for use in common code. A real * value for CONFIG_SYS_I2C_SLAVE should be defined for any board which does * support a slave interface. */ #ifndef CONFIG_SYS_I2C_SLAVE #define CONFIG_SYS_I2C_SLAVE 0xfe #endif " As the mxc_i2c driver does not support slave mode, there is no need to define CONFIG_SYS_I2C_SLAVE in i.MX board file. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/imx31_phycore.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 3153eb5..b3244b9 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -56,7 +56,6 @@ #define CONFIG_I2C_MXC #define CONFIG_SYS_I2C_MX31_PORT2 #define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0xfe #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE -- 1.7.1

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[U-Boot] [PATCH] mx53ard: Remove unused CONFIG_MII_GASKET
by Fabio Estevam 15 Jun '12

15 Jun '12

From: Fabio Estevam <fabio.estevam(a)freescale.com> CONFIG_MII_GASKET is not defined anywhere, so remove it. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- include/configs/mx53ard.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h index f48a41e..f59960e 100644 --- a/include/configs/mx53ard.h +++ b/include/configs/mx53ard.h @@ -68,7 +68,6 @@ /* Eth Configs */ #define CONFIG_HAS_ETH1 #define CONFIG_MII -#define CONFIG_MII_GASKET #define CONFIG_DISCOVER_PHY #define CONFIG_CMD_PING -- 1.7.1

2 1

[U-Boot] [PATCH] mx6: Avoid writing to read-only bits in imximage.cfg
by Vikram Narayanan 15 Jun '12

15 Jun '12

If in case this is valid according to the latest datasheet, ignore this patch. -- According to REV C manual, the register IOMUXC_IOMUXC_GPR4 has bits 4 and 5 read-only and the value is always set as zero. So write '0' to these bits instead of writing '1'. Signed-off-by: Vikram Narayanan <vikram186(a)gmail.com> Cc: Jason Liu <r64343(a)freescale.com> Cc: Dirk Behme <dirk.behme(a)googlemail.com> --- board/freescale/mx6qarm2/imximage.cfg | 2 +- board/freescale/mx6qsabrelite/imximage.cfg | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/mx6qarm2/imximage.cfg b/board/freescale/mx6qarm2/imximage.cfg index ceecbf9..bf941a3 100644 --- a/board/freescale/mx6qarm2/imximage.cfg +++ b/board/freescale/mx6qarm2/imximage.cfg @@ -167,7 +167,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F diff --git a/board/freescale/mx6qsabrelite/imximage.cfg b/board/freescale/mx6qsabrelite/imximage.cfg index c389427..62498ab 100644 --- a/board/freescale/mx6qsabrelite/imximage.cfg +++ b/board/freescale/mx6qsabrelite/imximage.cfg @@ -164,7 +164,7 @@ DATA 4 0x020c407c 0x0F0000C3 DATA 4 0x020c4080 0x000003FF # enable AXI cache for VDOA/VPU/IPU -DATA 4 0x020e0010 0xF00000FF +DATA 4 0x020e0010 0xF00000CF # set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 DATA 4 0x020e0018 0x007F007F DATA 4 0x020e001c 0x007F007F -- 1.7.4.1

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[U-Boot] [PATCH 1/2 V6] EXYNOS5: PINMUX: Added default pinumx settings
by Rajeshwari Shinde 15 Jun '12

15 Jun '12

This patch performs the pinmux configuration in a common file. As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is supported. Signed-off-by: Abhilash Kesavan <a.kesavan(a)samsung.com> Signed-off-by: Che-Liang Chiou <clchiou(a)chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s(a)samsung.com> Acked-by: Chander Kashyap <chander.kashyap(a)linaro.org> Acked-by: Simon Glass <sjg(a)chromium.org> --- Changes in V2: - Adding pinmux.c to Makefile moved to this patch. - exynos5_pinmux_config made static Changes in V3: - Separate functions made for each peripheral - enum periph_id moved to a separate periph.h Changes in V4: - removed variable declarations from exynos5_pinmux_config Changes in V5: - added a return statement for function exynos5_mmc_config and added a check for same Changes in V6: - Added a blank line arch/arm/cpu/armv7/exynos/Makefile | 2 +- arch/arm/cpu/armv7/exynos/pinmux.c | 220 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/periph.h | 47 ++++++ arch/arm/include/asm/arch-exynos/pinmux.h | 58 ++++++++ 4 files changed, 326 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/exynos/pinmux.c create mode 100644 arch/arm/include/asm/arch-exynos/periph.h create mode 100644 arch/arm/include/asm/arch-exynos/pinmux.h diff --git a/arch/arm/cpu/armv7/exynos/Makefile b/arch/arm/cpu/armv7/exynos/Makefile index 90ec2bd..9119961 100644 --- a/arch/arm/cpu/armv7/exynos/Makefile +++ b/arch/arm/cpu/armv7/exynos/Makefile @@ -22,7 +22,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o -COBJS += clock.o power.o soc.o system.o +COBJS += clock.o power.o soc.o system.o pinmux.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c new file mode 100644 index 0000000..d2b7d2c --- /dev/null +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2012 Samsung Electronics. + * Abhilash Kesavan <a.kesavan(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/sromc.h> + +static void exynos5_uart_config(int peripheral) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank; + int i, start, count; + + switch (peripheral) { + case PERIPH_ID_UART0: + bank = &gpio1->a0; + start = 0; + count = 4; + break; + case PERIPH_ID_UART1: + bank = &gpio1->a0; + start = 4; + count = 4; + break; + case PERIPH_ID_UART2: + bank = &gpio1->a1; + start = 0; + count = 4; + break; + case PERIPH_ID_UART3: + bank = &gpio1->a1; + start = 4; + count = 2; + break; + } + for (i = start; i < start + count; i++) { + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + } +} + +static int exynos5_mmc_config(int peripheral, int flags) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct s5p_gpio_bank *bank, *bank_ext; + int i; + + switch (peripheral) { + case PERIPH_ID_SDMMC0: + bank = &gpio1->c0; + bank_ext = &gpio1->c1; + break; + case PERIPH_ID_SDMMC1: + bank = &gpio1->c1; + bank_ext = NULL; + break; + case PERIPH_ID_SDMMC2: + bank = &gpio1->c2; + bank_ext = &gpio1->c3; + break; + case PERIPH_ID_SDMMC3: + bank = &gpio1->c3; + bank_ext = NULL; + break; + } + if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { + debug("SDMMC device %d does not support 8bit mode", + peripheral); + return -1; + } + if (flags & PINMUX_FLAG_8BIT_MODE) { + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + } + } + for (i = 0; i < 2; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + for (i = 3; i <= 6; i++) { + s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); + s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + } + return 0; +} + +static void exynos5_sromc_config(int flags) +{ + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + int i; + + /* + * SROM:CS1 and EBI + * + * GPY0[0] SROM_CSn[0] + * GPY0[1] SROM_CSn[1](2) + * GPY0[2] SROM_CSn[2] + * GPY0[3] SROM_CSn[3] + * GPY0[4] EBI_OEn(2) + * GPY0[5] EBI_EEn(2) + * + * GPY1[0] EBI_BEn[0](2) + * GPY1[1] EBI_BEn[1](2) + * GPY1[2] SROM_WAIT(2) + * GPY1[3] EBI_DATA_RDn(2) + */ + s5p_gpio_cfg_pin(&gpio1->y0, (flags & PINMUX_FLAG_BANK), + GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->y0, 4, GPIO_FUNC(2)); + s5p_gpio_cfg_pin(&gpio1->y0, 5, GPIO_FUNC(2)); + + for (i = 0; i < 4; i++) + s5p_gpio_cfg_pin(&gpio1->y1, i, GPIO_FUNC(2)); + + /* + * EBI: 8 Addrss Lines + * + * GPY3[0] EBI_ADDR[0](2) + * GPY3[1] EBI_ADDR[1](2) + * GPY3[2] EBI_ADDR[2](2) + * GPY3[3] EBI_ADDR[3](2) + * GPY3[4] EBI_ADDR[4](2) + * GPY3[5] EBI_ADDR[5](2) + * GPY3[6] EBI_ADDR[6](2) + * GPY3[7] EBI_ADDR[7](2) + * + * EBI: 16 Data Lines + * + * GPY5[0] EBI_DATA[0](2) + * GPY5[1] EBI_DATA[1](2) + * GPY5[2] EBI_DATA[2](2) + * GPY5[3] EBI_DATA[3](2) + * GPY5[4] EBI_DATA[4](2) + * GPY5[5] EBI_DATA[5](2) + * GPY5[6] EBI_DATA[6](2) + * GPY5[7] EBI_DATA[7](2) + * + * GPY6[0] EBI_DATA[8](2) + * GPY6[1] EBI_DATA[9](2) + * GPY6[2] EBI_DATA[10](2) + * GPY6[3] EBI_DATA[11](2) + * GPY6[4] EBI_DATA[12](2) + * GPY6[5] EBI_DATA[13](2) + * GPY6[6] EBI_DATA[14](2) + * GPY6[7] EBI_DATA[15](2) + */ + for (i = 0; i < 8; i++) { + s5p_gpio_cfg_pin(&gpio1->y3, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y3, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio1->y5, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y5, i, GPIO_PULL_UP); + + s5p_gpio_cfg_pin(&gpio1->y6, i, GPIO_FUNC(2)); + s5p_gpio_set_pull(&gpio1->y6, i, GPIO_PULL_UP); + } +} + +static int exynos5_pinmux_config(int peripheral, int flags) +{ + switch (peripheral) { + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + exynos5_uart_config(peripheral); + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + case PERIPH_ID_SDMMC2: + case PERIPH_ID_SDMMC3: + return exynos5_mmc_config(peripheral, flags); + case PERIPH_ID_SROMC: + exynos5_sromc_config(flags); + break; + default: + debug("%s: invalid peripheral %d", __func__, peripheral); + return -1; + } + + return 0; +} + +int exynos_pinmux_config(int peripheral, int flags) +{ + if (cpu_is_exynos5()) + return exynos5_pinmux_config(peripheral, flags); + else { + debug("pinmux functionality not supported\n"); + return -1; + } +} diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h new file mode 100644 index 0000000..5db25aa --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde <rajeshwari.s(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals requiring clock/pinmux configuration. List will + * grow with support for more devices getting added. + * + */ +enum periph_id { + PERIPH_ID_SDMMC0, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_SROMC, + PERIPH_ID_UART0, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + + PERIPH_ID_COUNT, + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-exynos/pinmux.h b/arch/arm/include/asm/arch-exynos/pinmux.h new file mode 100644 index 0000000..10ea736 --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/pinmux.h @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan <a.kesavan(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +#endif -- 1.7.4.4

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