April 2012 - U-Boot

[U-Boot] [PATCH] openrisc/cache: disable icache during invalidation
by Stefan Kristiansson 24 Apr '12

24 Apr '12

invalidating the memory area that is being executed while icache is on is a bit adventurous, make sure it's turned off during this operation Signed-off-by: Stefan Kristiansson <stefan.kristiansson(a)saunalahti.fi> --- arch/openrisc/cpu/cache.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/openrisc/cpu/cache.c b/arch/openrisc/cpu/cache.c index 2a73a4f..fedfd89 100644 --- a/arch/openrisc/cpu/cache.c +++ b/arch/openrisc/cpu/cache.c @@ -44,11 +44,15 @@ void invalidate_dcache_range(unsigned long addr, unsigned long stop) static void invalidate_icache_range(unsigned long addr, unsigned long stop) { ulong block_size = (mfspr(SPR_ICCFGR) & SPR_ICCFGR_CBS) ? 32 : 16; + ulong ie = icache_status(); + icache_disable(); while (addr < stop) { mtspr(SPR_ICBIR, addr); addr += block_size; } + if (ie) + icache_enable(); } void flush_cache(unsigned long addr, unsigned long size) -- 1.7.5.4

2 1

[U-Boot] [STATUS] Are we ready for v2012.04.1 ??
by Wolfgang Denk 24 Apr '12

24 Apr '12

Hi, are there any other urgent fixes that should make it into the imminent v2012.04.1 maintenance release ? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de God made the integers; all else is the work of Man. - Kronecker

6 7

[U-Boot] [PATCH V2] fs/fat: align disk buffers on cache line to enable DMA and cache
by Eric Nelson 24 Apr '12

24 Apr '12

Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> Acked-by: Mike Frysinger <vapier(a)gentoo.org> --- fs/fat/fat.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 1f95eb4..f3c48bb 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -31,6 +31,8 @@ #include <fat.h> #include <asm/byteorder.h> #include <part.h> +#include <malloc.h> +#include <linux/compiler.h> /* * Convert a string to lowercase. @@ -62,7 +64,7 @@ static int disk_read(__u32 block, __u32 nr_blocks, void *buf) int fat_register_device (block_dev_desc_t * dev_desc, int part_no) { - unsigned char buffer[dev_desc->blksz]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); /* First close any currently found FAT filesystem */ cur_dev = NULL; @@ -293,7 +295,7 @@ get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer, return -1; } if (size % mydata->sect_size) { - __u8 tmpbuf[mydata->sect_size]; + ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size); idx = size / mydata->sect_size; ret = disk_read(startsect + idx, 1, tmpbuf); @@ -428,8 +430,8 @@ static int slot2str (dir_slot *slotptr, char *l_name, int *idx) * into 'retdent' * Return 0 on success, -1 otherwise. */ -__attribute__ ((__aligned__ (__alignof__ (dir_entry)))) -__u8 get_vfatname_block[MAX_CLUSTSIZE]; +__u8 get_vfatname_block[MAX_CLUSTSIZE] + __aligned(ARCH_DMA_MINALIGN); static int get_vfatname (fsdata *mydata, int curclust, __u8 *cluster, @@ -709,7 +711,7 @@ read_bootsectandvi (boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } - block = malloc(cur_dev->blksz); + block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz); if (block == NULL) { debug("Error: allocating block\n"); return -1; @@ -828,7 +830,7 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, } mydata->fatbufnum = -1; - mydata->fatbuf = malloc(FATBUFSIZE); + mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE); if (mydata->fatbuf == NULL) { debug("Error: allocating memory\n"); return -1; -- 1.7.9

5 8

[U-Boot] [PATCH V3]fs/fat: align disk buffers on cache line to enable DMA and cache
by Eric Nelson 24 Apr '12

24 Apr '12

Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- V3 increases alignment of globals: get_dentfromdir_block do_fat_read_block fs/fat/fat.c | 22 ++++++++++++---------- 1 files changed, 12 insertions(+), 10 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 1f95eb4..a3085b5 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -31,6 +31,8 @@ #include <fat.h> #include <asm/byteorder.h> #include <part.h> +#include <malloc.h> +#include <linux/compiler.h> /* * Convert a string to lowercase. @@ -62,7 +64,7 @@ static int disk_read(__u32 block, __u32 nr_blocks, void *buf) int fat_register_device (block_dev_desc_t * dev_desc, int part_no) { - unsigned char buffer[dev_desc->blksz]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); /* First close any currently found FAT filesystem */ cur_dev = NULL; @@ -293,7 +295,7 @@ get_cluster (fsdata *mydata, __u32 clustnum, __u8 *buffer, return -1; } if (size % mydata->sect_size) { - __u8 tmpbuf[mydata->sect_size]; + ALLOC_CACHE_ALIGN_BUFFER(__u8, tmpbuf, mydata->sect_size); idx = size / mydata->sect_size; ret = disk_read(startsect + idx, 1, tmpbuf); @@ -428,8 +430,8 @@ static int slot2str (dir_slot *slotptr, char *l_name, int *idx) * into 'retdent' * Return 0 on success, -1 otherwise. */ -__attribute__ ((__aligned__ (__alignof__ (dir_entry)))) -__u8 get_vfatname_block[MAX_CLUSTSIZE]; +__u8 get_vfatname_block[MAX_CLUSTSIZE] + __aligned(ARCH_DMA_MINALIGN); static int get_vfatname (fsdata *mydata, int curclust, __u8 *cluster, @@ -533,8 +535,8 @@ static __u8 mkcksum (const char *str) * Get the directory entry associated with 'filename' from the directory * starting at 'startsect' */ -__attribute__ ((__aligned__ (__alignof__ (dir_entry)))) -__u8 get_dentfromdir_block[MAX_CLUSTSIZE]; +__u8 get_dentfromdir_block[MAX_CLUSTSIZE] + __aligned(ARCH_DMA_MINALIGN); static dir_entry *get_dentfromdir (fsdata *mydata, int startsect, char *filename, dir_entry *retdent, @@ -709,7 +711,7 @@ read_bootsectandvi (boot_sector *bs, volume_info *volinfo, int *fatsize) return -1; } - block = malloc(cur_dev->blksz); + block = memalign(ARCH_DMA_MINALIGN, cur_dev->blksz); if (block == NULL) { debug("Error: allocating block\n"); return -1; @@ -765,8 +767,8 @@ exit: return ret; } -__attribute__ ((__aligned__ (__alignof__ (dir_entry)))) -__u8 do_fat_read_block[MAX_CLUSTSIZE]; +__u8 do_fat_read_block[MAX_CLUSTSIZE] + __aligned(ARCH_DMA_MINALIGN); long do_fat_read (const char *filename, void *buffer, unsigned long maxsize, @@ -828,7 +830,7 @@ do_fat_read (const char *filename, void *buffer, unsigned long maxsize, } mydata->fatbufnum = -1; - mydata->fatbuf = malloc(FATBUFSIZE); + mydata->fatbuf = memalign(ARCH_DMA_MINALIGN, FATBUFSIZE); if (mydata->fatbuf == NULL) { debug("Error: allocating memory\n"); return -1; -- 1.7.9

3 2

[U-Boot] [PATCH] i2c: Add support for designware i2c controller
by Amit Virdi 24 Apr '12

24 Apr '12

From: Vipin KUMAR <vipin.kumar(a)st.com> Earlier, a driver exists in the u-boot source for designware i2c interface. That driver was specific to spear platforms. This patch implements the i2c controller as a generic driver which can be used by multiple platforms The driver files are now renamed to designware_i2c.c and designware_i2c.h and these are moved into drivers/i2c folder for reusability by other platforms Signed-off-by: Vipin Kumar <vipin.kumar(a)st.com> Signed-off-by: Amit Virdi <amit.virdi(a)st.com> --- drivers/i2c/Makefile | 2 +- drivers/i2c/{spr_i2c.c => designware_i2c.c} | 4 ++-- .../spr_i2c.h => drivers/i2c/designware_i2c.h | 6 +++--- include/configs/spear-common.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) rename drivers/i2c/{spr_i2c.c => designware_i2c.c} (98%) rename arch/arm/include/asm/arch-spear/spr_i2c.h => drivers/i2c/designware_i2c.h (98%) diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 504db03..0d268f2 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libi2c.o COBJS-$(CONFIG_BFIN_TWI_I2C) += bfin-twi_i2c.o COBJS-$(CONFIG_DRIVER_DAVINCI_I2C) += davinci_i2c.o +COBJS-$(CONFIG_DW_I2C) += designware_i2c.o COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_MVTWSI) += mvtwsi.o COBJS-$(CONFIG_I2C_MV) += mv_i2c.o @@ -40,7 +41,6 @@ COBJS-$(CONFIG_PPC4XX_I2C) += ppc4xx_i2c.o COBJS-$(CONFIG_DRIVER_S3C24X0_I2C) += s3c24x0_i2c.o COBJS-$(CONFIG_S3C44B0_I2C) += s3c44b0_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o -COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o COBJS-$(CONFIG_SH_I2C) += sh_i2c.o diff --git a/drivers/i2c/spr_i2c.c b/drivers/i2c/designware_i2c.c similarity index 98% rename from drivers/i2c/spr_i2c.c rename to drivers/i2c/designware_i2c.c index eabfe84..d352146 100644 --- a/drivers/i2c/spr_i2c.c +++ b/drivers/i2c/designware_i2c.c @@ -24,7 +24,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/hardware.h> -#include <asm/arch/spr_i2c.h> +#include "designware_i2c.h" static struct i2c_regs *const i2c_regs_p = (struct i2c_regs *)CONFIG_SYS_I2C_BASE; @@ -113,7 +113,7 @@ int i2c_get_bus_speed(void) /* * i2c_init - Init function * @speed: required i2c speed - * @slaveadd: slave address for the spear device + * @slaveadd: slave address for the device * * Initialization function. */ diff --git a/arch/arm/include/asm/arch-spear/spr_i2c.h b/drivers/i2c/designware_i2c.h similarity index 98% rename from arch/arm/include/asm/arch-spear/spr_i2c.h rename to drivers/i2c/designware_i2c.h index 7521ebc..03b520e 100644 --- a/arch/arm/include/asm/arch-spear/spr_i2c.h +++ b/drivers/i2c/designware_i2c.h @@ -21,8 +21,8 @@ * MA 02111-1307 USA */ -#ifndef __SPR_I2C_H_ -#define __SPR_I2C_H_ +#ifndef __DW_I2C_H_ +#define __DW_I2C_H_ struct i2c_regs { u32 ic_con; @@ -143,4 +143,4 @@ struct i2c_regs { #define I2C_FAST_SPEED 400000 #define I2C_STANDARD_SPEED 100000 -#endif /* __SPR_I2C_H_ */ +#endif /* __DW_I2C_H_ */ diff --git a/include/configs/spear-common.h b/include/configs/spear-common.h index 5a582e8..516b78e 100644 --- a/include/configs/spear-common.h +++ b/include/configs/spear-common.h @@ -41,7 +41,7 @@ /* I2C driver configuration */ #define CONFIG_HARD_I2C -#define CONFIG_SPEAR_I2C +#define CONFIG_DW_I2C #define CONFIG_SYS_I2C_SPEED 400000 #define CONFIG_SYS_I2C_SLAVE 0x02 -- 1.7.2.2

2 4

[U-Boot] [PATCH] sh: i2c: Add support I2C controller of SH7734
by Nobuhiro Iwamatsu 24 Apr '12

24 Apr '12

Renesas SH7734 has two I2C interfaceis. This supports these I2C. V5: - include i2c.h. - Add check of icsr bit polling logic. - Implement i2c_probe. V4: - Remove sh_i2c_dump_reg function. - Use puts() when there's no format. - Chnage check for I2C bus number. - Remove space before the semi-colon. V3: - Fix error for whitespace. V2: - Changed bit control to use the clr|set|clrsetbits_* functions. - Fix wrong comment style. - Add new line before for loop in i2c_read. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> Acked-by: Heiko Schocher <hs(a)denx.de> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/i2c/Makefile | 1 + drivers/i2c/sh_sh7734_i2c.c | 387 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 388 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/sh_sh7734_i2c.c diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 504db03..506269d 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -44,6 +44,7 @@ COBJS-$(CONFIG_SPEAR_I2C) += spr_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o COBJS-$(CONFIG_SH_I2C) += sh_i2c.o +COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/i2c/sh_sh7734_i2c.c b/drivers/i2c/sh_sh7734_i2c.c new file mode 100644 index 0000000..9da173d --- /dev/null +++ b/drivers/i2c/sh_sh7734_i2c.c @@ -0,0 +1,387 @@ +/* + * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj(a)renesas.com> + * Copyright (C) 2012 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> + +struct sh_i2c { + u8 iccr1; + u8 iccr2; + u8 icmr; + u8 icier; + u8 icsr; + u8 sar; + u8 icdrt; + u8 icdrr; + u8 nf2cyc; + u8 __pad0; + u8 __pad1; +}; + +static struct sh_i2c *base; +static u8 iccr1_cks, nf2cyc; + +/* ICCR1 */ +#define SH_I2C_ICCR1_ICE (1 << 7) +#define SH_I2C_ICCR1_RCVD (1 << 6) +#define SH_I2C_ICCR1_MST (1 << 5) +#define SH_I2C_ICCR1_TRS (1 << 4) +#define SH_I2C_ICCR1_MTRS \ + (SH_I2C_ICCR1_MST | SH_I2C_ICCR1_TRS) + +/* ICCR1 */ +#define SH_I2C_ICCR2_BBSY (1 << 7) +#define SH_I2C_ICCR2_SCP (1 << 6) +#define SH_I2C_ICCR2_SDAO (1 << 5) +#define SH_I2C_ICCR2_SDAOP (1 << 4) +#define SH_I2C_ICCR2_SCLO (1 << 3) +#define SH_I2C_ICCR2_IICRST (1 << 1) + +#define SH_I2C_ICIER_TIE (1 << 7) +#define SH_I2C_ICIER_TEIE (1 << 6) +#define SH_I2C_ICIER_RIE (1 << 5) +#define SH_I2C_ICIER_NAKIE (1 << 4) +#define SH_I2C_ICIER_STIE (1 << 3) +#define SH_I2C_ICIER_ACKE (1 << 2) +#define SH_I2C_ICIER_ACKBR (1 << 1) +#define SH_I2C_ICIER_ACKBT (1 << 0) + +#define SH_I2C_ICSR_TDRE (1 << 7) +#define SH_I2C_ICSR_TEND (1 << 6) +#define SH_I2C_ICSR_RDRF (1 << 5) +#define SH_I2C_ICSR_NACKF (1 << 4) +#define SH_I2C_ICSR_STOP (1 << 3) +#define SH_I2C_ICSR_ALOVE (1 << 2) +#define SH_I2C_ICSR_AAS (1 << 1) +#define SH_I2C_ICSR_ADZ (1 << 0) + +#define IRQ_WAIT 1000 + +static void sh_i2c_send_stop(struct sh_i2c *base) +{ + clrbits_8(&base->iccr2, SH_I2C_ICCR2_BBSY | SH_I2C_ICCR2_SCP); +} + +static int check_icsr_bits(struct sh_i2c *base, u8 bits) +{ + int i; + + for (i = 0; i < IRQ_WAIT; i++) { + if (bits & readb(&base->icsr)) + return 0; + udelay(10); + } + + return 1; +} + +static int check_stop(struct sh_i2c *base) +{ + int ret = check_icsr_bits(base, SH_I2C_ICSR_STOP); + clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); + + return ret; +} + +static int check_tend(struct sh_i2c *base, int stop) +{ + int ret = check_icsr_bits(base, SH_I2C_ICSR_TEND); + + if (stop) { + clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); + sh_i2c_send_stop(base); + } + + clrbits_8(&base->icsr, SH_I2C_ICSR_TEND); + return ret; +} + +static int check_tdre(struct sh_i2c *base) +{ + return check_icsr_bits(base, SH_I2C_ICSR_TDRE); +} + +static int check_rdrf(struct sh_i2c *base) +{ + return check_icsr_bits(base, SH_I2C_ICSR_RDRF); +} + +static int check_bbsy(struct sh_i2c *base) +{ + int i; + + for (i = 0 ; i < IRQ_WAIT ; i++) { + if (!(SH_I2C_ICCR2_BBSY & readb(&base->iccr2))) + return 0; + udelay(10); + } + return 1; +} + +static int check_ackbr(struct sh_i2c *base) +{ + int i; + + for (i = 0 ; i < IRQ_WAIT ; i++) { + if (!(SH_I2C_ICIER_ACKBR & readb(&base->icier))) + return 0; + udelay(10); + } + + return 1; +} + +static void sh_i2c_reset(struct sh_i2c *base) +{ + setbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); + + udelay(100); + + clrbits_8(&base->iccr2, SH_I2C_ICCR2_IICRST); +} + +static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg) +{ + if (check_bbsy(base)) { + puts("i2c bus busy\n"); + goto fail; + } + + setbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); + clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); + + writeb((id << 1), &base->icdrt); + + if (check_tend(base, 0)) { + puts("TEND check fail...\n"); + goto fail; + } + + if (check_ackbr(base)) { + check_tend(base, 0); + sh_i2c_send_stop(base); + goto fail; + } + + writeb(reg, &base->icdrt); + + if (check_tdre(base)) { + puts("TDRE check fail...\n"); + goto fail; + } + + if (check_tend(base, 0)) { + puts("TEND check fail...\n"); + goto fail; + } + + return 0; +fail: + + return 1; +} + +static int +i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 *val, int size) +{ + int i; + + if (i2c_set_addr(base, id, reg)) { + puts("Fail set slave address\n"); + return 1; + } + + for (i = 0; i < size; i++) { + writeb(val[i], &base->icdrt); + check_tdre(base); + } + + check_tend(base, 1); + check_stop(base); + + udelay(100); + + clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); + clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); + sh_i2c_reset(base); + + return 0; +} + +static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) +{ + u8 ret = 0; + + if (i2c_set_addr(base, id, reg)) { + puts("Fail set slave address\n"); + goto fail; + } + + clrsetbits_8(&base->iccr2, SH_I2C_ICCR2_SCP, SH_I2C_ICCR2_BBSY); + writeb((id << 1) | 1, &base->icdrt); + + if (check_tend(base, 0)) + puts("TDRE check fail...\n"); + + clrsetbits_8(&base->iccr1, SH_I2C_ICCR1_TRS, SH_I2C_ICCR1_MST); + clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); + setbits_8(&base->icier, SH_I2C_ICIER_ACKBT); + setbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); + + /* read data (dummy) */ + ret = readb(&base->icdrr); + + if (check_rdrf(base)) { + puts("check RDRF error\n"); + goto fail; + } + + clrbits_8(&base->icsr, SH_I2C_ICSR_STOP); + udelay(1000); + + sh_i2c_send_stop(base); + + if (check_stop(base)) { + puts("check STOP error\n"); + goto fail; + } + + clrbits_8(&base->iccr1, SH_I2C_ICCR1_MTRS); + clrbits_8(&base->icsr, SH_I2C_ICSR_TDRE); + + /* data read */ + ret = readb(&base->icdrr); + +fail: + clrbits_8(&base->iccr1, SH_I2C_ICCR1_RCVD); + + return ret; +} + +#ifdef CONFIG_I2C_MULTI_BUS +static unsigned int current_bus; + +/** + * i2c_set_bus_num - change active I2C bus + * @bus: bus index, zero based + * @returns: 0 on success, non-0 on failure + */ +int i2c_set_bus_num(unsigned int bus) +{ + switch (bus) { + case 0: + base = (void *)CONFIG_SH_I2C_BASE0; + break; + case 1: + base = (void *)CONFIG_SH_I2C_BASE1; + break; + default: + printf("Bad bus: %d\n", bus); + return -1; + } + + current_bus = bus; + + return 0; +} + +/** + * i2c_get_bus_num - returns index of active I2C bus + */ +unsigned int i2c_get_bus_num(void) +{ + return current_bus; +} +#endif + +void i2c_init(int speed, int slaveaddr) +{ +#ifdef CONFIG_I2C_MULTI_BUS + current_bus = 0; +#endif + base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; + + if (speed == 400000) + iccr1_cks = 0x07; + else + iccr1_cks = 0x0F; + + nf2cyc = 1; + + /* Reset */ + sh_i2c_reset(base); + + /* ICE enable and set clock */ + writeb(SH_I2C_ICCR1_ICE | iccr1_cks, &base->iccr1); + writeb(nf2cyc, &base->nf2cyc); +} + +/* + * i2c_read: - Read multiple bytes from an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be read + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to write the data + * @len: how much byte do we want to read + * @return: 0 in case of success + */ +int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) +{ + int i = 0; + for (i = 0; i < len; i++) + buffer[i] = i2c_raw_read(base, chip, addr + i); + + return 0; +} + +/* + * i2c_write: - Write multiple bytes to an i2c device + * + * The higher level routines take into account that this function is only + * called with len < page length of the device (see configuration file) + * + * @chip: address of the chip which is to be written + * @addr: i2c data address within the chip + * @alen: length of the i2c data address (1..2 bytes) + * @buffer: where to find the data to be written + * @len: how much byte do we want to read + * @return: 0 in case of success + */ +int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) +{ + return i2c_raw_write(base, chip, addr, buffer, len); +} + +/* + * i2c_probe: - Test if a chip answers for a given i2c address + * + * @chip: address of the chip which is searched for + * @return: 0 if a chip was found, -1 otherwhise + */ +int i2c_probe(u8 chip) +{ + u8 byte; + return i2c_read(chip, 0, 0, &byte, 1); +} -- 1.7.9.1

3 2

[U-Boot] [PATCH 1/2] part_dos: align disk buffers on cache line to enable DMA and cache
by Eric Nelson 24 Apr '12

24 Apr '12

Signed-off-by: Eric Nelson <eric.nelson(a)boundarydevices.com> --- disk/part_dos.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/disk/part_dos.c b/disk/part_dos.c index b5bcb37..c028aaf 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -87,7 +87,7 @@ static int test_block_type(unsigned char *buffer) int test_part_dos (block_dev_desc_t *dev_desc) { - unsigned char buffer[dev_desc->blksz]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); if ((dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) || (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || @@ -102,7 +102,7 @@ int test_part_dos (block_dev_desc_t *dev_desc) static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative, int part_num) { - unsigned char buffer[dev_desc->blksz]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); dos_partition_t *pt; int i; @@ -166,7 +166,7 @@ static int get_partition_info_extended (block_dev_desc_t *dev_desc, int ext_part int relative, int part_num, int which_part, disk_partition_t *info) { - unsigned char buffer[dev_desc->blksz]; + ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz); dos_partition_t *pt; int i; -- 1.7.9

4 3

[U-Boot] [PATCH v4 0/10] tegra: Enable keyboard with matrix keyboard driver
by Simon Glass 23 Apr '12

23 Apr '12

Tegra2 has a built-in a keyboard controller which we can use to scan a matrix keyboard. This series brings in a driver for this and adds support for the QUERTY keyboard on Seaboard as an example. This version uses the keyboard device-tree definition here: http://patchwork.ozlabs.org/patch/134093/ so it should work seemlessly with the kernel keyboard device tree node. Part of this series is an input library which is not tied to Tegra, but hopes to be more generic. It supports converting key codes (or scan codes as they are currently called) into ASCII characters, an input FIFO, multiple key maps and dealing with duplicate key codes under key-repeat situations (when a key is held down). Half of this library is taken from keyboard.c and expanded to keep its state in a structure. The other half of this library is new. Another part of the series is a keyboard matrix library, which understands how to convert (row, column) information into key codes in a device tree. Both of these new libraries are used by the Tegra driver. If this input library is accepted, then I will update keyboard.c and i8042.c to use it. If not, then I could subsume it into the Tegra driver for now. Or I could do something else. But it didn't seem right to add a third key decoder (ignoring USB which does its own thing). Changes in v2: - Remove status = "okay" since this is the default anyway - Use correct name for get_prop_check_min_len() function Changes in v3: - Add new patch for generic keyboard input handler - Adjust decode logic to work with new Linux fdt keyboard binding - Bring in linux/input.h header file in new patch - Move to new Linux device tree mapping for Tegra keyboard - Use funcmux to set up keyboard pinmux - Use new input library to handle key decode, fifo, getc()/tstc() Changes in v4: - Implement key auto-repeat in the input layer - Move matrix keyboard handling into a separate module - Simplify driver as much as possible using input/key matrix layers - Use new key_matrix handler to deal with key matrix decode Anton Staff (3): fdt: Add fdtdec functions to read byte array tegra: fdt: Add keyboard controller definition tegra: fdt: Add keyboard definitions for Seaboard Bernie Thompson (1): input: Add support for keyboard matrix decoding from an fdt Rakesh Iyer (1): tegra: Add tegra keyboard driver Simon Glass (5): input: Add linux/input.h for key code support input: Add generic keyboard input handler tegra: Add keyboard support to funcmux tegra: Switch on console mux and use environment for console tegra: Enable keyboard for Seaboard arch/arm/cpu/armv7/tegra2/funcmux.c | 16 ++ arch/arm/dts/tegra20.dtsi | 5 + board/nvidia/dts/tegra2-seaboard.dts | 27 +++ drivers/input/Makefile | 3 + drivers/input/input.c | 429 ++++++++++++++++++++++++++++++++++ drivers/input/key_matrix.c | 208 ++++++++++++++++ drivers/input/tegra-kbc.c | 375 +++++++++++++++++++++++++++++ include/configs/seaboard.h | 9 + include/configs/tegra2-common.h | 9 +- include/fdtdec.h | 33 +++ include/input.h | 145 ++++++++++++ include/key_matrix.h | 99 ++++++++ include/linux/input.h | 155 ++++++++++++ include/tegra-kbc.h | 33 +++ lib/fdtdec.c | 25 ++ 15 files changed, 1570 insertions(+), 1 deletions(-) create mode 100644 drivers/input/input.c create mode 100644 drivers/input/key_matrix.c create mode 100644 drivers/input/tegra-kbc.c create mode 100644 include/input.h create mode 100644 include/key_matrix.h create mode 100644 include/linux/input.h create mode 100644 include/tegra-kbc.h -- 1.7.7.3

3 18

[U-Boot] [PATCH 0/2] Add support for MINI2440
by Gabriel Huau 23 Apr '12

23 Apr '12

These patches add the support for the mini2440 (s3c2440 arm). Currently, I'm supporting only boot from NOR. The first patch move the PLL initialization to SoC specific directory. I also changed boards which depend on this SoC. Gabriel Huau (2): S3C2440 : PLL Initialization should be SoC specific Add support for MINI2440 (s3c2440). arch/arm/cpu/arm920t/s3c24x0/timer.c | 36 ++++++ board/friendlyarm/mini2440/Makefile | 44 +++++++ board/friendlyarm/mini2440/mini2440.c | 121 +++++++++++++++++++ board/mpl/vcma9/lowlevel_init.S | 22 ---- board/samsung/smdk2410/smdk2410.c | 19 --- boards.cfg | 1 + include/configs/mini2440.h | 212 +++++++++++++++++++++++++++++++++ 7 files changed, 414 insertions(+), 41 deletions(-) create mode 100644 board/friendlyarm/mini2440/Makefile create mode 100644 board/friendlyarm/mini2440/mini2440.c create mode 100644 include/configs/mini2440.h -- 1.7.9.5

3 8

[U-Boot] Add support for Mini2440
by Gabriel Huau 23 Apr '12

23 Apr '12

Hi all, This is a first patch to introduce the support of the Mini2440. It's a board based on the S3C2440, arm920t. I based the support on the code of BusError (old version of u-boot). I have a few work to do again, like some clean up in the configuration file. Currently, with this patch, we can boot from NOR and the network is available (tftp, dhcp, ...). Boot from NAND will be the next step (and laters MMC). Best regards,

6 40