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April 2012

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[U-Boot] [PATCH 1/4][v4] doc:Add documentation for e500 external debugger support
by Prabhakar Kushwaha 25 Apr '12

25 Apr '12

This describes requirement of e500 and e500v2 processor to support external debugger. It also provide an insight of the configuration switch required and their description. Signed-off-by: Radu Lazarescu <radu.lazarescu(a)freescale.com> Signed-off-by: Marius Grigoras <marius.grigoras(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git branch master Changes for v2: - Recreated README.mpc85xx - Added #define in README Changes for v3: Incorporated Scott's comments - Moved config switch to "85xx CPU options" - Added TLB entry information Changes for v4: - rebased for top of the tree - updated missing secure boot temporary TLB info Tested on - SoC having E500 Family processor (P1010RDB, BSC9131RDB) - SoC having E500MC Family processor (P4080DS, P3041DS) README | 9 +++ doc/README.mpc85xx | 166 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+), 0 deletions(-) create mode 100644 doc/README.mpc85xx diff --git a/README b/README index 43074cf..2e11c88 100644 --- a/README +++ b/README @@ -374,6 +374,15 @@ The following options need to be configured: Defines the string to utilize when trying to match PCIe device tree nodes for the given platform. + CONFIG_SYS_PPC_E500_DEBUG_TLB + + Enables a temporary TLB entry to be used during boot to work + around limitations in e500v1 and e500v2 external debugger + support. This reduces the portions of the boot code where + breakpoints and single stepping do not work. The value of this + symbol should be set to the TLB1 entry to be used for this + purpose. + - Generic CPU options: CONFIG_SYS_BIG_ENDIAN, CONFIG_SYS_LITTLE_ENDIAN diff --git a/doc/README.mpc85xx b/doc/README.mpc85xx new file mode 100644 index 0000000..2753b45 --- /dev/null +++ b/doc/README.mpc85xx @@ -0,0 +1,166 @@ +External Debug Support +---------------------- + +Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some +restrictions on external debugging (JTAG). In particular, for the debugger to +be able to receive control after a single step or breakpoint: + - MSR[DE] must be set + - A valid opcode must be fetchable, through the MMU, from the debug + exception vector (IVPR + IVOR15). + +To maximize the time during which this requirement is met, U-Boot sets MSR[DE] +immediately on entry and keeps it set. It also uses a temporary TLB to keep a +mapping to a valid opcode at the debug exception vector, even if we normally +don't support exception vectors being used that early, and that's not the area +where U-Boot currently executes from. + +Note that there may still be some small windows where debugging will not work, +such as in between updating IVPR and IVOR15. + +Config Switches: +---------------- + +Please refer README section "MPC85xx External Debug Support" + +Major Config Switches during various boot Modes +---------------------------------------------- + +NOR boot + !defined(CONFIG_SYS_RAMBOOT) +NOR boot Secure + !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +RAMBOOT(SD, SPI & NAND boot) + defined(CONFIG_SYS_RAMBOOT) +RAMBOOT Secure (SD, SPI & NAND) + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SECURE_BOOT) +NAND SPL BOOT + defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL) + + +TLB Entries during u-boot execution +----------------------------------- + +Note: Sequence number is in order of execution + +A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot + + 1) TLB entry to overcome e500 v1/v2 debug restriction + Location : Label "_start_e500" + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE + Properties : 256K, AS0, I, IPROT + + 2) TLB entry for working in AS1 + Location : Label "create_init_ram_area" + TLB Entry : 15 + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE + Properties : 1M, AS1, I, G, IPROT + + 3) TLB entry for the stack during AS1 + Location : Lable "create_init_ram_area" + TLB Entry : 14 + EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + Properties : 16K, AS1, IPROT + + 4) TLB entry for CCSRBAR during AS1 execution + Location : cpu_init_early_f + TLB Entry : 13 + EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + Properties : 1M, AS1, I, G + + 5) Invalidate unproctected TLB Entries + Location : cpu_init_early_f + Invalidated: 13 + + 6) Create TLB entries as per boards/freescale/<board>/tlb.c + Location : cpu_init_early_f --> init_tlbs() + Properties : ..., AS0, ... + Please note It can overwrites previous TLB Entries. + + 7) Disable TLB Entries of AS1 + Location : cpu_init_f --> disable_tlb() + Disable : 15, 14 + + 8) Update Flash's TLB entry + Location : Board_init_r + TLB entry : Search from TLB entries + EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + Properties : Board specific size, AS0, I, G, IPROT + + +B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot + + 1) TLB entry to overcome e500 v1/v2 debug restriction + Location : Label "_start_e500" + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB +#if defined(CONFIG_SECURE_BOOT) + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + Properties : 1M, AS1, I, G, IPROT +#else + EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 + Properties : 4M, AS0, I, G, IPROT +#endif + + 2) TLB entry for working in AS1 + Location : Label "create_init_ram_area" + TLB Entry : 15 +#if defined(CONFIG_SECURE_BOOT) + EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_PBI_FLASH_WINDOW + Properties : 1M, AS1, I, G, IPROT +#else + EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000 + Properties : 4M, AS1, I, G, IPROT +#endif + + 3) TLB entry for the stack during AS1 + Location : Lable "create_init_ram_area" + TLB Entry : 14 + EPN -->RPN : CONFIG_SYS_INIT_RAM_ADDR --> CONFIG_SYS_INIT_RAM_ADDR + Properties : 16K, AS1, IPROT + + 4) TLB entry for CCSRBAR during AS1 execution + Location : cpu_init_early_f + TLB Entry : 13 + EPN -->RPN : CONFIG_SYS_CCSRBAR --> CONFIG_SYS_CCSRBAR + Properties : 1M, AS1, I, G + + 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399 + Location : cpu_init_early_f + TLB Entry : 9 + EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR + Properties : 1M, AS1, I + + 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr + Location : cpu_init_early_f --> setup_ifc + TLB Entry : Get Flash TLB + EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys + Properties : 4M, AS1, I, G, IPROT + + 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction + Location : cpu_init_early_f --> setup_ifc + TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB + EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys + Properties : 4M, AS0, I, G, IPROT + + 8) Invalidate unproctected TLB Entries + Location : cpu_init_early_f + Invalidated: 13, 9 + + 9) Create TLB entries as per boards/freescale/<board>/tlb.c + Location : cpu_init_early_f --> init_tlbs() + Properties : ..., AS0, ... + Note: It can overwrites previous TLB Entries + + 10) Disable TLB Entries of AS1 + Location : cpu_init_f --> disable_tlb() + Disable : 15, 14 + + 11) Create DDR's TLB entriy + Location : Board_init_f -> init_func_ram -> initdram + TLB entry : Search free TLB entry + + 12) Update Flash's TLB entry + Location : Board_init_r + TLB entry : Search from TLB entries + EPN -->RPN : CONFIG_SYS_FLASH_BASE --> CONFIG_SYS_FLASH_BASE_PHYS + Properties : Board specific size, AS0, I, G, IPROT -- 1.7.5.4

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[U-Boot] [PATCH] EXYNOS: Change bits per pixel value proper for u-boot.
by Donghwa Lee 25 Apr '12

25 Apr '12

vl_bpix of vidinfo_t was changed proper value for u-boot. It is used to multiple of 2 by using NBITS() macro. Signed-off-by: Donghwa Lee <dh09.lee(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- board/samsung/trats/trats.c | 2 +- drivers/video/exynos_fb.c | 2 +- drivers/video/exynos_fimd.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index f0775fd..3085de1 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -467,7 +467,7 @@ void init_panel_info(vidinfo_t *vid) vid->vl_vsp = CONFIG_SYS_LOW; vid->vl_dp = CONFIG_SYS_LOW; - vid->vl_bpix = 32; + vid->vl_bpix = 5; vid->dual_lcd_enabled = 0; /* s6e8ax0 Panel */ diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 0eb7f58..a1cf449 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -52,7 +52,7 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) unsigned long palette_size; unsigned int fb_size; - fb_size = vid->vl_row * vid->vl_col * (vid->vl_bpix >> 3); + fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3); lcd_base = lcdbase; diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index 2a60fcf..6416b90 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -110,7 +110,7 @@ static void exynos_fimd_set_buffer_address(unsigned int win_id) (struct exynos4_fb *)samsung_get_base_fimd(); start_addr = (unsigned long)lcd_base_addr; - end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8)) * + end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) * pvid->vl_row); writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 + @@ -331,7 +331,7 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) exynos_fimd_set_buffer_address(pvid->win_id); /* set buffer size */ - cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8); + cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8); writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 + EXYNOS_BUFFER_SIZE(pvid->win_id)); @@ -350,5 +350,5 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) unsigned long exynos_fimd_calc_fbsize(void) { - return pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8); + return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8); } -- 1.7.4.1

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 25 Apr '12

25 Apr '12

Hello, The following changes since commit 5697158fd27c9cc938eb3e3308e3c1483a2a1ef8: Tom Rini (1): include/configs: Remove CONFIG_SYS_64BIT_STRTOUL are available in the git repository at: git://git.denx.de/u-boot-ti master Nikita Kiryanov (1): cm-t35: add I2C multi-bus support Nobuhiro Iwamatsu (2): arm: cam_enc_4xx: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT arm: ea20: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT board/cm_t35/cm_t35.c | 6 ++++++ board/davinci/ea20/ea20.c | 4 ++-- include/configs/cam_enc_4xx.h | 2 +- include/configs/cm_t35.h | 1 + include/configs/ea20.h | 2 +- 5 files changed, 11 insertions(+), 4 deletions(-) -- Tom

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[U-Boot] [PATCH][v2] powerpc/mpc85xx:Add BSC9131 RDB Support
by Prabhakar Kushwaha 25 Apr '12

25 Apr '12

BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC is an integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements BSC9131RDB Overview ----------------- -1Gbyte DDR3 (on board DDR) -128Mbyte 2K page size NAND Flash -256 Kbit M24256 I2C EEPROM -128 Mbit SPI Flash memory -USB-ULPI -eTSEC1: Connected to RGMII PHY -eTSEC2: Connected to RGMII PHY -DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal(a)freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Note: 1) Name of PSC9131 has been changed to BSC9131 because of new nomenclature. So please reject earlier patch"powerpc/85xx:Add PSC9131 RDB Support" http://patchwork.ozlabs.org/patch/141311/ 2) This patch only adds support of SPI boot. NAND boot support will be added later as per new spl/ architeture. 3) It incorporate all review comments suggested by Wolfgang for PSC9131RDB Changes for v2: Incorporated Andy Fleming's comments - Using halt_req_mask of ccsr_gur struct - Removed board_eth_init as it is doing generic work. cpu_eth_init() will take care its functionality MAINTAINERS | 2 + board/freescale/bsc9131rdb/Makefile | 53 ++++ board/freescale/bsc9131rdb/bsc9131rdb.c | 83 ++++++ board/freescale/bsc9131rdb/ddr.c | 187 ++++++++++++++ board/freescale/bsc9131rdb/law.c | 31 +++ board/freescale/bsc9131rdb/tlb.c | 67 +++++ boards.cfg | 1 + doc/README.bsc9131rdb | 137 ++++++++++ include/configs/BSC9131RDB.h | 428 +++++++++++++++++++++++++++++++ 9 files changed, 989 insertions(+), 0 deletions(-) create mode 100644 board/freescale/bsc9131rdb/Makefile create mode 100644 board/freescale/bsc9131rdb/bsc9131rdb.c create mode 100644 board/freescale/bsc9131rdb/ddr.c create mode 100644 board/freescale/bsc9131rdb/law.c create mode 100644 board/freescale/bsc9131rdb/tlb.c create mode 100644 doc/README.bsc9131rdb create mode 100644 include/configs/BSC9131RDB.h diff --git a/MAINTAINERS b/MAINTAINERS index 708ded7..2644df4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21,6 +21,8 @@ Poonam Aggrwal <poonam.aggrwal(a)freescale.com> P2020RDB P2020 + BSC9131RDB BSC9131 + Greg Allen <gallen(a)arlut.utexas.edu> UTX8245 MPC8245 diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile new file mode 100644 index 0000000..6f4cb26 --- /dev/null +++ b/board/freescale/bsc9131rdb/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2011-2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +#COBJS-y += bsc9131rdb_mux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c new file mode 100644 index 0000000..2e0e55f --- /dev/null +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -0,0 +1,83 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <netdev.h> + + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | + MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); + setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0); + clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | + MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, + MPC85xx_PMUXCR_IFC_AD_GPIO | + MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); + + return 0; +} + +int checkboard(void) +{ + struct cpu_type *cpu; + + cpu = gd->cpu; + printf("Board: %sRDB\n", cpu->name); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c new file mode 100644 index 0000000..c753edf --- /dev/null +++ b/board/freescale/bsc9131rdb/ddr.c @@ -0,0 +1,187 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_DRAM_SIZE 1024 + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {0, 0, NULL} +}; + +unsigned long get_sdram_size(void) +{ + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); +} + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) { + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + } + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_SYS_DDR_RAW_TIMING */ +/* Micron MT41J256M8HX-15E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c new file mode 100644 index 0000000..201c147 --- /dev/null +++ b/board/freescale/bsc9131rdb/law.c @@ -0,0 +1,31 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c new file mode 100644 index 0000000..5b68f4a --- /dev/null +++ b/board/freescale/bsc9131rdb/tlb.c @@ -0,0 +1,67 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR (PA) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1) + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 3cf75c3..4f19860 100644 --- a/boards.cfg +++ b/boards.cfg @@ -762,6 +762,7 @@ P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/doc/README.bsc9131rdb b/doc/README.bsc9131rdb new file mode 100644 index 0000000..065faa3 --- /dev/null +++ b/doc/README.bsc9131rdb @@ -0,0 +1,137 @@ +Overview +-------- +- BSC9131 is integrated device that targets Femto base station market. + It combines Power Architecture e500v2 and DSP StarCore SC3850 core + technologies with MAPLE-B2F baseband acceleration processing elements. +- It's MAPLE disabled personality is called 9231. + +The BSC9131 SoC includes the following function and features: +. Power Architecture subsystem including a e500 processor with 256-Kbyte shared + L2 cache +. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache +. The Multi Accelerator Platform Engine for Femto BaseStation Baseband + Processing (MAPLE-B2F) +. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, + Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, + and CRC algorithms +. Consists of accelerators for Convolution, Filtering, Turbo Encoding, + Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion + operations +. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with + ECC, up to 400-MHz clock/800 MHz data rate +. Dedicated security engine featuring trusted boot +. DMA controller +. OCNDMA with four bidirectional channels +. Interfaces +. Two triple-speed Gigabit Ethernet controllers featuring network acceleration + including IEEE 1588. v2 hardware support and virtualization (eTSEC) +. eTSEC 1 supports RGMII/RMII +. eTSEC 2 supports RGMII +. High-speed USB 2.0 host and device controller with ULPI interface +. Enhanced secure digital (SD/MMC) host controller (eSDHC) +. Antenna interface controller (AIC), supporting three industry standard + JESD207/three custom ADI RF interfaces (two dual port and one single port) + and three MAXIM's MaxPHY serial interfaces +. ADI lanes support both full duplex FDD support and half duplex TDD support +. Universal Subscriber Identity Module (USIM) interface that facilitates + communication to SIM cards or Eurochip pre-paid phone cards +. TDM with one TDM port +. Two DUART, four eSPI, and two I2C controllers +. Integrated Flash memory controller (IFC) +. TDM with 256 channels +. GPIO +. Sixteen 32-bit timers + +The e500 core subsystem within the Power Architecture consists of the following: +. 32-Kbyte L1 instruction cache +. 32-Kbyte L1 data cache +. 256-Kbyte L2 cache/L2 memory/L2 stash +. programmable interrupt controller (PIC) +. Debug support +. Timers + +The SC3850 core subsystem consists of the following: +. 32 Kbyte 8-way level 1 instruction cache (L1 ICache) +. 32 Kbyte 8-way level 1 data cache (L1 DCache) +. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory) +. Memory management unit (MMU) +. Enhanced programmable interrupt controller (EPIC) +. Debug and profiling unit (DPU) +. Two 32-bit timers + +BSC9131RDB board Overview +------------------------- + 1Gbyte DDR3 (on board DDR) + 128Mbyte 2K page size NAND Flash + 256 Kbit M24256 I2C EEPROM + 128 Mbit SPI Flash memory + USB-ULPI + eTSEC1: Connected to RGMII PHY + eTSEC2: Connected to RGMII PHY + DUART interface: supports one UARTs up to 115200 bps for console display + USIM connector + +Frequency Combinations Supported +-------------------------------- +Core MHz/CCB MHz/DDR(MT/s) +1. 1000/500/800 +2. 800/400/667 + +Boot Methods Supported +----------------------- +1. NAND Flash +2. SPI Flash + +Default Boot Method +-------------------- +NAND boot + +Building U-boot +-------------- +To build the u-boot for BSC9131RDB: +1. NAND Flash + make BSC9131RDB_NAND +2. SPI Flash + make BSC9131RDB_SPIFLASH + +Memory map +----------- + 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable + 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M + 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K + 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K + 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K + 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M + 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M + +Flashing Images +--------------- +To place a new u-boot image in the NAND flash and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot-nand.bin + nand erase 0 100000 + nand write 1000000 0 100000 + reset + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 bsc9131rdb.dtb + bootm 1000000 2000000 c00000 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h new file mode 100644 index 0000000..fd076e0 --- /dev/null +++ b/include/configs/BSC9131RDB.h @@ -0,0 +1,428 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * BSC9131 RDB board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_BSC9131RDB +#define CONFIG_BSC9131 +#define CONFIG_NAND_FSL_IFC +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_TSEC_ENET +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* enable branch predition */ + +#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01ffffff + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#undef CONFIG_SYS_DDR_RAW_TIMING +#undef CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#ifndef __ASSEMBLY__ +extern unsigned long get_sdram_size(void); +#endif +#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ + /* CONFIG_SYS_IMMR */ + +/* + * Memory map + * + * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable + * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M + * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K + * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K + * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M + * + */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NO_FLASH + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ + | FTIM0_NAND_TWP(0x06) \ + | FTIM0_NAND_TWCHT(0x03) \ + | FTIM0_NAND_TWH(0x04)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ + | FTIM1_NAND_TWBE(0x23) \ + | FTIM1_NAND_TRR(0x08) \ + | FTIM1_NAND_TRP(0x05)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ + | FTIM2_NAND_TREH(0x04) \ + | FTIM2_NAND_TWHRE(0x3f)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NAND */ +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +/* I2C EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_CMD_I2C + + +#define CONFIG_FSL_ESPI +/* eSPI - Enhanced SPI */ +#ifdef CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 + +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x400 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_HOSTNAME BSC9131rdb +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "loadaddr=1000000\0" \ + "bootfile=uImage\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=bsc9131rdb.dtb\0" \ + "bdev=sda1\0" \ + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ + "othbootargs=ramdisk_size=600000 \0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ -- 1.7.5.4

1 0

[U-Boot] [PATCH][v2] powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
by Prabhakar Kushwaha 25 Apr '12

25 Apr '12

- BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Note: Name of PSC9131 has been changed to BSC9131 because of new nomenclature. So please reject earlier patch: "PSC9131/PSC9130/PSC9231 Processor Support Added" http://patchwork.ozlabs.org/patch/141048/ Changes for v2: Incorporated Andy Fleming's comments - Added halt_req_mask in ccsr_gur struct arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/cpu.c | 6 +- arch/powerpc/include/asm/config_mpc85xx.h | 14 +++- arch/powerpc/include/asm/immap_85xx.h | 119 ++++++++++++++++++++++++++++- arch/powerpc/include/asm/processor.h | 5 + 5 files changed, 142 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 058d609..e3a7c14 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o +COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 0365ca8..7340f69 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -113,6 +113,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P5010, P5010_E, 1), CPU_TYPE_ENTRY(P5020, P5020, 2), CPU_TYPE_ENTRY(P5020, P5020_E, 2), + CPU_TYPE_ENTRY(BSC9130, 9130, 1), + CPU_TYPE_ENTRY(BSC9130, 9130_E, 1), + CPU_TYPE_ENTRY(BSC9131, 9131, 1), + CPU_TYPE_ENTRY(BSC9131, 9131_E, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8654625..d1b9d5b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -459,6 +459,18 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#elif defined(CONFIG_BSC9131) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b08cb8..f2ffcc5 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao(a)motorola.com) @@ -1870,7 +1870,11 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 #else +#ifdef CONFIG_BSC9131 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#else #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#endif #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 #endif #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 @@ -2017,6 +2021,50 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 #define MPC85xx_PMUXCR_SPI 0x00000000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 +#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 +#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 +#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 +#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 +#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 +#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 +#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 +#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 +#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 +#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 +#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 +#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 +#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 +#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 +#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 +#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 +#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 +#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 +#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 +#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 +#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 +#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 +#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 +#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 +#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 +#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 +#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 +#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 +#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 +#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 +#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 +#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 +#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 +#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C +#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 +#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 +#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 @@ -2047,7 +2095,69 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 +#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 +#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 +#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 +#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 +#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 +#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 +#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 +#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 +#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 +#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 +#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 +#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 +#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 + u32 pmuxcr3; + +#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 +#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 +#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 +#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 +#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 +#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 +#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 +#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 + u32 pmuxcr4; +#else u8 res6[8]; +#endif u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 #define MPC85xx_DEVDISR_PCI2 0x40000000 @@ -2102,7 +2212,14 @@ typedef struct ccsr_gur { u32 ddrdllcr; /* DDR DLL control */ u8 res14[12]; u32 lbcdllcr; /* LBC DLL control */ +#if defined(CONFIG_BSC9131) + u8 res15[12]; + u32 halt_req_mask; +#define HALTED_TO_HALT_REQ_MASK_0 0x80000000 + u8 res18[232]; +#else u8 res15[248]; +#endif u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */ u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */ u32 ddrioovcr; /* DDR IO Override Control */ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 4e32639..c9e112c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1136,6 +1136,11 @@ #define SVR_8641 0x809000 #define SVR_8641D 0x809001 +#define SVR_9130 0x860001 +#define SVR_9130_E 0x860801 +#define SVR_9131 0x860000 +#define SVR_9131_E 0x860800 + #define SVR_Unknown 0xFFFFFF #define _GLOBAL(n)\ -- 1.7.5.4

1 0

[U-Boot] [PATCH] powerpc/mpc85xx:Add BSC9131 RDB Support
by Prabhakar Kushwaha 25 Apr '12

25 Apr '12

BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC is an integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements BSC9131RDB Overview ----------------- -1Gbyte DDR3 (on board DDR) -128Mbyte 2K page size NAND Flash -256 Kbit M24256 I2C EEPROM -128 Mbit SPI Flash memory -USB-ULPI -eTSEC1: Connected to RGMII PHY -eTSEC2: Connected to RGMII PHY -DUART interface: supports one UARTs up to 115200 bps for console display Apart from the above it also consists various peripherals to support DSP functionalities. This patch adds support for mainly Power side functionalities and peripherals Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal(a)freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Note: 1) Name of PSC9131 has been changed to BSC9131 because of new nomenclature. So please reject earlier patch"powerpc/85xx:Add PSC9131 RDB Support" http://patchwork.ozlabs.org/patch/141311/ 2) This patch only adds support of SPI boot. NAND boot support will be added later as per new spl/ architeture. 3) It incorporate all review comments suggested by Wolfgang for PSC9131RDB MAINTAINERS | 2 + board/freescale/bsc9131rdb/Makefile | 53 ++++ board/freescale/bsc9131rdb/bsc9131rdb.c | 116 +++++++++ board/freescale/bsc9131rdb/ddr.c | 187 ++++++++++++++ board/freescale/bsc9131rdb/law.c | 31 +++ board/freescale/bsc9131rdb/tlb.c | 67 +++++ boards.cfg | 1 + doc/README.bsc9131rdb | 137 ++++++++++ include/configs/BSC9131RDB.h | 428 +++++++++++++++++++++++++++++++ 9 files changed, 1022 insertions(+), 0 deletions(-) create mode 100644 board/freescale/bsc9131rdb/Makefile create mode 100644 board/freescale/bsc9131rdb/bsc9131rdb.c create mode 100644 board/freescale/bsc9131rdb/ddr.c create mode 100644 board/freescale/bsc9131rdb/law.c create mode 100644 board/freescale/bsc9131rdb/tlb.c create mode 100644 doc/README.bsc9131rdb create mode 100644 include/configs/BSC9131RDB.h diff --git a/MAINTAINERS b/MAINTAINERS index 46f63a0..6024a15 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -21,6 +21,8 @@ Poonam Aggrwal <poonam.aggrwal(a)freescale.com> P2020RDB P2020 + BSC9131RDB BSC9131 + Greg Allen <gallen(a)arlut.utexas.edu> UTX8245 MPC8245 diff --git a/board/freescale/bsc9131rdb/Makefile b/board/freescale/bsc9131rdb/Makefile new file mode 100644 index 0000000..6f4cb26 --- /dev/null +++ b/board/freescale/bsc9131rdb/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2011-2012 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +#COBJS-y += bsc9131rdb_mux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/bsc9131rdb/bsc9131rdb.c b/board/freescale/bsc9131rdb/bsc9131rdb.c new file mode 100644 index 0000000..43757fb --- /dev/null +++ b/board/freescale/bsc9131rdb/bsc9131rdb.c @@ -0,0 +1,116 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <netdev.h> + + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS); + + clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43); + setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK | + MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD); + setbits_be32(HALTED_TO_HALT_REQ_MASK_REG, HALTED_TO_HALT_REQ_MASK_0); + clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK | + MPC85xx_PMUXCR_IFC_AD17_GPO_MASK, + MPC85xx_PMUXCR_IFC_AD_GPIO | + MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM); + + return 0; +} + +int checkboard(void) +{ + struct cpu_type *cpu; + + cpu = gd->cpu; + printf("Board: %sRDB\n", cpu->name); + + return 0; +} + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[2]; + + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif + +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + tsec_eth_init(bis, tsec_info, num); + + return num; +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + + fdt_fixup_dr_usb(blob, bd); +} +#endif diff --git a/board/freescale/bsc9131rdb/ddr.c b/board/freescale/bsc9131rdb/ddr.c new file mode 100644 index 0000000..c753edf --- /dev/null +++ b/board/freescale/bsc9131rdb/ddr.c @@ -0,0 +1,187 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <asm/fsl_law.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_DDR_RAW_TIMING +#define CONFIG_SYS_DRAM_SIZE 1024 + +fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = { + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS, + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG, + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2, + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800, + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800, + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800, + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL, + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2, + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800, + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800, + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL, + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800, + .ddr_data_init = CONFIG_MEM_INIT_VALUE, + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800, + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR, + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR, + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4, + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL, + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800, + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR, + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1, + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2 +}; + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {750, 850, &ddr_cfg_regs_800}, + {0, 0, NULL} +}; + +unsigned long get_sdram_size(void) +{ + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE); +} + +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +phys_size_t fixed_sdram(void) +{ + int i; + char buf[32]; + fsl_ddr_cfg_regs_t ddr_cfg_regs; + phys_size_t ddr_size; + ulong ddr_freq, ddr_freq_mhz; + + ddr_freq = get_ddr_freq(0); + ddr_freq_mhz = ddr_freq / 1000000; + + printf("Configuring DDR for %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + + for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) { + if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) && + (ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) { + memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings, + sizeof(ddr_cfg_regs)); + break; + } + } + + if (fixed_ddr_parm_0[i].max_freq == 0) { + panic("Unsupported DDR data rate %s MT/s data rate\n", + strmhz(buf, ddr_freq)); + } + + ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0); + + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size, + LAW_TRGT_IF_DDR_1) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + } + + return ddr_size; +} + +#else /* CONFIG_SYS_DDR_RAW_TIMING */ +/* Micron MT41J256M8HX-15E */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 1073741824u, + .capacity = 1073741824u, + .primary_sdram_width = 32, + .ec_sdram_width = 0, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 15, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 0, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1870, + .caslat_X = 0x1e << 4, /* 5,6,7,8 */ + .tAA_ps = 13125, + .tWR_ps = 15000, + .tRCD_ps = 13125, + .tRRD_ps = 7500, + .tRP_ps = 13125, + .tRAS_ps = 37500, + .tRC_ps = 50625, + .tRFC_ps = 160000, + .tWTR_ps = 7500, + .tRTP_ps = 7500, + .refresh_rate_ps = 7800000, + .tFAW_ps = 37500, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 6; + popts->cpo_override = 0x1f; + popts->write_data_delay = 2; + popts->half_strength_driver_enable = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x8; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} + +#endif /* CONFIG_SYS_DDR_RAW_TIMING */ diff --git a/board/freescale/bsc9131rdb/law.c b/board/freescale/bsc9131rdb/law.c new file mode 100644 index 0000000..201c147 --- /dev/null +++ b/board/freescale/bsc9131rdb/law.c @@ -0,0 +1,31 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/bsc9131rdb/tlb.c b/board/freescale/bsc9131rdb/tlb.c new file mode 100644 index 0000000..5b68f4a --- /dev/null +++ b/board/freescale/bsc9131rdb/tlb.c @@ -0,0 +1,67 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR (PA) */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#if defined(CONFIG_SYS_RAMBOOT) + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_1G, 1), +#endif + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1M, 1) + +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 28cc345..26f0f96 100644 --- a/boards.cfg +++ b/boards.cfg @@ -768,6 +768,7 @@ P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 +BSC9131RDB_SPIFLASH powerpc mpc85xx bsc9131rdb freescale - BSC9131RDB:BSC9131RDB,SPIFLASH stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/doc/README.bsc9131rdb b/doc/README.bsc9131rdb new file mode 100644 index 0000000..065faa3 --- /dev/null +++ b/doc/README.bsc9131rdb @@ -0,0 +1,137 @@ +Overview +-------- +- BSC9131 is integrated device that targets Femto base station market. + It combines Power Architecture e500v2 and DSP StarCore SC3850 core + technologies with MAPLE-B2F baseband acceleration processing elements. +- It's MAPLE disabled personality is called 9231. + +The BSC9131 SoC includes the following function and features: +. Power Architecture subsystem including a e500 processor with 256-Kbyte shared + L2 cache +. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache +. The Multi Accelerator Platform Engine for Femto BaseStation Baseband + Processing (MAPLE-B2F) +. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, + Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, + and CRC algorithms +. Consists of accelerators for Convolution, Filtering, Turbo Encoding, + Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion + operations +. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with + ECC, up to 400-MHz clock/800 MHz data rate +. Dedicated security engine featuring trusted boot +. DMA controller +. OCNDMA with four bidirectional channels +. Interfaces +. Two triple-speed Gigabit Ethernet controllers featuring network acceleration + including IEEE 1588. v2 hardware support and virtualization (eTSEC) +. eTSEC 1 supports RGMII/RMII +. eTSEC 2 supports RGMII +. High-speed USB 2.0 host and device controller with ULPI interface +. Enhanced secure digital (SD/MMC) host controller (eSDHC) +. Antenna interface controller (AIC), supporting three industry standard + JESD207/three custom ADI RF interfaces (two dual port and one single port) + and three MAXIM's MaxPHY serial interfaces +. ADI lanes support both full duplex FDD support and half duplex TDD support +. Universal Subscriber Identity Module (USIM) interface that facilitates + communication to SIM cards or Eurochip pre-paid phone cards +. TDM with one TDM port +. Two DUART, four eSPI, and two I2C controllers +. Integrated Flash memory controller (IFC) +. TDM with 256 channels +. GPIO +. Sixteen 32-bit timers + +The e500 core subsystem within the Power Architecture consists of the following: +. 32-Kbyte L1 instruction cache +. 32-Kbyte L1 data cache +. 256-Kbyte L2 cache/L2 memory/L2 stash +. programmable interrupt controller (PIC) +. Debug support +. Timers + +The SC3850 core subsystem consists of the following: +. 32 Kbyte 8-way level 1 instruction cache (L1 ICache) +. 32 Kbyte 8-way level 1 data cache (L1 DCache) +. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory) +. Memory management unit (MMU) +. Enhanced programmable interrupt controller (EPIC) +. Debug and profiling unit (DPU) +. Two 32-bit timers + +BSC9131RDB board Overview +------------------------- + 1Gbyte DDR3 (on board DDR) + 128Mbyte 2K page size NAND Flash + 256 Kbit M24256 I2C EEPROM + 128 Mbit SPI Flash memory + USB-ULPI + eTSEC1: Connected to RGMII PHY + eTSEC2: Connected to RGMII PHY + DUART interface: supports one UARTs up to 115200 bps for console display + USIM connector + +Frequency Combinations Supported +-------------------------------- +Core MHz/CCB MHz/DDR(MT/s) +1. 1000/500/800 +2. 800/400/667 + +Boot Methods Supported +----------------------- +1. NAND Flash +2. SPI Flash + +Default Boot Method +-------------------- +NAND boot + +Building U-boot +-------------- +To build the u-boot for BSC9131RDB: +1. NAND Flash + make BSC9131RDB_NAND +2. SPI Flash + make BSC9131RDB_SPIFLASH + +Memory map +----------- + 0x0000_0000 0x7FFF_FFFF DDR 1G cacheable + 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M + 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + 0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K + 0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K + 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K + 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M + 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M + +Flashing Images +--------------- +To place a new u-boot image in the NAND flash and then boot +with that new image temporarily, use this: + tftp 1000000 u-boot-nand.bin + nand erase 0 100000 + nand write 1000000 0 100000 + reset + +Using the Device Tree Source File +--------------------------------- +To create the DTB (Device Tree Binary) image file, +use a command similar to this: + + dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb + +Likely, that .dts file will come from here; + + linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts + +Booting Linux +------------- +Place a linux uImage in the TFTP disk area. + + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp c00000 bsc9131rdb.dtb + bootm 1000000 2000000 c00000 diff --git a/include/configs/BSC9131RDB.h b/include/configs/BSC9131RDB.h new file mode 100644 index 0000000..fd076e0 --- /dev/null +++ b/include/configs/BSC9131RDB.h @@ -0,0 +1,428 @@ +/* + * Copyright 2011-2012 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * BSC9131 RDB board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_BSC9131RDB +#define CONFIG_BSC9131 +#define CONFIG_NAND_FSL_IFC +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/ +#define CONFIG_FSL_IFC /* Enable IFC Support */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_TSEC_ENET +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */ + +#define CONFIG_HWCONFIG +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* enable branch predition */ + +#define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x01ffffff + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#undef CONFIG_SYS_DDR_RAW_TIMING +#undef CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef + +#ifndef __ASSEMBLY__ +extern unsigned long get_sdram_size(void); +#endif +#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 + +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 + +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 +#define CONFIG_SYS_DDR_RCW_1 0x00000000 +#define CONFIG_SYS_DDR_RCW_2 0x00000000 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */ +#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 +#define CONFIG_SYS_DDR_TIMING_4 0x00000001 +#define CONFIG_SYS_DDR_TIMING_5 0x02401400 + +#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 +#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 +#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 +#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf +#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 +#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 +#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 +#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100 +#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +/* relocated CCSRBAR */ +#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */ + /* CONFIG_SYS_IMMR */ + +/* + * Memory map + * + * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable + * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M + * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M + * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K + * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K + * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K + * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M + * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M + * + */ + +/* + * IFC Definitions + */ +#define CONFIG_SYS_NO_FLASH + +/* NAND Flash on IFC */ +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE + +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \ + | CSPR_MSEL_NAND /* MSEL = NAND */ \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) + +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2Byes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2K */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/ + +/* NAND Flash Timing Params */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x08) \ + | FTIM0_NAND_TWP(0x06) \ + | FTIM0_NAND_TWCHT(0x03) \ + | FTIM0_NAND_TWH(0x04)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x18) \ + | FTIM1_NAND_TWBE(0x23) \ + | FTIM1_NAND_TRR(0x08) \ + | FTIM1_NAND_TRP(0x05)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \ + | FTIM2_NAND_TREH(0x04) \ + | FTIM2_NAND_TWHRE(0x3f)) +#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x22) + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NAND */ +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 + +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ +#define CONFIG_SYS_INIT_RAM_END 0x00004000/* End of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/ +#define CONFIG_SYS_I2C_OFFSET 0x3000 + +/* I2C EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_CMD_I2C + + +#define CONFIG_FSL_ESPI +/* eSPI - Enhanced SPI */ +#ifdef CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 +#endif + +#if defined(CONFIG_TSEC_ENET) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 3 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define TSEC1_PHYIDX 0 + +#define TSEC2_PHYIDX 0 + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ + +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#else +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) +#define CONFIG_ENV_SIZE 0x400 +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_ELF +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SETEXPR + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI +#define CONFIG_CMD_USB +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_EHCI_FSL +#define CONFIG_USB_STORAGE +#define CONFIG_HAS_FSL_DR_USB +#endif + +/* + * Environment Configuration + */ + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#endif + +#define CONFIG_HOSTNAME BSC9131rdb +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=" CONFIG_UBOOTPATH "\0" \ + "loadaddr=1000000\0" \ + "bootfile=uImage\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=bsc9131rdb.dtb\0" \ + "bdev=sda1\0" \ + "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \ + "othbootargs=ramdisk_size=600000 \0" \ + "usbext2boot=setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "usb start;" \ + "ext2load usb 0:4 $loadaddr $bootfile;" \ + "ext2load usb 0:4 $fdtaddr $fdtfile;" \ + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */ -- 1.7.5.4

2 2

[U-Boot] [PATCH] powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support
by Prabhakar Kushwaha 25 Apr '12

25 Apr '12

- BSC9131 is integrated device that targets Femto base station market. It combines Power Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F baseband acceleration processing elements. - BSC9130 is exactly same as BSC9131 except that the max e500v2 core and DSP core frequencies are 800M(these are 1G in case of 9131). - BSC9231 is similar to BSC9131 except no MAPLE The BSC9131 SoC includes the following function and features: . Power Architecture subsystem including a e500 processor with 256-Kbyte shared L2 cache . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache . The Multi Accelerator Platform Engine for Femto BaseStation Baseband Processing (MAPLE-B2F) . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding, Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing, and CRC algorithms . Consists of accelerators for Convolution, Filtering, Turbo Encoding, Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion operations . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with ECC, up to 400-MHz clock/800 MHz data rate . Dedicated security engine featuring trusted boot . DMA controller . OCNDMA with four bidirectional channels . Interfaces . Two triple-speed Gigabit Ethernet controllers featuring network acceleration including IEEE 1588. v2 hardware support and virtualization (eTSEC) . eTSEC 1 supports RGMII/RMII . eTSEC 2 supports RGMII . High-speed USB 2.0 host and device controller with ULPI interface . Enhanced secure digital (SD/MMC) host controller (eSDHC) . Antenna interface controller (AIC), supporting three industry standard JESD207/three custom ADI RF interfaces (two dual port and one single port) and three MAXIM's MaxPHY serial interfaces . ADI lanes support both full duplex FDD support and half duplex TDD support . Universal Subscriber Identity Module (USIM) interface that facilitates communication to SIM cards or Eurochip pre-paid phone cards . TDM with one TDM port . Two DUART, four eSPI, and two I2C controllers . Integrated Flash memory controller (IFC) . TDM with 256 channels . GPIO . Sixteen 32-bit timers The DSP portion of the SoC consists of DSP core (SC3850) and various accelerators pertaining to DSP operations. This patch takes care of code pertaining to power side functionality only. Signed-off-by: Ramneek Mehresh <ramneek.mehresh(a)freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain(a)freescale.com> Signed-off-by: Akhil Goyal <Akhil.Goyal(a)freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Rajan Srivastava <rajan.srivastava(a)freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Note: Name of PSC9131 has been changed to BSC9131 because of new nomenclature. So please reject earlier patch: "PSC9131/PSC9130/PSC9231 Processor Support Added" http://patchwork.ozlabs.org/patch/141048/ arch/powerpc/cpu/mpc85xx/Makefile | 1 + arch/powerpc/cpu/mpc8xxx/cpu.c | 6 +- arch/powerpc/include/asm/config_mpc85xx.h | 14 +++- arch/powerpc/include/asm/immap_85xx.h | 117 ++++++++++++++++++++++++++++- arch/powerpc/include/asm/processor.h | 5 + 5 files changed, 140 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 058d609..e3a7c14 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -70,6 +70,7 @@ COBJS-$(CONFIG_PPC_P3041) += ddr-gen3.o COBJS-$(CONFIG_PPC_P3060) += ddr-gen3.o COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o COBJS-$(CONFIG_PPC_P5020) += ddr-gen3.o +COBJS-$(CONFIG_BSC9131) += ddr-gen3.o COBJS-$(CONFIG_CPM2) += ether_fcc.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 0365ca8..7340f69 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Copyright 2009-2012 Freescale Semiconductor, Inc. * * This file is derived from arch/powerpc/cpu/mpc85xx/cpu.c and * arch/powerpc/cpu/mpc86xx/cpu.c. Basically this file contains @@ -113,6 +113,10 @@ struct cpu_type cpu_type_list [] = { CPU_TYPE_ENTRY(P5010, P5010_E, 1), CPU_TYPE_ENTRY(P5020, P5020, 2), CPU_TYPE_ENTRY(P5020, P5020_E, 2), + CPU_TYPE_ENTRY(BSC9130, 9130, 1), + CPU_TYPE_ENTRY(BSC9130, 9130_E, 1), + CPU_TYPE_ENTRY(BSC9131, 9131, 1), + CPU_TYPE_ENTRY(BSC9131, 9131_E, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 8654625..d1b9d5b 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -1,5 +1,5 @@ /* - * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011-2012 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -459,6 +459,18 @@ #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003474 +#elif defined(CONFIG_BSC9131) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_TSECV2 +#define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 9b08cb8..9e52705 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1,7 +1,7 @@ /* * MPC85xx Internal Memory Map * - * Copyright 2007-2011 Freescale Semiconductor, Inc. + * Copyright 2007-2012 Freescale Semiconductor, Inc. * * Copyright(c) 2002,2003 Motorola Inc. * Xianghua Xiao (x.xiao(a)motorola.com) @@ -1870,7 +1870,11 @@ typedef struct ccsr_gur { #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 #else +#ifdef CONFIG_BSC9131 +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#else #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 +#endif #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 #endif #define MPC85xx_PORPLLSR_QE_RATIO 0x3e000000 @@ -2017,6 +2021,50 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR_SPI_MASK 0x00600000 #define MPC85xx_PMUXCR_SPI 0x00000000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ 0x40000000 +#define MPC85xx_PMUXCR_TSEC2_USB 0xC0000000 +#define MPC85xx_PMUXCR_TSEC2_1588_PPS 0x10000000 +#define MPC85xx_PMUXCR_TSEC2_1588_RSVD 0x30000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO 0x04000000 +#define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK 0x0C000000 +#define MPC85xx_PMUXCR_IFC_AD15_GPIO 0x01000000 +#define MPC85xx_PMUXCR_IFC_AD15_TIMER2 0x02000000 +#define MPC85xx_PMUXCR_IFC_AD16_GPO8 0x00400000 +#define MPC85xx_PMUXCR_IFC_AD16_MSRCID0 0x00800000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO 0x00100000 +#define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK 0x00300000 +#define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP 0x00200000 +#define MPC85xx_PMUXCR_IFC_CS2_GPO65 0x00040000 +#define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI 0x00080000 +#define MPC85xx_PMUXCR_SDHC_USIM 0x00010000 +#define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK 0x00020000 +#define MPC85xx_PMUXCR_SDHC_GPIO77 0x00030000 +#define MPC85xx_PMUXCR_SDHC_RESV 0x00004000 +#define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD 0x00008000 +#define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4 0x0000C000 +#define MPC85xx_PMUXCR_USB_CLK_UART_SIN 0x00001000 +#define MPC85xx_PMUXCR_USB_CLK_GPIO69 0x00002000 +#define MPC85xx_PMUXCR_USB_CLK_TIMER3 0x00003000 +#define MPC85xx_PMUXCR_USB_UART_GPIO0 0x00000400 +#define MPC85xx_PMUXCR_USB_RSVD 0x00000C00 +#define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN 0x00000800 +#define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL 0x00000100 +#define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72 0x00000200 +#define MPC85xx_PMUXCR_USB_D1_2_RSVD 0x00000300 +#define MPC85xx_PMUXCR_USB_DIR_GPIO2 0x00000040 +#define MPC85xx_PMUXCR_USB_DIR_TIMER1 0x00000080 +#define MPC85xx_PMUXCR_USB_DIR_MCP_B 0x000000C0 +#define MPC85xx_PMUXCR_SPI1_UART3 0x00000010 +#define MPC85xx_PMUXCR_SPI1_SIM 0x00000020 +#define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74 0x00000030 +#define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B 0x00000004 +#define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen 0x00000008 +#define MPC85xx_PMUXCR_SPI1_CS2_GPO75 0x0000000C +#define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM 0x00000001 +#define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen 0x00000002 +#define MPC85xx_PMUXCR_SPI1_CS3_GPO76 0x00000003 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 @@ -2047,7 +2095,69 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f8000 #define MPC85xx_PMUXCR2_USB 0x00150000 #endif +#if defined(CONFIG_BSC9131) +#define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD 0X40000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS 0X80000000 +#define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42 0xC0000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2 0x10000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK 0x20000000 +#define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43 0x30000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD 0x04000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B 0x08000000 +#define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44 0x0C000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED 0x01000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD 0x02000000 +#define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45 0x03000000 +#define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP 0x00400000 +#define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B 0x00800000 +#define MPC85xx_PMUXCR2_ANT1_TIMER5 0x00100000 +#define MPC85xx_PMUXCR2_ANT1_TSEC_1588 0x00200000 +#define MPC85xx_PMUXCR2_ANT1_GPIO95_19 0x00300000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK 0x00040000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD 0x00080000 +#define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20 0x000C0000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0 0x00010000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3 0x00020000 +#define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84 0x00030000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4 0x00004000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7 0x00008000 +#define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88 0x0000C000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK 0x00001000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9 0x00002000 +#define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22 0x00003000 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7 0x00000400 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11 0x00000800 +#define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24 0x00000C00 +#define MPC85xx_PMUXCR2_ANT2_RSVD 0x00000100 +#define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA 0x00000300 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB 0x00000040 +#define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO 0x000000C0 +#define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD 0x00000010 +#define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8 0x00000020 +#define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61 0x00000030 +#define MPC85xx_PMUXCR2_ANT3_AGC_GPO53 0x00000004 +#define MPC85xx_PMUXCR2_ANT3_DO_TDM 0x00000001 +#define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49 0x00000002 + u32 pmuxcr3; + +#define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM 0x40000000 +#define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51 0x80000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B 0x10000000 +#define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53 0x20000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B 0x04000000 +#define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54 0x08000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT 0x01000000 +#define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56 0x02000000 +#define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT 0x00400000 +#define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57 0x00800000 +#define MPC85xx_PMUXCR3_SPI2_CS2_GPO93 0x00100000 +#define MPC85xx_PMUXCR3_SPI2_CS3_GPO94 0x00040000 +#define MPC85xx_PMUXCR3_ANT2_AGC_RSVD 0x00010000 +#define MPC85xx_PMUXCR3_ANT2_GPO89 0x00030000 + u32 pmuxcr4; +#else u8 res6[8]; +#endif u32 devdisr; /* Device disable control */ #define MPC85xx_DEVDISR_PCI1 0x80000000 #define MPC85xx_DEVDISR_PCI2 0x40000000 @@ -2533,4 +2643,9 @@ struct ccsr_rman { #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET) +#if defined(CONFIG_BSC9131) +#define HALTED_TO_HALT_REQ_MASK_REG 0xff7e0e30 +#define HALTED_TO_HALT_REQ_MASK_0 0x80000000 +#endif + #endif /*__IMMAP_85xx__*/ diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 4e32639..c9e112c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1136,6 +1136,11 @@ #define SVR_8641 0x809000 #define SVR_8641D 0x809001 +#define SVR_9130 0x860001 +#define SVR_9130_E 0x860801 +#define SVR_9131 0x860000 +#define SVR_9131_E 0x860800 + #define SVR_Unknown 0xFFFFFF #define _GLOBAL(n)\ -- 1.7.5.4

2 2

[U-Boot] [PATCH v2 0/4] DFU initial implementation
by Andrzej Pietrasiewicz 24 Apr '12

24 Apr '12

Dear All, This is a quick-and-dirty proof-of-concept for splitting the dfu into core dfu gadget, generic parts of dfu backend, dfu command and target-specific implementation for Goni. This patch definitely needs some coding style cleanups. Also, the place for storing generic parts of dfu was chosen somewhat arbitrary and can be changed if a better alternative is found. The original idea of the flash_entity was to equip it with a void * to a context structure, which is not interpreted by the dfu gadget but passed to the dfu backend and understood there. I am still hesitating if flash_entity_ctx is generic enough to be generalized, as of now I assumed it is. If it wasn't then less common code could be extracted. @Stefan: you need the first 3 patches from this series, and then you need to implement your own target-specific parts. In fact, all is expected from the target, is to provide board_dfu_init/cleanup pair and call register_flash_entities. Andrzej Pietrasiewicz (4): dfu: protocol initial implementation dfu: generic backend parts dfu: command implementation dfu: target-specific implementation for Goni Makefile | 1 + board/samsung/goni/Makefile | 2 + board/samsung/goni/flash.c | 341 ++++++++++++++++ board/samsung/goni/flash.h | 28 ++ board/samsung/goni/goni.c | 17 + common/Makefile | 1 + common/cmd_dfu.c | 51 +++ drivers/usb/dfu/Makefile | 33 ++ drivers/usb/dfu/dfu.c | 109 +++++ drivers/usb/dfu/fat.c | 77 ++++ drivers/usb/dfu/mmc.c | 124 ++++++ drivers/usb/gadget/Makefile | 1 + drivers/usb/gadget/dfu.c | 920 +++++++++++++++++++++++++++++++++++++++++++ drivers/usb/gadget/dfu.h | 171 ++++++++ include/configs/s5p_goni.h | 4 + include/dfu.h | 28 ++ include/dfu_backend.h | 71 ++++ include/flash_entity.h | 39 ++ include/mbr.h | 49 +++ 19 files changed, 2067 insertions(+), 0 deletions(-) create mode 100644 board/samsung/goni/flash.c create mode 100644 board/samsung/goni/flash.h create mode 100644 common/cmd_dfu.c create mode 100644 drivers/usb/dfu/Makefile create mode 100644 drivers/usb/dfu/dfu.c create mode 100644 drivers/usb/dfu/fat.c create mode 100644 drivers/usb/dfu/mmc.c create mode 100644 drivers/usb/gadget/dfu.c create mode 100644 drivers/usb/gadget/dfu.h create mode 100644 include/dfu.h create mode 100644 include/dfu_backend.h create mode 100644 include/flash_entity.h create mode 100644 include/mbr.h

6 21

[U-Boot] [PATCH 1/2] LCD: drawing 32bpp uncompressed bitmap image
by Donghwa Lee 24 Apr '12

24 Apr '12

This patch supports drawing 32bpp uncompressed bitmap image. Signed-off-by: Donghwa Lee <dh09.lee(a)samsung.com> Signed-off-by: Kyungmin.park <kyungmin.park(a)samsung.com> --- common/lcd.c | 26 ++++++++++++++++++++++---- 1 files changed, 22 insertions(+), 4 deletions(-) diff --git a/common/lcd.c b/common/lcd.c index bf1a6a9..a7b04d2 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -645,14 +645,14 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bpix = NBITS(panel_info.vl_bpix); - if ((bpix != 1) && (bpix != 8) && (bpix != 16)) { + if ((bpix != 1) && (bpix != 8) && (bpix != 16) && (bpix != 32)) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, bmp_bpix); return 1; } /* We support displaying 8bpp BMPs on 16bpp LCDs */ - if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16)) { + if (bpix != bmp_bpix && (bmp_bpix != 8 || bpix != 16 || bpix != 32)) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, le16_to_cpu(bmp->header.bit_count)); @@ -669,7 +669,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) cmap = (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) cmap = (ushort *)&(cp->lcd_cmap[255*sizeof(ushort)]); -#elif !defined(CONFIG_ATMEL_LCD) +#elif !defined(CONFIG_ATMEL_LCD) && !defined(CONFIG_EXYNOS_FB) cmap = panel_info.cmap; #endif @@ -739,8 +739,14 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) height = panel_info.vl_row - y; bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); + +#ifndef CONFIG_EXYNOS_FB fb = (uchar *) (lcd_base + (y + height - 1) * lcd_line_length + x * bpix / 8); +#else + fb = (uchar *) (lcd_base + (y + height) * + (panel_info.vl_col * (bpix / 8)) + x * (bpix / 8)); +#endif switch (bmp_bpix) { case 1: /* pass through */ @@ -788,9 +794,21 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bmap += (padded_line - width) * 2; fb -= (width * 2 + lcd_line_length); } + break; #endif /* CONFIG_BMP_16BPP */ - + case 32: + for (i = 0; i < height; ++i) { + for (j = 0; j < width; j++) { + *(fb++) = *(bmap++); + *(fb++) = *(bmap++); + *(fb++) = *(bmap++); + *(fb++) = *(bmap++); + } + fb -= ((panel_info.vl_col * + (bpix / 8)) + width * (bpix / 8)); + } + break; default: break; }; -- 1.7.4.1

2 1

[U-Boot] [PATCH 2/2] EXYNOS: draw 32bpp bitmap TIZEN logo
by Donghwa Lee 24 Apr '12

24 Apr '12

This patches support drawing 32bpp bitmap TIZEN logo in exynos fb. asm/arch/trats_logo.h data is compressed by zip and decomressed at the exynos fb driver. And vl_bpix of vidinfo_t is changed proper value for u-boot. Signed-off-by: Donghwa Lee <dh09.lee(a)samsung.com> Signed-off-by: Kyungmin park <kyungmin.park(a)samsung.com> --- arch/arm/include/asm/arch-exynos/trats_logo.h | 5070 +++++++++++++++++++++++++ board/samsung/trats/trats.c | 2 +- drivers/video/exynos_fb.c | 40 +- drivers/video/exynos_fimd.c | 6 +- include/configs/trats.h | 4 +- 5 files changed, 5116 insertions(+), 6 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/trats_logo.h diff --git a/arch/arm/include/asm/arch-exynos/trats_logo.h b/arch/arm/include/asm/arch-exynos/trats_logo.h new file mode 100644 index 0000000..a595abd --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/trats_logo.h @@ -0,0 +1,5070 @@ +/* + * (C) Copyright 2012 Samsung Electronics + * Donghwa Lee <dh09.lee(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * aint with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#define TRATS_LOGO_WIDTH 520 +#define TRATS_LOGO_HEIGHT 120 +#define TRATS_LOGO_BPP 32 + +unsigned char trats_logo[]={ +0x1f,0x8b,0x08,0x08,0xe0,0x6f,0x8f,0x4f,0x00,0x03,0x74,0x72,0x61,0x74,0x73,0x2e, +0x62,0x6d,0x70,0x00,0xbc,0x5c,0xe9,0x53,0x1c,0x57,0x92,0xaf,0x6a,0xa0,0x81,0xa6, +0xb9,0x1b,0x04,0x48,0x02,0x04,0x7d,0xd0,0xdd,0x1c,0x12,0xba,0xd1,0x61,0x59,0x48, +0x96,0x67,0xc6,0xf6,0x8e,0x2f,0xc5,0x44,0xec,0x7c,0xd9,0x88,0x89,0x99,0xfd,0x60, +0x8f,0x23,0xc6,0x3b,0xf6,0xce,0x8c,0x67,0x6d,0x79,0xac,0x70,0x6c,0x38,0x24,0x3c, +0x06,0x74,0x41,0x83,0x0c,0x36,0x97,0x04,0x88,0xc3,0x5c,0x7d,0x09,0x79,0x3d,0x92, +0x6c,0x61,0x4b,0x8a,0x18,0xeb,0x1f,0xd9,0x3f,0x60,0x2b,0xab,0x3b,0xab,0xf3,0x65, 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+0xe2,0x73,0xc4,0x9b,0x4b,0xf8,0xd4,0x25,0xcb,0x11,0xf8,0xbb,0xc6,0x72,0x34,0xc1, +0x9b,0x5b,0x70,0x50,0xf2,0xaa,0x8a,0x35,0x81,0xe7,0x07,0xb5,0xb5,0x94,0xfa,0xab, +0x95,0xef,0x85,0xfd,0x02,0xd3,0x68,0x92,0x6e,0x85,0xf4,0x05,0xdb,0xc4,0xd0,0x58, +0x2b,0xd0,0xa6,0x4a,0x06,0x22,0x60,0xac,0xc1,0xcb,0x51,0xd8,0x93,0x53,0x3e,0x9c, +0xd2,0xdd,0x64,0x9e,0x98,0xeb,0xd6,0x85,0x7c,0xcd,0x14,0x38,0xfd,0x43,0x71,0x78, +0x25,0xf8,0x96,0x01,0x8d,0xe8,0x8c,0x0a,0x3c,0x26,0xde,0xab,0x28,0x5e,0x3f,0x6c, +0xdd,0xbc,0x57,0xdf,0x3e,0xc1,0x43,0xc2,0xe3,0xe4,0xc2,0x61,0x15,0xf9,0xf1,0x5f, +0x69,0xd7,0x24,0x79,0xb6,0xa9,0x03,0x00,0x00 +}; diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index f9894b1..d067bb4 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -467,7 +467,7 @@ void init_panel_info(vidinfo_t *vid) vid->vl_vsp = CONFIG_SYS_LOW; vid->vl_dp = CONFIG_SYS_LOW; - vid->vl_bpix = 32; + vid->vl_bpix = 5; vid->dual_lcd_enabled = 0; /* s6e8ax0 Panel */ diff --git a/drivers/video/exynos_fb.c b/drivers/video/exynos_fb.c index 0eb7f58..c111855 100644 --- a/drivers/video/exynos_fb.c +++ b/drivers/video/exynos_fb.c @@ -22,6 +22,7 @@ #include <config.h> #include <common.h> +#include <malloc.h> #include <lcd.h> #include <asm/io.h> #include <asm/arch/cpu.h> @@ -29,6 +30,7 @@ #include <asm/arch/clk.h> #include <asm/arch/mipi_dsim.h> #include <asm/arch/system.h> +#include <asm/arch/trats_logo.h> #include "exynos_fb.h" @@ -52,7 +54,7 @@ static void exynos_lcd_init_mem(void *lcdbase, vidinfo_t *vid) unsigned long palette_size; unsigned int fb_size; - fb_size = vid->vl_row * vid->vl_col * (vid->vl_bpix >> 3); + fb_size = vid->vl_row * vid->vl_col * (NBITS(vid->vl_bpix) >> 3); lcd_base = lcdbase; @@ -67,6 +69,38 @@ static void exynos_lcd_init(vidinfo_t *vid) exynos_fimd_lcd_init(vid); } +static void draw_logo(void *lcdbase) +{ + int x, y; + unsigned int in_len, width, height; + unsigned long out_len = + (ARRAY_SIZE(trats_logo) * sizeof(*trats_logo)) + 1; + void *dst = NULL; + + width = TRATS_LOGO_WIDTH; + height = TRATS_LOGO_HEIGHT; + x = ((panel_width - width) >> 1); + y = ((panel_height - height) >> 1) - 5; + + in_len = width * height * 8; + dst = malloc(in_len); + if (dst == NULL) { + printf("Error: malloc in gunzip failed!\n"); + return; + } + if (gunzip(dst, in_len, (uchar *)trats_logo, &out_len) != 0) { + free(dst); + return; + } + if (out_len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) + printf("Image could be truncated" + " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n"); + + lcd_display_bitmap((ulong)dst, x, y); + + free(dst); +} + static void lcd_panel_on(vidinfo_t *vid) { udelay(vid->init_delay); @@ -113,6 +147,10 @@ void lcd_ctrl_init(void *lcdbase) exynos_lcd_init_mem(lcdbase, &panel_info); + memset(lcdbase, 0, panel_width * panel_height * + (NBITS(panel_info.vl_bpix) >> 3)); + draw_logo(lcdbase); + exynos_lcd_init(&panel_info); } diff --git a/drivers/video/exynos_fimd.c b/drivers/video/exynos_fimd.c index cd2b1b6..8f2d667 100644 --- a/drivers/video/exynos_fimd.c +++ b/drivers/video/exynos_fimd.c @@ -110,7 +110,7 @@ static void exynos_fimd_set_buffer_address(unsigned int win_id) (struct exynos4_fb *)samsung_get_base_fimd(); start_addr = (unsigned long)lcd_base_addr; - end_addr = start_addr + ((pvid->vl_col * (pvid->vl_bpix / 8)) * + end_addr = start_addr + ((pvid->vl_col * (NBITS(pvid->vl_bpix) / 8)) * pvid->vl_row); writel(start_addr, (unsigned int)&fimd_ctrl->vidw00add0b0 + @@ -331,7 +331,7 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) exynos_fimd_set_buffer_address(pvid->win_id); /* set buffer size */ - cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * pvid->vl_bpix / 8); + cfg = EXYNOS_VIDADDR_PAGEWIDTH(pvid->vl_col * NBITS(pvid->vl_bpix) / 8); writel(cfg, (unsigned int)&fimd_ctrl->vidw00add2 + EXYNOS_BUFFER_SIZE(pvid->win_id)); @@ -350,5 +350,5 @@ void exynos_fimd_lcd_init(vidinfo_t *vid) unsigned long exynos_fimd_calc_fbsize(void) { - return pvid->vl_col * pvid->vl_row * (pvid->vl_bpix / 8); + return pvid->vl_col * pvid->vl_row * (NBITS(pvid->vl_bpix) / 8); } diff --git a/include/configs/trats.h b/include/configs/trats.h index 5f913ca..b326035 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -216,9 +216,11 @@ /* LCD */ #define CONFIG_EXYNOS_FB #define CONFIG_LCD +#define CONFIG_CMD_BMP #define CONFIG_FB_ADDR 0x52504000 #define CONFIG_S6E8AX0 #define CONFIG_EXYNOS_MIPI_DSIM -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1280 * 720 * 4) +#define CONFIG_VIDEO_BMP_GZIP +#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (500 * 120 * 4) #endif /* __CONFIG_H */ -- 1.7.4.1

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