April 2012 - U-Boot

[U-Boot] [PATCH] mtd, nand: move some printfs to debug output.
by Heiko Schocher 19 May '12

19 May '12

current U-Boot shows on startup (for example on the enbw_cmc board) the following printfs from the nand subsystem: Flash: 2 MiB NAND: Bad block table found at page 65472, version 0x01 Bad block table found at page 65408, version 0x01 nand_read_bbt: Bad block at 0x000002980000 nand_read_bbt: Bad block at 0x000003240000 128 MiB MMC: davinci: 0 remove them to debug output, so it shows with this patch: Flash: 2 MiB NAND: 128 MiB MMC: davinci: 0 Signed-off-by: Heiko Schocher <hs(a)denx.de> Cc: Scott Wood <scottwood(a)freescale.com> --- [hs@pollux u-boot]$ ./tools/checkpatch.pl 20120215/0001-mtd-nand-move-some-printfs-to-debug-output.patch total: 0 errors, 0 warnings, 25 lines checked NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX MULTISTATEMENT_MACRO_USE_DO_WHILE 20120215/0001-mtd-nand-move-some-printfs-to-debug-output.patch has no obvious style problems and is ready for submission. [hs@pollux u-boot]$ drivers/mtd/nand/nand_bbt.c | 13 +++++++------ 1 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 2b730e0..bf12df8 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -259,10 +259,10 @@ static int read_bbt(struct mtd_info *mtd, uint8_t *buf, int page, int num, mtd->ecc_stats.bbtblocks++; continue; } - /* Leave it for now, if its matured we can move this - * message to MTD_DEBUG_LEVEL0 */ - printk(KERN_DEBUG "nand_read_bbt: Bad block at 0x%012llx\n", - (loff_t)((offs << 2) + (act >> 1)) << this->bbt_erase_shift); + MTDDEBUG(MTD_DEBUG_LEVEL0, "nand_read_bbt: " \ + "Bad block at 0x%012llx\n", + (loff_t)((offs << 2) + (act >> 1)) + << this->bbt_erase_shift); /* Factory marked bad or worn out ? */ if (tmp == 0) this->bbt[offs + (act >> 3)] |= 0x3 << (act & 0x06); @@ -651,8 +651,9 @@ static int search_bbt(struct mtd_info *mtd, uint8_t *buf, struct nand_bbt_descr if (td->pages[i] == -1) printk(KERN_WARNING "Bad block table not found for chip %d\n", i); else - printk(KERN_DEBUG "Bad block table found at page %d, version 0x%02X\n", td->pages[i], - td->version[i]); + MTDDEBUG(MTD_DEBUG_LEVEL0, "Bad block table found " \ + "at page %d, version 0x%02X\n", td->pages[i], + td->version[i]); } return 0; } -- 1.7.7.6

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[U-Boot] [PATCH] nand_util: correct YAFFS image write function
by Liu, Wentao 19 May '12

19 May '12

In function nand_write_skip_bad(),for YAFFS filesystem part, write_oob() will return 0 when success, so when rval equals 0, it should continue to write the next page, and no break. Signed-off-by: Wentao, Liu <wentao.liu(a)intel.com> diff --git a/drivers/mtd/nand/nand_util.c b/drivers/mtd/nand/nand_util.c index 60c778e..7ed8b18 100644 --- a/drivers/mtd/nand/nand_util.c +++ b/drivers/mtd/nand/nand_util.c @@ -564,7 +564,7 @@ int nand_write_skip_bad(nand_info_t *nand, loff_t offset, size_t *length, ops.oobbuf = ops.datbuf + pagesize; rval = nand->write_oob(nand, offset, &ops); - if (!rval) + if (rval != 0) break; offset += pagesize; -- 1.7.4.1

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[U-Boot] [PATCH 1/2] nand: extend .raw accesses to work on multiple pages
by Scott Wood 19 May '12

19 May '12

A use for this is to read, modify, erase, and write an entire block as a single unit, as a replacement for the biterr command. This way gives more flexibility in that you can also test multiple bit errors, errors in the ECC, etc. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- common/cmd_nand.c | 95 +++++++++++++++++++++++++++++++++++++++------------- doc/README.nand | 16 ++++---- 2 files changed, 79 insertions(+), 32 deletions(-) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index bae630d..4456706 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -11,7 +11,7 @@ * Added 16-bit nand support * (C) 2004 Texas Instruments * - * Copyright 2010 Freescale Semiconductor + * Copyright 2010, 2012 Freescale Semiconductor * The portions of this file whose copyright is held by Freescale and which * are not considered a derived work of GPL v2-only code may be distributed * and/or modified under the terms of the GNU General Public License as @@ -390,6 +390,41 @@ static void nand_print_and_set_info(int idx) setenv("nand_erasesize", buf); } +static int raw_access(nand_info_t *nand, ulong addr, loff_t off, ulong count, + int read) +{ + int ret = 0; + size_t rwsize; + + while (count--) { + /* Raw access */ + mtd_oob_ops_t ops = { + .datbuf = (u8 *)addr, + .oobbuf = ((u8 *)addr) + nand->writesize, + .len = nand->writesize, + .ooblen = nand->oobsize, + .mode = MTD_OOB_RAW + }; + + rwsize = nand->writesize + nand->oobsize; + if (read) + ret = nand->read_oob(nand, off, &ops); + else + ret = nand->write_oob(nand, off, &ops); + + if (ret) { + printf("%s: error at offset %llx, ret %d\n", + __func__, (long long)off, ret); + break; + } + + addr += nand->writesize + nand->oobsize; + off += nand->writesize; + } + + return ret; +} + int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { int i, ret = 0; @@ -568,7 +603,9 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { size_t rwsize; + ulong pagecount = 1; int read; + int raw; if (argc < 4) goto usage; @@ -577,13 +614,36 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) read = strncmp(cmd, "read", 4) == 0; /* 1 = read, 0 = write */ printf("\nNAND %s: ", read ? "read" : "write"); - if (arg_off_size(argc - 3, argv + 3, &dev, &off, &size) != 0) - return 1; nand = &nand_info[dev]; - rwsize = size; s = strchr(cmd, '.'); + + if (!strcmp(s, ".raw")) { + raw = 1; + + if (arg_off(argv[3], &dev, &off, &size)) + return 1; + + if (argc > 4 && !str2long(argv[4], &pagecount)) { + printf("'%s' is not a number\n", argv[4]); + return 1; + } + + if (pagecount * nand->writesize > size) { + puts("Size exceeds partition or device limit\n"); + return -1; + } + + rwsize = pagecount * (nand->writesize + nand->oobsize); + } else { + if (arg_off_size(argc - 3, argv + 3, &dev, + &off, &size) != 0) + return 1; + + rwsize = size; + } + if (!s || !strcmp(s, ".jffs2") || !strcmp(s, ".e") || !strcmp(s, ".i")) { if (read) @@ -609,7 +669,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) return 1; } ret = nand_write_skip_bad(nand, off, &rwsize, - (u_char *)addr, WITH_YAFFS_OOB); + (u_char *)addr, + WITH_INLINE_OOB); #endif } else if (!strcmp(s, ".oob")) { /* out-of-band data */ @@ -623,22 +684,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) ret = nand->read_oob(nand, off, &ops); else ret = nand->write_oob(nand, off, &ops); - } else if (!strcmp(s, ".raw")) { - /* Raw access */ - mtd_oob_ops_t ops = { - .datbuf = (u8 *)addr, - .oobbuf = ((u8 *)addr) + nand->writesize, - .len = nand->writesize, - .ooblen = nand->oobsize, - .mode = MTD_OOB_RAW - }; - - rwsize = nand->writesize + nand->oobsize; - - if (read) - ret = nand->read_oob(nand, off, &ops); - else - ret = nand->write_oob(nand, off, &ops); + } else if (raw) { + ret = raw_access(nand, addr, off, pagecount, read); } else { printf("Unknown nand command suffix '%s'.\n", s); return 1; @@ -732,9 +779,9 @@ U_BOOT_CMD( "nand write - addr off|partition size\n" " read/write 'size' bytes starting at offset 'off'\n" " to/from memory address 'addr', skipping bad blocks.\n" - "nand read.raw - addr off|partition\n" - "nand write.raw - addr off|partition\n" - " Use read.raw/write.raw to avoid ECC and access the page as-is.\n" + "nand read.raw - addr off|partition [count]\n" + "nand write.raw - addr off|partition [count]\n" + " Use read.raw/write.raw to avoid ECC and access the flash as-is.\n" #ifdef CONFIG_CMD_NAND_TRIMFFS "nand write.trimffs - addr off|partition size\n" " write 'size' bytes starting at offset 'off' from memory address\n" diff --git a/doc/README.nand b/doc/README.nand index 04a87c9..1602b5e 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -94,14 +94,14 @@ Commands: of data for one 512-byte page or 2 256-byte pages. There is no check for bad blocks. - nand read.raw addr ofs|partition - Read page from `ofs' in NAND flash to `addr'. This reads the raw page, - so ECC is avoided and the OOB area is read as well. - - nand write.raw addr ofs|partition - Write page from `addr' to `ofs' in NAND flash. This writes the raw page, - so ECC is avoided and the OOB area is written as well, making the whole - page written as-is. + nand read.raw addr ofs|partition [count] + nand write.raw addr ofs|partition [count] + Read or write one or more pages at "ofs" in NAND flash, from or to + "addr" in memory. This is a raw access, so ECC is avoided and the + OOB area is transferred as well. If count is absent, it is assumed + to be one page. As with .yaffs2 accesses, the data is formatted as + a packed sequence of "data, oob, data, oob, ..." -- no alignment of + individual pages is maintained. Configuration Options: -- 1.7.7.rc3.4.g8d714

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[U-Boot] [PATCH v3] Correct corrupted NAND Flash access on KARO TX25 modules
by Gachet Daniel 19 May '12

19 May '12

Hi Stefano, You will find below the new patch for the NAND flash access problem on the TX25 module. I hope this version is fulfilling your expectations. Cordially, Daniel diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c index 35e89a0..fe1cef6 100644 --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@ -1290,7 +1290,9 @@ static void mxc_setup_config1(void) uint16_t tmp; tmp = readw(&host->regs->nfc_config1); +#ifndef CONFIG_NAND_MXC_NFC_TWO_CYCLES tmp |= NFC_ONE_CYCLE; +#endif tmp |= NFC_4_8N_ECC; writew(tmp, &host->regs->nfc_config1); if (host->pagesize_2k) diff --git a/include/configs/tx25.h b/include/configs/tx25.h index 87bd8a6..0c9aeb8 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -110,6 +110,7 @@ /* NAND */ #define CONFIG_NAND_MXC #define CONFIG_NAND_MXC_V1_1 +#define CONFIG_NAND_MXC_NFC_TWO_CYCLES #define CONFIG_MXC_NAND_REGS_BASE (0xBB000000) #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE (0xBB000000)

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[U-Boot] [PATCH v3] Allow for parallel builds and saved output
by Andy Fleming 18 May '12

18 May '12

The MAKEALL script cleverly runs make with the appropriate options to use all of the cores on the system, but your average U-Boot build can't make much use of more than a few cores. If you happen to have a many-core server, your builds will leave most of the system idle. In order to make full use of such a system, we need to build multiple targets in parallel, and this requires directing make output into multiple directories. We add a BUILD_NBUILDS variable, which allows users to specify how many builds to run in parallel. When BUILD_NBUILDS is set greater than 1, we redefine BUILD_DIR for each build to be ${BUILD_DIR}/${target}. Also, we make "./build" the default BUILD_DIR when BUILD_NBUILDS is greater than 1. MAKEALL now tracks which builds are still running, and when one finishes, it starts a new build. Once each build finishes, we run "make tidy" on its directory, to reduce the footprint. As a result, we are left with a build directory with all of the built targets still there for use, which means anyone who wanted to use MAKEALL as part of a test harness can now do so. Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- v2: - Update to keep BUILD_NBUILDS builds in flight, rather than batching - Clean up style things - Defer error output until build completion to make output *slightly* more readable v3: - Add BUILD_MANY variable to clarify logic - Added comment for done/skip prefixes, and renamed for clarity - Changed CURRENT_COUNT to CURRENT_CNT to match TOTAL_CNT - Put build wait logic into its own manage_build function - Used wildcards to delete build management files - Fixed a bug where error-less builds printed an error Once again, my unscientific tests on my 24-thread box: time ./MAKEALL 83xx real 4m2.951s user 26m6.534s sys 4m0.070s time ./MAKEALL 86xx real 0m27.271s user 3m10.706s sys 0m27.123s time BUILD_NBUILDS=50 BUILD_NCPUS=1 ./MAKEALL 86xx real 0m38.430s user 2m11.601s sys 0m18.610s time BUILD_NBUILDS=50 BUILD_NCPUS=1 ./MAKEALL 83xx real 1m15.642s user 15m2.125s sys 2m25.818s time BUILD_NBUILDS=50 BUILD_NCPUS=1 ./MAKEALL 85xx real 4m29.840s user 80m30.641s sys 10m49.643s Looks like 86xx was affected by having only 5 boards: time BUILD_NBUILDS=10 BUILD_NCPUS=4 ./MAKEALL 86xx real 0m11.887s user 2m22.299s sys 0m20.894s MAKEALL | 137 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++------- 1 files changed, 122 insertions(+), 15 deletions(-) diff --git a/MAKEALL b/MAKEALL index e5da6f1..e6c801c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -34,6 +34,7 @@ usage() CROSS_COMPILE cross-compiler toolchain prefix (default: "") MAKEALL_LOGDIR output all logs to here (default: ./LOG/) BUILD_DIR output build directory (default: ./) + BUILD_NBUILDS number of parallel targets (default: 1) Examples: - build all Power Architecture boards: @@ -178,11 +179,22 @@ else LOG_DIR="LOG" fi -if [ ! "${BUILD_DIR}" ] ; then - BUILD_DIR="." +: ${BUILD_NBUILDS:=1} +BUILD_MANY=0 + +if [ "${BUILD_NBUILDS}" -gt 1 ] ; then + BUILD_MANY=1 + : ${BUILD_DIR:=./build} + mkdir -p "${BUILD_DIR}/ERR" + find "${BUILD_DIR}/ERR/" -type f -exec rm -f {} + fi -[ -d ${LOG_DIR} ] || mkdir ${LOG_DIR} || exit 1 +: ${BUILD_DIR:=.} + +OUTPUT_PREFIX="${BUILD_DIR}" + +[ -d ${LOG_DIR} ] || mkdir "${LOG_DIR}" || exit 1 +find "${LOG_DIR}/" -type f -exec rm -f {} + LIST="" @@ -190,6 +202,8 @@ LIST="" ERR_CNT=0 ERR_LIST="" TOTAL_CNT=0 +CURRENT_CNT=0 +OLDEST_IDX=1 RC=0 # Helper funcs for parsing boards.cfg @@ -592,8 +606,26 @@ list_target() { echo "" } +# Each finished build will have a file called ${donep}${n}, +# where n is the index of the build. Each build +# we've already noted as finished will have ${skipp}${n}. +# The code managing the build process will use this information +# to ensure that only BUILD_NBUILDS builds are in flight at once +donep="${LOG_DIR}/._done_" +skipp="${LOG_DIR}/._skip_" + build_target() { target=$1 + build_idx=$2 + + if [ $BUILD_MANY == 1 ] ; then + output_dir="${OUTPUT_PREFIX}/${target}" + mkdir -p "${output_dir}" + else + output_dir="${OUTPUT_PREFIX}" + fi + + export BUILD_DIR="${output_dir}" if [ "$ONLY_LIST" == 'y' ] ; then list_target ${target} @@ -603,30 +635,75 @@ build_target() { ${MAKE} distclean >/dev/null ${MAKE} -s ${target}_config - ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \ - | tee ${LOG_DIR}/$target.ERR + ${MAKE} ${JOBS} all \ + >${LOG_DIR}/$target.MAKELOG 2> ${LOG_DIR}/$target.ERR # Check for 'make' errors if [ ${PIPESTATUS[0]} -ne 0 ] ; then RC=1 fi - if [ -s ${LOG_DIR}/$target.ERR ] ; then - ERR_CNT=$((ERR_CNT + 1)) - ERR_LIST="${ERR_LIST} $target" + if [ $BUILD_MANY == 1 ] ; then + ${MAKE} tidy + + if [ -s ${LOG_DIR}/${target}.ERR ] ; then + touch ${OUTPUT_PREFIX}/ERR/${target} + else + rm ${LOG_DIR}/${target}.ERR + fi else - rm ${LOG_DIR}/$target.ERR + if [ -s ${LOG_DIR}/${target}.ERR ] ; then + : $(( ERR_CNT += 1 )) + ERR_LIST="${ERR_LIST} $target" + else + rm ${LOG_DIR}/${target}.ERR + fi fi - TOTAL_CNT=$((TOTAL_CNT + 1)) - - OBJS=${BUILD_DIR}/u-boot - if [ -e ${BUILD_DIR}/spl/u-boot-spl ]; then - OBJS="${OBJS} ${BUILD_DIR}/spl/u-boot-spl" + OBJS=${output_dir}/u-boot + if [ -e ${output_dir}/spl/u-boot-spl ]; then + OBJS="${OBJS} ${output_dir}/spl/u-boot-spl" fi ${CROSS_COMPILE}size ${OBJS} | tee -a ${LOG_DIR}/$target.MAKELOG + + [ -e "${LOG_DIR}/${target}.ERR" ] && cat "${LOG_DIR}/${target}.ERR" + + #echo "Writing ${donep}${build_idx}" + touch "${donep}${build_idx}" } + +manage_builds() { + search_idx=${OLDEST_IDX} + #echo "Searching ${OLDEST_IDX} to ${TOTAL_CNT}" + while true; do + if [ -e "${donep}${search_idx}" ] ; then + # echo "Found ${donep}${search_idx}" + : $(( CURRENT_CNT-- )) + [ ${OLDEST_IDX} -eq ${search_idx} ] && + : $(( OLDEST_IDX++ )) + + # Only want to count it once + rm -f "${donep}${search_idx}" + touch "${skipp}${search_idx}" + elif [ -e "${skipp}${search_idx}" ] ; then + [ ${OLDEST_IDX} -eq ${search_idx} ] && + : $(( OLDEST_IDX++ )) + fi + #echo "Checking search ${search_idx} vs ${TOTAL_CNT}" + : $(( search_idx++ )) + if [ ${search_idx} -gt ${TOTAL_CNT} ] ; then + #echo "Checking current ${CURRENT_CNT} vs ${BUILD_NBUILDS}" + if [ ${CURRENT_CNT} -ge ${BUILD_NBUILDS} ] ; then + search_idx=${OLDEST_IDX} + sleep 1 + else + break + fi + fi + done +} + build_targets() { for t in "$@" ; do # If a LIST_xxx var exists, use it. But avoid variable @@ -639,7 +716,26 @@ build_targets() { if [ -n "${list}" ] ; then build_targets ${list} else - build_target ${t} + : $((TOTAL_CNT += 1)) + : $((CURRENT_CNT += 1)) + rm -f "${donep}${TOTAL_CNT}" + rm -f "${skipp}${TOTAL_CNT}" + build_target ${t} ${TOTAL_CNT} & + fi + + # We maintain a running count of all the builds we have done. + # Each finished build will have a file called ${donep}${n}, + # where n is the index of the build. Each build + # we've already noted as finished will have ${skipp}${n}. + # We track the current index via TOTAL_CNT, and the oldest + # index. When we exceed the maximum number of parallel builds, + # We look from oldest to current for builds that have completed, + # and update the current count and oldest index as appropriate. + # If we've gone through the entire list, wait a second, and + # reprocess the entire list until we find a build that has + # completed + if [ ${CURRENT_CNT} -ge ${BUILD_NBUILDS} ] ; then + manage_builds fi done } @@ -648,6 +744,16 @@ build_targets() { print_stats() { if [ "$ONLY_LIST" == 'y' ] ; then return ; fi + + rm -f ${donep}* ${skipp}* + + if [ $BUILD_MANY == 1 ] && [ -e "${OUTPUT_PREFIX}/ERR" ] ; then + ERR_LIST=$(ls ${OUTPUT_PREFIX}/ERR/) + ERR_CNT=`ls -1 ${OUTPUT_PREFIX}/ERR/ | wc | awk '{print $1}'` + else + ERR_CNT=0 + fi + echo "" echo "--------------------- SUMMARY ----------------------------" echo "Boards compiled: ${TOTAL_CNT}" @@ -666,3 +772,4 @@ set -- ${SELECTED} "$@" # run PowerPC by default [ $# = 0 ] && set -- powerpc build_targets "$@" +wait -- 1.7.3.4

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[U-Boot] [PATCH] Remove extra boards from LIST_ixp
by Andy Fleming 18 May '12

18 May '12

pdnb3 and scpu are explicitly on LIST_ixp, even though they are also specified in boards.cfg as having cpu ixp. This means that they will be built twice when doing ./MAKEALL ixp, or ./MAKEALL arm. This was pointless before, but actually breaks things if you launch both builds at the same time, as they overwrite each other. Signed-off-by: Andy Fleming <afleming(a)freescale.com> --- MAKEALL | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/MAKEALL b/MAKEALL index e6c801c..5b610bf 100755 --- a/MAKEALL +++ b/MAKEALL @@ -365,10 +365,7 @@ LIST_at91="$(boards_by_soc at91)" LIST_pxa="$(boards_by_cpu pxa)" -LIST_ixp="$(boards_by_cpu ixp) - pdnb3 \ - scpu \ -" +LIST_ixp="$(boards_by_cpu ixp)" ######################################################################### ## ARM groups -- 1.7.3.4

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[U-Boot] [PATCH 1/2] FSL/eSDHC: enable the peripheral clock to detect the card
by Chang-Ming.Huang＠freescale.com 18 May '12

18 May '12

From: Jerry Huang <Chang-Ming.Huang(a)freescale.com> According to the card detection of p1/p2 paltform RM, we should set SYSCTL[PEREN] to enable the clock. Otherwise, after booting the u-boot, and then inserting the SD card, the SD card can't be detected. Signed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> CC: Andy Fleming <afleming(a)gmail.com> --- drivers/mmc/fsl_esdhc.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a2f35e3..1682a79 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -491,6 +491,8 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) /* First reset the eSDHC controller */ esdhc_reset(regs); + esdhc_write32(&regs->sysctl, SYSCTL_PEREN); + mmc->priv = cfg; mmc->send_cmd = esdhc_send_cmd; mmc->set_ios = esdhc_set_ios; -- 1.7.5.4

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Re: [U-Boot] Status of fsl_elbc_nand driver and 4k page NAND / 4bit ECC
by Rafael Beims 16 May '12

16 May '12

On Wed, Apr 11, 2012 at 9:22 PM, Scott Wood <scottwood(a)freescale.com> wrote: > On 04/11/2012 07:14 PM, Rafael Beims wrote: > >> Hello Scott, >> On Wed, Apr 11, 2012 at 6:54 PM, Scott Wood <scottwood(a)freescale.com >> <mailto:scottwood@freescale.**com <scottwood(a)freescale.com>>> wrote: >> >> On 04/11/2012 04:28 PM, Rafael Beims wrote: >> >> Hello, >> I work with several MPC83xx boards in our company, and a while >> ago we were >> informed that the NAND chip we used was being discontinued. The >> only >> options for a replacement were the newer 4k page ones. >> Specifically, we are >> using now the Micron 29F8G08ABABA (8 gigabit). >> >> I was sweeping the repositories and this list's archives and I'm >> with the >> impression that these chips are not supported yet. I saw some >> patches sent >> hacking the driver to allow for the use of 4k pages. >> >> Additionally, I'm worried about the use of the 4 bit ECC lib >> (BCH), as it >> seems to me that the fsl_elbc_nand driver is not prepared to use >> a software >> ECC config. Maybe I'm wrong, but it seems that the driver always >> uses the 1 >> bit HW ECC that's present in freescale's controller. >> >> Because of this, I would like to ask for an overall status of >> these things. >> What can I expect to be working? What are the main areas of >> concern? >> If there is no complete implementation yet (as I saw some >> patches being >> rejected / not merged yet), what is currently missing? >> What is the area where most work is needed? >> >> >> The main thing that is missing from the current patches is migrating >> bad block markers on first use, and checking that this has happened >> before using the hack. See the discussion on the Linux version of >> these patches. I was hoping to take care of this earlier this year, >> but other tasks have intruded. >> >> >> Does this have to do with the fact that the oob size is different in the >> bigger page NAND's (sorry if my question seems dumb, but I'm not very >> familiar with the NAND drivers and the software use. Until now the NAND >> part was just plug and play :) ) >> > > The hack involves changing the flash layout from "4096 main 128 spare" to > "2048 main 64 spare 2048 main 64 spare". This means that the factory bad > block marker is now in an area we use for main data. We need to move it to > where it belongs in the new layout before doing anything else with the chip. > > > And as you note, many 4K-page NAND chips require 4-bit ECC which >> means the driver will need to be updated to support software ECC >> (this should be fairly straightforward, except maybe the decision of >> when to do this). >> >> -Scott >> >> >> I will have a look at the driver and try to do the modifications to >> support SW ECC. As I understand the fsl_elbc_nand driver is in sync with >> the linux kernel, and in this case the patches should be implemented and >> sent to the kernel first? >> > > Ordinarily yes, but in this case it might be better to start with U-Boot. > We'll likely do the bad block migration in U-Boot, whereas Linux will just > check that it's been done via some sort of marker. And the ECC stuff > doesn't make much sense until we have the 4K support (I haven't heard of a > 2K chip that needs 4-bit ECC). > > -Scott > > OK, I will have a look at it. I was just wondering, is there a tree somewhere that contains the patches for the 4k hack applied? I saw that a version 2 of the patch was sent by Shengzhou Liu in December 12, 2011, but I cannot find these patches applied in the main git:// git.denx.de/u-boot-nand-flash.git. I think that has something to do with the fact that the patches were not accepted in the way that they were presented, but I would like to know what's the procedure to start working from there to a possible solution. I even tried to apply the patches to the current tree, without success. I could manually apply them, but this code is not mine and if I manually applied it, it would appear as mine. Thanks for the support so far, Rafael

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[U-Boot] [PATCH 1/3] omap4: panda: disable uart2 pads during boot
by Tero Kristo 14 May '12

14 May '12

If uart2 is enabled during boot, spurious wifi chip transmission will hang the module and it is impossible to recover from this situation without hard reset. This will prevent any l4_per domain idle transitions. Signed-off-by: Tero Kristo <t-kristo(a)ti.com> --- board/ti/panda/panda_mux_data.h | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/board/ti/panda/panda_mux_data.h b/board/ti/panda/panda_mux_data.h index 3efc22a..dc8b388 100644 --- a/board/ti/panda/panda_mux_data.h +++ b/board/ti/panda/panda_mux_data.h @@ -168,10 +168,10 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = { {ABE_DMIC_DIN1, (IEN | M0)}, /* abe_dmic_din1 */ {ABE_DMIC_DIN2, (PTU | IEN | M3)}, /* gpio_121 */ {ABE_DMIC_DIN3, (IEN | M0)}, /* abe_dmic_din3 */ - {UART2_CTS, (PTU | IEN | M0)}, /* uart2_cts */ - {UART2_RTS, (M0)}, /* uart2_rts */ - {UART2_RX, (PTU | IEN | M0)}, /* uart2_rx */ - {UART2_TX, (M0)}, /* uart2_tx */ + {UART2_CTS, (PTU | IEN | M7)}, /* uart2_cts */ + {UART2_RTS, (M7)}, /* uart2_rts */ + {UART2_RX, (PTU | IEN | M7)}, /* uart2_rx */ + {UART2_TX, (M7)}, /* uart2_tx */ {HDQ_SIO, (M3)}, /* gpio_127 */ {MCSPI1_CLK, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_clk */ {MCSPI1_SOMI, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* mcspi1_somi */ -- 1.7.4.1

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[U-Boot] [PATCH 4/5] Add support for mmc read and writes
by mohamed.haneef＠lntinfotech.com 10 May '12

10 May '12

From: Mohamed Haneef <mohamed.haneef(a)lntinfotech.com> *Support for msm7x30 mmc read and writes Signed-off-by: Mohamed Haneef <mohamed.haneef(a)lntinfotech.com> --- arch/arm/include/asm/arch-msm7630/mmc.h | 399 +++++++++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/qc_mmc.c | 584 +++++++++++++++++++++++++++++++ 3 files changed, 984 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-msm7630/mmc.h create mode 100644 drivers/mmc/qc_mmc.c diff --git a/arch/arm/include/asm/arch-msm7630/mmc.h b/arch/arm/include/asm/arch-msm7630/mmc.h new file mode 100644 index 0000000..949e43c --- /dev/null +++ b/arch/arm/include/asm/arch-msm7630/mmc.h @@ -0,0 +1,399 @@ +/* + * (C) Copyright 2012 + * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MMC_H__ +#define __MMC_H__ + +#ifndef MMC_SLOT +#define MMC_SLOT 0 +#endif + +#include <common.h> +#include <part.h> +#include <mmc.h> + +/* + * Define Macros for SDCC Registers + */ +/* 8 bit */ +#define MMC_BOOT_MCI_POWER 0x000 + +/* MCICMD output control - 6th bit */ +#ifdef PLATFORM_MSM7X30 +#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6) +#define MMC_BOOT_MCI_PWR_OFF 0x00 +#define MMC_BOOT_MCI_PWR_UP 0x01 +#define MMC_BOOT_MCI_PWR_ON 0x01 +#else +#define MMC_BOOT_MCI_OPEN_DRAIN (1 << 6) +#define MMC_BOOT_MCI_PWR_OFF 0x00 +#define MMC_BOOT_MCI_PWR_UP 0x02 +#define MMC_BOOT_MCI_PWR_ON 0x03 +#endif + +/* 16 bits */ +#define MMC_BOOT_MCI_CLK 0x004 +/* Enable MCI bus clock - 0: clock disabled 1: enabled */ +#define MMC_BOOT_MCI_CLK_ENABLE (1 << 8) +/* Disable clk o/p when bus idle- 0:always enabled 1:enabled when bus active */ +#define MMC_BOOT_MCI_CLK_PWRSAVE (1 << 9) +/* Enable Widebus mode - 00: 1 bit mode 10:4 bit mode 01/11: 8 bit mode */ +#define MMC_BOOT_MCI_CLK_WIDEBUS_MODE (3 << 10) +#define MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT 0 +#define MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT (2 << 10) +#define MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT (1 << 10) +/* Enable flow control- 0: disable 1: enable */ +#define MMC_BOOT_MCI_CLK_ENA_FLOW (1 << 12) +/* Set/clear to select rising/falling edge for data/cmd output */ +#define MMC_BOOT_MCI_CLK_INVERT_OUT (1 << 13) +/* Select to lach data/cmd coming in falling/rising/feedbk/loopbk of MCIclk */ +#define MMC_BOOT_MCI_CLK_IN_FALLING 0x0 +#define MMC_BOOT_MCI_CLK_IN_RISING (1 << 14) +#define MMC_BOOT_MCI_CLK_IN_FEEDBACK (2 << 14) +#define MMC_BOOT_MCI_CLK_IN_LOOPBACK (3 << 14) + +/* Bus Width */ +#define MMC_BOOT_BUS_WIDTH_1_BIT 0 +#define MMC_BOOT_BUS_WIDTH_4_BIT 2 +#define MMC_BOOT_BUS_WIDTH_8_BIT 3 + +/* 32 bits */ +#define MMC_BOOT_MCI_ARGUMENT 0x008 + +/* 16 bits */ +#define MMC_BOOT_MCI_CMD 0x00C +/* Command Index: 0 -5 */ +/* Waits for response if set */ +#define MMC_BOOT_MCI_CMD_RESPONSE (1 << 6) +/* Receives a 136-bit long response if set */ +#define MMC_BOOT_MCI_CMD_LONGRSP (1 << 7) +/* If set, CPSM disables command timer and waits for interrupt */ +#define MMC_BOOT_MCI_CMD_INTERRUPT (1 << 8) +/* If set waits for CmdPend before starting to send a command */ +#define MMC_BOOT_MCI_CMD_PENDING (1 << 9) +/* CPSM is enabled if set */ +#define MMC_BOOT_MCI_CMD_ENABLE (1 << 10) +/* If set PROG_DONE status bit asserted when busy is de-asserted */ +#define MMC_BOOT_MCI_CMD_PROG_ENA (1 << 11) +/* To indicate that this is a Command with Data (for SDIO interrupts) */ +#define MMC_BOOT_MCI_CMD_DAT_CMD (1 << 12) +/* Signals the next command to be an abort (stop) command. Always read 0 */ +#define MMC_BOOT_MCI_CMD_MCIABORT (1 << 13) +/* Waits for Command Completion Signal if set */ +#define MMC_BOOT_MCI_CMD_CCS_ENABLE (1 << 14) +/* If set sends CCS disable sequence */ +#define MMC_BOOT_MCI_CMD_CCS_DISABLE (1 << 15) + +#define MMC_BOOT_MCI_RESP_CMD 0x010 + +#define MMC_BOOT_MCI_RESP_0 0x014 +#define MMC_BOOT_MCI_RESP_1 0x018 +#define MMC_BOOT_MCI_RESP_2 0x01C +#define MMC_BOOT_MCI_RESP_3 0x020 + +#define MMC_BOOT_MCI_DATA_TIMER 0x024 +#define MMC_BOOT_MCI_DATA_LENGTH 0x028 +/* 16 bits */ +#define MMC_BOOT_MCI_DATA_CTL 0x02C +/* Data transfer enabled */ +#define MMC_BOOT_MCI_DATA_ENABLE (1 << 0) +/* Data transfer direction - 0: controller to card 1:card to controller */ +#define MMC_BOOT_MCI_DATA_DIR (1 << 1) +/* Data transfer mode - 0: block data transfer 1: stream data transfer */ +#define MMC_BOOT_MCI_DATA_MODE (1 << 2) +/* Enable DM interface - 0: DM disabled 1: DM enabled */ +#define MMC_BOOT_MCI_DATA_DM_ENABLE (1 << 3) +/* Data block length in bytes (1-4096) */ +#define MMC_BOOT_MCI_BLKSIZE_POS 4 +#define MMC_BOOT_MCI_DATA_COUNT 0x030 +#define MMC_BOOT_MCI_STATUS 0x034 +/* Command response received - CRC check failed */ +#define MMC_BOOT_MCI_STAT_CMD_CRC_FAIL (1 << 0) +/* Data block sent/received - CRC check failed */ +#define MMC_BOOT_MCI_STAT_DATA_CRC_FAIL (1 << 1) +/* Command resonse timeout */ +#define MMC_BOOT_MCI_STAT_CMD_TIMEOUT (1 << 2) +/* Data timeout */ +#define MMC_BOOT_MCI_STAT_DATA_TIMEOUT (1 << 3) +/* Transmit FIFO underrun error */ +#define MMC_BOOT_MCI_STAT_TX_UNDRUN (1 << 4) +/* Receive FIFO overrun error */ +#define MMC_BOOT_MCI_STAT_RX_OVRRUN (1 << 5) +/* Command response received - CRC check passed */ +#define MMC_BOOT_MCI_STAT_CMD_RESP_END (1 << 6) +/* Command sent - no response required */ +#define MMC_BOOT_MCI_STAT_CMD_SENT (1 << 7) +/* Data end - data counter zero */ +#define MMC_BOOT_MCI_STAT_DATA_END (1 << 8) +/* Start bit not detected on all data signals in wide bus mode */ +#define MMC_BOOT_MCI_STAT_START_BIT_ERR (1 << 9) +/* Data block sent/received - CRC check passed */ +#define MMC_BOOT_MCI_STAT_DATA_BLK_END (1 << 10) +/* Command transfer in progress */ +#define MMC_BOOT_MCI_STAT_CMD_ACTIVE (1 << 11) +/* Data transmit in progress */ +#define MMC_BOOT_MCI_STAT_TX_ACTIVE (1 << 12) +/* Data receive in progress */ +#define MMC_BOOT_MCI_STAT_RX_ACTIVE (1 << 13) +/* Transmit FIFO half full */ +#define MMC_BOOT_MCI_STAT_TX_FIFO_HFULL (1 << 14) +/* Receive FIFO half full */ +#define MMC_BOOT_MCI_STAT_RX_FIFO_HFULL (1 << 15) +/* Transmit FIFO full */ +#define MMC_BOOT_MCI_STAT_TX_FIFO_FULL (1 << 16) +/* Receive FIFO full */ +#define MMC_BOOT_MCI_STAT_RX_FIFO_FULL (1 << 17) +/* Transmit FIFO empty */ +#define MMC_BOOT_MCI_STAT_TX_FIFO_EMPTY (1 << 18) +/* Receive FIFO empty */ +#define MMC_BOOT_MCI_STAT_RX_FIFO_EMPTY (1 << 19) +/* Data available in transmit FIFO */ +#define MMC_BOOT_MCI_STAT_TX_DATA_AVLBL (1 << 20) +/* Data available in receive FIFO */ +#define MMC_BOOT_MCI_STAT_RX_DATA_AVLBL (1 << 21) +/* SDIO interrupt indicator for wake-up */ +#define MMC_BOOT_MCI_STAT_SDIO_INTR (1 << 22) +/* Programming done */ +#define MMC_BOOT_MCI_STAT_PROG_DONE (1 << 23) +/* CE-ATA command completion signal detected */ +#define MMC_BOOT_MCI_STAT_ATA_CMD_CMPL (1 << 24) +/* SDIO interrupt indicator for normal operation */ +#define MMC_BOOT_MCI_STAT_SDIO_INTR_OP (1 << 25) +/* Commpand completion signal timeout */ +#define MMC_BOOT_MCI_STAT_CCS_TIMEOUT (1 << 26) + +#define MMC_BOOT_MCI_STATIC_STATUS (MMC_BOOT_MCI_STAT_CMD_CRC_FAIL| \ + MMC_BOOT_MCI_STAT_DATA_CRC_FAIL| \ + MMC_BOOT_MCI_STAT_CMD_TIMEOUT| \ + MMC_BOOT_MCI_STAT_DATA_TIMEOUT| \ + MMC_BOOT_MCI_STAT_TX_UNDRUN| \ + MMC_BOOT_MCI_STAT_RX_OVRRUN| \ + MMC_BOOT_MCI_STAT_CMD_RESP_END| \ + MMC_BOOT_MCI_STAT_CMD_SENT| \ + MMC_BOOT_MCI_STAT_DATA_END| \ + MMC_BOOT_MCI_STAT_START_BIT_ERR| \ + MMC_BOOT_MCI_STAT_DATA_BLK_END| \ + MMC_BOOT_MCI_SDIO_INTR_CLR| \ + MMC_BOOT_MCI_STAT_PROG_DONE| \ + MMC_BOOT_MCI_STAT_ATA_CMD_CMPL |\ + MMC_BOOT_MCI_STAT_CCS_TIMEOUT) + +#define MMC_BOOT_MCI_CLEAR 0x038 +#define MMC_BOOT_MCI_CMD_CRC_FAIL_CLR (1 << 0) +#define MMC_BOOT_MCI_DATA_CRC_FAIL_CLR (1 << 1) +#define MMC_BOOT_MCI_CMD_TIMEOUT_CLR (1 << 2) +#define MMC_BOOT_MCI_DATA_TIMEOUT_CLR (1 << 3) +#define MMC_BOOT_MCI_TX_UNDERRUN_CLR (1 << 4) +#define MMC_BOOT_MCI_RX_OVERRUN_CLR (1 << 5) +#define MMC_BOOT_MCI_CMD_RESP_END_CLR (1 << 6) +#define MMC_BOOT_MCI_CMD_SENT_CLR (1 << 7) +#define MMC_BOOT_MCI_DATA_END_CLR (1 << 8) +#define MMC_BOOT_MCI_START_BIT_ERR_CLR (1 << 9) +#define MMC_BOOT_MCI_DATA_BLK_END_CLR (1 << 10) +#define MMC_BOOT_MCI_SDIO_INTR_CLR (1 << 22) +#define MMC_BOOT_MCI_PROG_DONE_CLR (1 << 23) +#define MMC_BOOT_MCI_ATA_CMD_COMPLR_CLR (1 << 24) +#define MMC_BOOT_MCI_CCS_TIMEOUT_CLR (1 << 25) + +#define MMC_BOOT_MCI_INT_MASK0 0x03C +#define MMC_BOOT_MCI_CMD_CRC_FAIL_MASK (1 << 0) +#define MMC_BOOT_MCI_DATA_CRC_FAIL_MASK (1 << 1) +#define MMC_BOOT_MCI_CMD_TIMEOUT_MASK (1 << 2) +#define MMC_BOOT_MCI_DATA_TIMEOUT_MASK (1 << 3) +#define MMC_BOOT_MCI_TX_OVERRUN_MASK (1 << 4) +#define MMC_BOOT_MCI_RX_OVERRUN_MASK (1 << 5) +#define MMC_BOOT_MCI_CMD_RESP_END_MASK (1 << 6) +#define MMC_BOOT_MCI_CMD_SENT_MASK (1 << 7) +#define MMC_BOOT_MCI_DATA_END_MASK (1 << 8) +#define MMC_BOOT_MCI_START_BIT_ERR_MASK (1 << 9) +#define MMC_BOOT_MCI_DATA_BLK_END_MASK (1 << 10) +#define MMC_BOOT_MCI_CMD_ACTIVE_MASK (1 << 11) +#define MMC_BOOT_MCI_TX_ACTIVE_MASK (1 << 12) +#define MMC_BOOT_MCI_RX_ACTIVE_MASK (1 << 13) +#define MMC_BOOT_MCI_TX_FIFO_HFULL_MASK (1 << 14) +#define MMC_BOOT_MCI_RX_FIFO_HFULL_MASK (1 << 15) +#define MMC_BOOT_MCI_TX_FIFO_FULL_MASK (1 << 16) +#define MMC_BOOT_MCI_RX_FIFO_FULL_MASK (1 << 17) +#define MMC_BOOT_MCI_TX_FIFO_EMPTY_MASK (1 << 18) +#define MMC_BOOT_MCI_RX_FIFO_EMPTY_MASK (1 << 19) +#define MMC_BOOT_MCI_TX_DATA_AVLBL_MASK (1 << 20) +#define MMC_BOOT_MCI_RX_DATA_AVLBL_MASK (1 << 21) +#define MMC_BOOT_MCI_SDIO_INT_MASK (1 << 22) +#define MMC_BOOT_MCI_PROG_DONE_MASK (1 << 23) +#define MMC_BOOT_MCI_ATA_CMD_COMPL_MASK (1 << 24) +#define MMC_BOOT_MCI_SDIO_INT_OPER_MASK (1 << 25) +#define MMC_BOOT_MCI_CCS_TIME_OUT_MASK (1 << 26) + +#define MMC_BOOT_MCI_INT_MASK1 0x040 + +#define MMC_BOOT_MCI_FIFO_COUNT 0x044 + +#define MMC_BOOT_MCI_CCS_TIMER 0x0058 + +#define MMC_BOOT_MCI_FIFO 0x080 + +/* OCR Register */ +#define MMC_BOOT_OCR_17_19 (1 << 7) +#define MMC_BOOT_OCR_27_36 (0x1FF << 15) +#define MMC_BOOT_OCR_SEC_MODE (2 << 29) +#define MMC_BOOT_OCR_BUSY (1 << 31) + +/* Commands type */ +#define MMC_BOOT_CMD_BCAST (1 << 0) +#define MMC_BOOT_CMD_BCAST_W_RESP (1 << 1) +#define MMC_BOOT_CMD_ADDRESS (1 << 2) +#define MMC_BOOT_CMD_ADDR_DATA_XFER (1 << 3) + +/* Card Status bits (R1 register) */ +#define MMC_BOOT_R1_AKE_SEQ_ERROR (1 << 3) +#define MMC_BOOT_R1_APP_CMD (1 << 5) +#define MMC_BOOT_R1_RDY_FOR_DATA (1 << 6) +#define MMC_BOOT_R1_CURR_STATE_IDLE (0 << 9) +#define MMC_BOOT_R1_CURR_STATE_RDY (1 << 9) +#define MMC_BOOT_R1_CURR_STATE_IDENT (2 << 9) +#define MMC_BOOT_R1_CURR_STATE_STBY (3 << 9) +#define MMC_BOOT_R1_CURR_STATE_TRAN (4 << 9) +#define MMC_BOOT_R1_CURR_STATE_DATA (5 << 9) +#define MMC_BOOT_R1_CURR_STATE_RCV (6 << 9) +#define MMC_BOOT_R1_CURR_STATE_PRG (7 << 9) +#define MMC_BOOT_R1_CURR_STATE_DIS (8 << 9) +#define MMC_BOOT_R1_ERASE_RESET (1 << 13) +#define MMC_BOOT_R1_CARD_ECC_DISABLED (1 << 14) +#define MMC_BOOT_R1_WP_ERASE_SKIP (1 << 15) +#define MMC_BOOT_R1_ERROR (1 << 19) +#define MMC_BOOT_R1_CC_ERROR (1 << 20) +#define MMC_BOOT_R1_CARD_ECC_FAILED (1 << 21) +#define MMC_BOOT_R1_ILLEGAL_CMD (1 << 22) +#define MMC_BOOT_R1_COM_CRC_ERR (1 << 23) +#define MMC_BOOT_R1_LOCK_UNLOCK_FAIL (1 << 24) +#define MMC_BOOT_R1_CARD_IS_LOCKED (1 << 25) +#define MMC_BOOT_R1_WP_VIOLATION (1 << 26) +#define MMC_BOOT_R1_ERASE_PARAM (1 << 27) +#define MMC_BOOT_R1_ERASE_SEQ_ERR (1 << 28) +#define MMC_BOOT_R1_BLOCK_LEN_ERR (1 << 29) +#define MMC_BOOT_R1_ADDR_ERR (1 << 30) +#define MMC_BOOT_R1_OUT_OF_RANGE (1 << 31) + +/* Macros for Common Errors */ +#define MMC_BOOT_E_SUCCESS 0 +#define MMC_BOOT_E_FAILURE 1 +/* Not used..use instead TIMEOUT in include/mmc.h */ +#define MMC_BOOT_E_TIMEOUT 2 +#define MMC_BOOT_E_INVAL 3 +#define MMC_BOOT_E_CRC_FAIL 4 +#define MMC_BOOT_E_INIT_FAIL 5 +#define MMC_BOOT_E_CMD_INDX_MISMATCH 6 +#define MMC_BOOT_E_RESP_VERIFY_FAIL 7 +#define MMC_BOOT_E_NOT_SUPPORTED 8 +#define MMC_BOOT_E_CARD_BUSY 9 +#define MMC_BOOT_E_MEM_ALLOC_FAIL 10 +#define MMC_BOOT_E_CLK_ENABLE_FAIL 11 +#define MMC_BOOT_E_CMMC_DECODE_FAIL 12 +#define MMC_BOOT_E_CID_DECODE_FAIL 13 +#define MMC_BOOT_E_BLOCKLEN_ERR 14 +#define MMC_BOOT_E_ADDRESS_ERR 15 +#define MMC_BOOT_E_DATA_CRC_FAIL 16 +#define MMC_BOOT_E_DATA_TIMEOUT 17 +#define MMC_BOOT_E_RX_OVRRUN 18 +#define MMC_BOOT_E_VREG_SET_FAILED 19 +#define MMC_BOOT_E_GPIO_CFG_FAIL 20 +#define MMC_BOOT_E_DATA_ADM_ERR 21 + +/* EXT_CSD */ +#define MMC_BOOT_ACCESS_WRITE 0x3 +#define MMC_BOOT_EXT_CMMC_HS_TIMING 185 +#define MMC_BOOT_EXT_CMMC_BUS_WIDTH 183 + +#define MMC_BOOT_EXT_USER_WP 171 +#define MMC_BOOT_EXT_ERASE_GROUP_DEF 175 +#define MMC_BOOT_EXT_HC_WP_GRP_SIZE 221 +#define MMC_BOOT_EXT_HC_ERASE_GRP_SIZE 224 + +#define MMC_BOOT_US_PERM_WP_EN 2 +#define MMC_BOOT_US_PWR_WP_DIS 3 + +#define MMC_BOOT_US_PERM_WP_DIS (1<<4) +#define MMC_BOOT_US_PWR_WP_EN 1 + +/* For SD */ +#define MMC_BOOT_SD_HC_VOLT_SUPPLIED 0x000001AA +#define MMC_BOOT_SD_NEG_OCR 0x00FF8000 +#define MMC_BOOT_SD_HC_HCS 0x40000000 +#define MMC_BOOT_SD_DEV_READY 0x80000000 +#define MMC_BOOT_SD_SWITCH_HS 0x80FFFFF1 + +/* Data structure definitions */ + +#define MMC_BOOT_XFER_MODE_BLOCK 0 +#define MMC_BOOT_XFER_MODE_STREAM 1 +#define MMC_BOOT_PROGRAM_ENABLED 2 + + +#define MMC_RCA 2 + +#define MMC_BOOT_MAX_COMMAND_RETRY 1000 +#define MMC_BOOT_RD_BLOCK_LEN 512 +#define MMC_BOOT_WR_BLOCK_LEN 512 + +/* We have 16 32-bits FIFO registers */ +#define MMC_BOOT_MCI_FIFO_DEPTH 16 +#define MMC_BOOT_MCI_HFIFO_COUNT (MMC_BOOT_MCI_FIFO_DEPTH / 2) +#define MMC_BOOT_MCI_FIFO_SIZE (MMC_BOOT_MCI_FIFO_DEPTH * 4) + +#define MAX_PARTITIONS 64 + +#define MMC_BOOT_CHECK_PATTERN 0xAA /* 10101010b */ + +#define MMC_CLK_400KHZ 400000 +#define MMC_CLK_144KHZ 144000 +#define MMC_CLK_20MHZ 20000000 +#define MMC_CLK_24MHZ 24000000 +#define MMC_CLK_25MHZ 25000000 +#define MMC_CLK_26MHZ 26000000 +#define MMC_CLK_48MHZ 48000000 +#define MMC_CLK_50MHZ 49152000 +#define MMC_CLK_52MHZ 52000000 + +#define MMC_CLK_ENABLE 1 +#define MMC_CLK_DISABLE 0 + +#if 0 +#define MSM_SDC1_BASE 0x12400000 +#define MSM_SDC2_BASE 0x12140000 +#define MSM_SDC3_BASE 0x12180000 +#define MSM_SDC4_BASE 0x121C0000 +#endif +struct mmc_priv { + unsigned int instance; + unsigned int base; + unsigned int rd_timeout_ns; /* for read timeout */ +}; + +void mmc_boot_set_ios(struct mmc *mmc); +int mmc_boot_send_command_map(struct mmc *mmc, + struct mmc_cmd *cmd, + struct mmc_data *data); +unsigned long int mmc_boot_mci_reg(unsigned long base, unsigned long offset); +unsigned int mmc_boot_main(struct mmc *mmc); + +extern void clock_config_mmc(uint32_t interface, uint32_t freq); +extern void clock_init_mmc(uint32_t interface); +#endif + diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 506f1d6..2d926ec 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -44,6 +44,7 @@ COBJS-$(CONFIG_S5P_MMC) += s5p_mmc.o COBJS-$(CONFIG_SDHCI) += sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o COBJS-$(CONFIG_TEGRA2_MMC) += tegra2_mmc.o +COBJS-$(CONFIG_QC_MMC) += qc_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/qc_mmc.c b/drivers/mmc/qc_mmc.c new file mode 100644 index 0000000..7b7a1ed --- /dev/null +++ b/drivers/mmc/qc_mmc.c @@ -0,0 +1,584 @@ +/* + * (C) Copyright 2012 + * LARSEN & TOUBRO INFOTECH LTD <www.lntinfotech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <linux/types.h> +#include <asm/io.h> +#include <asm/arch/mmc.h> +#include <asm/arch/iomap.h> +#include <common.h> + +#if MMC_BOOT_ADM +#include "adm.h" +#endif + +#ifndef NULL +#define NULL 0 +#endif + +#define MMC_BOOT_DATA_READ 0 +#define MMC_BOOT_DATA_WRITE 1 +/* + * Calculates the address of registers according to the base address + */ +unsigned long int mmc_boot_mci_reg(unsigned long base, unsigned long offset) +{ + return base + offset; +} + + +/* + * Sets a timeout for read operation. + */ +static unsigned int mmc_boot_set_read_timeout(struct mmc *mmc) +{ + if (mmc == NULL) + return MMC_BOOT_E_INVAL; + + /* todo: Add a check for HC, only if HC do this. + * If not, taac and nsac must be taken into account + */ + ((struct mmc_priv *)(mmc->priv))->rd_timeout_ns = 100000000; + debug(" Read timeout set: %d ns\n", + ((struct mmc_priv *)(mmc->priv))->rd_timeout_ns); + + return MMC_BOOT_E_SUCCESS; +} + +/* + * Check to ensure that there is no alignment or data length errors + */ +static unsigned int mmc_boot_check_read_data(struct mmc_cmd *cmd) +{ + + if (cmd->response[0] & MMC_BOOT_R1_BLOCK_LEN_ERR) + return MMC_BOOT_E_BLOCKLEN_ERR; + + /* Misaligned address not matching block length */ + if (cmd->response[0] & MMC_BOOT_R1_ADDR_ERR) + return MMC_BOOT_E_ADDRESS_ERR; + + return MMC_BOOT_E_SUCCESS; +} + +/* + * Decode type of error caused during read and write + */ +static unsigned int mmc_boot_status_error(unsigned mmc_status) +{ + unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; + + /* If DATA_CRC_FAIL bit is set to 1 then CRC error + * was detected by card/device during the data transfer + */ + if (mmc_status & MMC_BOOT_MCI_STAT_DATA_CRC_FAIL) + mmc_ret = MMC_BOOT_E_DATA_CRC_FAIL; + /* If DATA_TIMEOUT bit is set to 1 then the data transfer time + * exceeded the data timeout period without completing the + * transfer + */ + else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_TIMEOUT) + mmc_ret = MMC_BOOT_E_DATA_TIMEOUT; + /* If RX_OVERRUN bit is set to 1 then SDCC2 tried to + * receive data from the card before empty storage for new + * received data was available. + * Verify that bit FLOW_ENA in MCI_CLK is set to 1 during + * the data xfer. + */ + else if (mmc_status & MMC_BOOT_MCI_STAT_RX_OVRRUN) + /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. + * so no need to verify for now + */ + mmc_ret = MMC_BOOT_E_RX_OVRRUN; + /* If TX_UNDERRUN bit is set to 1 then SDCC2 tried to send + * data to the card before new data for sending was available. + * Verify that bit FLOW_ENA in MCI_CLK + * is set to 1 during the data xfer. + */ + else if (mmc_status & MMC_BOOT_MCI_STAT_TX_UNDRUN) + /* Note: We've set FLOW_ENA bit in MCI_CLK to 1. + * so skipping it now + */ + mmc_ret = MMC_BOOT_E_RX_OVRRUN; + + return mmc_ret; +} + +/* + * Read data to SDC FIFO. + */ +static unsigned int mmc_boot_fifo_read(unsigned int *mmc_ptr, + unsigned int data_len, + struct mmc *mmc) +{ + unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; + unsigned int mmc_status = 0; + unsigned int mmc_count = 0; + unsigned int read_error = MMC_BOOT_MCI_STAT_DATA_CRC_FAIL | \ + MMC_BOOT_MCI_STAT_DATA_TIMEOUT | \ + MMC_BOOT_MCI_STAT_RX_OVRRUN; + unsigned int i; + struct mmc_priv *priv = (struct mmc_priv *)mmc->priv; + unsigned long reg_status, reg_fifo; + + reg_status = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_STATUS); + reg_fifo = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_FIFO); + + /* Read the data from the MCI_FIFO register as long as + * RXDATA_AVLBL bit of MCI_STATUS register is set to 1 and bits + * DATA_CRC_FAIL, DATA_TIMEOUT, RX_OVERRUN of MCI_STATUS + * register are cleared to 0. + * Continue the reads until the whole transfer data is received + */ + + do { + mmc_ret = MMC_BOOT_E_SUCCESS; + mmc_status = readl(reg_status); + + if (mmc_status & read_error) { + mmc_ret = mmc_boot_status_error(mmc_status); + break; + } + + if (mmc_status & MMC_BOOT_MCI_STAT_RX_DATA_AVLBL) { + unsigned read_count = 1; + if (mmc_status & MMC_BOOT_MCI_STAT_RX_FIFO_HFULL) + read_count = MMC_BOOT_MCI_HFIFO_COUNT; + + for (i = 0; i < read_count; i++) { + /* FIFO contains 16 32-bit data buffer + * on 16 sequential addresses + */ + *mmc_ptr = readl(reg_fifo + + (mmc_count % MMC_BOOT_MCI_FIFO_SIZE)); + mmc_ptr++; + /* increase mmc_count by word size */ + mmc_count += sizeof(unsigned int); + } + /* quit if we have read enough of data */ + if (mmc_count == data_len) + break; + } else if (mmc_status & MMC_BOOT_MCI_STAT_DATA_END) + break; + } while (1); + return mmc_ret; +} + +static unsigned int mmc_boot_fifo_data_transfer(unsigned int *data_ptr, + unsigned int data_len, + unsigned char direction, + struct mmc *mmc) +{ + unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; + + if (direction == MMC_BOOT_DATA_READ) + mmc_ret = mmc_boot_fifo_read(data_ptr, data_len, mmc); + + return mmc_ret; +} + +/* + * Sends specified command to a card and waits for a response. + */ +static unsigned int mmc_boot_send_command(struct mmc_cmd *cmd, + struct mmc *mmc) +{ + unsigned int mmc_cmd = 0; + unsigned int mmc_status = 0; + unsigned int mmc_resp = 0; + unsigned int mmc_return = MMC_BOOT_E_SUCCESS; + unsigned int cmd_index = 0; + int i = 0; + unsigned long reg, reg_status, reg_resp_cmd, reg_resp_0; + struct mmc_priv *priv = (struct mmc_priv *)mmc->priv; + + /* basic check */ + if (cmd == NULL) + return MMC_BOOT_E_INVAL; + + /* 1. Write command argument to MMC_BOOT_MCI_ARGUMENT register */ + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_ARGUMENT); + writel(cmd->cmdarg, reg); + + /* Writes to MCI port are not effective for 3 ticks of PCLK. + * ticks calculated using 400KHz clock speed + */ + udelay(8); + + /* 2. Set appropriate fields and write MMC_BOOT_MCI_CMD */ + /* 2a. Write command index in CMD_INDEX field */ + cmd_index = cmd->cmdidx; + mmc_cmd |= cmd->cmdidx; + /* 2b. Set RESPONSE bit to 1 for all cmds except CMD0 */ + if (cmd_index != MMC_CMD_GO_IDLE_STATE) + mmc_cmd |= MMC_BOOT_MCI_CMD_RESPONSE; + + /* 2c. Set LONGRESP bit to 1 for CMD2, CMD9 and CMD10 */ + if (cmd->resp_type & MMC_RSP_136) + mmc_cmd |= MMC_BOOT_MCI_CMD_LONGRSP; + + /* 2d. Set INTERRUPT bit to 1 to disable command timeout */ + + /* 2e. Set PENDING bit to 1 for CMD12 in the beginning of stream + * mode data transfer + */ + if (cmd->flags & MMC_BOOT_XFER_MODE_STREAM) + mmc_cmd |= MMC_BOOT_MCI_CMD_PENDING; + + /* 2f. Set ENABLE bit to 1 */ + mmc_cmd |= MMC_BOOT_MCI_CMD_ENABLE; + + /* 2g. Set PROG_ENA bit to 1 for CMD12, CMD13 issued at the end of + * write data transfer + */ + if ((cmd_index == MMC_CMD_STOP_TRANSMISSION || + cmd_index == MMC_CMD_SEND_STATUS) && + (cmd->flags & MMC_BOOT_PROGRAM_ENABLED)) + mmc_cmd |= MMC_BOOT_MCI_CMD_PROG_ENA; + + + /* 2h. Set MCIABORT bit to 1 for CMD12 when working with SDIO card */ + /* 2i. Set CCS_ENABLE bit to 1 for CMD61 when Command Completion Signal + * of CE-ATA device is enabled + */ + + /* 2j. clear all static status bits */ + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_CLEAR); + writel(MMC_BOOT_MCI_STATIC_STATUS, reg); + + /* 2k. Write to MMC_BOOT_MCI_CMD register */ + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_CMD); + writel(mmc_cmd, reg); + + /* Writes to MCI port are not effective for 3 ticks of PCLK. + * ticks calculated using 400KHz clock speed + */ + udelay(8); + + reg_status = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_STATUS); + reg_resp_cmd = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_RESP_CMD); + reg_resp_0 = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_RESP_0); + + /* 3. Wait for interrupt or poll on the following bits of MCI_STATUS + * register + */ + do { + /* 3a. Read MCI_STATUS register */ + mmc_status = readl(reg_status); + while (mmc_status & MMC_BOOT_MCI_STAT_CMD_ACTIVE) + mmc_status = readl(reg_status); + + /* 3b. CMD_SENT bit supposed to be set to 1 only + * after CMD0 is sent -no response required. + */ + if ((cmd->resp_type == MMC_RSP_NONE) && + (mmc_status & MMC_BOOT_MCI_STAT_CMD_SENT)) + break; + + /* 3c. If CMD_TIMEOUT bit is set then no response + * was received */ + else if (mmc_status & MMC_BOOT_MCI_STAT_CMD_TIMEOUT) { + mmc_return = TIMEOUT; + break; + } + /* 3d. If CMD_RESPONSE_END bit is set to 1 then command's + * response was received and CRC check passed + * Spcial case for ACMD41: it seems to always fail CRC even if + * the response is valid + */ + else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_RESP_END) || + (cmd_index == MMC_CMD_SEND_OP_COND) + || (cmd_index == SD_CMD_SEND_IF_COND)) { + /* 3i. Read MCI_RESP_CMD register to verify that + * response index is equal to command index + */ + mmc_resp = readl(reg_resp_cmd) & 0x3F; + + /* However, long response does not contain the + * command index field. + * In that case, response index field must be set to + * 111111b (0x3F) + */ + if ((mmc_resp == cmd_index) || + (cmd->resp_type == MMC_RSP_R2 || + cmd->resp_type == MMC_RSP_R3 || + cmd->resp_type == MMC_RSP_R6 || + cmd->resp_type == MMC_RSP_R7)){ + /* 3j. If resp index is equal to cmd index, + * read command resp from MCI_RESPn registers + * - MCI_RESP0/1/2/3 for CMD2/9/10 + * - MCI_RESP0 for all other registers + */ + if (cmd->resp_type & MMC_RSP_136) { + for (i = 0; i < 4; i++) + cmd->response[3-i] = + readl(reg_resp_0 + \ + (i * 4)); + } else + cmd->response[0] = readl(reg_resp_0); + } else + /* command index mis-match */ + mmc_return = MMC_BOOT_E_CMD_INDX_MISMATCH; + + break; + } + + /* 3e. If CMD_CRC_FAIL bit is set to 1 then cmd's response + * was recvd, but CRC check failed. + */ + else if ((mmc_status & MMC_BOOT_MCI_STAT_CMD_CRC_FAIL)) { + if (cmd_index == SD_CMD_APP_SEND_OP_COND) + cmd->response[0] = readl(reg_resp_0); + else + mmc_return = MMC_BOOT_E_CRC_FAIL; + break; + } + + } while (1); + + return mmc_return; +} + +static void mmc_boot_init_data(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + uint32_t data_ctrl, mmc_reg, data_len; + struct mmc_priv *priv = (struct mmc_priv *)mmc->priv; + unsigned long reg; + + /* Write data timeout period to MCI_DATA_TIMER register. */ + /* Data timeout period should be in card bus clock periods */ + mmc_reg = (unsigned long)(((struct mmc_priv *) + (mmc->priv))->rd_timeout_ns / + 1000000) * (mmc->clock / 1000); + /* add some extra clock cycles to be safe */ + mmc_reg += 1000; + mmc_reg = mmc_reg/2; + + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_DATA_TIMER); + writel(mmc_reg, reg); + + /* Write the total size of the transfer data to MCI_DATA_LENGTH + * register. For block xfer it must be multiple of the block + * size. + */ + + data_len = data->blocks*data->blocksize; + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_DATA_LENGTH); + writel(data_len, reg); + + /* Writes to MCI port are not effective for 3 ticks of PCLK. + * ticks calculated using 400KHz clock speed + */ + udelay(8); + + data_ctrl = MMC_BOOT_MCI_DATA_ENABLE | + (data->blocksize << MMC_BOOT_MCI_BLKSIZE_POS); + + + if (data->flags == MMC_DATA_READ) + data_ctrl |= MMC_BOOT_MCI_DATA_DIR; + + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_DATA_CTL); + writel(data_ctrl, reg); + + /* Writes to MCI port are not effective for 3 ticks of PCLK. + * ticks calculated using 400KHz clock speed + */ + udelay(8); + +} + +/* + * Function to map mmc send command to board send command + */ +int mmc_boot_send_command_map(struct mmc *mmc, + struct mmc_cmd *cmd, + struct mmc_data *data) +{ + unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; + + /* todo: do we need to fill in command type ?? */ + + if (cmd->cmdidx == MMC_CMD_SEND_STATUS) { + /* u-boot doesn't fill in the correct argument value */ + cmd->cmdarg = mmc->rca << 16; + /* this is to explicitly disable the prg enabled flag */ + cmd->flags &= ~MMC_BOOT_PROGRAM_ENABLED; + + } else if (cmd->cmdidx == MMC_CMD_READ_SINGLE_BLOCK) { + if (mmc->read_bl_len != MMC_BOOT_RD_BLOCK_LEN && + mmc->version & SD_VERSION_SD) { + mmc->read_bl_len = MMC_BOOT_RD_BLOCK_LEN; + data->blocksize = MMC_BOOT_RD_BLOCK_LEN; + } + } else if (cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK) { + if (mmc->read_bl_len != MMC_BOOT_RD_BLOCK_LEN && + mmc->version & SD_VERSION_SD) { + mmc->read_bl_len = MMC_BOOT_RD_BLOCK_LEN; + data->blocksize = MMC_BOOT_RD_BLOCK_LEN; + } + } else if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) { + /* explicitly disable the prg enabled flag */ + cmd->flags &= ~MMC_BOOT_PROGRAM_ENABLED; + /* set the XFER mode */ + cmd->flags |= MMC_BOOT_XFER_MODE_BLOCK; + } + + + /* For Data cmd's */ + if (data != NULL) + mmc_boot_init_data(mmc, cmd, data); + + /* send command */ + mmc_ret = mmc_boot_send_command(cmd, mmc); + + if (mmc_ret != MMC_BOOT_E_SUCCESS) { + debug("Return Error = %d\n", mmc_ret); + return mmc_ret; + } + + if (data != NULL) { + mmc_ret = mmc_boot_check_read_data(cmd); + if (mmc_ret) + return mmc_ret; + mmc_boot_fifo_data_transfer((unsigned int *) data->dest, + data->blocks * data->blocksize, + MMC_BOOT_DATA_READ, + mmc); + } + + if (cmd->cmdidx == MMC_CMD_SEND_CSD) { + /* Set read timeout once csd is received */ + mmc_ret = mmc_boot_set_read_timeout(mmc); + if (mmc_ret != MMC_BOOT_E_SUCCESS) { + printf("Error No.%d: Failure setting \ + write Timeout value!\n", + mmc_ret); + return mmc_ret; + } + } else if ((cmd->cmdidx == SD_CMD_SWITCH_FUNC) && (data != NULL)) { + /* cmd6 needs at least 8 clocks after the + * End Data of Status. + * ticks calculated using 400KHz clock speed + */ + udelay(20); + } + + return mmc_ret; +} + +/* + * Initialize host structure, set and enable clock-rate and power mode. + */ +unsigned int mmc_boot_init(struct mmc *mmc) +{ + unsigned int mmc_pwr = 0; + struct mmc_priv *priv = (struct mmc_priv *) mmc->priv; + int mmc_slot = priv->instance; + unsigned long reg; + + /* Initialize any clocks needed for SDC controller */ + clock_init_mmc(mmc_slot); + + /* Setup initial freq to 400KHz */ + clock_config_mmc(mmc_slot, MMC_CLK_400KHZ); + + /* set power mode*/ + mmc_pwr &= ~MMC_BOOT_MCI_PWR_UP; + mmc_pwr |= MMC_BOOT_MCI_PWR_ON; + mmc_pwr |= MMC_BOOT_MCI_PWR_UP; + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_POWER); + writel(mmc_pwr, reg); + + /* Writes to MCI port are not effective for 3 ticks of PCLK. + * ticks calculated using 400KHz clock speed + */ + udelay(8); + + return MMC_BOOT_E_SUCCESS; +} + +static unsigned int mmc_boot_set_bus_width(unsigned int width, + struct mmc *mmc) +{ + unsigned int mmc_reg; + struct mmc_priv *priv = (struct mmc_priv *)mmc->priv; + unsigned long reg; + + /* set MCI_CLK accordingly */ + reg = mmc_boot_mci_reg(priv->base, MMC_BOOT_MCI_CLK); + mmc_reg = readl(reg); + mmc_reg &= ~MMC_BOOT_MCI_CLK_WIDEBUS_MODE; + if (width == 1) + mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_1_BIT; + else if (width == 4) + mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_4_BIT; + else if (width == 8) + mmc_reg |= MMC_BOOT_MCI_CLK_WIDEBUS_8_BIT; + else + return MMC_BOOT_E_INVAL; + + writel(mmc_reg, reg); + + /* Writes to MCI port are not effective for 3 ticks of PCLK. + * ticks calculated using 400KHz clock speed + */ + udelay(8); + + debug("Setting bus width to %d\n", width); + return MMC_BOOT_E_SUCCESS; +} + +void mmc_boot_set_ios(struct mmc *mmc) +{ + unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; + struct mmc_priv *priv = (struct mmc_priv *)mmc->priv; + int mmc_slot = priv->instance; + + /* clock frequency should be less than 400KHz in identification mode */ + clock_config_mmc(mmc_slot, mmc->clock); + /* + * give atleast 2 MCLK cycles delay for clocks + * and SDCC core to stabilize. + * ticks calculated using 400KHz clock speed + */ + udelay(5); + mmc_ret = mmc_boot_set_bus_width(mmc->bus_width, mmc); + if (mmc_ret != MMC_BOOT_E_SUCCESS) + printf("Set bus width error %d\n", mmc_ret); +} + +/* + * Board specific initializations + */ +unsigned int mmc_boot_main(struct mmc *mmc) +{ + unsigned int mmc_ret = MMC_BOOT_E_SUCCESS; + + /* Initialize necessary data structure and enable/set clock and power */ + debug(" Initializing MMC host data structure and clock!\n"); + mmc_ret = mmc_boot_init(mmc); + if (mmc_ret != MMC_BOOT_E_SUCCESS) { + printf("MMC Boot: Error Initializing MMC Card!!!\n"); + return MMC_BOOT_E_FAILURE; + } + + return MMC_BOOT_E_SUCCESS; +} -- 1.7.1 The contents of this e-mail and any attachment(s) may contain confidential or privileged information for the intended recipient(s). Unintended recipients are prohibited from taking action on the basis of information in this e-mail and using or disseminating the information, and must notify the sender and delete it from their system. L&T Infotech will not accept responsibility or liability for the accuracy or completeness of, or the presence of any virus or disabling code in this e-mail"

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