February 2012 - U-Boot

[U-Boot] [PATCH 1/3] MX35: add missing get_ticks() and get_tbclk()
by Stefano Babic 06 Feb '12

06 Feb '12

commit f31a911fe (arm, post: add missing post_time_ms for arm) enables get_ticks and get_tbclk for all arm based boards, MX5/MX6 have not yet implemented. Signed-off-by: Stefano Babic <sbabic(a)denx.de> --- arch/arm/cpu/arm1136/mx35/timer.c | 103 +++++++++++++++++++++++-------------- 1 files changed, 64 insertions(+), 39 deletions(-) diff --git a/arch/arm/cpu/arm1136/mx35/timer.c b/arch/arm/cpu/arm1136/mx35/timer.c index 80c0675..04937a1 100644 --- a/arch/arm/cpu/arm1136/mx35/timer.c +++ b/arch/arm/cpu/arm1136/mx35/timer.c @@ -25,7 +25,14 @@ #include <common.h> #include <asm/io.h> +#include <div64.h> #include <asm/arch/imx-regs.h> +#include <asm/arch/clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define timestamp (gd->tbl) +#define lastinc (gd->lastinc) /* General purpose timers bitfields */ #define GPTCR_SWR (1<<15) /* Software reset */ @@ -33,7 +40,24 @@ #define GPTCR_CLKSOURCE_32 (0x100<<6) /* Clock source */ #define GPTCR_CLKSOURCE_IPG (0x001<<6) /* Clock source */ #define GPTCR_TEN (1) /* Timer enable */ -#define GPTPR_VAL (66) + +#define TIMER_FREQ_HZ mxc_get_clock(MXC_IPG_CLK) + +static inline unsigned long long tick_to_time(unsigned long long tick) +{ + tick *= CONFIG_SYS_HZ; + do_div(tick, TIMER_FREQ_HZ); + + return tick; +} + +static inline unsigned long long us_to_tick(unsigned long long usec) +{ + usec *= TIMER_FREQ_HZ; + do_div(usec, 1000000); + + return usec; +} int timer_init(void) { @@ -45,7 +69,7 @@ int timer_init(void) for (i = 0; i < 100; i++) writel(0, &gpt->ctrl); /* We have no udelay by now */ - writel(GPTPR_VAL, &gpt->pre); + writel(0, &gpt->pre); /* Freerun Mode, PERCLK1 input */ writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_IPG | GPTCR_TEN, @@ -54,58 +78,59 @@ int timer_init(void) return 0; } -void reset_timer_masked(void) +unsigned long long get_ticks(void) { struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; - - writel(0, &gpt->ctrl); - /* Freerun Mode, PERCLK1 input */ - writel(GPTCR_CLKSOURCE_IPG | GPTCR_TEN, - &gpt->ctrl); + ulong now = readl(&gpt->counter); /* current tick value */ + + if (now >= lastinc) { + /* + * normal mode (non roll) + * move stamp forward with absolut diff ticks + */ + timestamp += (now - lastinc); + } else { + /* we have rollover of incrementer */ + timestamp += (0xFFFFFFFF - lastinc) + now; + } + lastinc = now; + return timestamp; } -inline ulong get_timer_masked(void) +ulong get_timer_masked(void) { - - struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR; - ulong val = readl(&gpt->counter); - - return val; + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return tick_to_time(get_ticks()); } ulong get_timer(ulong base) { - ulong tmp; + return get_timer_masked() - base; +} - tmp = get_timer_masked(); +/* delay x useconds AND preserve advance timstamp value */ +void __udelay(unsigned long usec) +{ + unsigned long long tmp; + ulong tmo; - if (tmp <= (base * 1000)) { - /* Overflow */ - tmp += (0xffffffff - base); - } + tmo = us_to_tick(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ - return (tmp / 1000) - base; + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; } /* - * delay x useconds AND preserve advance timstamp value - * GPTCNT is now supposed to tick 1 by 1 us. + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. */ -void __udelay(unsigned long usec) +ulong get_tbclk(void) { - ulong tmp; - - tmp = get_timer_masked(); /* get current timestamp */ - - /* if setting this forward will roll time stamp */ - if ((usec + tmp + 1) < tmp) { - /* reset "advancing" timestamp to 0, set lastinc value */ - reset_timer_masked(); - } else { - /* else, set advancing stamp wake up time */ - tmp += usec; - } - - while (get_timer_masked() < tmp) /* loop till event */ - /*NOP*/; + return TIMER_FREQ_HZ; } -- 1.7.5.4

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[U-Boot] [PATCH 0/2] mmc: card status polling fixes
by Jan Kloetzke 06 Feb '12

06 Feb '12

Hi, These are two patches for some card status polling issues that we ran across lately. The first patch fixes single block writes to cards because the card status was not always checked (only for multi block writes). Also, if the card status could not be obtained, the error was not propagated upwards. The second patch aligns the status polling with the Linux kernel (retrying the command five times) to make it more robust... Regards, Jan Kloetzke

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[U-Boot] [PATCH V4] AT91: pio: Add PIO3 features
by Hong Xu 06 Feb '12

06 Feb '12

This patch adds the support for new PIO controller introduced by some AT91 SoCs. New features include * More peripheral multiplexing * Pull-down, Schmitt trigger, Debouncer * More irq trigger mode (may be not interesting in U-Boot) Signed-off-by: Hong Xu <hong.xu(a)atmel.com> Acked-by: Remy Bohmer <linux(a)bohmer.net> --- Changes since V3 Add Acked-by from Remy Bohmer arch/arm/include/asm/arch-at91/at91_pio.h | 48 ++++++++++- drivers/gpio/at91_gpio.c | 130 +++++++++++++++++++++++++++- 2 files changed, 171 insertions(+), 7 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf..069368d 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) * * Parallel I/O Controller (PIO) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. @@ -17,7 +18,6 @@ #ifndef AT91_PIO_H #define AT91_PIO_H - #define AT91_ASM_PIO_RANGE 0x200 #define AT91_ASM_PIOC_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) @@ -66,14 +66,51 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; +#if defined(ATMEL_CPU_HAS_PIO3) + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ +#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; +#else u32 asr; /* 0x70 Select A Register */ u32 bsr; /* 0x74 Select B Register */ u32 absr; /* 0x78 AB Select Status Register */ u32 reserved5[9]; /* */ +#endif u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ + u32 owsr; /* OxA8 Output Write Status Register */ +#if defined(ATMEL_CPU_HAS_PIO3) + u32 reserved7; /* */ + u32 aimer; /* Additional Interrupt Modes Enable Register*/ + u32 aimdr; /* Additional Interrupt Modes Disable Register*/ + u32 aimmr; /* Additional Intterupt Modes Mask Register */ + u32 reserved8; /* */ + u32 esr; /* 0xC0 Edge Select Register */ + u32 lsr; /* 0xC4 Level Select Register */ + u32 elsr; /* 0xC8 Edge/Level Status Register */ + u32 reserved9; /* 0xCC */ + u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/ + u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/ + u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ + u32 reserved10; /* */ + u32 locksr; /* 0xE0 Lock Status */ + u32 wpmr; /* 0xE4 Write Protect Mode Register */ + u32 wpsr; /* 0xE4 Write Protect Status Register */ + u32 reserved11[5]; /* */ + u32 schmitt; /* 0x100 Schmitt Trigger Register */ + u32 reserved12[63]; +#else u32 reserved6[85]; +#endif } at91_port_t; typedef union at91_pio { @@ -94,6 +131,13 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); +#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index be2a026..3676ba1 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -1,6 +1,8 @@ /* * Memory Setup stuff - taken from blob memsetup.S * + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) + * * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) * * Copyright (C) 2005 HP Labs @@ -58,7 +60,7 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "GPIO" peripheral role. + * mux the pin to the "GPIO" peripheral function. */ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) { @@ -75,7 +77,7 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "A" internal peripheral role. + * mux the pin to the "A" internal peripheral function. */ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) { @@ -86,14 +88,21 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].asr); +#endif writel(mask, &pio->port[port].pdr); } return 0; } /* - * mux the pin to the "B" internal peripheral role. + * mux the pin to the "B" internal peripheral function. */ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) { @@ -104,13 +113,120 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].bsr); +#endif + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +#if defined(ATMEL_CPU_HAS_PIO3) +/* + * mux the pin to the "C" internal peripheral function. + */ +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); writel(mask, &pio->port[port].pdr); } return 0; } /* + * mux the pin to the "D" internal peripheral function. + */ +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * enable/disable the debounce filter. + */ +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (is_on) { + writel(1 << pin, &pio->port[port].ifscer); + writel(div & PIO_SCDR_DIV_MASK, &pio->port[port].scdr); + writel(1 << pin, &pio->port[port].ifer); + } else { + writel(1 << pin, &pio->port[port].ifdr); + } + } + return 0; +} + +/* + * enable/disable the pull-down. + * If pull-up already enabled while calling the function, we disable it. + */ +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_pulldown) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + writel(1 << pin, &pio->port[port].pudr); + if (is_pulldown) + writel(1 << pin, &pio->port[port].ppder); + else + writel(1 << pin, &pio->port[port].ppddr); + } + return 0; +} + +/* + * Set Schmitt trigger mode + */ +int at91_set_pio_schmitt_trig(unsigned port, unsigned pin, int is_enabled) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 data; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + data = readl(&pio->port[port].schmitt); + if (is_enabled) + data &= ~(1 << pin); + else + data |= (1 << pin); + writel(data, &pio->port[port].schmitt); + } + return 0; +} +#endif + +/* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. */ @@ -162,10 +278,14 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; - if (is_on) + if (is_on) { +#if defined(ATMEL_CPU_HAS_PIO3) + writel(mask, &pio->port[port].ifscdr); +#endif writel(mask, &pio->port[port].ifer); - else + } else { writel(mask, &pio->port[port].ifdr); + } } return 0; } -- 1.7.3.3

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[U-Boot] [PATCH v8 0/4] Add SMDK5250 board support
by Chander Kashyap 06 Feb '12

06 Feb '12

This patchset add support for Samsung's SMDK5250 board based on EXYNOS5250 based SoC. It also adds support for MMC SPL booting. The porting is done by Samsung engineers at HQ in System LSI Team. I am contributing in upstreaming the code for the board. Based upon discussions following patches are dropped in this version: Exynos: Add CONFIG_EXYNOS4 Macro to EXYNOS4 based boards Exynos: Clock.c: Replace exynos4 prefix with exynos SMDK5250: enable device tree support is squashed with EXYNOS: Add SMDK5250 board support Chander Kashyap (4): Exynos: Clock.c: Use CONFIG_SYS_CLK_FREQ macro ARM: EXYNOS: Add support for Exynos5 based SoCs EXYNOS: Add SMDK5250 board support EXYNOS: SMDK5250: Add MMC SPL support MAINTAINERS | 1 + arch/arm/cpu/armv7/exynos/clock.c | 214 +++++++++++++- arch/arm/include/asm/arch-exynos/clock.h | 326 +++++++++++++++++++++ arch/arm/include/asm/arch-exynos/cpu.h | 35 +++- arch/arm/include/asm/arch-exynos/dmc.h | 146 ++++++++++ arch/arm/include/asm/arch-exynos/gpio.h | 99 ++++++- arch/arm/include/asm/arch-exynos/tzpc.h | 52 ++++ board/samsung/smdk5250/Makefile | 58 ++++ board/samsung/smdk5250/clock_init.c | 202 +++++++++++++ board/samsung/smdk5250/dmc_init.c | 462 ++++++++++++++++++++++++++++++ board/samsung/smdk5250/lowlevel_init.S | 96 ++++++ board/samsung/smdk5250/mmc_boot.c | 58 ++++ board/samsung/smdk5250/setup.h | 451 +++++++++++++++++++++++++++++ board/samsung/smdk5250/smdk5250.c | 146 ++++++++++ board/samsung/smdk5250/tzpc_init.c | 48 +++ boards.cfg | 1 + include/configs/s5pc210_universal.h | 1 + include/configs/smdk5250.h | 197 +++++++++++++ include/configs/trats.h | 1 + tools/Makefile | 6 + tools/mksmdk5250spl.c | 119 ++++++++ 21 files changed, 2702 insertions(+), 17 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/dmc.h create mode 100644 arch/arm/include/asm/arch-exynos/tzpc.h create mode 100644 board/samsung/smdk5250/Makefile create mode 100644 board/samsung/smdk5250/clock_init.c create mode 100644 board/samsung/smdk5250/dmc_init.c create mode 100644 board/samsung/smdk5250/lowlevel_init.S create mode 100644 board/samsung/smdk5250/mmc_boot.c create mode 100644 board/samsung/smdk5250/setup.h create mode 100644 board/samsung/smdk5250/smdk5250.c create mode 100644 board/samsung/smdk5250/tzpc_init.c create mode 100644 include/configs/smdk5250.h create mode 100644 tools/mksmdk5250spl.c -- 1.7.5.4

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[U-Boot] [PATCH] TRATS: set gpio of UART correctly
by Minkyu Kang 06 Feb '12

06 Feb '12

Signed-off-by: Minkyu Kang <mk7.kang(a)samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim(a)samsung.com> Cc: Chander Kashyap <chander.kashyap(a)linaro.org> --- board/samsung/trats/trats.c | 18 +++++++----------- 1 files changed, 7 insertions(+), 11 deletions(-) diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index f795ff0..aa4291d 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -336,21 +336,17 @@ static void board_uart_init(void) (struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2(); int i; - /* UART0-UART1 GPIOs (part1) : 0x22222222 */ - for (i = 0; i < 7; i++) { - s5p_gpio_set_pull(&gpio1->a0, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a0, i, GPIO_FUNC(0x2)); - } - /* - * UART2-UART3 GPIOs (part2) : 0x00223322 - * GPA1CON[3] = I2C_3_SCL (3) + * UART2 GPIOs + * GPA1CON[0] = UART_2_RXD(2) + * GPA1CON[1] = UART_2_TXD(2) * GPA1CON[2] = I2C_3_SDA (3) + * GPA1CON[3] = I2C_3_SCL (3) */ - for (i = 0; i < 5; i++) { + + for (i = 0; i < 4; i++) { s5p_gpio_set_pull(&gpio1->a1, i, GPIO_PULL_NONE); - s5p_gpio_cfg_pin(&gpio1->a1, i, - GPIO_FUNC((i == 2 || i == 3) ? 0x3 : 0x2)); + s5p_gpio_cfg_pin(&gpio1->a1, i, GPIO_FUNC((i > 1) ? 0x3 : 0x2)); } /* UART_SEL GPY4[7] (part2) at EXYNOS4 */ -- 1.7.5.4

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[U-Boot] [PATCH 0/2] da850evm: add board specific functions
by Manjunath Hadli 06 Feb '12

06 Feb '12

There are two da850 SOC based EVMs, one from Spectrum digital and other from Logic PD. Boards from Spectrum digital have mac address stored in I2C EEPROM and they have spi flash manufactured by WINBOND. Boards from Logic PD store mac address in ST Microelectronics SPI flash. This patch series adds support to read mac address from the appropriate device. These patches have undergone a review previously, but since the tree has moved ahead Christian and Tom asked to resubmit the patches for review. (http://www.mail-archive.com/u-boot@lists.denx.de/msg76220.html) Manjunath Hadli (2): da850evm: add support to read mac address from spi flash da850evm: read mac address from I2C EEPROM on AM18x EVM board/davinci/da8xxevm/da850evm.c | 66 +++++++++++++++++++++++++++++++++++++ boards.cfg | 4 +- 2 files changed, 68 insertions(+), 2 deletions(-)

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[U-Boot] ARM ld: .bss overlaps section .rel.dyn
by Amit Virdi 05 Feb '12

05 Feb '12

Hi All, I'm in the process of updating platform support for spear series of SoC on the latest u-boot. I picked u-boot v2011.12. I tried compiling for different spear boards (spear 300, 310, 300 and spear600). In every compilation, I'm getting following errors: ----------------------- arm-linux-ld: section .bss [007263cc -> 00728c5b] overlaps section .rel.dyn [007263cc -> 0072a623] arm-linux-ld: u-boot: section .bss lma 0x7263cc overlaps previous sections make: *** [u-boot] Error 1 ----------------------- This is one case. Now if I apply some patches -all of them are either enhancing the features or are bug fixes - over the base line code, my code compiles *after* certain patch. None of these patches is changing any linker script. I drilled down to the last patch that made the code compile without error. Specifically, that commit is configuring Network support for SPEAr SoCs. Anyways, I did try to compare the map files generated for the good and the bad case but really couldn't conclude much!! Any pointers? Thanks Amit Virdi

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Re: [U-Boot] Avoiding reload on ARM U-BOOT
by Marek Vasut 05 Feb '12

05 Feb '12

> Hello Marek ALWAYS CC U-BOOT ML > > Thank you for your answer > > My SOC (Marvells Armada Controller) uses a bootrom code to copy to > initialize the DRAM and to copy the u-boot image. so the entire DRAM init > and copy sequence in u-boot is redundant. I see. I know about this soc's bootrom. Though it still can't place the bootloader properly to the end of DRAM. > > in previous version there was a way to avoid this. i find it limiting that > there isn't a way in the new version. > > Why would i want to relocate the code anyway ? See above, to place it to the end of DRAM. > > Yehuda > > On Thu, Feb 2, 2012 at 11:34 AM, Marek Vasut <marek.vasut(a)gmail.com> wrote: > > > Hello everyone > > > > > > im trying to port u-boot 2011-09 to a new board with an arm based SOC > > > > > > i found that u-boot will always relocate the code even if it is placed > > > already in DDR which is the case with my SOC. > > > > The u-boot is always relocated to the end of the DRAM, which is likely > > what you > > want. And it's quite a quick process. So if you are manufacturing your > > soc with > > various size of RAM, you want the relocation to happen. What SoC is that > > anyway? > > > > > is there any clean way to avoid relocating the u-boot ? does the > > > various SPL configs have something to do with that ? > > > > Not really and you don't want this to happen. > > > > M > > > > > if yes which one should i define ? > > > > > > Thanks in advance > > > > > > Yehuda

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[U-Boot] [PATCH] mx28: fix SPL code to make USB booting work
by Matthias Fuchs 04 Feb '12

04 Feb '12

This patch fixes booting i.MX28 CPUs via USB download. In this mode the CPU's bootrom implements a USB HID device that accepts a bootstream. When downloading the bootstream via USB, first the SPL code is received and executed. Then the u-boot image is received and called. The USB bootmode is interrupt driven. This patch fixes two things: 1) The ARM's fast interrupt mode is disabled when the SPL code has been run. This is the default state when called by the bootrom. 2) The exception vector location is set back to bootrom space to make the USB interrupts work again. The SPL code needs to change this option for the ram size probing. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- arch/arm/cpu/arm926ejs/mx28/start.S | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/mx28/start.S b/arch/arm/cpu/arm926ejs/mx28/start.S index 2cd4d73..4116bb1 100644 --- a/arch/arm/cpu/arm926ejs/mx28/start.S +++ b/arch/arm/cpu/arm926ejs/mx28/start.S @@ -185,6 +185,23 @@ _reset: bl board_init_ll + /* + * turn of fast interrupt mode (required by bootrom for USB boot) + */ + mrs r0,cpsr + bic r0,r0,#0x80 + msr cpsr,r0 + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + /* + * set exception vector location back to bootrom space. + * (required by bootrom for USB boot) + */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #0x00002000 /* set bit 13 'V' */ + mcr p15, 0, r0, c1, c0, 0 +#endif + pop {r0-r12,r14} bx lr -- 1.6.1

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[U-Boot] [PATCH 0/7] tegra: Add I2C driver and associated parts
by Simon Glass 04 Feb '12

04 Feb '12

This series brings in an I2C driver for Tegra which can be configured by a flat device tree. It supports 8- and 16-bit addresses and both the normal I2C ports and the DVC port (for controlling the power management unit (PMU)). Simon Glass (6): tegra: Rename NV_PA_PMC_BASE to TEGRA2_PMC_BASE tegra: fdt: Add extra I2C definitions for U-Boot tegra: Add I2C support to funcmux tegra: Initialise I2C on Nvidia boards tegra: Select I2C ordering for Seaboard tegra: Enable I2C on Seaboard Yen Lin (1): tegra: Add I2C driver arch/arm/cpu/armv7/tegra2/ap20.c | 10 +- arch/arm/cpu/armv7/tegra2/board.c | 2 +- arch/arm/cpu/armv7/tegra2/funcmux.c | 75 +++- arch/arm/dts/tegra20.dtsi | 12 + arch/arm/include/asm/arch-tegra2/funcmux.h | 3 + arch/arm/include/asm/arch-tegra2/tegra2.h | 8 +- arch/arm/include/asm/arch-tegra2/tegra2_i2c.h | 167 ++++++++ board/nvidia/common/board.c | 4 + board/nvidia/dts/tegra2-seaboard.dts | 5 + drivers/i2c/Makefile | 1 + drivers/i2c/tegra2_i2c.c | 533 +++++++++++++++++++++++++ include/configs/seaboard.h | 8 + include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 14 files changed, 809 insertions(+), 21 deletions(-) create mode 100644 arch/arm/include/asm/arch-tegra2/tegra2_i2c.h create mode 100644 drivers/i2c/tegra2_i2c.c -- 1.7.3.1

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