November 2012 - U-Boot

[U-Boot] Pull request - microblaze
by Michal Simek 04 Feb '13

04 Feb '13

Hi Tom, please add these 5 patches to u-boot. Currently microblaze can't be compiled and this patch "microblaze: Remove asm/bitops.h from asm/posix_types.h" fixed it. Thanks, Michal The following changes since commit 1cc619be8b73abbee2fd6faf2cd4ade27b516531: Tom Rini (1): Merge branch 'master' of git://git.denx.de/u-boot-avr32 are available in the git repository at: git://www.denx.de/git/u-boot-microblaze.git master Michal Simek (5): microblaze: Fix compilation warning in ext2_find_next_zero_bit microblaze: Fix byteorder for microblaze microblaze: Flush caches before enabling them microblaze: Remove asm/bitops.h from asm/posix_types.h microblaze: Fix compilation failure because of missing libdts arch/microblaze/cpu/cache.c | 5 ----- arch/microblaze/cpu/start.S | 6 ++++++ arch/microblaze/cpu/u-boot.lds | 2 ++ arch/microblaze/include/asm/bitops.h | 3 ++- arch/microblaze/include/asm/byteorder.h | 23 ----------------------- arch/microblaze/include/asm/posix_types.h | 3 --- arch/microblaze/lib/bootm.c | 5 ----- include/configs/microblaze-generic.h | 4 ++++ 8 files changed, 14 insertions(+), 37 deletions(-) -- Michal Simek, Ing. (M.Eng) w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel 2.6 Microblaze Linux - http://www.monstr.eu/fdt/ Microblaze U-BOOT custodian

2 4

[U-Boot] [PATCH] configs:Remove unused macro CONFIG_DISCOVER_PHY
by Ashok Kumar Reddy 04 Feb '13

04 Feb '13

Remove unused macro CONFIG_DISCOVER_PHY from configs. Signed-off-by: Ashok Kumar Reddy <ashokkourla2000(a)gmail.com> --- include/configs/apx4devkit.h | 1 - include/configs/sc_sps_1.h | 1 - 2 files changed, 2 deletions(-) diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h index 6764b47..73c66af 100644 --- a/include/configs/apx4devkit.h +++ b/include/configs/apx4devkit.h @@ -175,7 +175,6 @@ #define CONFIG_FEC_MXC_PHYADDR 0 #define IMX_FEC_BASE MXS_ENET0_BASE #define CONFIG_MII -#define CONFIG_DISCOVER_PHY #define CONFIG_FEC_XCV_TYPE RMII #endif diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h index f5dc393..6140d5b 100644 --- a/include/configs/sc_sps_1.h +++ b/include/configs/sc_sps_1.h @@ -160,7 +160,6 @@ #define CONFIG_FEC_MXC #define CONFIG_FEC_MXC_MULTI #define CONFIG_MII -#define CONFIG_DISCOVER_PHY #define CONFIG_FEC_XCV_TYPE RMII #define CONFIG_PHYLIB #define CONFIG_PHY_SMSC -- 1.7.9.5

3 3

[U-Boot] [PATCH 04/22] ARM: sunxi: watchdog support
by Henrik Nordström 03 Feb '13

03 Feb '13

This adds support for the hardware watchdog in Allwinner sun4i & sun5i (sunxi) SoC familiy. From: Henrik Nordstrom <henrik(a)henriknordstrom.net> Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/arm/cpu/armv7/sunxi/board.c | 3 ++ arch/arm/include/asm/arch-sunxi/sys_proto.h | 1 - drivers/watchdog/Makefile | 1 + drivers/watchdog/sunxi_watchdog.c | 49 +++++++++++++++++++++++++++ include/configs/sunxi-common.h | 4 ++ 5 files changed, 57 insertions(+), 1 deletions(-) create mode 100644 drivers/watchdog/sunxi_watchdog.c diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 652c19d..5c94110 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -59,6 +59,9 @@ int gpio_init(void) /* do some early init */ void s_init(void) { +#if defined(CONFIG_WATCHDOG) && defined(CONFIG_SUNXI_WATCHDOG) + watchdog_set(23); /* max possible timeout */ +#endif clock_init(); gpio_init(); } diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h index 1e8ae5d..9729100 100644 --- a/arch/arm/include/asm/arch-sunxi/sys_proto.h +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -27,6 +27,5 @@ void sr32(u32 *, u32, u32, u32); void sdelay(unsigned long); -void watchdog_init(void); #endif diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile index 923acb9..50b5fae 100644 --- a/drivers/watchdog/Makefile +++ b/drivers/watchdog/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libwatchdog.o COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o +COBJS-$(CONFIG_SUNXI_WATCHDOG) += sunxi_watchdog.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/watchdog/sunxi_watchdog.c b/drivers/watchdog/sunxi_watchdog.c new file mode 100644 index 0000000..65a763d --- /dev/null +++ b/drivers/watchdog/sunxi_watchdog.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom <henrik(a)hno.se> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/timer.h> +#include <asm/armv7.h> +#include <asm/io.h> + +void watchdog_reset(void) +{ + static struct sunxi_wdog *const wdog = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* a little magic to reload the watchdog */ + writel(0xA57 << 1 | 1 << 0, &wdog->ctl); +} + +static void watchdog_set(int interval) +{ + static struct sunxi_wdog *const wdog = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; + + /* Set timeout, reset & enable */ + writel(interval << 2 | 1 << 1 | 1 << 0, &wdog->mode); + watchdog_reset(); +} + +void watchdog_init(void) +{ +#ifdef CONFIG_WATCHDOG + watchdog_set(23); /* max possible timeout */ +#endif +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index c2d16fb..5bf8eea 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -202,4 +202,8 @@ #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_CMD_I2C +/* Watchdog */ +/* #define CONFIG_WATCHDOG */ +/* #define CONFIG_SUNXI_WATCHDOG */ + #endif /* __CONFIG_H */ -- 1.7.7.6

2 1

[U-Boot] [PATCH] ARM: Fix malloc area size for versatile and integrator
by Marek Vasut 03 Feb '13

03 Feb '13

These boards couldn't save their environment because they couldn't malloc() the whole size of the sector. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Linus Walleij <linus.walleij(a)linaro.org> --- include/configs/integratorcp.h | 2 +- include/configs/versatile.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 57610a6..511fa1f 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -56,7 +56,7 @@ /* * Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128*1024) /* * Hardware drivers diff --git a/include/configs/versatile.h b/include/configs/versatile.h index bb835e0..6a9aa30 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -71,7 +71,7 @@ * Size of malloc() pool */ #define CONFIG_ENV_SIZE 8192 -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SECT_SIZE + 128 * 1024) /* * Hardware drivers -- 1.7.9

3 5

[U-Boot] [PATCH] patman: Look for checkpatch in the scripts directory
by Doug Anderson 01 Feb '13

01 Feb '13

The Linux kernel stores checkpatch.pl in the scripts directory. Add that to the search path to make things more automatic for kernel development. Signed-off-by: Doug Anderson <dianders(a)chromium.org> --- tools/patman/checkpatch.py | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/tools/patman/checkpatch.py b/tools/patman/checkpatch.py index d831087..f72f8ee 100644 --- a/tools/patman/checkpatch.py +++ b/tools/patman/checkpatch.py @@ -26,10 +26,12 @@ import re import terminal def FindCheckPatch(): + top_level = gitutil.GetTopLevel() try_list = [ os.getcwd(), os.path.join(os.getcwd(), '..', '..'), - os.path.join(gitutil.GetTopLevel(), 'tools'), + os.path.join(top_level, 'tools'), + os.path.join(top_level, 'scripts'), '%s/bin' % os.getenv('HOME'), ] # Look in current dir -- 1.7.7.3

2 2

[U-Boot] [PATCH 1/2] patman: Add spaces back into patman test
by Doug Anderson 01 Feb '13

01 Feb '13

The patman test code was failing because some extra spaces got stripped when it was applied. These spaces are critical to the test code working. Signed-off-by: Doug Anderson <dianders(a)chromium.org> --- tools/patman/test.py | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/patman/test.py b/tools/patman/test.py index cf42480..f801ced 100644 --- a/tools/patman/test.py +++ b/tools/patman/test.py @@ -119,8 +119,8 @@ index 6f3748d..f9e4e65 100644 --- a/README +++ b/README @@ -2026,6 +2026,17 @@ The following options need to be configured: - example, some LED's) on your board. At the moment, - the following checkpoints are implemented: + example, some LED's) on your board. At the moment, + the following checkpoints are implemented: +- Time boot progress + CONFIG_BOOTSTAGE @@ -134,7 +134,7 @@ index 6f3748d..f9e4e65 100644 + You can add calls to bootstage_mark() to set time markers. + - Standalone program support: - CONFIG_STANDALONE_LOAD_ADDR + CONFIG_STANDALONE_LOAD_ADDR diff --git a/common/bootstage.c b/common/bootstage.c new file mode 100644 -- 1.7.7.3

2 5

[U-Boot] [PATCH V1 1/3] phy: add phy_connect_by_mask
by Troy Kisky 28 Jan '13

28 Jan '13

It is useful to be able to try a range of possible phy addresses to connect. Signed-off-by: Troy Kisky <troy.kisky(a)boundarydevices.com> --- v2: no change --- drivers/net/phy/phy.c | 108 +++++++++++++++++++++++++++++++------------------ include/phy.h | 2 + 2 files changed, 71 insertions(+), 39 deletions(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index baef60f..a22d2e0 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -31,6 +31,7 @@ #include <miiphy.h> #include <phy.h> #include <errno.h> +#include <linux/err.h> /* Generic PHY support and helper functions */ @@ -573,6 +574,61 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) return 0; } +static struct phy_device *create_phy_by_mask(struct mii_dev *bus, + unsigned phy_mask, int devad, phy_interface_t interface) +{ + u32 phy_id = 0xffffffff; + while (phy_mask) { + int addr = ffs(phy_mask) - 1; + int r = get_phy_id(bus, addr, devad, &phy_id); + if (r < 0) + return ERR_PTR(r); + /* If the PHY ID is mostly f's, we didn't find anything */ + if ((phy_id & 0x1fffffff) != 0x1fffffff) + return phy_device_create(bus, addr, phy_id, interface); + phy_mask &= ~(1 << addr); + } + return NULL; +} + +static struct phy_device *search_for_existing_phy(struct mii_dev *bus, + unsigned phy_mask, phy_interface_t interface) +{ + /* If we have one, return the existing device, with new interface */ + while (phy_mask) { + int addr = ffs(phy_mask) - 1; + if (bus->phymap[addr]) { + bus->phymap[addr]->interface = interface; + return bus->phymap[addr]; + } + phy_mask &= ~(1 << addr); + } + return NULL; +} + +static struct phy_device *get_phy_device_by_mask(struct mii_dev *bus, + unsigned phy_mask, phy_interface_t interface) +{ + int i; + struct phy_device *phydev; + + phydev = search_for_existing_phy(bus, phy_mask, interface); + if (phydev) + return phydev; + /* Try Standard (ie Clause 22) access */ + /* Otherwise we have to try Clause 45 */ + for (i = 0; i < 5; i++) { + phydev = create_phy_by_mask(bus, phy_mask, + i ? i : MDIO_DEVAD_NONE, interface); + if (IS_ERR(phydev)) + return NULL; + if (phydev) + return phydev; + } + printf("Phy not found\n"); + return phy_device_create(bus, ffs(phy_mask) - 1, 0xffffffff, interface); +} + /** * get_phy_device - reads the specified PHY device and returns its @phy_device struct * @bus: the target MII bus @@ -584,38 +640,7 @@ int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id) struct phy_device *get_phy_device(struct mii_dev *bus, int addr, phy_interface_t interface) { - u32 phy_id = 0x1fffffff; - int i; - int r; - - /* If we have one, return the existing device, with new interface */ - if (bus->phymap[addr]) { - bus->phymap[addr]->interface = interface; - - return bus->phymap[addr]; - } - - /* Try Standard (ie Clause 22) access */ - r = get_phy_id(bus, addr, MDIO_DEVAD_NONE, &phy_id); - if (r) - return NULL; - - /* If the PHY ID is mostly f's, we didn't find anything */ - if ((phy_id & 0x1fffffff) != 0x1fffffff) - return phy_device_create(bus, addr, phy_id, interface); - - /* Otherwise we have to try Clause 45 */ - for (i = 1; i < 5; i++) { - r = get_phy_id(bus, addr, i, &phy_id); - if (r) - return NULL; - - /* If the phy_id is mostly Fs, there is no device there */ - if ((phy_id & 0x1fffffff) != 0x1fffffff) - break; - } - - return phy_device_create(bus, addr, phy_id, interface); + return get_phy_device_by_mask(bus, 1 << addr, interface); } int phy_reset(struct phy_device *phydev) @@ -688,9 +713,8 @@ int miiphy_reset(const char *devname, unsigned char addr) return phy_reset(phydev); } -struct phy_device *phy_connect(struct mii_dev *bus, int addr, - struct eth_device *dev, - phy_interface_t interface) +struct phy_device *phy_connect_by_mask(struct mii_dev *bus, unsigned phy_mask, + struct eth_device *dev, phy_interface_t interface) { struct phy_device *phydev; @@ -701,11 +725,11 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, /* Wait 15ms to make sure the PHY has come out of hard reset */ udelay(15000); - phydev = get_phy_device(bus, addr, interface); + phydev = get_phy_device_by_mask(bus, phy_mask, interface); if (!phydev) { - printf("Could not get PHY for %s:%d\n", bus->name, addr); - + printf("Could not get PHY for %s: phy mask %x\n", + bus->name, phy_mask); return NULL; } @@ -714,7 +738,7 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, if (phydev->dev) printf("%s:%d is connected to %s. Reconnecting to %s\n", - bus->name, addr, phydev->dev->name, dev->name); + bus->name, phydev->addr, phydev->dev->name, dev->name); phydev->dev = dev; @@ -723,6 +747,12 @@ struct phy_device *phy_connect(struct mii_dev *bus, int addr, return phydev; } +struct phy_device *phy_connect(struct mii_dev *bus, int addr, + struct eth_device *dev, phy_interface_t interface) +{ + return phy_connect_by_mask(bus, 1 << addr, dev, interface); +} + /* * Start the PHY. Returns 0 on success, or a negative error code. */ diff --git a/include/phy.h b/include/phy.h index 3c30f11..aea462f 100644 --- a/include/phy.h +++ b/include/phy.h @@ -202,6 +202,8 @@ int phy_reset(struct phy_device *phydev); struct phy_device *phy_connect(struct mii_dev *bus, int addr, struct eth_device *dev, phy_interface_t interface); +struct phy_device *phy_connect_by_mask(struct mii_dev *bus, unsigned phy_mask, + struct eth_device *dev, phy_interface_t interface); int phy_startup(struct phy_device *phydev); int phy_config(struct phy_device *phydev); int phy_shutdown(struct phy_device *phydev); -- 1.7.9.5

5 31

[U-Boot] [PATCH] AM335X: Set fdt_high for AM335X devices to enable booting with Device Tree
by Vaibhav Hiremath 28 Jan '13

28 Jan '13

For AM335X boards, such as the EVM and Bone Linux kernel fails to locate the device tree blob on boot. The reason being is that u-boot is copying the DT blob to the upper part of RAM when booting the kernel and the kernel is unable to access the blob. By setting the fdt_high variable to 0xffffffff (to prevent the copy) the kernel is able to locate the DT blob and boot. This patch is tested on BeagleBone platform. Signed-off-by: Vaibhav Hiremath <hvaibhav(a)ti.com> Cc: Tom Rini <trini(a)ti.com> --- include/configs/am335x_evm.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index a3752bc..1af9b97 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -49,6 +49,7 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x80200000\0" \ "fdtaddr=0x80F80000\0" \ + "fdt_high=0xffffffff\0" \ "rdaddr=0x81000000\0" \ "bootfile=/boot/uImage\0" \ "console=ttyO0,115200n8\0" \ -- 1.7.0.4

3 2

Re: [U-Boot] Nand flash R/W,saveenv issue..
by Marek Vasut 25 Jan '13

25 Jan '13

Dear Manukumar, > Hello, CCing someone who might actually help you, CCing the uboot mailing list, please keep it that way. > i can able to detect nand flash. > but i had an issue that i could not do operation(Read/write) > on nand flash. > i tried to erase the nand flash i got the error as below: > > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > NAND 32MiB 3,3V 8-bit: MTD Erase failure: -5 > > even if i try to saveenv then also is not saving the envionment > variables > > processor used: P1012 > nand flash: samsung K9F5608U0D > > please reply ASAP. > > manukumar > signal-networks Best regards, Marek Vasut

9 39

[U-Boot] [PATCH v4] Marvell MV88E61XX Switch Driver support
by Prafulla Wadaskar 25 Jan '13

25 Jan '13

Chips supported:- 1. 88E6161 6 port gbe swtich with 5 integrated PHYs 2. 88E6165 6 port gbe swtich with 5 integrated PHYs 2. 88E6132 3 port gbe swtich with 2 integrated PHYs Platform specific configuration supported Note: This driver is supported and tested against kirkwood egiga interface Contributors: Yotam Admon <yotam(a)marvell.com> Michael Blostein <michaelbl(a)marvell.com Reviewed by: Ronen Shitrit <rshitrit(a)marvell.com> Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- Changelog:- v2: updated as per review comments for v1 removed other two drivers form earlier patch debug_prints removed driver moved to drivers/net/ v3: updated as per review comments for v2 miiphy interface used, platform specific dependency resolved Chip id detection and printing added common code forked out some cosmetic and magic number fixes v4: updated as per review comments for v3 mv88e61xx.h added platform specific configuration support added some more documentation references provided cleaned rgmii delay enable related code drivers/net/Makefile | 1 + drivers/net/mv88e61xx.c | 296 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/mv88e61xx.h | 73 ++++++++++++ 3 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 drivers/net/mv88e61xx.c create mode 100644 drivers/net/mv88e61xx.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index a360a50..7d397d6 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_MACB) += macb.o COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o +COBJS-$(CONFIG_MV88E61XX_SWITCH) += mv88e61xx.o COBJS-$(CONFIG_NATSEMI) += natsemi.o COBJS-$(CONFIG_DRIVER_NE2000) += ne2000.o ne2000_base.o COBJS-$(CONFIG_DRIVER_AX88796L) += ax88796.o ne2000_base.o diff --git a/drivers/net/mv88e61xx.c b/drivers/net/mv88e61xx.c new file mode 100644 index 0000000..713e728 --- /dev/null +++ b/drivers/net/mv88e61xx.c @@ -0,0 +1,296 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <miiphy.h> +#include "mv88e61xx.h" + +/* Chip Address mode + * The Switch support two modes of operation + * 1. single chip mode and + * 2. Multi-chip mode + * Refer section 9.2 &9.3 in chip datasheet-02 for more details + * + * By default single chip mode is configured + * multichip mode operation can be configured in board header + */ +#ifndef CONFIG_MV88E61XX_MULTICHIP_ADRMODE +#define mv88e61xx_wr_phy miiphy_write +#define mv88e61xx_rd_phy miiphy_read +#else + +static int mv88e61xx_busychk_multic(u32 devaddr) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + + /* Poll till SMIBusy bit is clear */ + do { + miiphy_read(name, devaddr, 0x0, &reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT15); + return 0; +} + +static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write data to Switch indirect data register */ + miiphy_write(name, mii_dev_addr, 0x1, data); + /* Write command to Switch indirect command register (write) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); +} + +static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data) +{ + u16 reg; + u32 mii_dev_addr; + + /* command to read PHY dev address */ + miiphy_read(name, 0xEE, 0xEE, &mii_dev_addr); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Write command to Switch indirect command register (read) */ + miiphy_write(name, mii_dev_addr, 0x0, + reg_ofs | (phy_adr << 5) | BIT10 | BIT12 | BIT15); + mv88e61xx_busychk_multic(mii_dev_addr); + /* Read data from Switch indirect data register */ + miiphy_read(name, mii_dev_addr, 0x1, (u16 *) & data); +} +#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */ + +static void mv88e61xx_vlaninit(struct mv88f61xx_config *swconfig, + u32 max_prtnum, u32 ports_ofs) +{ + u32 prt; + u16 reg; + char *name = swconfig->name; + u32 cpu_port = swconfig->cpuport; + u32 port_mask = swconfig->ports_enabled; + + /* be sure all ports are disabled */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_CTRL_REG, + reg); + } + /* Set CPU port VID to 0x1 */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xfff; + reg |= 0x1; + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VID_REG, + reg); + + /* Setting Port default priority for all ports to zero */ + for (prt = 0; prt < max_prtnum; prt++) { + mv88e61xx_rd_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + &reg); + reg &= ~0xc000; + mv88e61xx_wr_phy(name, ports_ofs + prt, MV88E61XX_PRT_VID_REG, + reg); + } + /* Setting VID and VID map for all ports except CPU port */ + for (prt = 0; prt < max_prtnum; prt++) { + /* only for enabled ports */ + if ((1 << prt) & port_mask) { + /* skip CPU port */ + if (prt == cpu_port) + continue; + + /* + * set Ports VLAN Mapping. + * port prt <--> cpu_port VLAN #prt+1. + */ + + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, &reg); + reg &= ~0x0fff; + reg |= (prt + 1); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VID_REG, reg); + + /* + * Set Vlan map table for all ports to send only to + * cpu_port + */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= (1 << cpu_port); + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_VMAP_REG, reg); + } + } + /* Set Vlan map table for cpu_port to see all ports */ + mv88e61xx_rd_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + &reg); + reg &= ~((1 << max_prtnum) - 1); + reg |= port_mask & ~(1 << cpu_port); + mv88e61xx_wr_phy(name, (ports_ofs + cpu_port), MV88E61XX_PRT_VMAP_REG, + reg); + + /* + * enable only appropriate ports to forwarding mode + * and disable the others + */ + for (prt = 0; prt < max_prtnum; prt++) { + if ((1 << prt) & port_mask) { + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg |= 0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } else { + /* Disable port */ + mv88e61xx_rd_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + reg &= ~0x3; + mv88e61xx_wr_phy(name, ports_ofs + prt, + MV88E61XX_PRT_CTRL_REG, reg); + } + } +} + +/* + * Make sure SMIBusy bit cleared before another + * SMI operation can take place + */ +static int mv88361xx_busychk(char *name) +{ + u32 reg = 0; + u32 timeout = MV88E61XX_PHY_TIMEOUT; + do { + mv88e61xx_rd_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, (u16 *) & reg); + if (timeout-- == 0) { + printf("SMI busy timeout\n"); + return -1; + } + } while (reg & BIT28); /* busy mask */ + return 0; +} + +/* + * Marvell 88E61XX Switch initialization + */ +int mv_switch_88e61xx_init(struct mv88f61xx_config *swconfig) +{ + u32 prt; + u16 reg; + char *idstr; + char *name = swconfig->name; + + if (miiphy_set_current_dev(name)) { + printf("%s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->mode != MV88F61XX_MODE_SW_MANAGEED) { + printf("Unsupported mode %s failed\n", __FUNCTION__); + return -1; + } + + if (swconfig->cpuport < 4) { + swconfig->cpuport = 5; + printf("Invalid cpu port config, using default port5\n"); + } + + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST, PHY_PHYIDR2, &reg); + reg &= 0xfff0; + if (reg == 0x1610) + idstr = "88E6161"; + if (reg == 0x1650) + idstr = "88E6165"; + if (reg == 0x1210) { + idstr = "88E6123"; + swconfig->ports_enabled &= 0x023; /* ports 2,3,4 no available */ + } + + /* Init vlan */ + mv88e61xx_vlaninit(swconfig, MV88E61XX_MAX_PORTS_NUM, + MV88E61XX_PRT_OFST); + + if (swconfig->rgmii_delay == MV88F61XX_RGMII_DELAY_EN) { + /* + * Enable RGMII delay on Tx and Rx for CPU port + * Ref: sec 9.5 of chip datasheet-02 + */ + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 5, + MV88E61XX_RGMII_TIMECTRL_REG, 0x18); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + 4, + MV88E61XX_RGMII_TIMECTRL_REG, 0xc1e7); + } + + for (prt = 0; prt < MV88E61XX_MAX_PORTS_NUM; prt++) { + if (prt != swconfig->cpuport) { + /* Write Copper Specific control reg1 (0x14) for- + * Enable Phy power up + * Energy Detect on (sense&Xmit NLP Periodically + * reset other settings default + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x3360); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9410 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + + /* Write PHY ctrl reg (0x0) to apply + * Phy reset (BIT15=low) + * reset other default values + */ + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_DATA, 0x1140); + mv88e61xx_wr_phy(name, MV88E61XX_GLB2REG_DEVADR, + MV88E61XX_PHY_CMD, + (0x9400 | (prt << 5))); + + if (mv88361xx_busychk(name)) + return -1; + } + + /*Program port state */ + mv88e61xx_rd_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, &reg); + mv88e61xx_wr_phy(name, MV88E61XX_PRT_OFST + prt, + MV88E61XX_PRT_CTRL_REG, + reg | (swconfig->portstate & 0x03)); + } + + printf("%s Initialized on %s\n", idstr, name); + return 0; +} diff --git a/drivers/net/mv88e61xx.h b/drivers/net/mv88e61xx.h new file mode 100644 index 0000000..f1c86a6 --- /dev/null +++ b/drivers/net/mv88e61xx.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 + * Marvell Semiconductor <www.marvell.com> + * Prafulla Wadaskar <prafulla(a)marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _MV88E61XX_H +#define _MV88E61XX_H + +#define PORT(_x) (1 << _x) +#define MV88E61XX_CPU_PORT 0x5 +#define MV88E61XX_MAX_PORTS_NUM 0x6 + +#define MV88E61XX_PHY_TIMEOUT 100000 + +#define MV88E61XX_PRT_STS_REG 0x1 +#define MV88E61XX_PRT_CTRL_REG 0x4 +#define MV88E61XX_PRT_VMAP_REG 0x6 +#define MV88E61XX_PRT_VID_REG 0x7 + +#define MV88E61XX_PRT_OFST 0x10 +#define MV88E61XX_PHY_CMD 0x18 +#define MV88E61XX_PHY_DATA 0x19 +#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A +#define MV88E61XX_GLB2REG_DEVADR 0x1C + +/* constants for switch configuration */ +enum mv88f61xx_cfg_mode { + MV88F61XX_MODE_SW_MANAGEED, + MV88F61XX_MODE_SW_UNMANAGEED +}; + +enum mv88f61xx_cfg_rgmiid { + MV88F61XX_RGMII_DELAY_DIS, + MV88F61XX_RGMII_DELAY_EN +}; + +enum mv88f61xx_cfg_prtstt { + MV88E61XX_PORTSTT_DISABLED, + MV88E61XX_PORTSTT_BLOCKING, + MV88E61XX_PORTSTT_LEARNING, + MV88E61XX_PORTSTT_FORWARDING +}; + +/* switch configuration structure */ +struct mv88f61xx_config { + char *name; + enum mv88f61xx_cfg_mode mode; + enum mv88f61xx_cfg_rgmiid rgmii_delay; + enum mv88f61xx_cfg_prtstt portstate; + u32 ports_enabled; + u8 cpuport; +}; + +#endif /* _MV88E61XX_H */ -- 1.5.3.3

5 11