November 2012 - U-Boot

Re: [U-Boot] [Patch 2/2] MIPS: do not modify variable before relocate_code
by Daniel Schwierzeck 25 Nov '12

25 Nov '12

2012/11/24 Zhi-zhou Zhang <zhizhou.zh(a)gmail.com>: > Because timestamp is declared as `static', we needn't initialize > it by writing it a zero. If we do it before relocate_code, we > will write into a flash address(0xffffffffbfc0xxxx). > > Signed-off-by: Zhi-zhou Zhang <zhizhou.zh(a)gmail.com> > --- > arch/mips/cpu/mips32/time.c | 1 - > arch/mips/cpu/mips64/time.c | 1 - > 2 files changed, 2 deletions(-) > > diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c > index 350896a..09fc842 100644 > --- a/arch/mips/cpu/mips32/time.c > +++ b/arch/mips/cpu/mips32/time.c > @@ -36,7 +36,6 @@ static unsigned long timestamp; > int timer_init(void) > { > /* Set up the timer for the first expiration. */ > - timestamp = 0; > write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); > > return 0; > diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c > index 5154280..720f7b7 100644 > --- a/arch/mips/cpu/mips64/time.c > +++ b/arch/mips/cpu/mips64/time.c > @@ -37,7 +37,6 @@ static unsigned long timestamp; > int timer_init(void) > { > /* Set up the timer for the first expiration. */ > - timestamp = 0; > write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY); > > return 0; > -- > 1.7.9.5 > applied to u-boot-mips/master with a tiny fixup of the commit summary, thanks -- Best regards, Daniel

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[U-Boot] [PATCH 02/22] ARM: sunxi: MMC driver
by Henrik Nordström 25 Nov '12

25 Nov '12

This adds a basic MMC driver for Allwinner sun4i/sun5i family of SoC this driver is limited to a single MMC channel. Signed-off-by: Tom Cubie <tangliang(a)allwinnertech.com> Signed-off-by: Henrik Nodstrom <henrik(a)henriknordstrom.net> Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/arm/include/asm/arch-sunxi/mmc.h | 64 +++ board/sunxi/board.c | 9 + drivers/mmc/Makefile | 1 + drivers/mmc/sunxi_mmc.c | 674 +++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 14 +- 5 files changed, 759 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h create mode 100644 drivers/mmc/sunxi_mmc.c diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h new file mode 100644 index 0000000..e96e7d2 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Aaron <leafy.myeh(a)allwinnertech.com> + * + * MMC register definition for allwinner sunxi platform. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SUNXI_MMC_H +#define _SUNXI_MMC_H + +struct sunxi_mmc { + u32 gctrl; /* (0x00) SMC Global Control Register */ + u32 clkcr; /* (0x04) SMC Clock Control Register */ + u32 timeout; /* (0x08) SMC Time Out Register */ + u32 width; /* (0x0C) SMC Bus Width Register */ + u32 blksz; /* (0x10) SMC Block Size Register */ + u32 bytecnt; /* (0x14) SMC Byte Count Register */ + u32 cmd; /* (0x18) SMC Command Register */ + u32 arg; /* (0x1C) SMC Argument Register */ + u32 resp0; /* (0x20) SMC Response Register 0 */ + u32 resp1; /* (0x24) SMC Response Register 1 */ + u32 resp2; /* (0x28) SMC Response Register 2 */ + u32 resp3; /* (0x2C) SMC Response Register 3 */ + u32 imask; /* (0x30) SMC Interrupt Mask Register */ + u32 mint; /* (0x34) SMC Masked Interrupt Status Reg */ + u32 rint; /* (0x38) SMC Raw Interrupt Status Register */ + u32 status; /* (0x3C) SMC Status Register */ + u32 ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Reg */ + u32 funcsel; /* (0x44) SMC Function Select Register */ + u32 cbcr; /* (0x48) SMC CIU Byte Count Register */ + u32 bbcr; /* (0x4C) SMC BIU Byte Count Register */ + u32 dbgc; /* (0x50) SMC Debug Enable Register */ + u32 res0[11]; /* (0x54~0x7c) */ + u32 dmac; /* (0x80) SMC IDMAC Control Register */ + u32 dlba; /* (0x84) SMC IDMAC Descr List Base Addr Reg */ + u32 idst; /* (0x88) SMC IDMAC Status Register */ + u32 idie; /* (0x8C) SMC IDMAC Interrupt Enable Register */ + u32 chda; /* (0x90) */ + u32 cbda; /* (0x94) */ + u32 res1[26]; /* (0x98~0xff) */ + u32 fifo; /* (0x100) SMC FIFO Access Address */ +}; + +int sunxi_mmc_init(int sdc_no); +#endif /* _SUNXI_MMC_H */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index ae05953..50fb40f 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -55,3 +55,12 @@ int dram_init(void) return 0; } + +#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); + + return 0; +} +#endif diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index a1dd730..6128910 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -47,6 +47,7 @@ COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o COBJS-$(CONFIG_DWMMC) += dw_mmc.o +COBJS-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c new file mode 100644 index 0000000..05bc231 --- /dev/null +++ b/drivers/mmc/sunxi_mmc.c @@ -0,0 +1,674 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Aaron <leafy.myeh(a)allwinnertech.com> + * + * MMC driver for allwinner sunxi platform. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> +#include <malloc.h> +#include <mmc.h> + +#undef SUNXI_MMCDBG + +#ifdef SUNXI_MMCDBG +#define MMCDBG(fmt...) printf("[mmc]: "fmt) + +static void dumphex32(char *name, char *base, int len) +{ + __u32 i; + + printf("dump %s registers:", name); + for (i = 0; i < len; i += 4) { + if (!(i & 0xf)) + printf("\n0x%p : ", base + i); + printf("0x%08x ", readl(base + i)); + } + printf("\n"); +} + +static void dumpmmcreg(struct sunxi_mmc *reg) +{ + printf("dump mmc registers:\n"); + printf("gctrl 0x%08x\n", reg->gctrl); + printf("clkcr 0x%08x\n", reg->clkcr); + printf("timeout 0x%08x\n", reg->timeout); + printf("width 0x%08x\n", reg->width); + printf("blksz 0x%08x\n", reg->blksz); + printf("bytecnt 0x%08x\n", reg->bytecnt); + printf("cmd 0x%08x\n", reg->cmd); + printf("arg 0x%08x\n", reg->arg); + printf("resp0 0x%08x\n", reg->resp0); + printf("resp1 0x%08x\n", reg->resp1); + printf("resp2 0x%08x\n", reg->resp2); + printf("resp3 0x%08x\n", reg->resp3); + printf("imask 0x%08x\n", reg->imask); + printf("mint 0x%08x\n", reg->mint); + printf("rint 0x%08x\n", reg->rint); + printf("status 0x%08x\n", reg->status); + printf("ftrglevel 0x%08x\n", reg->ftrglevel); + printf("funcsel 0x%08x\n", reg->funcsel); + printf("dmac 0x%08x\n", reg->dmac); + printf("dlba 0x%08x\n", reg->dlba); + printf("idst 0x%08x\n", reg->idst); + printf("idie 0x%08x\n", reg->idie); +} +#else +#define MMCDBG(fmt...) +#define dumphex32(fmt...) +#define dumpmmcreg(fmt...) +#endif /* SUNXI_MMCDBG */ + +struct sunxi_mmc_des { + u32 reserved1_1:1; + u32 dic:1; /* disable interrupt on completion */ + u32 last_des:1; /* 1-this data buffer is the last buffer */ + u32 first_des:1; /* 1-data buffer is the first buffer, + 0-data buffer contained in the next + descriptor is 1st buffer */ + u32 des_chain:1; /* 1-the 2nd address in the descriptor is the + next descriptor address */ + u32 end_of_ring:1; /* 1-last descriptor flag when using dual + data buffer in descriptor */ + u32 reserved1_2:24; + u32 card_err_sum:1; /* transfer error flag */ + u32 own:1; /* des owner:1-idma owns it, 0-host owns it */ +#if defined CONFIG_SUN4I +#define SDXC_DES_NUM_SHIFT 13 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) + u32 data_buf1_sz:13; + u32 data_buf2_sz:13; + u32 reserverd2_1:6; +#elif defined CONFIG_SUN5I +#define SDXC_DES_NUM_SHIFT 16 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) + u32 data_buf1_sz:16; + u32 data_buf2_sz:16; +#else +#error ">>>> Wrong Platform for MMC <<<<" +#endif + u32 buf_addr_ptr1; + u32 buf_addr_ptr2; +}; + +struct sunxi_mmc_host { + unsigned mmc_no; + uint32_t *mclkreg; + unsigned database; + unsigned fatal_err; + unsigned mod_clk; + struct sunxi_mmc *reg; + struct sunxi_mmc_des *pdes; +}; + +/* support 4 mmc hosts */ +struct mmc mmc_dev[4]; +struct sunxi_mmc_host mmc_host[4]; + +static int mmc_resource_init(int sdc_no) +{ + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + MMCDBG("init mmc %d resource\n", sdc_no); + + switch (sdc_no) { + case 0: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; + mmchost->mclkreg = &ccm->sd0_clk_cfg; + break; + case 1: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; + mmchost->mclkreg = &ccm->sd1_clk_cfg; + break; + case 2: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; + mmchost->mclkreg = &ccm->sd2_clk_cfg; + break; + case 3: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; + mmchost->mclkreg = &ccm->sd3_clk_cfg; + break; + default: + printf("Wrong mmc number %d\n", sdc_no); + return -1; + } + mmchost->database = (unsigned int)mmchost->reg + 0x100; + mmchost->mmc_no = sdc_no; + + return 0; +} + +static int mmc_clk_io_on(int sdc_no) +{ + unsigned int rval; + unsigned int pll5_clk; + unsigned int divider; + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + static struct sunxi_gpio *gpio_c = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_C]; + static struct sunxi_gpio *gpio_f = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_F]; +#if CONFIG_MMC1_PG + static struct sunxi_gpio *gpio_g = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_G]; +#endif + static struct sunxi_gpio *gpio_h = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_H]; + static struct sunxi_gpio *gpio_i = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[SUNXI_GPIO_I]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + MMCDBG("init mmc %d clock and io\n", sdc_no); + + /* config gpio */ + switch (sdc_no) { + case 0: + /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ + writel(0x222222, &gpio_f->cfg[0]); + writel(0x555, &gpio_f->pull[0]); + writel(0xaaa, &gpio_f->drv[0]); + break; + + case 1: +#if CONFIG_MMC1_PG + /* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */ + writel(0x444444, &gpio_g->cfg[0]); + writel(0x555, &gpio_g->pull[0]); + writel(0xaaa, &gpio_g->drv[0]); +#else + /* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */ + writel(0x55 << 24, &gpio_h->cfg[2]); + writel(0x5555, &gpio_h->cfg[3]); + writel(0x555 << 12, &gpio_h->pull[1]); + writel(0xaaa << 12, &gpio_h->drv[1]); +#endif + break; + + case 2: + /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ + writel(0x33 << 24, &gpio_c->cfg[0]); + writel(0x3333, &gpio_c->cfg[1]); + writel(0x555 << 12, &gpio_c->pull[0]); + writel(0xaaa << 12, &gpio_c->drv[0]); + break; + + case 3: + /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */ + writel(0x2222 << 16, &gpio_i->cfg[0]); + writel(0x22, &gpio_i->cfg[1]); + writel(0x555 << 8, &gpio_i->pull[0]); + writel(0x555 << 8, &gpio_i->drv[0]); + break; + + default: + return -1; + } + + /* config ahb clock */ + rval = readl(&ccm->ahb_gate0); + rval |= (1 << (8 + sdc_no)); + writel(rval, &ccm->ahb_gate0); + + /* config mod clock */ + pll5_clk = clock_get_pll5(); + if (pll5_clk > 400000000) + divider = 4; + else + divider = 3; + writel((1U << 31) | (2U << 24) | divider, mmchost->mclkreg); + mmchost->mod_clk = pll5_clk / (divider + 1); + + dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100); + dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100); + dumphex32("mmc", (char *)mmchost->reg, 0x100); + + return 0; +} + +static int mmc_update_clk(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned int cmd; + unsigned timeout = 0xfffff; + + cmd = (1U << 31) | (1 << 21) | (1 << 13); + writel(cmd, &mmchost->reg->cmd); + while ((readl(&mmchost->reg->cmd) & 0x80000000) && timeout--) + ; + if (!timeout) + return -1; + + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); + + return 0; +} + +static int mmc_config_clock(struct mmc *mmc, unsigned div) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned rval = readl(&mmchost->reg->clkcr); + + /* + * CLKCREG[7:0]: divider + * CLKCREG[16]: on/off + * CLKCREG[17]: power save + */ + /* Disable Clock */ + rval &= ~(1 << 16); + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + + /* Change Divider Factor */ + rval &= ~(0xFF); + rval |= div; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + /* Re-enable Clock */ + rval |= (1 << 16); + writel(rval, &mmchost->reg->clkcr); + + if (mmc_update_clk(mmc)) + return -1; + + return 0; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned int clkdiv = 0; + + MMCDBG("set ios: bus_width: %x, clock: %d, mod_clk\n", mmc->bus_width, + mmc->clock, mmchost->mod_clk); + + /* Change clock first */ + clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2; + if (mmc->clock) + if (mmc_config_clock(mmc, clkdiv)) { + mmchost->fatal_err = 1; + return; + } + + /* Change bus width */ + if (mmc->bus_width == 8) + writel(2, &mmchost->reg->width); + else if (mmc->bus_width == 4) + writel(1, &mmchost->reg->width); + else + writel(0, &mmchost->reg->width); +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + + /* Reset controller */ + writel(0x7, &mmchost->reg->gctrl); + + return 0; +} + +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned i; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned *buff; + unsigned timeout = 0xfffff; + + if (data->flags & MMC_DATA_READ) { + buff = (unsigned int *)data->dest; + for (i = 0; i < (byte_cnt >> 2); i++) { + while (--timeout + && (readl(&mmchost->reg->status) & (1 << 2))) + ; + if (timeout <= 0) + goto out; + buff[i] = readl(mmchost->database); + timeout = 0xfffff; + } + } else { + buff = (unsigned int *)data->src; + for (i = 0; i < (byte_cnt >> 2); i++) { + while (--timeout + && (readl(&mmchost->reg->status) & (1 << 3))) + ; + if (timeout <= 0) + goto out; + writel(buff[i], mmchost->database); + timeout = 0xfffff; + } + } + +out: + if (timeout <= 0) + return -1; + + return 0; +} + +static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + struct sunxi_mmc_des *pdes = mmchost->pdes; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned char *buff; + unsigned des_idx = 0; + unsigned buff_frag_num = 0; + unsigned remain; + unsigned i, rval; + + buff = data->flags & MMC_DATA_READ ? + (unsigned char *)data->dest : (unsigned char *)data->src; + buff_frag_num = byte_cnt >> SDXC_DES_NUM_SHIFT; + + remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1); + if (remain) + buff_frag_num++; + else + remain = SDXC_DES_BUFFER_MAX_LEN; + + flush_cache((unsigned long)buff, (unsigned long)byte_cnt); + for (i = 0; i < buff_frag_num; i++, des_idx++) { + memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des)); + pdes[des_idx].des_chain = 1; + pdes[des_idx].own = 1; + pdes[des_idx].dic = 1; + if (buff_frag_num > 1 && i != buff_frag_num - 1) + pdes[des_idx].data_buf1_sz = + (SDXC_DES_BUFFER_MAX_LEN - + 1) & SDXC_DES_BUFFER_MAX_LEN; + else + pdes[des_idx].data_buf1_sz = remain; + + pdes[des_idx].buf_addr_ptr1 = + (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN; + if (i == 0) + pdes[des_idx].first_des = 1; + + if (i == buff_frag_num - 1) { + pdes[des_idx].dic = 0; + pdes[des_idx].last_des = 1; + pdes[des_idx].end_of_ring = 1; + pdes[des_idx].buf_addr_ptr2 = 0; + } else { + pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1]; + } + MMCDBG("frag %d, remain %d, des[%d](%08x): " + "[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n", + i, remain, des_idx, (u32)&pdes[des_idx], + (u32)((u32 *)&pdes[des_idx])[0], + (u32)((u32 *)&pdes[des_idx])[1], + (u32)((u32 *)&pdes[des_idx])[2], + (u32)((u32 *)&pdes[des_idx])[3]); + } + flush_cache((unsigned long)pdes, + sizeof(struct sunxi_mmc_des) * (des_idx + 1)); + + /* + * GCTRLREG + * GCTRL[2] : DMA reset + * GCTRL[5] : DMA enable + * + * IDMACREG + * IDMAC[0] : IDMA soft reset + * IDMAC[1] : IDMA fix burst flag + * IDMAC[7] : IDMA on + * + * IDIECREG + * IDIE[0] : IDMA transmit interrupt flag + * IDIE[1] : IDMA receive interrupt flag + */ + rval = readl(&mmchost->reg->gctrl); + writel(rval | (1 << 5) | (1 << 2), &mmchost->reg->gctrl); /* dma enable */ + writel((1 << 0), &mmchost->reg->dmac); /* idma reset */ + writel((1 << 1) | (1 << 7), &mmchost->reg->dmac); /* idma on */ + rval = readl(&mmchost->reg->idie) & (~3); + if (data->flags & MMC_DATA_WRITE) + rval |= (1 << 0); + else + rval |= (1 << 1); + writel(rval, &mmchost->reg->idie); + writel((u32) pdes, &mmchost->reg->dlba); + writel((2U << 28) | (7 << 16) | 8, &mmchost->reg->ftrglevel); + + return 0; +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned int cmdval = 0x80000000; + signed int timeout = 0; + int error = 0; + unsigned int status = 0; + unsigned int usedma = 0; + unsigned int bytecnt = 0; + + if (mmchost->fatal_err) + return -1; + if (cmd->resp_type & MMC_RSP_BUSY) + MMCDBG("mmc cmd %d check rsp busy\n", cmd->cmdidx); + if (cmd->cmdidx == 12) + return 0; + + /* + * CMDREG + * CMD[5:0] : Command index + * CMD[6] : Has response + * CMD[7] : Long response + * CMD[8] : Check response CRC + * CMD[9] : Has data + * CMD[10] : Write + * CMD[11] : Steam mode + * CMD[12] : Auto stop + * CMD[13] : Wait previous over + * CMD[14] : About cmd + * CMD[15] : Send initialization + * CMD[21] : Update clock + * CMD[31] : Load cmd + */ + if (!cmd->cmdidx) + cmdval |= (1 << 15); + if (cmd->resp_type & MMC_RSP_PRESENT) + cmdval |= (1 << 6); + if (cmd->resp_type & MMC_RSP_136) + cmdval |= (1 << 7); + if (cmd->resp_type & MMC_RSP_CRC) + cmdval |= (1 << 8); + + if (data) { + if ((u32) data->dest & 0x3) { + error = -1; + goto out; + } + + cmdval |= (1 << 9) | (1 << 13); + if (data->flags & MMC_DATA_WRITE) + cmdval |= (1 << 10); + if (data->blocks > 1) + cmdval |= (1 << 12); + writel(data->blocksize, &mmchost->reg->blksz); + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); + } + + MMCDBG("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); + writel(cmd->cmdarg, &mmchost->reg->arg); + + if (!data) + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { + int ret = 0; + + bytecnt = data->blocksize * data->blocks; + MMCDBG("trans data %d bytes\n", bytecnt); +#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD) + if (bytecnt > 64) { +#else + if (0) { +#endif + usedma = 1; + writel(readl(&mmchost->reg->gctrl) & (~0x80000000), + &mmchost->reg->gctrl); + ret = mmc_trans_data_by_dma(mmc, data); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + } else { + writel(readl(&mmchost->reg->gctrl) | 0x80000000, + &mmchost->reg->gctrl); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + ret = mmc_trans_data_by_cpu(mmc, data); + } + if (ret) { + error = readl(&mmchost->reg->rint) & 0xbfc2; + goto out; + } + } + + timeout = 0xfffff; + do { + status = readl(&mmchost->reg->rint); + if (!timeout-- || (status & 0xbfc2)) { + error = status & 0xbfc2; + MMCDBG("cmd timeout %x\n", error); + goto out; + } + } while (!(status & 0x4)); + + if (data) { + unsigned done = 0; + timeout = usedma ? 0xffff * bytecnt : 0xffff; + MMCDBG("cacl timeout %x\n", timeout); + do { + status = readl(&mmchost->reg->rint); + if (!timeout-- || (status & 0xbfc2)) { + error = status & 0xbfc2; + MMCDBG("data timeout %x\n", error); + goto out; + } + if (data->blocks > 1) + done = status & (1 << 14); + else + done = status & (1 << 3); + } while (!done); + } + + if (cmd->resp_type & MMC_RSP_BUSY) { + timeout = 0xfffff; + do { + status = readl(&mmchost->reg->status); + if (!timeout--) { + error = -1; + MMCDBG("busy timeout\n"); + goto out; + } + } while (status & (1 << 9)); + } + + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&mmchost->reg->resp3); + cmd->response[1] = readl(&mmchost->reg->resp2); + cmd->response[2] = readl(&mmchost->reg->resp1); + cmd->response[3] = readl(&mmchost->reg->resp0); + MMCDBG("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + cmd->response[3], cmd->response[2], + cmd->response[1], cmd->response[0]); + } else { + cmd->response[0] = readl(&mmchost->reg->resp0); + MMCDBG("mmc resp 0x%08x\n", cmd->response[0]); + } +out: + if (data && usedma) { + /* IDMASTAREG + * IDST[0] : idma tx int + * IDST[1] : idma rx int + * IDST[2] : idma fatal bus error + * IDST[4] : idma descriptor invalid + * IDST[5] : idma error summary + * IDST[8] : idma normal interrupt sumary + * IDST[9] : idma abnormal interrupt sumary + */ + status = readl(&mmchost->reg->idst); + writel(status, &mmchost->reg->idst); + writel(0, &mmchost->reg->idie); + writel(0, &mmchost->reg->dmac); + writel(readl(&mmchost->reg->gctrl) & (~(1 << 5)), + &mmchost->reg->gctrl); + } + if (error) { + writel(0x7, &mmchost->reg->gctrl); + mmc_update_clk(mmc); + MMCDBG("mmc cmd %d err 0x%08x\n", cmd->cmdidx, error); + } + writel(0xffffffff, &mmchost->reg->rint); + writel(readl(&mmchost->reg->gctrl) | (1 << 1), &mmchost->reg->gctrl); + + if (error) + return -1; + else + return 0; +} + +int sunxi_mmc_init(int sdc_no) +{ + struct mmc *mmc; + + memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc)); + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); + mmc = &mmc_dev[sdc_no]; + + sprintf(mmc->name, "SUNXI SD/MMC"); + mmc->priv = &mmc_host[sdc_no]; + mmc->send_cmd = mmc_send_cmd; + mmc->set_ios = mmc_set_ios; + mmc->init = mmc_core_init; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->host_caps = MMC_MODE_4BIT; + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + + mmc->f_min = 400000; + mmc->f_max = 52000000; + + mmc_host[sdc_no].pdes = (struct sunxi_mmc_des *)0x50000000; + mmc_resource_init(sdc_no); + mmc_clk_io_on(sdc_no); + + mmc_register(mmc); + + return 0; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 33309f3..8a026e0 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -77,6 +77,16 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING +/* mmc config */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SUNXI +#define CONFIG_MMC_SUNXI_SLOT 0 /* which mmc slot to use, could be 0,1,2,3 */ +#define CONFIG_MMC_SUNXI_USE_DMA +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_SUNXI_SLOT /* env in which mmc */ + /* * Size of malloc() pool * 1MB = 0x100000, 0x100000 = 1024 * 1024 @@ -127,9 +137,7 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KB */ #define CONFIG_IDENT_STRING " Allwinner Technology " -#define CONFIG_ENV_IS_NOWHERE /* No storage defined yet */ - -#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512)KB */ +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512)KB */ #define CONFIG_ENV_SIZE (128 << 10) /* 128KB */ #define CONFIG_BOOTCOMMAND \ -- 1.7.7.6

4 7

[U-Boot] [PATCH 05/22] power: Add AXP209 Power Management controller (I2C)
by Henrik Nordström 25 Nov '12

25 Nov '12

This adds support for AXP209 Power Management controller, used by most sunxi (Allwinner A10/A13) based boards. From: Henrik Nordstrom <henrik(a)henriknordstrom.net> Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/power/Makefile | 1 + drivers/power/axp209.c | 183 ++++++++++++++++++++++++++++++++++++++++++++++++ include/axp209.h | 29 ++++++++ 3 files changed, 213 insertions(+), 0 deletions(-) create mode 100644 drivers/power/axp209.c create mode 100644 include/axp209.h diff --git a/drivers/power/Makefile b/drivers/power/Makefile index 8c71901..ad768ff 100644 --- a/drivers/power/Makefile +++ b/drivers/power/Makefile @@ -25,6 +25,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libpower.o +COBJS-$(CONFIG_AXP209_POWER) += axp209.o COBJS-$(CONFIG_FTPMU010_POWER) += ftpmu010.o COBJS-$(CONFIG_TPS6586X_POWER) += tps6586x.o COBJS-$(CONFIG_TWL4030_POWER) += twl4030.o diff --git a/drivers/power/axp209.c b/drivers/power/axp209.c new file mode 100644 index 0000000..be98d80 --- /dev/null +++ b/drivers/power/axp209.c @@ -0,0 +1,183 @@ +/* + * (C) Copyright 2012 + * Henrik Nordstrom <henrik(a)henriknordstrom.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <axp209.h> + +enum axp209_reg { + AXP209_CHIP_VERSION = 0x3, + AXP209_DCDC2_VOLTAGE = 0x23, + AXP209_DCDC3_VOLTAGE = 0x27, + AXP209_LDO24_VOLTAGE = 0x28, + AXP209_LDO3_VOLTAGE = 0x29, + AXP209_SHUTDOWN = 0x32, +}; + +int axp209_write(enum axp209_reg reg, u8 val) +{ + return i2c_write(0x34, reg, 1, &val, 1); +} + +int axp209_read(enum axp209_reg reg, u8 *val) +{ + return i2c_read(0x34, reg, 1, val, 1); +} + +int axp209_set_dcdc2(int mvolt) +{ + int cfg = (mvolt - 700) / 25; + int rc; + u8 current; + + if (cfg < 0) + cfg = 0; + if (cfg > (1 << 6) - 1) + cfg = (1 << 6) - 1; + + /* Do we really need to be this gentle? It has built-in voltage slope */ + while ((rc = axp209_read(AXP209_DCDC2_VOLTAGE, &current)) == 0 + && current != cfg) { + if (current < cfg) + current++; + else + current--; + + rc = axp209_write(AXP209_DCDC2_VOLTAGE, current); + if (rc) + break; + } + + return rc; +} + +int axp209_set_dcdc3(int mvolt) +{ + int cfg = (mvolt - 700) / 25; + u8 reg; + int rc; + + if (cfg < 0) + cfg = 0; + if (cfg > (1 << 7) - 1) + cfg = (1 << 7) - 1; + + rc = axp209_write(AXP209_DCDC3_VOLTAGE, cfg); + rc |= axp209_read(AXP209_DCDC3_VOLTAGE, &reg); + + return rc; +} + +int axp209_set_ldo2(int mvolt) +{ + int cfg = (mvolt - 1800) / 100; + int rc; + u8 reg; + + if (cfg < 0) + cfg = 0; + if (cfg > 15) + cfg = 15; + + rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg); + if (rc) + return rc; + + reg = (reg & 0x0f) | (cfg << 4); + rc = axp209_write(AXP209_LDO24_VOLTAGE, reg); + if (rc) + return rc; + + return 0; +} + +int axp209_set_ldo3(int mvolt) +{ + int cfg = (mvolt - 700) / 25; + + if (cfg < 0) + cfg = 0; + if (cfg > 127) + cfg = 127; + if (mvolt == -1) + cfg = 0x80; /* detemined by LDO3IN pin */ + + return axp209_write(AXP209_LDO3_VOLTAGE, cfg); +} + +int axp209_set_ldo4(int mvolt) +{ + int cfg = (mvolt - 1800) / 100; + int rc; + static const int vindex[] = { + 1250, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2500, + 2700, 2800, 3000, 3100, 3200, 3300 + }; + u8 reg; + + /* Translate mvolt to register cfg value, requested <= selected */ + for (cfg = 0; mvolt < vindex[cfg] && cfg < 15; cfg++) + ; + + rc = axp209_read(AXP209_LDO24_VOLTAGE, &reg); + if (rc) + return rc; + + /* LDO4 configuration is in lower 4 bits */ + reg = (reg & 0xf0) | (cfg << 0); + rc = axp209_write(AXP209_LDO24_VOLTAGE, reg); + if (rc) + return rc; + + return 0; +} + +void axp209_poweroff(void) +{ + u8 val; + + if (axp209_read(AXP209_SHUTDOWN, &val) != 0) + return; + + val |= 1 << 7; + + if (axp209_write(AXP209_SHUTDOWN, val) != 0) + return; + + udelay(10000); /* wait for power to drain */ +} + +int axp209_init(void) +{ + u8 ver; + int rc; + + rc = axp209_read(AXP209_CHIP_VERSION, &ver); + if (rc) + return rc; + + if (ver != 0x21) + return -1; + + return 0; +} diff --git a/include/axp209.h b/include/axp209.h new file mode 100644 index 0000000..61338ac --- /dev/null +++ b/include/axp209.h @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +extern int axp209_set_dcdc2(int mvolt); +extern int axp209_set_dcdc3(int mvolt); +extern int axp209_set_ldo2(int mvolt); +extern int axp209_set_ldo3(int mvolt); +extern int axp209_set_ldo4(int mvolt); +extern void axp209_poweroff(void); +extern int axp209_init(void); -- 1.7.7.6

4 3

[U-Boot] [PULL] : Please pull u-boot-imx
by Stefano Babic 25 Nov '12

25 Nov '12

Hi Albert, please pull from u-boot-imx, thanks. The following changes since commit 34275d70fec6cc369a931090ebb686bc213bb80d: arch-mx6: add mx6dl_pins.h (2012-11-10 08:15:40 +0100) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master for you to fetch changes up to 1d4fd0dc3b45de7b7a706285845ef5b527422014: mx28: Fix typo in POWER_DCLIMITS_NEGLIMIT_OFFSET (2012-11-24 16:21:37 +0100) ---------------------------------------------------------------- Benoît Thébaudeau (16): mx31: Move EHCI definitions to ehci-fsl.h ehci-mxc: Clean up ehci-mx5: Clean up ehci-mx5: Fix OC_DIS usage ehci-mx5: Fix OPM usage ehci-mx5: Fix *PM usage for i.MX53 ehci-mx5: Add missing OC_DIS for i.MX53 ehci-mxc: Make EHCI power/oc polarities configurable ehci-mxc: Make i.MX25 EHCI configurable ehci-mxc: Define host offsets ehci-mxc: Add support for i.MX35 mx35pdk: Add support for OTG ehci-mx5/6: Make board_ehci_hcd_init() optional ehci-mxc: Fix host power mask bit for i.MX35 ehci-mxc: Fix host power mask bit for i.MX25 mx5: Mark lowlevel_init board-specific code Fabio Estevam (13): mx5: Align SPI CS naming with i.MX53 reference manual mx5: Print CSPI clock in 'clock' command spi: mxc_spi: Fix handling of chip select spi: mxc_spi: Fix spi clock glitch durant reset mx6: clock: Only show CSPI clock if CSPI is enabled mx28evk: Configure CONFIG_BOOTDELAY to one second mx53loco: Configure CONFIG_BOOTDELAY to one second mx6qsabrelite: Configure CONFIG_BOOTDELAY to one second mx6qsabre_common: Configure CONFIG_BOOTDELAY to one second mx51evk: Configure CONFIG_BOOTDELAY to one second mx25pdk: Configure CONFIG_BOOTDELAY to one second mx31pdk: Configure CONFIG_BOOTDELAY to one second mx35pdk: Configure CONFIG_BOOTDELAY to one second Marek Vasut (2): mx28: Fix typo in POWER_MINPWR_VBG_OFF mx28: Fix typo in POWER_DCLIMITS_NEGLIMIT_OFFSET arch/arm/cpu/armv7/mx5/clock.c | 4 +- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 2 +- arch/arm/cpu/armv7/mx6/clock.c | 2 + arch/arm/include/asm/arch-mx25/imx-regs.h | 1 + arch/arm/include/asm/arch-mx31/imx-regs.h | 27 +--- arch/arm/include/asm/arch-mx35/imx-regs.h | 2 + arch/arm/include/asm/arch-mx5/mx5x_pins.h | 6 +- arch/arm/include/asm/arch-mxs/regs-power.h | 4 +- board/freescale/mx35pdk/lowlevel_init.S | 4 + board/freescale/mx35pdk/mx35pdk.c | 21 +++ doc/README.imx5 | 5 + drivers/spi/mxc_spi.c | 9 +- drivers/usb/host/ehci-mx5.c | 146 ++++++++++++++---- drivers/usb/host/ehci-mx6.c | 5 + drivers/usb/host/ehci-mxc.c | 225 +++++++++++++++++++++------- include/configs/mx25pdk.h | 2 +- include/configs/mx28evk.h | 2 +- include/configs/mx31pdk.h | 2 +- include/configs/mx35pdk.h | 16 +- include/configs/mx51_efikamx.h | 1 + include/configs/mx51evk.h | 3 +- include/configs/mx53loco.h | 2 +- include/configs/mx6qsabre_common.h | 2 +- include/configs/mx6qsabrelite.h | 2 +- include/configs/vision2.h | 1 + include/configs/zmx25.h | 6 +- include/usb/ehci-fsl.h | 28 +++- 27 files changed, 401 insertions(+), 129 deletions(-) -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sbabic(a)denx.de =====================================================================

2 1

[U-Boot] [PATCH] mx28: Rename regs-power.h to regs-power-mx28.h
by Marek Vasut 25 Nov '12

25 Nov '12

The i.MX23 has different register layout and bit placement in the power supply. Thus, in order to be able to add support for MX23, rename the MX28's regs-power.h to regs-power-mx28.h . Moreover, add ifdef around inclusion of regs-*-mx28.h in imx-regs.h so the MX23 boards will include proper set of registers. Signed-off-by: Marek Vasut <marex(a)denx.de> Cc: Stefano Babic <sbabic(a)denx.de> --- arch/arm/include/asm/arch-mxs/imx-regs.h | 7 +++++-- .../include/asm/arch-mxs/{regs-power.h => regs-power-mx28.h} | 0 2 files changed, 5 insertions(+), 2 deletions(-) rename arch/arm/include/asm/arch-mxs/{regs-power.h => regs-power-mx28.h} (100%) diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h index 5e1901e..9764041 100644 --- a/arch/arm/include/asm/arch-mxs/imx-regs.h +++ b/arch/arm/include/asm/arch-mxs/imx-regs.h @@ -26,7 +26,6 @@ #include <asm/arch/regs-apbh.h> #include <asm/arch/regs-base.h> #include <asm/arch/regs-bch.h> -#include <asm/arch/regs-clkctrl-mx28.h> #include <asm/arch/regs-digctl.h> #include <asm/arch/regs-gpmi.h> #include <asm/arch/regs-i2c.h> @@ -34,9 +33,13 @@ #include <asm/arch/regs-lradc.h> #include <asm/arch/regs-ocotp.h> #include <asm/arch/regs-pinctrl.h> -#include <asm/arch/regs-power.h> #include <asm/arch/regs-rtc.h> #include <asm/arch/regs-ssp.h> #include <asm/arch/regs-timrot.h> +#ifdef CONFIG_MX28 +#include <asm/arch/regs-clkctrl-mx28.h> +#include <asm/arch/regs-power-mx28.h> +#endif + #endif /* __IMX_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-power.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h similarity index 100% rename from arch/arm/include/asm/arch-mxs/regs-power.h rename to arch/arm/include/asm/arch-mxs/regs-power-mx28.h -- 1.7.10.4

2 2

[U-Boot] [PATCH 07/22] tools: mksunixboot adding a Allwinner boot header
by Henrik Nordström 25 Nov '12

25 Nov '12

This tool adds a boot header to the supplied file, for booting code directly from the SoC embedded boot rom. Needed for making the SPL loader bootable. From: Tom Cubie <Mr.hipboi(a)gmail.com> Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> Signed-off-by: Stefan Roese <sr(a)denx.de> --- Makefile | 1 + tools/.gitignore | 1 + tools/Makefile | 6 ++ tools/mksunxiboot.README | 13 ++++ tools/mksunxiboot.c | 162 ++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 183 insertions(+), 0 deletions(-) create mode 100644 tools/mksunxiboot.README create mode 100644 tools/mksunxiboot.c diff --git a/Makefile b/Makefile index 5a98745..81fe532 100644 --- a/Makefile +++ b/Makefile @@ -799,6 +799,7 @@ clean: $(obj)tools/gen_eth_addr $(obj)tools/img2srec \ $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \ $(obj)tools/mk{smdk5250,}spl \ + $(obj)tools/mksunxiboot \ $(obj)tools/mxsboot \ $(obj)tools/ncb $(obj)tools/ubsha1 \ $(obj)tools/kernel-doc/docproc diff --git a/tools/.gitignore b/tools/.gitignore index 9bce719..92fcbbd 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -7,6 +7,7 @@ /mkimage /mpc86x_clk /mxsboot +/mksunxiboot /ncb /ncp /ubsha1 diff --git a/tools/Makefile b/tools/Makefile index 686840a..508112d 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -69,6 +69,7 @@ BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX) BIN_FILES-y += mkenvimage$(SFX) BIN_FILES-y += mkimage$(SFX) BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX) +BIN_FILES-$(CONFIG_SUNXI) += mksunxiboot$(SFX) BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX) BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) @@ -98,6 +99,7 @@ NOPED_OBJ_FILES-y += omapimage.o NOPED_OBJ_FILES-y += mkenvimage.o NOPED_OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o +OBJ_FILES-$(CONFIG_SUNXI) += mksunxiboot.o OBJ_FILES-$(CONFIG_MX28) += mxsboot.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o NOPED_OBJ_FILES-y += os_support.o @@ -228,6 +230,10 @@ $(obj)mpc86x_clk$(SFX): $(obj)mpc86x_clk.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ +$(obj)mksunxiboot$(SFX): $(obj)mksunxiboot.o + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ + $(HOSTSTRIP) $@ + $(obj)mxsboot$(SFX): $(obj)mxsboot.o $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^ $(HOSTSTRIP) $@ diff --git a/tools/mksunxiboot.README b/tools/mksunxiboot.README new file mode 100644 index 0000000..9a4b379 --- /dev/null +++ b/tools/mksunxiboot.README @@ -0,0 +1,13 @@ +This program make a arm binary file can be loaded by Allwinner A10 and releated +chips from storage media such as nand and mmc. + +More information about A10 boot, please refer to +http://rhombus-tech.net/allwinner_a10/a10_boot_process/ + +To compile this program, just type make, you will get 'mksunxiboot'. + +To use it, +$./mksunxiboot u-boot.bin u-boot-mmc.bin +then you can write it to a mmc card with dd. +$sudo dd if=u-boot-mmc.bin of=/dev/sdb bs=1024 seek=8 +then insert your mmc card to your A10 tablet, you can boot from mmc card. diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c new file mode 100644 index 0000000..fd81529 --- /dev/null +++ b/tools/mksunxiboot.c @@ -0,0 +1,162 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * a simple tool to generate bootable image for sunxi platform. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <fcntl.h> +#include <stdio.h> +#include <unistd.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> + +typedef unsigned char u8; +typedef unsigned int u32; + +/* boot head definition from sun4i boot code */ +typedef struct boot_file_head { + u32 jump_instruction; /* one intruction jumping to real code */ + u8 magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + u32 check_sum; /* generated by PC */ + u32 length; /* generated by PC */ +#if 1 + /* We use a simplified header, only filling in what is needed by the + * boot ROM. To be compatible with Allwinner tools the larger header + * below should be used, followed by a custom header if desired. */ + u8 pad[12]; /* align to 32 bytes */ +#else + u32 pub_head_size; /* the size of boot_file_head_t */ + u8 pub_head_vsn[4]; /* the version of boot_file_head_t */ + u8 file_head_vsn[4]; /* the version of boot0_file_head_t or + boot1_file_head_t */ + u8 Boot_vsn[4]; /* Boot version */ + u8 eGON_vsn[4]; /* eGON version */ + u8 platform[8]; /* platform information */ +#endif +} boot_file_head_t; + +#define BOOT0_MAGIC "eGON.BT0" +#define STAMP_VALUE 0x5F0A6C39 + +/* check sum functon from sun4i boot code */ +int gen_check_sum(void *boot_buf) +{ + boot_file_head_t *head_p; + u32 length; + u32 *buf; + u32 loop; + u32 i; + u32 sum; + + head_p = (boot_file_head_t *) boot_buf; + length = head_p->length; + if ((length & 0x3) != 0) /* must 4-byte-aligned */ + return -1; + buf = (u32 *) boot_buf; + head_p->check_sum = STAMP_VALUE; /* fill stamp */ + loop = length >> 2; + + /* calculate the sum */ + for (i = 0, sum = 0; i < loop; i++) + sum += buf[i]; + + /* write back check sum */ + head_p->check_sum = sum; + + return 0; +} + +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) + +#define SUN4I_SRAM_SIZE (24 * 1024) +#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(boot_file_head_t)) +#define BLOCK_SIZE 512 + +struct boot_img { + boot_file_head_t header; + char code[SRAM_LOAD_MAX_SIZE]; + char pad[BLOCK_SIZE]; +}; + +int main(int argc, char *argv[]) +{ + int fd_in, fd_out; + struct boot_img img; + unsigned file_size, load_size; + int count; + + if (argc < 2) { + printf + ("\tThis program makes an input bin file to sun4i bootable image.\n" + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = open(argv[1], O_RDONLY); + if (fd_in < 0) { + perror("Open input file:"); + return EXIT_FAILURE; + } + + fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666); + if (fd_out < 0) { + perror("Open output file:"); + return EXIT_FAILURE; + } + + memset((void *)img.pad, 0, BLOCK_SIZE); + + /* get input file size */ + file_size = lseek(fd_in, 0, SEEK_END); + printf("File size: 0x%x\n", file_size); + + if (file_size > SRAM_LOAD_MAX_SIZE) + load_size = SRAM_LOAD_MAX_SIZE; + else + load_size = ALIGN(file_size, sizeof(int)); + printf("Load size: 0x%x\n", load_size); + + /* read file to buffer to calculate checksum */ + lseek(fd_in, 0, SEEK_SET); + count = read(fd_in, img.code, load_size); + printf("Read 0x%x bytes\n", count); + + /* fill the header */ + img.header.jump_instruction = /* b instruction */ + 0xEA000000 | /* jump to the first instr after the header */ + ((sizeof(boot_file_head_t) / sizeof(int) - 2) + & 0x00FFFFFF); + memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */ + img.header.length = + ALIGN(load_size + sizeof(boot_file_head_t), BLOCK_SIZE); + gen_check_sum((void *)&img); + + count = write(fd_out, (void *)&img, img.header.length); + printf("Write 0x%x bytes\n", count); + + close(fd_in); + close(fd_out); + + return EXIT_SUCCESS; +} -- 1.7.7.6

3 2

[U-Boot] [PATCH 12/22] ARM sunxi: SPL support for Olimex A13-OLinuXino board
by Henrik Nordström 25 Nov '12

25 Nov '12

Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> --- board/sunxi/Makefile | 1 + board/sunxi/dram_a13_olinuxino.c | 31 +++++++++++++++++++++++++++++++ boards.cfg | 1 + 3 files changed, 33 insertions(+), 0 deletions(-) create mode 100644 board/sunxi/dram_a13_olinuxino.c diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 43acbab..0351935 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)lib$(BOARD).o COBJS-y := board.o +COBJS-$(CONFIG_A13_OLINUXINO) += dram_a13_olinuxino.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/board/sunxi/dram_a13_olinuxino.c b/board/sunxi/dram_a13_olinuxino.c new file mode 100644 index 0000000..12b66d9 --- /dev/null +++ b/board/sunxi/dram_a13_olinuxino.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 408, + .type = 3, + .rank_num = 1, + .density = 2048, + .io_width = 8, + .bus_width = 16, + .cas = 9, + .zq = 123, + .odt_en = 0, + .size = 512, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0, + .tpr4 = 0, + .tpr5 = 0, + .emr1 = 0, + .emr2 = 0x10, + .emr3 = 0, +}; + +int sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/boards.cfg b/boards.cfg index 13d1f74..0db382d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -288,6 +288,7 @@ whistler arm armv7:arm720t whistler nvidia colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 snowball arm armv7 snowball st-ericsson u8500 +A13-OLinuXino arm armv7 sunxi - sunxi sun5i:A13_OLINUXINO,SPL sun4i arm armv7 sunxi - sunxi sun4i sun4i_sdcon arm armv7 sunxi - sunxi sun4i:UART0_PORT_F sun5i arm armv7 sunxi - sunxi sun5i -- 1.7.7.6

2 1

[U-Boot] [PATCH 11/22] ARM: sunxi: U-Boot SPL capable of booting directly from MMC
by Henrik Nordström 25 Nov '12

25 Nov '12

Allwinner sunxi family of SoCs boots from MMC0/NAND/NOR/MMC2 loading boot code into an embedded 32KB SRAM. This patch adds support for booting u-boot SPL from MMC0 We first initializes the console UART, then DRAM controller with board specific DRAM configuration details, configure CPU core voltage and clocks before loading the full u-boot image into DRAM. From: Henrik Nordstrom <henrik(a)henriknordstrom.net> Signed-off-by: Tom Cubie <tangliang(a)allwinnertech.com> Signed-off-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> --- Makefile | 11 + arch/arm/cpu/armv7/sunxi/board.c | 38 +++ arch/arm/cpu/armv7/sunxi/clock.c | 99 +++++++ arch/arm/cpu/armv7/sunxi/dram.c | 445 +++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 63 +++++ arch/arm/include/asm/arch-sunxi/spl.h | 34 +++ board/sunxi/board.c | 46 ++++ include/configs/sunxi-common.h | 30 ++- spl/Makefile | 10 + 9 files changed, 775 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/dram.c create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-sunxi/spl.h diff --git a/Makefile b/Makefile index 81fe532..d1b7f97 100644 --- a/Makefile +++ b/Makefile @@ -517,6 +517,16 @@ $(obj)u-boot.spr: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin conv=notrunc 2>/dev/null cat $(obj)spl/u-boot-spl-pad.img $(obj)u-boot.img > $@ +# sunxi: Combined object with SPL U-Boot with sunxi header (sunxi-spl.bin) +# and the full-blown U-Boot attached to it +$(obj)u-boot-sunxi-with-spl.bin: $(obj)spl/sunxi-spl.bin $(obj)u-boot.bin + tr "\000" "\377" < /dev/zero | dd ibs=1 count=$(CONFIG_SPL_PAD_TO) \ + of=$(obj)spl/sunxi-spl-pad.bin 2>/dev/null + dd if=$(obj)spl/sunxi-spl.bin of=$(obj)spl/sunxi-spl-pad.bin \ + conv=notrunc 2>/dev/null + cat $(obj)spl/sunxi-spl-pad.bin $(obj)u-boot.bin > $@ + rm $(obj)spl/sunxi-spl-pad.bin + ifeq ($(SOC),tegra20) ifeq ($(CONFIG_OF_SEPARATE),y) nodtb=dtb @@ -854,6 +864,7 @@ clobber: tidy @[ ! -d $(obj)nand_spl ] || find $(obj)nand_spl -name "*" -type l -print | xargs rm -f @rm -f $(obj)dts/*.tmp @rm -f $(obj)spl/u-boot-spl{,-pad}.ais + @rm -f $(obj)spl/sun?i-spl.bin mrproper \ distclean: clobber unconfig diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 29cc4bd..6dc2bd0 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -27,12 +27,37 @@ #include <common.h> #include <asm/io.h> #include <serial.h> +#include <i2c.h> #include <asm/gpio.h> #include <asm/arch/clock.h> #include <asm/arch/timer.h> #include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> #include <netdev.h> +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#endif + +#ifdef CONFIG_SPL_BUILD +/* Pointer to the global data structure for SPL */ +DECLARE_GLOBAL_DATA_PTR; + +/* The sunxi internal brom will try to loader external bootloader + * from mmc0, nannd flash, mmc2. + * Unfortunately we can't check how SPL was loaded so assume + * it's always the first SD/MMC controller + */ +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +/* No confiration data available in SPL yet. Hardcode bootmode */ +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_RAW; +} +#endif int gpio_init(void) { @@ -65,6 +90,19 @@ void s_init(void) #endif clock_init(); gpio_init(); + +#ifdef CONFIG_SPL_BUILD + gd = &gdata; + preloader_console_init(); + +#ifdef CONFIG_SPL_I2C_SUPPORT + /* Needed early by sunxi_board_init if PMU is enabled */ + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#endif + + sunxi_board_init(); +#endif + } void reset_cpu(ulong addr) diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c index b9bbb7d..91cfae3 100644 --- a/arch/arm/cpu/armv7/sunxi/clock.c +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -24,13 +24,34 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/clock.h> +#include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> +#ifdef CONFIG_SPL_BUILD +static void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set safe defaults until PMU is configured */ + writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 | + CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg); + writel(0xa1005000, &ccm->pll1_cfg); + sdelay(200); + writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 | + CPU_CLK_SRC_PLL1 << 16, &ccm->cpu_ahb_apb0_cfg); +} +#endif + int clock_init(void) { struct sunxi_ccm_reg *const ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; +#ifdef CONFIG_SPL_BUILD + clock_init_safe(); +#endif + /* uart clock source is apb1 */ sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M); sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N); @@ -70,3 +91,81 @@ int clock_twi_onoff(int port, int state) return 0; } + +#ifdef CONFIG_SPL_BUILD +#define PLL1_CFG(N, K, M, P) (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \ + 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \ + (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0) +#define RDIV(a, b) ((a + (b) - 1) / (b)) + +struct { + u32 pll1_cfg; + unsigned int freq; +} pll1_para[] = { + { PLL1_CFG(16, 0, 0, 0), 384000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(31, 1, 0, 0), 1488000000}, + { PLL1_CFG(31, 1, 0, 0), ~0}, +}; + +void clock_set_pll1(int hz) +{ + int i = 0; + int axi, ahb, apb0; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Find target frequency */ + while (pll1_para[i].freq < hz) + i++; + + hz = pll1_para[i].freq; + + /* Calculate system clock divisors */ + axi = RDIV(hz, 432000000); /* Max 450MHz */ + ahb = RDIV(hz/axi, 204000000); /* Max 250MHz */ + apb0 = 2; /* Max 150MHz */ + + /* Map divisors to register values */ + axi = axi - 1; + if (ahb > 4) + ahb = 3; + else if (ahb > 2) + ahb = 2; + else if (ahb > 1) + ahb = 1; + else + ahb = 0; + + apb0 = apb0 - 1; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_1 << 0 | AHB_DIV_2 << 4 | APB0_DIV_1 << 8 | + CPU_CLK_SRC_OSC24M << 16, &ccm->cpu_ahb_apb0_cfg); + sdelay(20); + + /* Configure sys clock divisors */ + writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_OSC24M << 16, + &ccm->cpu_ahb_apb0_cfg); + + /* Configure PLL1 at the desired frequency */ + writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(axi << 0 | ahb << 4 | apb0 << 8 | CPU_CLK_SRC_PLL1 << 16, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/dram.c b/arch/arm/cpu/armv7/sunxi/dram.c new file mode 100644 index 0000000..f169b7b --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/dram.c @@ -0,0 +1,445 @@ +/* + * sunxi DRAM controller initialization + * (C) Copyright 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * + * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c + * and earlier U-Boot Allwiner A10 SPL work + * + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing(a)allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/dram.h> +#include <asm/arch/timer.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +static void mctl_ddr3_reset(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + +#ifdef CONFIG_SUN4I + struct sunxi_timer_reg *timer = (struct sunxi_timer_reg *)SUNXI_TIMER_BASE; + u32 reg_val; + + writel(0, &timer->cpu_cfg); + reg_val = readl(&timer->cpu_cfg); + reg_val >>= 6; + reg_val &= 0x3; + + if (reg_val != 0) { + setbits_le32(&dram->mcr, 0x1 << 12); + sdelay(0x100); + clrbits_le32(&dram->mcr, 0x1 << 12); + } else +#endif + { + clrbits_le32(&dram->mcr, 0x1 << 12); + sdelay(0x100); + setbits_le32(&dram->mcr, 0x1 << 12); + } +} + +static void mctl_set_drive(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->mcr, 0x3, (0x6 << 12) | 0xFFC); +} + +static void mctl_itm_disable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + setbits_le32(&dram->ccr, 0x1 << 28); +} + +static void mctl_itm_enable(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrbits_le32(&dram->ccr, 0x1 << 28); +} + +static void mctl_enable_dll0(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + clrsetbits_le32(&dram->dllcr[0], 0x40000000, 0x80000000); + sdelay(0x100); + + clrbits_le32(&dram->dllcr[0], 0xC0000000); + sdelay(0x1000); + + clrsetbits_le32(&dram->dllcr[0], 0x80000000, 0x40000000); + sdelay(0x1000); +} + +/* + * Note: This differs from pm/standby in that it checks the bus width + */ +static void mctl_enable_dllx(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i, n, bus_width; + + bus_width = readl(&dram->dcr); + bus_width >>= 6; + bus_width &= 7; + + if (bus_width == 3) + n = 5; + else + n = 3; + + for (i = 1; i < n; i++) + clrsetbits_le32(&dram->dllcr[i], 0x40000000, 0x80000000); + sdelay(0x100); + + for (i = 1; i < n; i++) + clrbits_le32(&dram->dllcr[i], 0xC0000000); + sdelay(0x1000); + + for (i = 1; i < n; i++) + clrsetbits_le32(&dram->dllcr[i], 0x80000000, 0x40000000); + sdelay(0x1000); +} + +static u32 hpcr_value[32] = { +#ifdef CONFIG_SUN5I + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0, + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0x0301, 0 +#endif +#ifdef CONFIG_SUN4I + 0x0301, 0x0301, 0x0301, 0x0301, + 0x0301, 0x0301, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0x1031, 0x1031, 0x0735, 0x1035, + 0x1035, 0x0731, 0x1031, 0x0735, + 0x1035, 0x1031, 0x0731, 0x1035, + 0x1031, 0x0301, 0x0301, 0x0731 +#endif +}; + +static void mctl_configure_hostport(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 i; + + for (i = 0; i < 32; i++) + writel(hpcr_value[i], &dram->hpcr[i]); +} + +static void mctl_setup_dram_clock(u32 clk) +{ + u32 reg_val; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* setup DRAM PLL */ + reg_val = readl(&ccm->pll5_cfg); + reg_val &= ~0x3; + reg_val |= 0x1; /* m factor */ + reg_val &= ~(0x3 << 4); + reg_val |= 0x1 << 4; /* k factor */ + reg_val &= ~(0x1f << 8); + reg_val |= ((clk / 24) & 0x1f) << 8; /* n factor */ + reg_val &= ~(0x3 << 16); + reg_val |= 0x1 << 16; /* p factor */ + reg_val &= ~(0x1 << 29); /* PLL on */ + reg_val |= (u32) 0x1 << 31; /* PLL En */ + writel(reg_val, &ccm->pll5_cfg); + sdelay(0x100000); + + setbits_le32(&ccm->pll5_cfg, 0x1 << 29); + +#ifdef CONFIG_SUN4I + /* reset GPS */ + clrbits_le32(&ccm->gps_clk_cfg, 0x3); + setbits_le32(&ccm->ahb_gate0, 0x1 << 26); + sdelay(0x20); + clrbits_le32(&ccm->ahb_gate0, 0x1 << 26); +#endif + + /* setup MBUS clock */ + reg_val = (0x1 << 31) | (0x2 << 24) | (0x1); + writel(reg_val, &ccm->mbus_clk_cfg); + + /* + * open DRAMC AHB & DLL register clock + * close it first + */ +#ifdef CONFIG_SUN5I + clrbits_le32(&ccm->ahb_gate0, 0x3 << 14); +#else + clrbits_le32(&ccm->ahb_gate0, 0x1 << 14); +#endif + sdelay(0x1000); + + /* then open it */ +#ifdef CONFIG_SUN5I + setbits_le32(&ccm->ahb_gate0, 0x3 << 14); +#else + setbits_le32(&ccm->ahb_gate0, 0x1 << 14); +#endif + sdelay(0x1000); +} + +static int dramc_scan_readpipe(void) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + + /* data training trigger */ + setbits_le32(&dram->ccr, 0x1 << 30); + + /* check whether data training process is end */ + while (readl(&dram->ccr) & (0x1 << 30)) + ; + + /* check data training result */ + reg_val = readl(&dram->csr); + if (reg_val & (0x1 << 20)) + return -1; + + return 0; +} + +static void dramc_clock_output_en(u32 on) +{ +#ifdef CONFIG_SUN5I + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + + if (on) + setbits_le32(&dram->mcr, 0x1 << SUN5I_DRAM_MCR_DCLK_OUT_OFFSET); + else + clrbits_le32(&dram->mcr, 0x1 << SUN5I_DRAM_MCR_DCLK_OUT_OFFSET); +#endif +#ifdef CONFIG_SUN4I + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + if (on) + setbits_le32(&ccm->dram_clk_cfg, 0x1 << SUN4I_CCM_SDRAM_DCLK_OUT_OFFSET); + else + clrbits_le32(&ccm->dram_clk_cfg, 0x1 << SUN4I_CCM_SDRAM_DCLK_OUT_OFFSET); +#endif +} + +#ifdef CONFIG_SUN4I +static void dramc_set_autorefresh_cycle(u32 clk) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + u32 tmp_val; + u32 dram_size; + + if (clk < 600) { + dram_size = readl(&dram->dcr); + dram_size >>= 3; + dram_size &= 0x7; + if (dram_size <= 0x2) + reg_val = (131 * clk) >> 10; + else + reg_val = (336 * clk) >> 10; + + tmp_val = (7987 * clk) >> 10; + tmp_val = tmp_val * 9 - 200; + reg_val |= tmp_val << 8; + reg_val |= 0x8 << 24; + writel(reg_val, &dram->drr); + } else { + writel(0x0, &dram->drr); + } +} +#endif /* SUN4I */ + +#ifdef CONFIG_SUN5I +static void dramc_set_autorefresh_cycle(u32 clk) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + u32 tmp_val; + reg_val = 131; + + tmp_val = (7987 * clk) >> 10; + tmp_val = tmp_val * 9 - 200; + reg_val |= tmp_val << 8; + reg_val |= 0x8 << 24; + writel(reg_val, &dram->drr); +} +#endif /* SUN5I */ + +int dramc_init(struct dram_para *para) +{ + struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; + u32 reg_val; + int ret_val; + + /* check input dram parameter structure */ + if (!para) + return -1; + + /* setup DRAM relative clock */ + mctl_setup_dram_clock(para->clock); + +#ifdef CONFIG_SUN5I + /* Disable any pad power save control */ + writel(0, &dram->ppwrsctl); +#endif + + /* reset external DRAM */ + mctl_ddr3_reset(); + mctl_set_drive(); + + /* dram clock off */ + dramc_clock_output_en(0); + +#ifdef CONFIG_SUN4I + /* select dram controller 1 */ + writel(0x16237495, &dram->csel); +#endif + + mctl_itm_disable(); + mctl_enable_dll0(); + + /* configure external DRAM */ + reg_val = 0; + if (para->type == 3) + reg_val |= 0x1; + reg_val |= (para->io_width >> 3) << 1; + + if (para->density == 256) + reg_val |= 0x0 << 3; + else if (para->density == 512) + reg_val |= 0x1 << 3; + else if (para->density == 1024) + reg_val |= 0x2 << 3; + else if (para->density == 2048) + reg_val |= 0x3 << 3; + else if (para->density == 4096) + reg_val |= 0x4 << 3; + else if (para->density == 8192) + reg_val |= 0x5 << 3; + else + reg_val |= 0x0 << 3; + + reg_val |= ((para->bus_width >> 3) - 1) << 6; + + reg_val |= (para->rank_num - 1) << 10; + + reg_val |= 0x1 << 12; + reg_val |= ((0x1) & 0x3) << 13; + + writel(reg_val, &dram->dcr); + +#ifdef CONFIG_SUN5I + /* set odt impendance divide ratio */ + reg_val = ((para->zq) >> 8) & 0xfffff; + reg_val |= ((para->zq) & 0xff) << 20; + reg_val |= (para->zq) & 0xf0000000; + writel(reg_val, &dram->zqcr0); +#endif + + /* dram clock on */ + dramc_clock_output_en(1); + + sdelay(0x10); + + while (readl(&dram->ccr) & (0x1U << 31)) + ; + + mctl_enable_dllx(); + +#ifdef CONFIG_SUN4I + /* set odt impendance divide ratio */ + reg_val = ((para->zq) >> 8) & 0xfffff; + reg_val |= ((para->zq) & 0xff) << 20; + reg_val |= (para->zq) & 0xf0000000; + writel(reg_val, &dram->zqcr0); +#endif + +#ifdef CONFIG_SUN4I + /* set I/O configure register */ + reg_val = 0x00cc0000; + reg_val |= (para->odt_en) & 0x3; + reg_val |= ((para->odt_en) & 0x3) << 30; + writel(reg_val, &dram->iocr); +#endif + + /* set refresh period */ + dramc_set_autorefresh_cycle(para->clock); + + /* set timing parameters */ + writel(para->tpr0, &dram->tpr0); + writel(para->tpr1, &dram->tpr1); + writel(para->tpr2, &dram->tpr2); + + /* set mode register */ + if (para->type == 3) { + /* ddr3 */ + reg_val = 0x0; +#ifdef CONFIG_SUN5I + reg_val |= 0x1000; +#endif + reg_val |= (para->cas - 4) << 4; + reg_val |= 0x5 << 9; + } else if (para->type == 2) { + /* ddr2 */ + reg_val = 0x2; + reg_val |= para->cas << 4; + reg_val |= 0x5 << 9; + } + writel(reg_val, &dram->mr); + + writel(para->emr1, &dram->emr); + writel(para->emr2, &dram->emr2); + writel(para->emr3, &dram->emr3); + + /* set DQS window mode */ + clrsetbits_le32(&dram->ccr, 0x1U << 17, 0x1U << 14); + + /* initial external DRAM */ + setbits_le32(&dram->ccr, 0x1U << 31); + + while (readl(&dram->ccr) & (0x1U << 31)) + ; + + /* scan read pipe value */ + mctl_itm_enable(); + ret_val = dramc_scan_readpipe(); + + if (ret_val < 0) + return 0; + + /* configure all host port */ + mctl_configure_hostport(); + + return get_ram_size((long *)PHYS_SDRAM_1, 1 << 30); +} diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds new file mode 100644 index 0000000..cb418e1 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <garyj(a)denx.de> + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V <aneesh(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } > .sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end__ = .; + } > .sdram +} diff --git a/arch/arm/include/asm/arch-sunxi/spl.h b/arch/arm/include/asm/arch-sunxi/spl.h new file mode 100644 index 0000000..404e16a --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/spl.h @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2012 + * Texas Instruments, <www.ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _ASM_ARCH_SPL_H_ +#define _ASM_SPL_H_ + +#define BOOT_DEVICE_NONE 0 +#define BOOT_DEVICE_XIP 1 +#define BOOT_DEVICE_NAND 2 +#define BOOT_DEVICE_ONE_NAND 3 +#define BOOT_DEVICE_MMC2 5 /*emmc*/ +#define BOOT_DEVICE_MMC1 6 +#define BOOT_DEVICE_XIPWAIT 7 +#define BOOT_DEVICE_MMC2_2 0xFF +#endif diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 50fb40f..b917a0a 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -64,3 +64,49 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#ifdef CONFIG_SPL_BUILD +void sunxi_board_init(void) +{ + int power_failed = 0; + int ramsize; + + printf("DRAM:"); + ramsize = sunxi_dram_init(); + if (!ramsize) { + printf(" ?"); + ramsize = sunxi_dram_init(); + } + if (!ramsize) { + printf(" ?"); + ramsize = sunxi_dram_init(); + } + printf(" %dMB\n", ramsize>>20); + if (!ramsize) + hang(); + +#ifdef CONFIG_AXP209_POWER + power_failed |= axp209_init(); + power_failed |= axp209_set_dcdc2(1400); + power_failed |= axp209_set_dcdc3(1250); + power_failed |= axp209_set_ldo2(3000); + power_failed |= axp209_set_ldo3(2800); + power_failed |= axp209_set_ldo4(2800); +#endif + + /* + * Only clock up the CPU to full speed if we are reasonably + * assured it's being powered with suitable core voltage + */ + if (!power_failed) + clock_set_pll1(1008000000); +} + +#ifdef CONFIG_SPL_DISPLAY_PRINT +void spl_display_print(void) +{ + printf("Board: %s\n", CONFIG_SYS_BOARD_NAME); +} +#endif + +#endif diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index bc1f200..b0dcfdb 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -134,7 +134,7 @@ */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KB */ +#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KB */ #define CONFIG_IDENT_STRING " Allwinner Technology " #define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512)KB */ @@ -190,6 +190,30 @@ #define CONFIG_CMD_EXT4 /* with this we can access ext4 bootfs */ #define CONFIG_CMD_ZFS /* with this we can access ZFS bootfs */ +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_BSS_START_ADDR 0x50000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x8000 /* 32 KB */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_DISPLAY_PRINT + +/* end of 24KB in sram */ +#define LOW_LEVEL_SRAM_STACK 0x00006000 +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" + +/* 32KB offset */ +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 64 +/* SPL starts at offset 8KiB im MMC and has the size of 24KiB */ +#define CONFIG_SPL_PAD_TO 24576 /* decimal for 'dd' */ + #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS @@ -210,4 +234,8 @@ #define CONFIG_SUNXI_GPIO #define CONFIG_CMD_GPIO +/* PMU */ +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_AXP209_POWER + #endif /* __CONFIG_H */ diff --git a/spl/Makefile b/spl/Makefile index 3195390..74d27b1 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -126,6 +126,10 @@ ifdef CONFIG_SAMSUNG ALL-y += $(obj)$(BOARD)-spl.bin endif +ifdef CONFIG_SUNXI +ALL-y += $(obj)sunxi-spl.bin +endif + all: $(ALL-y) ifdef CONFIG_SAMSUNG @@ -134,6 +138,12 @@ $(obj)$(BOARD)-spl.bin: $(obj)u-boot-spl.bin $(obj)u-boot-spl.bin $(obj)$(BOARD)-spl.bin endif +ifdef CONFIG_SUNXI +$(obj)sunxi-spl.bin: $(obj)u-boot-spl.bin + $(OBJTREE)/tools/mksunxiboot \ + $(obj)u-boot-spl.bin $(obj)sunxi-spl.bin +endif + $(obj)u-boot-spl.bin: $(obj)u-boot-spl $(OBJCOPY) $(OBJCFLAGS) -O binary $< $@ -- 1.7.7.6

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[U-Boot] [PATCH 10/22] sunxi: Add more network commands and netconsole support
by Henrik Nordström 25 Nov '12

25 Nov '12

Add most network related commands Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> --- include/configs/sun4i.h | 21 ++++++++++++++++++++- 1 files changed, 20 insertions(+), 1 deletions(-) diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index ad51446..a58f82b 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -47,9 +47,28 @@ /* Ethernet support on A10 */ #define CONFIG_SUNXI_WEMAC #define CONFIG_MII /* MII PHY management */ - #define CONFIG_CMD_MII #define CONFIG_CMD_NET #define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_DNS +#define CONFIG_NETCONSOLE +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_NISDOMAIN +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_BOOTP_NTPSERVER +#define CONFIG_BOOTP_TIMEOFFSET +#define CONFIG_BOOTP_MAY_FAIL +#define CONFIG_BOOTP_SERVERIP +#define CONFIG_BOOTP_DHCP_REQUEST_DELAY 50000 +#define CONFIG_TIMESTAMP #endif /* __CONFIG_H */ -- 1.7.7.6

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[U-Boot] [PATCH 09/22] ARM: sun4i: Enable ethernet support (wemac) on A10 boards
by Henrik Nordström 25 Nov '12

25 Nov '12

From: Stefan Roese <sr(a)denx.de> Signed-off-by: Stefan Roese <sr(a)denx.de> Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> --- arch/arm/cpu/armv7/sunxi/board.c | 14 ++++++++++++++ include/configs/sun4i.h | 8 ++++++++ 2 files changed, 22 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index 5c94110..29cc4bd 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -32,6 +32,7 @@ #include <asm/arch/timer.h> #include <asm/arch/gpio.h> #include <asm/arch/sys_proto.h> +#include <netdev.h> int gpio_init(void) { @@ -78,3 +79,16 @@ void enable_caches(void) dcache_enable(); } #endif + +#if defined(CONFIG_SUNXI_WEMAC) +/* + * Initializes on-chip ethernet controllers. + * to override, implement board_eth_init() + */ +int cpu_eth_init(bd_t *bis) +{ + sunxi_wemac_initialize(bis); + + return 0; +} +#endif diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h index 513f618..ad51446 100644 --- a/include/configs/sun4i.h +++ b/include/configs/sun4i.h @@ -44,4 +44,12 @@ #define CONFIG_CONS_INDEX 1 /* UART0 */ +/* Ethernet support on A10 */ +#define CONFIG_SUNXI_WEMAC +#define CONFIG_MII /* MII PHY management */ + +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING + #endif /* __CONFIG_H */ -- 1.7.7.6

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