November 2012 - U-Boot

[U-Boot] [PATCH 03/22] ARM sunxi: I2C driver
by Henrik Nordström 26 Nov '12

26 Nov '12

A basic basic driver for the I2C controller found in Allwinner sunXi (A10 & A13) SoCs. Signed-off-by: Henrik Nordstrom <henrik(a)henriknordstrom.net> Signed-off-by: Stefan Roese <sr(a)denx.de> --- arch/arm/cpu/armv7/sunxi/clock.c | 15 ++ arch/arm/include/asm/arch-sunxi/i2c.h | 185 ++++++++++++++++++++++ drivers/i2c/Makefile | 1 + drivers/i2c/sunxi_i2c.c | 278 +++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 8 + 5 files changed, 487 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-sunxi/i2c.h create mode 100644 drivers/i2c/sunxi_i2c.c diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c index 424acfc..b9bbb7d 100644 --- a/arch/arm/cpu/armv7/sunxi/clock.c +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -42,6 +42,7 @@ int clock_init(void) return 0; } + /* Return PLL5 frequency in Hz * Note: Assumes PLL5 reference is 24MHz clock */ @@ -55,3 +56,17 @@ unsigned int clock_get_pll5(void) int p = 1 << ((rval >> 16) & 3); return 24000000 * n * k / p; } + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 2) + return -1; + + /* set the apb1 clock gate for twi */ + sr32(&ccm->apb1_gate, 0 + port, 1, state); + + return 0; +} diff --git a/arch/arm/include/asm/arch-sunxi/i2c.h b/arch/arm/include/asm/arch-sunxi/i2c.h new file mode 100644 index 0000000..9a6e168 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/i2c.h @@ -0,0 +1,185 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * + * Based on sun4i linux kernle i2c.h + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tanglaing(a)allwinnertech.com> + * Victor Wei <weiziheng(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SUNXI_I2C_H_ +#define _SUNXI_I2C_H_ + +struct i2c { + u32 saddr; /* 31:8bit res,7-1bit for slave addr,0 bit for GCE */ + u32 xsaddr; /* 31:8bit res,7-0bit for second addr in 10bit addr */ + u32 data; /* 31:8bit res, 7-0bit send or receive data byte */ + u32 ctl; /* INT_EN,BUS_EN,M_STA,INT_FLAG,A_ACK */ + u32 status; /* 28 interrupt types + 0xF8 normal type = 29 */ + u32 clkr; /* 31:7bit res,6-3bit,CLK_M,2-0bit CLK_N */ + u32 reset; /* 31:1bit res;0bit,write 1 to clear 0. */ + u32 efr; /* 31:2bit res,1:0 bit data byte follow read comand */ + u32 lctl; /* 31:6bits res 5:0bit for sda&scl control */ +}; + +/* TWI address register */ +#define TWI_GCE_EN (0x1 << 0) /* gen call addr enable slave mode */ +#define TWI_ADDR_MASK (0x7f << 1) /* 7:1bits */ +#define TWI_XADDR_MASK 0xff /* 7:0bits for extend slave address */ + +#define TWI_DATA_MASK 0xff /* 7:0bits for send or received */ + +/* TWI Control Register Bit Fields */ +/* 1:0 bits reserved */ +/* set 1 to send A_ACK,then low level on SDA */ +#define TWI_CTL_ACK (0x1 << 2) +/* INT_FLAG,interrupt status flag: set '1' when interrupt coming */ +#define TWI_CTL_INTFLG (0x1 << 3) +#define TWI_CTL_STP (0x1 << 4) /* M_STP,Automatic clear 0 */ +#define TWI_CTL_STA (0x1 << 5) /* M_STA,atutomatic clear 0 */ +#define TWI_CTL_BUSEN (0x1 << 6) /* BUS_EN, mastr mode should be set 1 */ +#define TWI_CTL_INTEN (0x1 << 7) /* INT_EN */ +/* 31:8 bit reserved */ + +/* + * TWI Clock Register Bit Fields & Masks,default value:0x0000_0000 + * Fin is APB CLOCK INPUT; + * Fsample = F0 = Fin/2^CLK_N; + * F1 = F0/(CLK_M+1); + * + * Foscl = F1/10 = Fin/(2^CLK_N * (CLK_M+1)*10); + * Foscl is clock SCL;standard mode:100KHz or fast mode:400KHz + */ + +#define TWI_CLK_DIV_M (0xF << 3) /* 6:3bit */ +#define TWI_CLK_DIV_N (0x7 << 0) /* 2:0bit */ +#define TWI_CLK_DIV(N, M) ((((N) & 0xF) << 3) | (((M) & 0x7) << 0)) + +/* TWI Soft Reset Register Bit Fields & Masks */ +/* write 1 to clear 0, when complete soft reset clear 0 */ +#define TWI_SRST_SRST (0x1 << 0) + +/* TWI Enhance Feature Register Bit Fields & Masks */ +/* default -- 0x0 */ +/* 00:no,01: 1byte, 10:2 bytes, 11: 3bytes */ +#define TWI_EFR_MASK (0x3 << 0) +#define TWI_EFR_WARC_0 (0x0 << 0) +#define TWI_EFR_WARC_1 (0x1 << 0) +#define TWI_EFR_WARC_2 (0x2 << 0) +#define TWI_EFR_WARC_3 (0x3 << 0) + +/* twi line control register -default value: 0x0000_003a */ +/* SDA line state control enable ,1:enable;0:disable */ +#define TWI_LCR_SDA_EN (0x01 << 0) +/* SDA line state control bit, 1:high level;0:low level */ +#define TWI_LCR_SDA_CTL (0x01 << 1) +/* SCL line state control enable ,1:enable;0:disable */ +#define TWI_LCR_SCL_EN (0x01 << 2) +/* SCL line state control bit, 1:high level;0:low level */ +#define TWI_LCR_SCL_CTL (0x01 << 3) +/* current state of SDA,readonly bit */ +#define TWI_LCR_SDA_STATE_MASK (0x01 << 4) +/* current state of SCL,readonly bit */ +#define TWI_LCR_SCL_STATE_MASK (0x01 << 5) +/* 31:6bits reserved */ +#define TWI_LCR_IDLE_STATUS 0x3a + +/* TWI Status Register Bit Fields & Masks */ +#define TWI_STAT_MASK 0xff +/* 7:0 bits use only,default is 0xF8 */ +#define TWI_STAT_BUS_ERR 0x00 /* BUS ERROR */ + +/* Master mode use only */ +#define TWI_STAT_TX_STA 0x08 /* START condition transmitted */ +/* Repeated START condition transmitted */ +#define TWI_STAT_TX_RESTA 0x10 +/* Address+Write bit transmitted, ACK received */ +#define TWI_STAT_TX_AW_ACK 0x18 +/* Address+Write bit transmitted, ACK not received */ +#define TWI_STAT_TX_AW_NAK 0x20 +/* data byte transmitted in master mode,ack received */ +#define TWI_STAT_TXD_ACK 0x28 +/* data byte transmitted in master mode ,ack not received */ +#define TWI_STAT_TXD_NAK 0x30 +/* arbitration lost in address or data byte */ +#define TWI_STAT_ARBLOST 0x38 +/* Address+Read bit transmitted, ACK received */ +#define TWI_STAT_TX_AR_ACK 0x40 +/* Address+Read bit transmitted, ACK not received */ +#define TWI_STAT_TX_AR_NAK 0x48 +/* Second Address byte + Write bit transmitted, ACK received */ +#define TWI_STAT_TX_2AW_ACK 0xD0 +/* Second Address byte + Write bit transmitted, ACK received */ +#define TWI_STAT_TX_2AW_NAK 0xD8 +/* data byte received in master mode ,ack transmitted */ +#define TWI_STAT_RXD_ACK 0x50 +/* date byte received in master mode,not ack transmitted */ +#define TWI_STAT_RXD_NAK 0x58 + +/* Slave mode use only */ +/* Slave address+Write bit received, ACK transmitted */ +#define TWI_STAT_RXWS_ACK 0x60 +/* + * Arbitration lost in address as master, slave address + Write bit received, + * ACK transmitted + */ +#define TWI_STAT_ARBLOST_RXWS_ACK 0x68 +/* General Call address received, ACK transmitted */ +#define TWI_STAT_RXGCAS_ACK 0x70 +/* + * Arbitration lost in address as master, General Call address received, + * ACK transmitted + */ +#define TWI_STAT_ARBLOST_RXGCAS_ACK 0x78 +/* Data byte received after slave address received, ACK transmitted */ +#define TWI_STAT_RXDS_ACK 0x80 +/* Data byte received after slave address received, not ACK transmitted */ +#define TWI_STAT_RXDS_NAK 0x88 +/* Data byte received after General Call received, ACK transmitted */ +#define TWI_STAT_RXDGCAS_ACK 0x90 +/* Data byte received after General Call received, not ACK transmitted */ +#define TWI_STAT_RXDGCAS_NAK 0x98 +/* STOP or repeated START condition received in slave */ +#define TWI_STAT_RXSTPS_RXRESTAS 0xA0 +/* Slave address + Read bit received, ACK transmitted */ +#define TWI_STAT_RXRS_ACK 0xA8 +/* + * Arbitration lost in address as master, slave address + Read bit received, + * ACK transmitted + */ +#define TWI_STAT_ARBLOST_SLAR_ACK 0xB0 +/* Data byte transmitted in slave mode, ACK received */ +#define TWI_STAT_TXDS_ACK 0xB8 +/* Data byte transmitted in slave mode, ACK not received */ +#define TWI_STAT_TXDS_NAK 0xC0 +/* Last byte transmitted in slave mode, ACK received */ +#define TWI_STAT_TXDSL_ACK 0xC8 + +/* 10bit Address, second part of address */ +/* Second Address byte+Write bit transmitted,ACK received */ +#define TWI_STAT_TX_SAW_ACK 0xD0 +/* Second Address byte+Write bit transmitted,ACK not received */ +#define TWI_STAT_TX_SAW_NAK 0xD8 + +/* No relevant status infomation,INT_FLAG = 0 */ +#define TWI_STAT_IDLE 0xF8 + +#endif diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 5dbdbe3..9f929e6 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -46,6 +46,7 @@ COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o COBJS-$(CONFIG_U8500_I2C) += u8500_i2c.o COBJS-$(CONFIG_SH_I2C) += sh_i2c.o COBJS-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o +COBJS-$(CONFIG_SUNXI_I2C) += sunxi_i2c.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/i2c/sunxi_i2c.c b/drivers/i2c/sunxi_i2c.c new file mode 100644 index 0000000..6bf5309 --- /dev/null +++ b/drivers/i2c/sunxi_i2c.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2012 Henrik Nordstrom <henrik(a)henriknordstrom.net> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> +#include <asm/arch/i2c.h> +#include <asm/arch/gpio.h> +#include <asm/arch/clock.h> + +static struct i2c __attribute__ ((section(".data"))) *i2c_base = + (struct i2c *)0x1c2ac00; + +void i2c_init(int speed, int slaveaddr) +{ + sunxi_gpio_set_cfgpin(SUNXI_GPB(0), 2); + sunxi_gpio_set_cfgpin(SUNXI_GPB(1), 2); + clock_twi_onoff(0, 1); + + /* Enable the i2c bus */ + writel(TWI_CTL_BUSEN, &i2c_base->ctl); + + /* 400KHz operation M=2, N=1, 24MHz APB clock */ + writel(TWI_CLK_DIV(2, 1), &i2c_base->clkr); + writel(TWI_SRST_SRST, &i2c_base->reset); + + while ((readl(&i2c_base->reset) & TWI_SRST_SRST)) + ; +} + +int i2c_probe(uchar chip) +{ + return -1; +} + +static int i2c_wait_ctl(int mask, int state) +{ + int timeout = 0x2ff; + int value = state ? mask : 0; + + debug("i2c_wait_ctl(%x == %x), ctl=%x, status=%x\n", mask, value, + i2c_base->ctl, i2c_base->status); + + while (((readl(&i2c_base->ctl) & mask) != value) && timeout-- > 0) + ; + + debug("i2c_wait_ctl(), timeout=%d, ctl=%x, status=%x\n", timeout, + i2c_base->ctl, i2c_base->status); + + if (timeout != 0) + return 0; + else + return -1; +} + +static void i2c_clear_irq(void) +{ + writel(readl(&i2c_base->ctl) & ~TWI_CTL_INTFLG, &i2c_base->ctl); +} + +static int i2c_wait_irq(void) +{ + return i2c_wait_ctl(TWI_CTL_INTFLG, 1); +} + +static int i2c_wait_status(int status) +{ + int timeout = 0x2ff; + + while (readl(&i2c_base->status) != status && timeout-- > 0) + ; + + if (timeout != 0) + return 0; + else + return -1; +} + +static int i2c_wait_irq_status(int status) +{ + if (i2c_wait_irq() != 0) + return -1; + + if (readl(&i2c_base->status) != status) + return -1; + + return 0; +} + +static int i2c_wait_bus_idle(void) +{ + int timeout = 0x2ff; + + while (readl(&i2c_base->lctl) != 0x3a && timeout-- > 0) + ; + + if (timeout != 0) + return 0; + else + return -1; +} + +static int i2c_stop(void) +{ + u32 ctl; + + ctl = readl(&i2c_base->ctl) & 0xc0; + ctl |= TWI_CTL_STP; + + writel(ctl, &i2c_base->ctl); + + /* dummy to delay one I/O operation to make sure it's started */ + (void)readl(&i2c_base->ctl); + + if (i2c_wait_ctl(TWI_CTL_STP, 0) != 0) + return -1; + if (i2c_wait_status(TWI_STAT_IDLE)) + return -1; + if (i2c_wait_bus_idle() != 0) + return -1; + + return 0; +} + +static int i2c_send_data(u8 data, u8 status) +{ + debug("i2c_write(%02x, %x), ctl=%x, status=%x\n", data, status, + i2c_base->ctl, i2c_base->status); + + writel(data, &i2c_base->data); + i2c_clear_irq(); + + if (i2c_wait_irq_status(status) != 0) + return -1; + + return 0; +} + +static int i2c_start(int status) +{ + u32 ctl; + + debug("i2c_start(%x), ctl=%x, status=%x\n", status, i2c_base->ctl, + i2c_base->status); + /* Check that the controller is idle */ + if (status == TWI_STAT_TX_STA + && readl(&i2c_base->status) != TWI_STAT_IDLE) { + return -1; + } + + writel(0, &i2c_base->efr); + + /* Send start */ + ctl = readl(&i2c_base->ctl); + ctl |= TWI_CTL_STA; /* Set start bit */ + ctl &= ~TWI_CTL_INTFLG; /* Clear int flag */ + writel(ctl, &i2c_base->ctl); + + if (i2c_wait_ctl(TWI_CTL_STA, 0) != 0) + return -1; + if (i2c_wait_irq_status(status) != 0) + return -1; + + return 0; +} + +int i2c_do_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + u32 status; + u32 ctl; + + if (i2c_start(TWI_STAT_TX_STA) != 0) + return -1; + + /* Send chip address */ + if (i2c_send_data(chip << 1 | 0, TWI_STAT_TX_AW_ACK) != 0) + return -1; + + /* Send data address */ + if (i2c_send_data(addr, TWI_STAT_TXD_ACK) != 0) + return -1; + + /* Send restart for read */ + if (i2c_start(TWI_STAT_TX_RESTA) != 0) + return -1; + + /* Send chip address */ + if (i2c_send_data(chip << 1 | 1, TWI_STAT_TX_AR_ACK) != 0) + return -1; + + /* Set ACK mode */ + ctl = readl(&i2c_base->ctl); + ctl |= TWI_CTL_ACK; + writel(ctl, &i2c_base->ctl); + status = TWI_STAT_RXD_ACK; + + /* Read data */ + while (len > 0) { + if (len == 1) { + /* Set NACK mode (last byte) */ + ctl = readl(&i2c_base->ctl); + ctl &= ~TWI_CTL_ACK; + writel(ctl, &i2c_base->ctl); + status = TWI_STAT_RXD_NAK; + } + + i2c_clear_irq(); + if (i2c_wait_irq_status(status) != 0) + return -1; + + *buffer++ = readl(&i2c_base->data); + len--; + } + + return 0; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int rc = i2c_do_read(chip, addr, alen, buffer, len); + + i2c_stop(); + + return rc; +} + +static int i2c_do_write(uchar chip, uint addr, int alen, uchar *buffer, + int len) +{ + if (i2c_start(TWI_STAT_TX_STA) != 0) + return -1; + + /* Send chip address */ + if (i2c_send_data(chip << 1 | 0, TWI_STAT_TX_AW_ACK) != 0) + return -1; + + /* Send data address */ + if (i2c_send_data(addr, TWI_STAT_TXD_ACK) != 0) + return -1; + + /* Send data */ + while (len > 0) { + if (i2c_send_data(*buffer++, TWI_STAT_TXD_ACK) != 0) + return -1; + len--; + } + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) +{ + int rc = i2c_do_write(chip, addr, alen, buffer, len); + + i2c_stop(); + + return rc; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 8a026e0..c2d16fb 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -194,4 +194,12 @@ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS +/* I2C */ +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_HARD_I2C +#define CONFIG_SUNXI_I2C +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_CMD_I2C + #endif /* __CONFIG_H */ -- 1.7.7.6

5 6

[U-Boot] [PATCH v2] powerpc/corenet_ds: move SATA config to board configuration
by Roy Zang 26 Nov '12

26 Nov '12

board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- v2: update according to Timur's comment arch/powerpc/include/asm/config_mpc85xx.h | 7 ------- include/configs/P1010RDB.h | 1 + include/configs/P1022DS.h | 1 + include/configs/P2041RDB.h | 4 +++- include/configs/P3041DS.h | 1 + include/configs/P5020DS.h | 1 + 6 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 03baaee..445fa3d 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -131,7 +131,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -175,7 +174,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -188,7 +186,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 @@ -242,7 +239,6 @@ #define CONFIG_SYS_PPC_E500_DEBUG_TLB 2 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_SEC_COMPAT 2 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 #define CONFIG_SYS_FSL_ERRATUM_ELBC_A001 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -318,7 +314,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -350,7 +345,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 @@ -425,7 +419,6 @@ #define CONFIG_SYS_FSL_NUM_CC_PLLS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 -#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 57aef21..437ee6e 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -553,6 +553,7 @@ extern unsigned long get_sdram_size(void); /* SATA */ #define CONFIG_FSL_SATA +#define CONFIG_FSL_SATA_V2 #define CONFIG_LIBATA #ifdef CONFIG_FSL_SATA diff --git a/include/configs/P1022DS.h b/include/configs/P1022DS.h index b3c850d..14d597a 100644 --- a/include/configs/P1022DS.h +++ b/include/configs/P1022DS.h @@ -360,6 +360,7 @@ /* SATA */ #define CONFIG_LIBATA #define CONFIG_FSL_SATA +#define CONFIG_FSL_SATA_V2 #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 5cdb628..8509d20 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -560,8 +560,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif /* CONFIG_PCI */ /* SATA */ +#define CONFIG_FSL_SATA_V2 + +#ifdef CONFIG_FSL_SATA_V2 #define CONFIG_FSL_SATA -#ifdef CONFIG_FSL_SATA #define CONFIG_LIBATA #define CONFIG_SYS_SATA_MAX_DEVICE 2 diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index cf184e7..ce8f9b0 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -32,6 +32,7 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC +#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_DPAA_RMAN diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 7018d7a..778230d 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -32,6 +32,7 @@ #define CONFIG_MMC #define CONFIG_NAND_FSL_ELBC +#define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_FSL_RAID_ENGINE -- 1.7.8.1

1 0

[U-Boot] [PATCH 01/22] ARM: sunxi: Basic Allwinner A10/A13 (sun4i/sun5i) support
by Henrik Nordström 26 Nov '12

26 Nov '12

This adds support for the Allwinner A10/A13 SoC's. Additionally board support for the dev-boards sun4i/sun5i is added. Signed-off-by: Tom Cubie <tangliang(a)allwinnertech.com> Signed-off-by: Henrik Nordström <henrik(a)henriknordstrom.net> Signed-off-by: Stefan Roese <sr(a)denx.de> --- MAINTAINERS | 13 ++ arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/sunxi/Makefile | 51 +++++++ arch/arm/cpu/armv7/sunxi/board.c | 77 +++++++++++ arch/arm/cpu/armv7/sunxi/clock.c | 57 ++++++++ arch/arm/cpu/armv7/sunxi/pinmux.c | 61 +++++++++ arch/arm/cpu/armv7/sunxi/reset.S | 39 ++++++ arch/arm/cpu/armv7/sunxi/timer.c | 117 +++++++++++++++++ arch/arm/include/asm/arch-sunxi/clock.h | 179 +++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 146 +++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/dram.h | 114 ++++++++++++++++ arch/arm/include/asm/arch-sunxi/gpio.h | 164 +++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/sys_proto.h | 32 +++++ arch/arm/include/asm/arch-sunxi/timer.h | 102 ++++++++++++++ board/sunxi/Makefile | 46 +++++++ board/sunxi/board.c | 57 ++++++++ boards.cfg | 4 + include/configs/sun4i.h | 47 +++++++ include/configs/sun5i.h | 56 ++++++++ include/configs/sunxi-common.h | 189 +++++++++++++++++++++++++++ 20 files changed, 1552 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/Makefile create mode 100644 arch/arm/cpu/armv7/sunxi/board.c create mode 100644 arch/arm/cpu/armv7/sunxi/clock.c create mode 100644 arch/arm/cpu/armv7/sunxi/pinmux.c create mode 100644 arch/arm/cpu/armv7/sunxi/reset.S create mode 100644 arch/arm/cpu/armv7/sunxi/timer.c create mode 100644 arch/arm/include/asm/arch-sunxi/clock.h create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h create mode 100644 arch/arm/include/asm/arch-sunxi/dram.h create mode 100644 arch/arm/include/asm/arch-sunxi/gpio.h create mode 100644 arch/arm/include/asm/arch-sunxi/sys_proto.h create mode 100644 arch/arm/include/asm/arch-sunxi/timer.h create mode 100644 board/sunxi/Makefile create mode 100644 board/sunxi/board.c create mode 100644 include/configs/sun4i.h create mode 100644 include/configs/sun5i.h create mode 100644 include/configs/sunxi-common.h diff --git a/MAINTAINERS b/MAINTAINERS index c430574..80c1bd7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -331,6 +331,19 @@ Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> TOP5200 MPC5200 TOP9000 ARM926EJS (AT91SAM9xxx SoC) +Henrik Nordstrom <henrik(a)henriknordstrom.net> + A13_OLINUXINO ARM V7 (Allwinner A13 SoC) + A13_MID ARM V7 (Allwinner A13 SoC) + CUBIEBOARD ARM V7 (Allwinner A10 SoC) + CUBIEBOARD_512 ARM V7 (Allwinner A10 SoC) + HACKBERRY ARM V7 (Allwinner A10 SoC) + MELE_A1000 ARM V7 (Allwinner A10 SoC) + MINI-X ARM V7 (Allwinner A10 SoC) + SUN4I ARM V7 (Allwinner A10 SoC) + SUN4I_SDCON ARM V7 (Allwinner A10 SoC) + SUN5I ARM V7 (Allwinner A13 SoC) + SUN5I_SDCON ARM V7 (Allwinner A13 SoC) + Kyle Moffett <Kyle.D.Moffett(a)boeing.com> HWW1U1A P2020 diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index da1b5e8..56f51b5 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -33,7 +33,7 @@ COBJS += cpu.o COBJS += syslib.o COBJS += cmd_boot.o -ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),) +ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20)$(CONFIG_SUNXI),) SOBJS += lowlevel_init.o endif diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile new file mode 100644 index 0000000..cbe1015 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).o + +SOBJS += reset.o + +COBJS += timer.o +COBJS += dram.o +COBJS += board.o +COBJS += clock.o +COBJS += pinmux.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c new file mode 100644 index 0000000..652c19d --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * Some init for sunxi platform. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <serial.h> +#include <asm/gpio.h> +#include <asm/arch/clock.h> +#include <asm/arch/timer.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sys_proto.h> + +int gpio_init(void) +{ +#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F) +#ifdef CONFIG_SUN4I + /* disable GPB22,23 as uart0 tx,rx to avoid conflict */ + gpio_direction_input(SUNXI_GPB(22)); + gpio_direction_input(SUNXI_GPB(23)); +#endif + sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN4I) + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); +#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_SUN5I) + sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG3_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG4_UART0_RX); +#else +#error Unsupported console port number. Please fix pin mux settings in board.c +#endif + + return 0; +} + +/* do some early init */ +void s_init(void) +{ + clock_init(); + gpio_init(); +} + +void reset_cpu(ulong addr) +{ + sunxi_reset(); +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c new file mode 100644 index 0000000..424acfc --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> + +int clock_init(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* uart clock source is apb1 */ + sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M); + sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N); + sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M); + + /* open the clock for uart */ + sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN); + + return 0; +} + +/* Return PLL5 frequency in Hz + * Note: Assumes PLL5 reference is 24MHz clock + */ +unsigned int clock_get_pll5(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll5_cfg); + int n = (rval >> 8) & 0x1f; + int k = ((rval >> 4) & 3) + 1; + int p = 1 << ((rval >> 16) & 3); + return 24000000 * n * k / p; +} diff --git a/arch/arm/cpu/armv7/sunxi/pinmux.c b/arch/arm/cpu/armv7/sunxi/pinmux.c new file mode 100644 index 0000000..77e1d90 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/pinmux.c @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> + +int sunxi_gpio_set_cfgpin(u32 pin, u32 val) +{ + u32 cfg; + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_CFG_INDEX(pin); + u32 offset = GPIO_CFG_OFFSET(pin); + struct sunxi_gpio *pio = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + + cfg = readl(&pio->cfg[0] + index); + cfg &= ~(0xf << offset); + cfg |= val << offset; + + writel(cfg, &pio->cfg[0] + index); + + return 0; +} + +int sunxi_gpio_get_cfgpin(u32 pin) +{ + u32 cfg; + u32 bank = GPIO_BANK(pin); + u32 index = GPIO_CFG_INDEX(pin); + u32 offset = GPIO_CFG_OFFSET(pin); + struct sunxi_gpio *pio = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + + cfg = readl(&pio->cfg[0] + index); + cfg >>= offset; + + return cfg & 0xf; +} + diff --git a/arch/arm/cpu/armv7/sunxi/reset.S b/arch/arm/cpu/armv7/sunxi/reset.S new file mode 100644 index 0000000..36714e7 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/reset.S @@ -0,0 +1,39 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * Configuration settings for the Allwinner A10-evb board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/cpu.h> + +#define SUNXI_WDOG_CTL 0x01C20C90 +#define SUNXI_WDOG_MODE 0x01C20C94 + +.globl sunxi_reset +sunxi_reset: + ldr r1, =SUNXI_WDOG_MODE + mov r3, #0x3 + str r3, [r1] + mov r0, r0 +_loop_forever: + b _loop_forever diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c new file mode 100644 index 0000000..e19df09 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/timer.c @@ -0,0 +1,117 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_MODE (0 << 7) /* continuous mode */ +#define TIMER_DIV (0 << 4) /* pre scale 1 */ +#define TIMER_SRC (1 << 2) /* osc24m */ +#define TIMER_RELOAD (1 << 1) /* reload internal value */ +#define TIMER_EN (1 << 0) /* enable timer */ + +#define TIMER_CLOCK (24 * 1000 * 1000) +#define COUNT_TO_USEC(x) ((x) / 24) +#define USEC_TO_COUNT(x) ((x) * 24) +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) + +#define TIMER_LOAD_VAL 0xffffffff + +#define TIMER_NUM 0 /* we use timer 0 */ + +static struct sunxi_timer *timer_base = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM]; + +/* macro to read the 32 bit timer: since it decrements, we invert read value */ +#define READ_TIMER() (~readl(&timer_base->val)) + +/* init timer register */ +int timer_init(void) +{ + writel(TIMER_LOAD_VAL, &timer_base->inter); + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN, + &timer_base->ctl); + + return 0; +} + +/* timer without interrupts */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = TICKS_TO_HZ(READ_TIMER()); + + if (now >= gd->lastinc) /* normal (non rollover) */ + gd->tbl += (now - gd->lastinc); + else /* rollover */ + gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now; + gd->lastinc = now; + + return gd->tbl; +} + +/* delay x useconds */ +void __udelay(unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + ulong now, last = READ_TIMER(); + + while (tmo > 0) { + now = READ_TIMER(); + if (now > last) /* normal (non rollover) */ + tmo -= now - last; + else /* rollover */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h new file mode 100644 index 0000000..863e59e --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SUNXI_CLOCK_H +#define _SUNXI_CLOCK_H + +/* clock control module regs definition */ + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_cfg; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ +}; + +/* apb1 bit field */ +#define APB1_CLK_SRC_OSC24M 0 +#define APB1_FACTOR_M 0 +#define APB1_FACTOR_N 0 + +/* clock divide */ +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define AHB_DIV_1 0 +#define AHB_DIV_2 1 +#define AHB_DIV_4 2 +#define AHB_DIV_8 3 +#define APB0_DIV_1 0 +#define APB0_DIV_2 1 +#define APB0_DIV_4 2 +#define APB0_DIV_8 3 + +#ifdef CONFIG_SUN5I +#define AHB_CLK_SRC_AXI 0 +#endif + +#define CLK_GATE_OPEN 0x1 +#define CLK_GATE_CLOSE 0x0 + +/* nand clock */ +#define NAND_CLK_SRC_OSC24 0 +#define NAND_CLK_DIV_N 0 +#define NAND_CLK_DIV_M 0 + +/* gps clock */ +#define GPS_SCLK_GATING_OFF 0 +#define GPS_RESET 0 + +/* ahb clock gate bit offset */ +#define AHB_GATE_OFFSET_GPS 26 +#define AHB_GATE_OFFSET_SATA 25 +#define AHB_GATE_OFFSET_PATA 24 +#define AHB_GATE_OFFSET_SPI3 23 +#define AHB_GATE_OFFSET_SPI2 22 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_TS0 18 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_ACE 16 +#define AHB_GATE_OFFSET_DLL 15 +#define AHB_GATE_OFFSET_SDRAM 14 +#define AHB_GATE_OFFSET_NAND 13 +#define AHB_GATE_OFFSET_MS 12 +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_BIST 7 +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 +#define AHB_GATE_OFFSET_USB_OHCI1 4 +#define AHB_GATE_OFFSET_USB_EHCI1 3 +#define AHB_GATE_OFFSET_USB_OHCI0 2 +#define AHB_GATE_OFFSET_USB_EHCI0 1 +#define AHB_GATE_OFFSET_USB 0 + +#ifndef __ASSEMBLY__ +int clock_init(void); +int clock_twi_onoff(int port, int state); +void clock_set_pll1(int mhz); +unsigned int clock_get_pll5(void); +#endif + +#endif /* _SUNXI_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h new file mode 100644 index 0000000..6c8eaeb --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -0,0 +1,146 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SUNXI_CPU_H +#define _SUNXI_CPU_H + +#define SUNXI_SRAM_A1_BASE 0x00000000 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16k */ + +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16k */ +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13k */ +#define SUNXI_SRAM_A4_BASE 0x0000B400 /* 3k */ +#define SUNXI_SRAM_D_BASE 0x01C00000 +#define SUNXI_SRAM_B_BASE 0x01C00000 /* 64k(secure) */ + +#define SUNXI_SRAMC_BASE 0x01C00000 +#define SUNXI_DRAMC_BASE 0x01C01000 +#define SUNXI_DMA_BASE 0x01C02000 +#define SUNXI_NFC_BASE 0x01C03000 +#define SUNXI_TS_BASE 0x01C04000 +#define SUNXI_SPI0_BASE 0x01C05000 +#define SUNXI_SPI1_BASE 0x01C06000 +#define SUNXI_MS_BASE 0x01C07000 +#define SUNXI_TVD_BASE 0x01C08000 +#define SUNXI_CSI0_BASE 0x01C09000 +#define SUNXI_TVE0_BASE 0x01C0A000 +#define SUNXI_EMAC_BASE 0x01C0B000 +#define SUNXI_LCD0_BASE 0x01C0C000 +#define SUNXI_LCD1_BASE 0x01C0D000 +#define SUNXI_VE_BASE 0x01C0E000 +#define SUNXI_MMC0_BASE 0x01C0F000 +#define SUNXI_MMC1_BASE 0x01C10000 +#define SUNXI_MMC2_BASE 0x01C11000 +#define SUNXI_MMC3_BASE 0x01C12000 +#define SUNXI_USB0_BASE 0x01C13000 +#define SUNXI_USB1_BASE 0x01C14000 +#define SUNXI_SS_BASE 0x01C15000 +#define SUNXI_HDMI_BASE 0x01C16000 +#define SUNXI_SPI2_BASE 0x01C17000 +#define SUNXI_SATA_BASE 0x01C18000 +#define SUNXI_PATA_BASE 0x01C19000 +#define SUNXI_ACE_BASE 0x01C1A000 +#define SUNXI_TVE1_BASE 0x01C1B000 +#define SUNXI_USB2_BASE 0x01C1C000 +#define SUNXI_CSI1_BASE 0x01C1D000 +#define SUNXI_TZASC_BASE 0x01C1E000 +#define SUNXI_SPI3_BASE 0x01C1F000 + +#define SUNXI_CCM_BASE 0x01C20000 +#define SUNXI_INTC_BASE 0x01C20400 +#define SUNXI_PIO_BASE 0x01C20800 +#define SUNXI_TIMER_BASE 0x01C20C00 +#define SUNXI_SPDIF_BASE 0x01C21000 +#define SUNXI_AC97_BASE 0x01C21400 +#define SUNXI_IR0_BASE 0x01C21800 +#define SUNXI_IR1_BASE 0x01C21C00 + +#define SUNXI_IIS_BASE 0x01C22400 +#define SUNXI_LRADC_BASE 0x01C22800 +#define SUNXI_AD_DA_BASE 0x01C22C00 +#define SUNXI_KEYPAD_BASE 0x01C23000 +#define SUNXI_TZPC_BASE 0x01C23400 +#define SUNXI_SID_BASE 0x01C23800 +#define SUNXI_SJTAG_BASE 0x01C23C00 + +#define SUNXI_TP_BASE 0x01C25000 +#define SUNXI_PMU_BASE 0x01C25400 + +#define SUNXI_UART0_BASE 0x01C28000 +#define SUNXI_UART1_BASE 0x01C28400 +#define SUNXI_UART2_BASE 0x01C28800 +#define SUNXI_UART3_BASE 0x01C28C00 +#define SUNXI_UART4_BASE 0x01C29000 +#define SUNXI_UART5_BASE 0x01C29400 +#define SUNXI_UART6_BASE 0x01C29800 +#define SUNXI_UART7_BASE 0x01C29C00 +#define SUNXI_PS2_0_BASE 0x01C2A000 +#define SUNXI_PS2_1_BASE 0x01C2A400 + +#define SUNXI_TWI0_BASE 0x01C2AC00 +#define SUNXI_TWI1_BASE 0x01C2B000 +#define SUNXI_TWI2_BASE 0x01C2B400 + +#define SUNXI_CAN_BASE 0x01C2BC00 + +#define SUNXI_SCR_BASE 0x01C2C400 + +#define SUNXI_GPS_BASE 0x01C30000 +#define SUNXI_MALI400_BASE 0x01C40000 + +/* module sram */ +#define SUNXI_SRAM_C_BASE 0x01D00000 + +#define SUNXI_DE_FE0_BASE 0x01E00000 +#define SUNXI_DE_FE1_BASE 0x01E20000 +#define SUNXI_DE_BE0_BASE 0x01E60000 +#define SUNXI_DE_BE1_BASE 0x01E40000 +#define SUNXI_MP_BASE 0x01E80000 +#define SUNXI_AVG_BASE 0x01EA0000 + +/* CoreSight Debug Module */ +#define SUNXI_CSDM_BASE 0x3F500000 + +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2G */ + +#define SUNXI_BROM_BASE 0xFFFF0000 /* 32K */ + +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +#ifndef __ASSEMBLY__ +/* boot type */ +enum sunxi_boot_type_t { + SUNXI_BOOT_TYPE_NULL, + SUNXI_BOOT_TYPE_MMC0, + SUNXI_BOOT_TYPE_NAND, + SUNXI_BOOT_TYPE_MMC2, + SUNXI_BOOT_TYPE_SPI +}; + +sunxi_boot_type_t get_boot_type(void); +void sunxi_board_init(void); +extern void sunxi_reset(void); +#endif /* __ASSEMBLY__ */ + +#endif /* _CPU_H */ diff --git a/arch/arm/include/asm/arch-sunxi/dram.h b/arch/arm/include/asm/arch-sunxi/dram.h new file mode 100644 index 0000000..d3c0e9f --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/dram.h @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Berg Xing <bergxing(a)allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * Sunxi platform dram register definition. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SUNXI_DRAM_H +#define _SUNXI_DRAM_H + +struct sunxi_dram_reg { + u32 ccr; /* 0x00 controller configuration register */ + u32 dcr; /* 0x04 dram configuration register */ + u32 iocr; /* 0x08 i/o configuration register */ + u32 csr; /* 0x0c controller status register */ + u32 drr; /* 0x10 dram refresh register */ + u32 tpr0; /* 0x14 dram timing parameters register 0 */ + u32 tpr1; /* 0x18 dram timing parameters register 1 */ + u32 tpr2; /* 0x1c dram timing parameters register 2 */ + u32 gdllcr; /* 0x20 global dll control register */ + u8 res0[0x28]; + u32 rslr0; /* 0x4c rank system latency register */ + u32 rslr1; /* 0x50 rank system latency register */ + u8 res1[0x8]; + u32 rdgr0; /* 0x5c rank dqs gating register */ + u32 rdgr1; /* 0x60 rank dqs gating register */ + u8 res2[0x34]; + u32 odtcr; /* 0x98 odt configuration register */ + u32 dtr0; /* 0x9c data training register 0 */ + u32 dtr1; /* 0xa0 data training register 1 */ + u32 dtar; /* 0xa4 data training address register */ + u32 zqcr0; /* 0xa8 zq control register 0 */ + u32 zqcr1; /* 0xac zq control register 1 */ + u32 zqsr; /* 0xb0 zq status register */ + u32 idcr; /* 0xb4 initializaton delay configure reg */ + u8 res3[0x138]; + u32 mr; /* 0x1f0 mode register */ + u32 emr; /* 0x1f4 extended mode register */ + u32 emr2; /* 0x1f8 extended mode register */ + u32 emr3; /* 0x1fc extended mode register */ + u32 dllctr; /* 0x200 dll control register */ + u32 dllcr[5]; /* 0x204 dll control register 0(byte 0) */ + /* 0x208 dll control register 1(byte 1) */ + /* 0x20c dll control register 2(byte 2) */ + /* 0x210 dll control register 3(byte 3) */ + /* 0x214 dll control register 4(byte 4) */ + u32 dqtr0; /* 0x218 dq timing register */ + u32 dqtr1; /* 0x21c dq timing register */ + u32 dqtr2; /* 0x220 dq timing register */ + u32 dqtr3; /* 0x224 dq timing register */ + u32 dqstr; /* 0x228 dqs timing register */ + u32 dqsbtr; /* 0x22c dqsb timing register */ + u32 mcr; /* 0x230 mode configure register */ + u8 res[0x8]; + u32 ppwrsctl; /* 0x23c pad power save control */ + u32 apr; /* 0x240 arbiter period register */ + u32 pldtr; /* 0x244 priority level data threshold reg */ + u8 res5[0x8]; + u32 hpcr[32]; /* 0x250 host port configure register */ + u8 res6[0x10]; + u32 csel; /* 0x2e0 controller select register */ +}; + +struct dram_para { + u32 clock; + u32 type; + u32 rank_num; + u32 density; + u32 io_width; + u32 bus_width; + u32 cas; + u32 zq; + u32 odt_en; + u32 size; + u32 tpr0; + u32 tpr1; + u32 tpr2; + u32 tpr3; + u32 tpr4; + u32 tpr5; + u32 emr1; + u32 emr2; + u32 emr3; +}; + +#define SUN5I_DRAM_MCR_DCLK_OUT_OFFSET 16 +#define SUN4I_CCM_SDRAM_DCLK_OUT_OFFSET 15 + +#define DRAM_CTRL_SELECT_MAGIC 0x16237495 + +int sunxi_dram_init(void); +int dramc_init(struct dram_para *para); + +#endif /* _SUNXI_DRAM_H */ diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h new file mode 100644 index 0000000..fceee6b --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -0,0 +1,164 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SUNXI_GPIO_H +#define _SUNXI_GPIO_H + +/* + * sunxi has 9 banks of gpio, they are: + * PA0 - PA17 | PB0 - PB23 | PC0 - PC24 + * PD0 - PD27 | PE0 - PE31 | PF0 - PF5 + * PG0 - PG9 | PH0 - PH27 | PI0 - PI12 + */ + +#define SUNXI_GPIO_A 0 +#define SUNXI_GPIO_B 1 +#define SUNXI_GPIO_C 2 +#define SUNXI_GPIO_D 3 +#define SUNXI_GPIO_E 4 +#define SUNXI_GPIO_F 5 +#define SUNXI_GPIO_G 6 +#define SUNXI_GPIO_H 7 +#define SUNXI_GPIO_I 8 + +struct sunxi_gpio { + u32 cfg[4]; + u32 dat; + u32 drv[2]; + u32 pull[2]; +}; + +/* gpio interrupt control */ +struct sunxi_gpio_int { + u32 cfg[3]; + u32 ctl; + u32 sta; + u32 deb; /* interrupt debounce */ +}; + +struct sunxi_gpio_reg { + struct sunxi_gpio gpio_bank[9]; + u8 res[0xbc]; + struct sunxi_gpio_int gpio_int; +}; + +#define GPIO_BANK(pin) ((pin) >> 5) +#define GPIO_NUM(pin) ((pin) & 0x1F) + +#define GPIO_CFG_INDEX(pin) (((pin) & 0x1F) >> 3) +#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1F) & 0x7) << 2) + +/* GPIO bank sizes */ +#define SUNXI_GPIO_A_NR 32 +#define SUNXI_GPIO_B_NR 32 +#define SUNXI_GPIO_C_NR 32 +#define SUNXI_GPIO_D_NR 32 +#define SUNXI_GPIO_E_NR 32 +#define SUNXI_GPIO_F_NR 32 +#define SUNXI_GPIO_G_NR 32 +#define SUNXI_GPIO_H_NR 32 +#define SUNXI_GPIO_I_NR 32 + +#define SUNXI_GPIO_NEXT(__gpio) \ + ((__gpio##_START) + (__gpio##_NR) + 0) + +enum sunxi_gpio_number { + SUNXI_GPIO_A_START = 0, + SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), + SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), + SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), + SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), + SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), + SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), + SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), + SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), +}; + +/* SUNXI GPIO number definitions */ +#define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) +#define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) +#define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) +#define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) +#define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) +#define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) +#define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) +#define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) +#define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) + +/* GPIO pin function config */ +#define SUNXI_GPIO_INPUT 0 +#define SUNXI_GPIO_OUTPUT 1 + +#define SUNXI_GPA0_ERXD3 2 +#define SUNXI_GPA0_SPI1_CS0 3 +#define SUNXI_GPA0_UART2_RTS 4 + +#define SUNXI_GPA1_ERXD2 2 +#define SUNXI_GPA1_SPI1_CLK 3 +#define SUNXI_GPA1_UART2_CTS 4 + +#define SUNXI_GPA2_ERXD1 2 +#define SUNXI_GPA2_SPI1_MOSI 3 +#define SUNXI_GPA2_UART2_TX 4 + +#define SUNXI_GPA10_UART1_TX 4 +#define SUNXI_GPA11_UART1_RX 4 + +#define SUN4I_GPB22_UART0_TX 2 +#define SUN4I_GPB23_UART0_RX 2 + +#define SUN5I_GPG3_UART0_TX 4 +#define SUN5I_GPG4_UART0_RX 4 + +#define SUNXI_GPC2_NCLE 2 +#define SUNXI_GPC2_SPI0_CLK 3 + +#define SUNXI_GPC6_NRB0 2 +#define SUNXI_GPC6_SDC2_CMD 3 + +#define SUNXI_GPC7_NRB1 2 +#define SUNXI_GPC7_SDC2_CLK 3 + +#define SUNXI_GPC8_NDQ0 2 +#define SUNXI_GPC8_SDC2_D0 3 + +#define SUNXI_GPC9_NDQ1 2 +#define SUNXI_GPC9_SDC2_D1 3 + +#define SUNXI_GPC10_NDQ2 2 +#define SUNXI_GPC10_SDC2_D2 3 + +#define SUNXI_GPC11_NDQ3 2 +#define SUNXI_GPC11_SDC2_D3 3 + +#define SUNXI_GPF2_SDC0_CLK 2 +#define SUNXI_GPF2_UART0_TX 4 + +#define SUNXI_GPF4_SDC0_D3 2 +#define SUNXI_GPF4_UART0_RX 4 + +int sunxi_gpio_set_cfgpin(u32 pin, u32 val); +int sunxi_gpio_get_cfgpin(u32 pin); + +#endif /* _SUNXI_GPIO_H */ diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h new file mode 100644 index 0000000..1e8ae5d --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -0,0 +1,32 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +void sr32(u32 *, u32, u32, u32); +void sdelay(unsigned long); +void watchdog_init(void); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h new file mode 100644 index 0000000..cbfec53 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * Configuration settings for the Allwinner A10-evb board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SUNXI_TIMER_H_ +#define _SUNXI_TIMER_H_ + +#ifndef __ASSEMBLY__ + +/* General purpose timer */ +struct sunxi_timer { + u32 ctl; + u32 inter; + u32 val; + u8 res[4]; +}; + +/* Audio video sync*/ +struct sunxi_avs { + u32 ctl; /* 0x80 */ + u32 cnt0; /* 0x84 */ + u32 cnt1; /* 0x88 */ + u32 div; /* 0x8c */ +}; + +/* 64 bit counter */ +struct sunxi_64cnt { + u32 ctl; /* 0xa0 */ + u32 lo; /* 0xa4 */ + u32 hi; /* 0xa8 */ +}; + +/* Watchdog */ +struct sunxi_wdog { + u32 ctl; /* 0x90 */ + u32 mode; /* 0x94 */ +}; + +/* Rtc */ +struct sunxi_rtc { + u32 ctl; /* 0x100 */ + u32 yymmdd; /* 0x104 */ + u32 hhmmss; /* 0x108 */ +}; + +/* Alarm */ +struct sunxi_alarm { + u32 ddhhmmss; /* 0x10c */ + u32 hhmmss; /* 0x110 */ + u32 en; /* 0x114 */ + u32 irqen; /* 0x118 */ + u32 irqsta; /* 0x11c */ +}; + +/* Timer general purpose register */ +struct sunxi_tgp { + u32 tgpd; +}; + +struct sunxi_timer_reg { + u32 tirqen; /* 0x00 */ + u32 tirqsta; /* 0x04 */ + u8 res1[8]; + struct sunxi_timer timer[6]; /* We have 6 timers */ + u8 res2[16]; + struct sunxi_avs avs; + struct sunxi_wdog wdog; + u8 res3[8]; + struct sunxi_64cnt cnt64; + u8 res4[0x58]; + struct sunxi_rtc rtc; + struct sunxi_alarm alarm; + struct sunxi_tgp tgp[4]; + u8 res5[8]; + u32 cpu_cfg; +}; + +#endif /* __ASSEMBLY__ */ + +#endif diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile new file mode 100644 index 0000000..43acbab --- /dev/null +++ b/board/sunxi/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).o + +COBJS-y := board.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################## diff --git a/board/sunxi/board.c b/board/sunxi/board.c new file mode 100644 index 0000000..ae05953 --- /dev/null +++ b/board/sunxi/board.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * Some board init for the Allwinner A10-evb board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/dram.h> +#include <asm/arch/clock.h> +#include <asm/arch/mmc.h> +#include <axp209.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* add board specific code here */ +int board_init(void) +{ + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100); + + return 0; +} + +#ifdef CONFIG_DISPLAY_BOARDINFO +int checkboard(void) +{ + printf("Board: %s\n", CONFIG_SYS_BOARD_NAME); + + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, 1 << 30); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 7ae663c..13d1f74 100644 --- a/boards.cfg +++ b/boards.cfg @@ -288,6 +288,10 @@ whistler arm armv7:arm720t whistler nvidia colibri_t20_iris arm armv7:arm720t colibri_t20_iris toradex tegra20 u8500_href arm armv7 u8500 st-ericsson u8500 snowball arm armv7 snowball st-ericsson u8500 +sun4i arm armv7 sunxi - sunxi sun4i +sun4i_sdcon arm armv7 sunxi - sunxi sun4i:UART0_PORT_F +sun5i arm armv7 sunxi - sunxi sun5i +sun5i_sdcon arm armv7 sunxi - sunxi sun5i:UART0_PORT_F kzm9g arm armv7 kzm9g kmc rmobile armadillo-800eva arm armv7 armadillo-800eva atmark-techno rmobile zynq arm armv7 zynq xilinx zynq diff --git a/include/configs/sun4i.h b/include/configs/sun4i.h new file mode 100644 index 0000000..513f618 --- /dev/null +++ b/include/configs/sun4i.h @@ -0,0 +1,47 @@ +/* + * (C) Copyright 2012 + * Henrik Nordstrom <henrik(a)henriknordstrom.net> + * + * Configuration settings for the Allwinner A10 (sun4i) CPU + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +/* + * A10 specific configuration + */ +#define CONFIG_SUN4I /* sun4i SoC generation */ + +#define CONFIG_SYS_PROMPT "sun4i#" +#define CONFIG_MACH_TYPE 4104 + +/* Define this to have console redirected to SD port */ +/* #define CONFIG_UART0_PORT_F */ + +#define CONFIG_CONS_INDEX 1 /* UART0 */ + +#endif /* __CONFIG_H */ diff --git a/include/configs/sun5i.h b/include/configs/sun5i.h new file mode 100644 index 0000000..dc84aba --- /dev/null +++ b/include/configs/sun5i.h @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2012 + * Henrik Nordstrom <henrik(a)henriknordstrom.net> + * + * Configuration settings for the Allwinner A13 (sun5i) CPU + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * Include common sunxi configuration where most the settings are + */ +#include <configs/sunxi-common.h> + +/* + * High Level Configuration Options + */ +#define CONFIG_SUN5I /* sun5i SoC generation */ + +#define CONFIG_SYS_PROMPT "sun5i#" +#define CONFIG_MACH_TYPE 4138 + +/* Define this to have serial channel 1 (UART0) redirected to SD port */ +/* #define CONFIG_UART0_PORT_F */ + +#ifndef CONFIG_CONS_INDEX +#ifdef CONFIG_UART0_PORT_F +#define CONFIG_CONS_INDEX 1 /* UART0 on PORT_F (sdcard) */ +#else +#define CONFIG_CONS_INDEX 2 /* UART1 */ +#endif +#endif + +/* Leave ICACHE off while debugging with OpenOCD */ +#define CONFIG_SYS_ICACHE_OFF + +#endif /* __CONFIG_H */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h new file mode 100644 index 0000000..33309f3 --- /dev/null +++ b/include/configs/sunxi-common.h @@ -0,0 +1,189 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * Configuration settings for the Allwinner A10-evb board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _SUNXI_CONFIG_H +#define _SUNXI_CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ALLWINNER /* It's a Allwinner chip */ +#define CONFIG_SUNXI /* which is sunxi family */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ + +#define CONFIG_SYS_TEXT_BASE 0x4A000000 + +/* + * Display CPU and Board information + */ +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ + +/* Serial & console */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +/* ns16550 reg in the low bits of cpu reg */ +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK (24000000) +#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE +#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE +#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE +#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE + +/* DRAM Base */ +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define CONFIG_SYS_INIT_RAM_ADDR 0x0 +#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32K */ + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* A10-EVB has 1 banks of DRAM, we use only one in U-Boot */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE + +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_SETEXPR + +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_CMDLINE_TAG +#define CONFIG_INITRD_TAG +#define CONFIG_CMDLINE_EDITING + +/* + * Size of malloc() pool + * 1MB = 0x100000, 0x100000 = 1024 * 1024 + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* Flat Device Tree (FDT/DT) support */ +#define CONFIG_OF_LIBFDT +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_CMD_ECHO +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (256 << 20)) +#define CONFIG_SYS_LOAD_ADDR 0x50000000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 + +/* valid baudrates */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KB */ + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KB */ +#define CONFIG_IDENT_STRING " Allwinner Technology " + +#define CONFIG_ENV_IS_NOWHERE /* No storage defined yet */ + +#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512)KB */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128KB */ + +#define CONFIG_BOOTCOMMAND \ + "if run loadbootenv; then " \ + "echo Loaded environment from ${bootenv};" \ + "env import -t ${scriptaddr} ${filesize};" \ + "fi;" \ + "if test -n ${uenvcmd}; then " \ + "echo Running uenvcmd ...;" \ + "run uenvcmd;" \ + "fi;" \ + "if run loadbootscr; then "\ + "echo Jumping to ${bootscr};" \ + "source ${scriptaddr};" \ + "fi;" \ + "run setargs boot_mmc;" \ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "console=ttyS0,115200\0" \ + "root=/dev/mmcblk0p2 rootwait\0" \ + "panicarg=panic=10\0" \ + "extraargs=\0" \ + "loglevel=8\0" \ + "scriptaddr=0x44000000\0" \ + "setargs=setenv bootargs console=${console} root=${root}" \ + " loglevel=${loglevel} ${panicarg} ${extraargs}\0" \ + "kernel=uImage\0" \ + "bootenv=uEnv.txt\0" \ + "bootscr=boot.scr\0" \ + "loadbootscr=fatload mmc 0 $scriptaddr ${bootscr} ||" \ + " ext2load mmc 0 $scriptaddr ${bootscr} ||" \ + " ext2load mmc 0 $scriptaddr boot/${bootscr}\0" \ + "loadbootenv=fatload mmc 0 $scriptaddr ${bootenv} ||" \ + " ext2load mmc 0 $scriptaddr ${bootenv} ||" \ + " ext2load mmc 0 $scriptaddr boot/${bootenv}\0" \ + "boot_mmc=fatload mmc 0 0x43000000 script.bin &&" \ + " fatload mmc 0 0x48000000 ${kernel} &&" \ + " bootm 0x48000000\0" + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_SYS_BOOT_GET_CMDLINE +#define CONFIG_AUTO_COMPLETE + +#include <config_cmd_default.h> + +#define CONFIG_DOS_PARTITION +#define CONFIG_CMD_FAT /* with this we can access fat bootfs */ +#define CONFIG_FAT_WRITE /* enable write access */ +#define CONFIG_CMD_EXT2 /* with this we can access ext2 bootfs */ +#define CONFIG_CMD_EXT4 /* with this we can access ext4 bootfs */ +#define CONFIG_CMD_ZFS /* with this we can access ZFS bootfs */ + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS + +#endif /* __CONFIG_H */ -- 1.7.7.6

5 14

[U-Boot] Reg Bootstrapping u-boot on x86-64 for tizen
by manohar.betham＠smartplayin.com 26 Nov '12

26 Nov '12

Hi, I am Manohar,started boot the X86-64 (Intel(R) Core(TM) i5-2400 CPU @ 3.10GHz) using u-boot to work for TIZEN . As I am unable to configure/build my pc using u-boot-x86 . I request you please help me how to configure it/build the u-boot-x86 on my pc as my pc is loaded with Ubuntu 11.10 and my aim is to make my PC as host and target are the same. Please resolve the issue/is my PC support for the u-boot. Best Regards, Manohar 8790215215

3 10

[U-Boot] [PATCH v2 0/10] x86: Patches to enable running U-Boot from coreboot
by Simon Glass 26 Nov '12

26 Nov '12

This series carries on from Gabe Black's work to upstream support for running U-Boot from coreboot. Aditional follow-on patches are also required, depending on feedback here. Changes in v2: - Put CONFIG_NO_RESET_CODE into Makefile instead of source files - Add new patch to remove coreboot start16 code. Gabe Black (4): x86: Allow excluding reset vector code from u-boot x86: Add some missing includes. x86: coreboot: Tell u-boot about PCI bus 0 when initializing x86: coreboot: Implement recursively scanning PCI busses Simon Glass (4): x86: Change board baud_rate to ulong x86: Add initial memory barrier macros x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE x86: Remove coreboot start16 code Stefan Reinauer (1): x86: coreboot: Move non-board specific files to coreboot arch directory Vadim Bendebury (1): x86: coreboot: Modify u-boot code to allow building coreboot payload Makefile | 7 +++- arch/x86/cpu/Makefile | 5 ++- arch/x86/cpu/coreboot/Makefile | 2 + .../x86/cpu}/coreboot/coreboot.c | 0 .../coreboot_pci.c => arch/x86/cpu/coreboot/pci.c | 35 ++++++++++++++++++ arch/x86/cpu/u-boot.lds | 3 ++ arch/x86/include/asm/global_data.h | 2 + arch/x86/include/asm/io.h | 8 ++++ arch/x86/include/asm/pci.h | 2 +- arch/x86/include/asm/u-boot.h | 5 ++- board/chromebook-x86/coreboot/Makefile | 2 - board/chromebook-x86/coreboot/config.mk | 37 ++++++++++++++++++++ board/chromebook-x86/coreboot/coreboot_start16.S | 13 ------- common/cmd_bdinfo.c | 2 +- include/configs/coreboot.h | 6 +++- 15 files changed, 107 insertions(+), 22 deletions(-) rename {board/chromebook-x86 => arch/x86/cpu}/coreboot/coreboot.c (100%) rename board/chromebook-x86/coreboot/coreboot_pci.c => arch/x86/cpu/coreboot/pci.c (51%) create mode 100644 board/chromebook-x86/coreboot/config.mk -- 1.7.7.3

4 32

[U-Boot] [PATCH] fsl/sata: remove read only bit writing in host control register
by Roy Zang 26 Nov '12

26 Nov '12

HC_OFF bit in HControl register is read only bit, which should not be written. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> --- check mpc8379, mpc8536, P3041, P5020 and T4240. HC_OFF bit is read only. drivers/block/fsl_sata.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/block/fsl_sata.c b/drivers/block/fsl_sata.c index fda3389..f647545 100644 --- a/drivers/block/fsl_sata.c +++ b/drivers/block/fsl_sata.c @@ -190,7 +190,6 @@ int init_sata(int dev) /* To have safe state, force the controller offline */ val32 = in_le32(&reg->hcontrol); val32 &= ~HCONTROL_ONOFF; - val32 |= HCONTROL_FORCE_OFFLINE; out_le32(&reg->hcontrol, val32); /* Wait the controller offline */ -- 1.7.8.1

1 0

[U-Boot] [PATCH 00/22] ARM: Allwinner sunXi (A10 & A13) SoC support
by Henrik Nordström 26 Nov '12

26 Nov '12

This patch series adds support for Allwinner sunxi (A10 & A13) SoC families, including SPL loader to boot u-boot directly from MMC/SD. Aaron (1): ARM: sunxi: MMC driver Henrik Nordstrom (14): ARM sunxi: I2C driver ARM: sunxi: watchdog support power: Add AXP209 Power Management controller (I2C) ARM sunxi: Basic GPIO driver tools: mksunixboot adding a Allwinner boot header sunxi: Add more network commands and netconsole support ARM: sunxi: U-Boot SPL capable of booting directly from MMC ARM sunxi: SPL support for Olimex A13-OLinuXino board ARM sunxi: SPL support for Mele A1000 board ARM sunxi: SPL support for Cubieboard board ARM sunxi: SPL support for Hackberry 1GB board ARM sunxi: SPL support for Mini-X board ARM sunxi: SPL support for hyundai A7HD board ARM sunxi: SPL support for Mele A3700 board Jari Helaakoski (1): ARM sunxi: SPL support for a13_mid board Sergey Lapin (1): ARM sunxi: SPL support for MK802 board Stefan Roese (2): net: Add sunxi (Allwinner) wemac driver ARM: sun4i: Enable ethernet support (wemac) on A10 boards Tom Cubie (1): ARM: sunxi: Basic Allwinner A10/A13 (sun4i/sun5i) support hehopmajieh (1): ARM sunxi: SPL support for Olinuxino A13 Micro j (1): ARM sunxi: SPL support for Rikomagic MK802II board MAINTAINERS | 13 + Makefile | 12 + arch/arm/cpu/armv7/Makefile | 2 +- arch/arm/cpu/armv7/sunxi/Makefile | 51 ++ arch/arm/cpu/armv7/sunxi/board.c | 132 ++++++ arch/arm/cpu/armv7/sunxi/clock.c | 171 +++++++ arch/arm/cpu/armv7/sunxi/dram.c | 445 ++++++++++++++++++ arch/arm/cpu/armv7/sunxi/pinmux.c | 61 +++ arch/arm/cpu/armv7/sunxi/reset.S | 39 ++ arch/arm/cpu/armv7/sunxi/timer.c | 117 +++++ arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 63 +++ arch/arm/include/asm/arch-sunxi/clock.h | 179 +++++++ arch/arm/include/asm/arch-sunxi/cpu.h | 146 ++++++ arch/arm/include/asm/arch-sunxi/dram.h | 114 +++++ arch/arm/include/asm/arch-sunxi/gpio.h | 166 +++++++ arch/arm/include/asm/arch-sunxi/i2c.h | 185 ++++++++ arch/arm/include/asm/arch-sunxi/mmc.h | 64 +++ arch/arm/include/asm/arch-sunxi/spl.h | 34 ++ arch/arm/include/asm/arch-sunxi/sys_proto.h | 31 ++ arch/arm/include/asm/arch-sunxi/timer.h | 102 ++++ board/sunxi/Makefile | 58 +++ board/sunxi/board.c | 112 +++++ board/sunxi/dram_a13_mid.c | 31 ++ board/sunxi/dram_a13_oli_micro.c | 32 ++ board/sunxi/dram_a13_olinuxino.c | 31 ++ board/sunxi/dram_cubieboard.c | 31 ++ board/sunxi/dram_cubieboard_512.c | 31 ++ board/sunxi/dram_hackberry.c | 31 ++ board/sunxi/dram_hyundai_a7hd.c | 31 ++ board/sunxi/dram_mele_a1000.c | 24 + board/sunxi/dram_mele_a3700.c | 31 ++ board/sunxi/dram_mini_x.c | 31 ++ board/sunxi/dram_mk802.c | 24 + board/sunxi/dram_mk802ii.c | 31 ++ boards.cfg | 16 + drivers/gpio/Makefile | 1 + drivers/gpio/sunxi_gpio.c | 116 +++++ drivers/i2c/Makefile | 1 + drivers/i2c/sunxi_i2c.c | 278 +++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/sunxi_mmc.c | 674 +++++++++++++++++++++++++++ drivers/net/Makefile | 1 + drivers/net/sunxi_wemac.c | 533 +++++++++++++++++++++ drivers/power/Makefile | 1 + drivers/power/axp209.c | 183 ++++++++ drivers/watchdog/Makefile | 1 + drivers/watchdog/sunxi_watchdog.c | 49 ++ include/axp209.h | 29 ++ include/configs/sun4i.h | 74 +++ include/configs/sun5i.h | 56 +++ include/configs/sunxi-common.h | 243 ++++++++++ include/netdev.h | 1 + spl/Makefile | 10 + tools/.gitignore | 1 + tools/Makefile | 6 + tools/mksunxiboot.README | 13 + tools/mksunxiboot.c | 162 +++++++ 57 files changed, 5105 insertions(+), 1 deletions(-) create mode 100644 arch/arm/cpu/armv7/sunxi/Makefile create mode 100644 arch/arm/cpu/armv7/sunxi/board.c create mode 100644 arch/arm/cpu/armv7/sunxi/clock.c create mode 100644 arch/arm/cpu/armv7/sunxi/dram.c create mode 100644 arch/arm/cpu/armv7/sunxi/pinmux.c create mode 100644 arch/arm/cpu/armv7/sunxi/reset.S create mode 100644 arch/arm/cpu/armv7/sunxi/timer.c create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl.lds create mode 100644 arch/arm/include/asm/arch-sunxi/clock.h create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h create mode 100644 arch/arm/include/asm/arch-sunxi/dram.h create mode 100644 arch/arm/include/asm/arch-sunxi/gpio.h create mode 100644 arch/arm/include/asm/arch-sunxi/i2c.h create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h create mode 100644 arch/arm/include/asm/arch-sunxi/spl.h create mode 100644 arch/arm/include/asm/arch-sunxi/sys_proto.h create mode 100644 arch/arm/include/asm/arch-sunxi/timer.h create mode 100644 board/sunxi/Makefile create mode 100644 board/sunxi/board.c create mode 100644 board/sunxi/dram_a13_mid.c create mode 100644 board/sunxi/dram_a13_oli_micro.c create mode 100644 board/sunxi/dram_a13_olinuxino.c create mode 100644 board/sunxi/dram_cubieboard.c create mode 100644 board/sunxi/dram_cubieboard_512.c create mode 100644 board/sunxi/dram_hackberry.c create mode 100644 board/sunxi/dram_hyundai_a7hd.c create mode 100644 board/sunxi/dram_mele_a1000.c create mode 100644 board/sunxi/dram_mele_a3700.c create mode 100644 board/sunxi/dram_mini_x.c create mode 100644 board/sunxi/dram_mk802.c create mode 100644 board/sunxi/dram_mk802ii.c create mode 100644 drivers/gpio/sunxi_gpio.c create mode 100644 drivers/i2c/sunxi_i2c.c create mode 100644 drivers/mmc/sunxi_mmc.c create mode 100644 drivers/net/sunxi_wemac.c create mode 100644 drivers/power/axp209.c create mode 100644 drivers/watchdog/sunxi_watchdog.c create mode 100644 include/axp209.h create mode 100644 include/configs/sun4i.h create mode 100644 include/configs/sun5i.h create mode 100644 include/configs/sunxi-common.h create mode 100644 tools/mksunxiboot.README create mode 100644 tools/mksunxiboot.c -- 1.7.7.6

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[U-Boot] [PATCH 2/2] Makefile: Accept target names in all lower case to ease matching
by Henrik Nordström 26 Nov '12

26 Nov '12

--- Makefile | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index 1a17be9..5a98745 100644 --- a/Makefile +++ b/Makefile @@ -752,6 +752,7 @@ unconfig: sinclude $(obj).boards.depend $(obj).boards.depend: boards.cfg @awk '(NF && $$1 !~ /^#/) { print $$1 ": " $$1 "_config; $$(MAKE)" }' $< > $@ + @awk '(NF && $$1 !~ /^#/ && tolower($$1) != $$1) { print tolower($$1) ": " $$1 "_config; $$(MAKE)" }' $< > $@ # # Functions to generate common board directory names -- 1.7.7.6

2 4

[U-Boot] [PATCH 06/22] ARM sunxi: Basic GPIO driver
by Henrik Nordström 26 Nov '12

26 Nov '12

GPIO driver for Allwinner sun4i/sun5i family of SoCs GPIO Pins are named by their symbolic pin names P<g><#> such as PH19 or H19. Note: This do not perform any validation if the pin is in use for some other I/O function. Use with care. --- arch/arm/include/asm/arch-sunxi/gpio.h | 2 + drivers/gpio/Makefile | 1 + drivers/gpio/sunxi_gpio.c | 116 ++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 4 + 4 files changed, 123 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/sunxi_gpio.c diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index fceee6b..a3f8a74 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -160,5 +160,7 @@ enum sunxi_gpio_number { int sunxi_gpio_set_cfgpin(u32 pin, u32 val); int sunxi_gpio_get_cfgpin(u32 pin); +int name_to_gpio(const char *name); +#define name_to_gpio name_to_gpio #endif /* _SUNXI_GPIO_H */ diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index d50ac3b..6d692e6 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -45,6 +45,7 @@ COBJS-$(CONFIG_OMAP_GPIO) += omap_gpio.o COBJS-$(CONFIG_DB8500_GPIO) += db8500_gpio.o COBJS-$(CONFIG_BCM2835_GPIO) += bcm2835_gpio.o COBJS-$(CONFIG_S3C2440_GPIO) += s3c2440_gpio.o +COBJS-$(CONFIG_SUNXI_GPIO) += sunxi_gpio.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c new file mode 100644 index 0000000..d99071e --- /dev/null +++ b/drivers/gpio/sunxi_gpio.c @@ -0,0 +1,116 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie <tangliang(a)allwinnertech.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/gpio.h> + +static int sunxi_gpio_output(u32 pin, u32 val) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + + dat = readl(&pio->dat); + if (val) + dat |= 1 << num; + else + dat &= ~(1 << num); + + writel(dat, &pio->dat); + + return 0; +} + +static int sunxi_gpio_input(u32 pin) +{ + u32 dat; + u32 bank = GPIO_BANK(pin); + u32 num = GPIO_NUM(pin); + struct sunxi_gpio *pio = + &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; + + dat = readl(&pio->dat); + dat >>= num; + + return dat & 0x1; +} + +int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +int gpio_free(unsigned gpio) +{ + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT); + + return sunxi_gpio_input(gpio); +} + +int gpio_direction_output(unsigned gpio, int value) +{ + sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT); + + return sunxi_gpio_output(gpio, value); +} + +int gpio_get_value(unsigned gpio) +{ + return sunxi_gpio_input(gpio); +} + +int gpio_set_value(unsigned gpio, int value) +{ + return sunxi_gpio_output(gpio, value); +} + +int name_to_gpio(const char *name) +{ + int group = 0; + int groupsize = 9 * 32; + long pin; + const char *eptr; + if (*name == 'P' || *name == 'p') + name++; + if (*name >= 'A') { + group = *name - (*name > 'a' ? 'a' : 'A'); + groupsize = 32; + name++; + } + + pin = simple_strtol(name, &eptr, 10); + if (!*name || *eptr) + return -1; + if (pin < 0 || pin > groupsize || group >= 9) + return -1; + return group * 32 + pin; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 5bf8eea..bc1f200 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -206,4 +206,8 @@ /* #define CONFIG_WATCHDOG */ /* #define CONFIG_SUNXI_WATCHDOG */ +/* GPIO */ +#define CONFIG_SUNXI_GPIO +#define CONFIG_CMD_GPIO + #endif /* __CONFIG_H */ -- 1.7.7.6

4 5

[U-Boot] [PATCH] ARM v7: Flush icache when executing a program with go
by Henrik Nordström 26 Nov '12

26 Nov '12

ARM v7 runs with icache enabled. For reliable results the go command needs to flush the icache before jumping or it may risk running cached instructions that differ from what currently is in memory. --- arch/arm/cpu/armv7/Makefile | 1 + arch/arm/cpu/armv7/cmd_boot.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/cmd_boot.c diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile index 4fdbee4..da1b5e8 100644 --- a/arch/arm/cpu/armv7/Makefile +++ b/arch/arm/cpu/armv7/Makefile @@ -31,6 +31,7 @@ COBJS += cache_v7.o COBJS += cpu.o COBJS += syslib.o +COBJS += cmd_boot.o ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA20),) SOBJS += lowlevel_init.o diff --git a/arch/arm/cpu/armv7/cmd_boot.c b/arch/arm/cpu/armv7/cmd_boot.c new file mode 100644 index 0000000..6758a55 --- /dev/null +++ b/arch/arm/cpu/armv7/cmd_boot.c @@ -0,0 +1,37 @@ +/* + * (C) Copyright 2000-2003 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Misc boot support + */ +#include <common.h> +#include <command.h> + +#ifdef CONFIG_CMD_GO +unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, + char * const argv[]) +{ + invalidate_icache_all(); + return entry(argc, argv); +} +#endif -- 1.7.7.6

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