October 2012 - U-Boot

[U-Boot] [PATCH v3 2/2] EXYNOS: mmc: support DesignWare Controller for Samsung-SoC
by Jaehoon Chung 22 Nov '12

22 Nov '12

Support DesignWare MMC Controller for Samsung Specific. Signed-off-by: Jaehoon Chung <jh80.chung(a)samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> Signed-off-by: Rajeshawari Shinde <rajeshwari.s(a)samsung.com> --- Changelog V3: - Removed the unnecessary code. Changelog V2: - Nothing --- arch/arm/include/asm/arch-exynos/dwmmc.h | 36 +++++++++++++++++++ drivers/mmc/Makefile | 1 + drivers/mmc/exynos_dw_mmc.c | 57 ++++++++++++++++++++++++++++++ 3 files changed, 94 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-exynos/dwmmc.h create mode 100644 drivers/mmc/exynos_dw_mmc.c diff --git a/arch/arm/include/asm/arch-exynos/dwmmc.h b/arch/arm/include/asm/arch-exynos/dwmmc.h new file mode 100644 index 0000000..8acdf9b --- /dev/null +++ b/arch/arm/include/asm/arch-exynos/dwmmc.h @@ -0,0 +1,36 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung <jh80.chung(a)samsung.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#define DWMCI_CLKSEL 0x09C +#define DWMCI_SHIFT_0 0x0 +#define DWMCI_SHIFT_1 0x1 +#define DWMCI_SHIFT_2 0x2 +#define DWMCI_SHIFT_3 0x3 +#define DWMCI_SET_SAMPLE_CLK(x) (x) +#define DWMCI_SET_DRV_CLK(x) ((x) << 16) +#define DWMCI_SET_DIV_RATIO(x) ((x) << 24) + +int exynos_dwmci_init(u32 regbase, int bus_width, int index); + +static inline unsigned int exynos_dwmmc_init(int index, int bus_width) +{ + unsigned int base = samsung_get_base_mmc() + (0x10000 * index); + return exynos_dwmci_init(base, bus_width, index); +} diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 9ef82a6..cb7c7f6 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -48,6 +48,7 @@ COBJS-$(CONFIG_S5P_SDHCI) += s5p_sdhci.o COBJS-$(CONFIG_SH_MMCIF) += sh_mmcif.o COBJS-$(CONFIG_TEGRA_MMC) += tegra_mmc.o COBJS-$(CONFIG_DWMMC) += dw_mmc.o +COBJS-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/exynos_dw_mmc.c b/drivers/mmc/exynos_dw_mmc.c new file mode 100644 index 0000000..72a31b7 --- /dev/null +++ b/drivers/mmc/exynos_dw_mmc.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2012 SAMSUNG Electronics + * Jaehoon Chung <jh80.chung(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <dwmmc.h> +#include <asm/arch/dwmmc.h> +#include <asm/arch/clk.h> + +static char *EXYNOS_NAME = "EXYNOS DWMMC"; + +static void exynos_dwmci_clksel(struct dwmci_host *host) +{ + u32 val; + val = DWMCI_SET_SAMPLE_CLK(DWMCI_SHIFT_0) | + DWMCI_SET_DRV_CLK(DWMCI_SHIFT_0) | DWMCI_SET_DIV_RATIO(0); + + dwmci_writel(host, DWMCI_CLKSEL, val); +} + +int exynos_dwmci_init(u32 regbase, int bus_width, int index) +{ + struct dwmci_host *host = NULL; + host = malloc(sizeof(struct dwmci_host)); + if (!host) { + printf("dwmci_host malloc fail!\n"); + return 1; + } + + host->name = EXYNOS_NAME; + host->ioaddr = (void *)regbase; + host->buswidth = bus_width; + host->clksel = exynos_dwmci_clksel; + host->dev_index = index; + + add_dwmci(host, 52000000, 400000); + + return 0; +} + -- 1.7.4.1

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[U-Boot] analyze/change assembly code
by Gerlando Falauto 20 Nov '12

20 Nov '12

Hi all, we recently to had face some nasty issues, where for some reason two (functionally identical) versions of some code behave very differently. Namely, one version works and the other doesn't always work. It was clear from the beginning this was because of HW- (or compiler-) related issues. I thought it would then be useful to have a peek at what the compiler is doing behind the scenes, and possibly make some simple changes to the code. For instance, inserting some nops here and there, or reordering some instructions, may help in tracking down these different behaviors. I know the easiest way to LOOK at the file is simply to use objdump to disassemble an .o file. In the end I somehow managed to tamper with the makefiles so to get what I wanted for a given file, by adding a fake new ".s" target with the recipe to build it, and having the .o file depend on a ".S" file (which would be a manual/changed copy of the generated ".s" file) instead of the original ".c" file. This is however not linear and nice at all. So I was wondering whether there already is a well-established way of having the make process create (and keep) assembly files which can be then manually changed. Does my question make any sense at all? Any ideas? Thank you, Gerlando

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[U-Boot] [PATCH 0/4] EXYNOS5: Add GPIO numbering feature
by Rajeshwari Shinde 20 Nov '12

20 Nov '12

This patchset adds GPIO numbering feature where pinmux setting can be done just by seding the pin munber and we do not have to remember which bank it belongs to. Rajeshwari Shinde (4): EXYNOS5: Add GPIO unique pin numbering support S5P: GPIO: Add GPIO pin numbering to driver EXYNOS5: Enable GPIO Numbering. EXYNOS: Update pinmux to use gpio numbering arch/arm/cpu/armv7/exynos/pinmux.c | 150 ++++++-------- arch/arm/include/asm/arch-exynos/gpio.h | 351 +++++++++++++++++++++++++++++++ drivers/gpio/s5p_gpio.c | 158 +++++++++++++- include/configs/smdk5250.h | 3 + 4 files changed, 569 insertions(+), 93 deletions(-) -- 1.7.4.4

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[U-Boot] [PATCH 1/4] mx5: cosmetic: Clean up lowlevel_init
by Benoît Thébaudeau 19 Nov '12

19 Nov '12

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau(a)advansee.com> Cc: Stefano Babic <sbabic(a)denx.de> --- .../arch/arm/cpu/armv7/mx5/lowlevel_init.S | 46 ++++++++++---------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 683a7b5..a40b84f 100644 --- u-boot-4d3c95f.orig/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ u-boot-4d3c95f/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -36,9 +36,9 @@ /* reconfigure L2 cache aux control reg */ mov r0, #0xC0 /* tag RAM */ add r0, r0, #0x4 /* data RAM */ - orr r0, r0, #(1 << 24) /* disable write allocate delay */ - orr r0, r0, #(1 << 23) /* disable write allocate combine */ - orr r0, r0, #(1 << 22) /* disable write allocate */ + orr r0, r0, #1 << 24 /* disable write allocate delay */ + orr r0, r0, #1 << 23 /* disable write allocate combine */ + orr r0, r0, #1 << 22 /* disable write allocate */ #if defined(CONFIG_MX51) ldr r1, =0x0 @@ -46,7 +46,7 @@ cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ - orrls r0, r0, #(1 << 25) + orrls r0, r0, #1 << 25 #endif mcr 15, 1, r0, c9, c0, 2 @@ -247,9 +247,9 @@ movhi r1, #0 #else mov r1, #0 - #endif str r1, [r0, #CLKCTL_CACRR] + /* Switch ARM back to PLL 1 */ mov r1, #0 str r1, [r0, #CLKCTL_CCSR] @@ -288,9 +288,9 @@ /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 - orr r1, r1, #(2 << 10) - orr r1, r1, #(0 << 16) - orr r1, r1, #(1 << 19) + orr r1, r1, #2 << 10 + orr r1, r1, #0 << 16 + orr r1, r1, #1 << 19 str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x00016154 @@ -331,10 +331,10 @@ ENTRY(lowlevel_init) #if defined(CONFIG_MX51) ldr r0, =GPIO1_BASE_ADDR ldr r1, [r0, #0x0] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x0] ldr r1, [r0, #0x4] - orr r1, r1, #(1 << 23) + orr r1, r1, #1 << 23 str r1, [r0, #0x4] #endif @@ -351,16 +351,16 @@ ENTRY(lowlevel_init) ENDPROC(lowlevel_init) /* Board level setting value */ -W_DP_OP_864: .word DP_OP_864 -W_DP_MFD_864: .word DP_MFD_864 -W_DP_MFN_864: .word DP_MFN_864 -W_DP_MFN_800_DIT: .word DP_MFN_800_DIT -W_DP_OP_800: .word DP_OP_800 -W_DP_MFD_800: .word DP_MFD_800 -W_DP_MFN_800: .word DP_MFN_800 -W_DP_OP_665: .word DP_OP_665 -W_DP_MFD_665: .word DP_MFD_665 -W_DP_MFN_665: .word DP_MFN_665 -W_DP_OP_216: .word DP_OP_216 -W_DP_MFD_216: .word DP_MFD_216 -W_DP_MFN_216: .word DP_MFN_216 +W_DP_OP_864: .word DP_OP_864 +W_DP_MFD_864: .word DP_MFD_864 +W_DP_MFN_864: .word DP_MFN_864 +W_DP_MFN_800_DIT: .word DP_MFN_800_DIT +W_DP_OP_800: .word DP_OP_800 +W_DP_MFD_800: .word DP_MFD_800 +W_DP_MFN_800: .word DP_MFN_800 +W_DP_OP_665: .word DP_OP_665 +W_DP_MFD_665: .word DP_MFD_665 +W_DP_MFN_665: .word DP_MFN_665 +W_DP_OP_216: .word DP_OP_216 +W_DP_MFD_216: .word DP_MFD_216 +W_DP_MFN_216: .word DP_MFN_216

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[U-Boot] ping failed; host 192.168.1.101 is not alive
by akdas75 19 Nov '12

19 Nov '12

Hi http://old.nabble.com/file/p34608548/uboot-log.rtf uboot-log.rtf I am using beagle board C4 with zippy expansion board. I am able to do NFS at the kernel level. I want to o tftp at the u-boot level. my beagle board is connected to the host via cross ethernet cable. the phy chip is enc28j60. when i ping the host it says host not alive. i have attached the env variables please help -- View this message in context: http://old.nabble.com/ping-failed--host-192.168.1.101-is-not-alive-tp346085… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] Custodian branch base commits
by Stephen Warren 18 Nov '12

18 Nov '12

The instructions at: http://www.denx.de/wiki/U-Boot/CustodianGitTrees ... indicate that downstream branches should be rebased onto ${upstream}/master immediately prior to sending a pull request. I'm not sure this is correct any more, given that upstream master branches now pull in downstream branches via "git merge" rather than "git rebase". Should that page be changed? The question then becomes: What commit should downstream branches use as their baseline. I assert that they should be free to choose any commit in their upstream master branch (or merge in any upstream commit), or any further upstream branch all the way up to u-boot/master. As background, I want to send a commit to the Tegra tree that enables use of CONFIG_CMD_FS_GENERIC, and additionally, re-write bootcmd in Tegra's default environment to use the new shell commands that config option enables. However, the commits that implement CONFIG_CMD_FS_GENERIC are in u-boot/master but not yet in u-boot-arm/master. So, Tegra's master branch can't simply be based on current u-boot-arm/master, since if it was, applying my patch would break functionality until it was merged with u-boot/master and so picked up the actual implementation. Hopefully, u-boot-arm/master will merge in (or get reset to) u-boot/master fairly shortly. However, should Tegra's repo have to wait for this? Instead, I propose that 2nd-level custodians should be able to do something like: # (in u-boot-tegra.git, assuming everything is merged already) git checkout master git reset --hard u-boot/master git am patch_that_depends_on_uboot_master # send pull request to u-boot-arm/master # (in u-boot-tegra.git, assuming some patches already applied locally) git checkout master git merge u-boot/master git am patch_that_depends_on_uboot_master # send pull request to u-boot-arm/master This should work fine provided that u-boot/master and u-boot-arm/master guarantee never to rebase. If they don't make that guarantee, then I don't think we can be using merges at all anyway, so that shouldn't be an issue. What do people think?

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[U-Boot] [PATCH] nand: Extending the nand_ecclayout struct based on Linux 3.5
by Charles Hardin 16 Nov '12

16 Nov '12

NANDs with large page sizes are getting oob ares of 218 and 224 so the eccpos field needs to support these larger areas since BCH ECC correction with 24-bit over 1024 bytes will use 168 bytes of the oob for ECC and is required for current MLC NAND parts circa 2012. Signed-off-by: Charles Hardin <ckhardin(a)exablox.com> diff --git a/include/linux/mtd/mtd-abi.h b/include/linux/mtd/mtd-abi.h index 1e7a18f..c321d6b 100644 --- a/include/linux/mtd/mtd-abi.h +++ b/include/linux/mtd/mtd-abi.h @@ -116,16 +116,17 @@ struct nand_oobfree { uint32_t length; }; -#define MTD_MAX_OOBFREE_ENTRIES 8 +#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32 +#define MTD_MAX_ECCPOS_ENTRIES_LARGE 448 /* * ECC layout control structure. Exported to userspace for * diagnosis and to allow creation of raw images */ struct nand_ecclayout { uint32_t eccbytes; - uint32_t eccpos[128]; + uint32_t eccpos[MTD_MAX_ECCPOS_ENTRIES_LARGE]; uint32_t oobavail; - struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES]; + struct nand_oobfree oobfree[MTD_MAX_OOBFREE_ENTRIES_LARGE]; }; /**

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[U-Boot] [PATCH] driver/mtd:IFC NAND:Initialise internal SRAM before any write
by Prabhakar Kushwaha 16 Nov '12

16 Nov '12

IFC-1.1.0 uses 28nm techenology for SRAM. This tech has known limitaion for SRAM i.e. "byte select" is not supported. Hence Read Modify Write is implemented in IFC for any "system side write" into sram buffer. Reading an uninitialized memory results in ECC Error from sram wrapper. Hence we must initialize/prefill SRAM buffer by any data before writing anything in SRAM from system side. To initialize SRAM user can use "READID" NAND command with read bytes equal to SRAM size. It will be a one time activity post boot Signed-off-by: Prabhakar Kushwaha <prabhakar(a)freescale.com> --- Based upon git://git.denx.de/u-boot.git (branch master) This patchs depends upon following patch http://patchwork.ozlabs.org/patch/178332/ drivers/mtd/nand/fsl_ifc_nand.c | 62 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c index a518526..140fdc7 100644 --- a/drivers/mtd/nand/fsl_ifc_nand.c +++ b/drivers/mtd/nand/fsl_ifc_nand.c @@ -30,6 +30,7 @@ #include <asm/errno.h> #include <asm/fsl_ifc.h> +#define FSL_IFC_V1_1_0 0x01010000 #define MAX_BANKS 4 #define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ @@ -738,11 +739,66 @@ static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip) { } +static void fsl_ifc_sram_init() +{ + struct fsl_ifc *ifc = ifc_ctrl->regs; + uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0; + long long end_tick; + + cs = ifc_ctrl->cs_nand >> IFC_NAND_CSEL_SHIFT; + + /* Save CSOR and CSOR_ext */ + csor = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor); + csor_ext = in_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext); + + /* chage PageSize 8K and SpareSize 1K*/ + csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000; + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor_8k); + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, 0x0000400); + + /* READID */ + out_be32(&ifc->ifc_nand.nand_fir0, + (IFC_FIR_OP_CMD0 << IFC_NAND_FIR0_OP0_SHIFT) | + (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) | + (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT)); + out_be32(&ifc->ifc_nand.nand_fcr0, + NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT); + out_be32(&ifc->ifc_nand.row3, 0x0); + + out_be32(&ifc->ifc_nand.nand_fbcr, 0x0); + + /* Program ROW0/COL0 */ + out_be32(&ifc->ifc_nand.row0, 0x0); + out_be32(&ifc->ifc_nand.col0, 0x0); + + /* set the chip select for NAND Transaction */ + out_be32(&ifc->ifc_nand.nand_csel, ifc_ctrl->cs_nand); + + /* start read seq */ + out_be32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT); + + /* wait for NAND Machine complete flag or timeout */ + end_tick = usec2ticks(IFC_TIMEOUT_MSECS * 1000) + get_ticks(); + + while (end_tick > get_ticks()) { + ifc_ctrl->status = in_be32(&ifc->ifc_nand.nand_evter_stat); + + if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC) + break; + } + + out_be32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status); + + /* Restore CSOR and CSOR_ext */ + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor, csor); + out_be32(&ifc_ctrl->regs->csor_cs[cs].csor_ext, csor_ext); +} + int board_nand_init(struct nand_chip *nand) { struct fsl_ifc_mtd *priv; struct nand_ecclayout *layout; - uint32_t cspr = 0, csor = 0; + uint32_t cspr = 0, csor = 0, ver = 0; if (!ifc_ctrl) { fsl_ifc_ctrl_init(); @@ -860,5 +916,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.mode = NAND_ECC_SOFT; } + ver = in_be32(&ifc_ctrl->regs->ifc_rev); + if (ver == FSL_IFC_V1_1_0) + fsl_ifc_sram_init(); + return 0; } -- 1.7.9.5

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[U-Boot] [PATCH] cosmetic: Reference nand monitor commands in U-Boot README
by Karl O. Pinc 15 Nov '12

15 Nov '12

Signed-off-by: Karl O. Pinc <kop(a)meme.com> --- README | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/README b/README index fb9d904..6bb5992 100644 --- a/README +++ b/README @@ -3725,6 +3725,7 @@ saveenv - save environment variables to persistent storage protect - enable or disable FLASH write protection erase - erase FLASH memory flinfo - print FLASH memory information +nand - NAND memory operations (see doc/README.nand) bdinfo - print Board Info structure iminfo - print header information for application image coninfo - print console devices and informations -- 1.7.2.5

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[U-Boot] [PATCH 2/2] usb: r8a66597: Switched from variable to only macro
by Nobuhiro Iwamatsu 15 Nov '12

15 Nov '12

Some variables are initialized with a value defined by macro. This was changed to use the macro directly. And the variable not to use deleted it. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> --- drivers/usb/host/r8a66597-hcd.c | 15 +++++---------- 1 files changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index ab1b8d0..f5a7e30 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c @@ -31,9 +31,6 @@ #endif static const char hcd_name[] = "r8a66597_hcd"; -static unsigned short clock = CONFIG_R8A66597_XTAL; -static unsigned short vif = CONFIG_R8A66597_LDRV; -static unsigned short endian = CONFIG_R8A66597_ENDIAN; static struct r8a66597 gr8a66597; static void get_hub_data(struct usb_device *dev, u16 *hub_devnum, u16 *hubport) @@ -96,7 +93,7 @@ static int r8a66597_clock_enable(struct r8a66597 *r8a66597) } } while ((tmp & USBE) != USBE); r8a66597_bclr(r8a66597, USBE, SYSCFG0); - r8a66597_mdfy(r8a66597, clock, XTAL, SYSCFG0); + r8a66597_mdfy(r8a66597, CONFIG_R8A66597_XTAL, XTAL, SYSCFG0); i = 0; r8a66597_bset(r8a66597, XCKE, SYSCFG0); @@ -162,7 +159,7 @@ static int enable_controller(struct r8a66597 *r8a66597) if (ret < 0) return ret; - r8a66597_bset(r8a66597, vif & LDRV, PINCFG); + r8a66597_bset(r8a66597, CONFIG_R8A66597_LDRV & LDRV, PINCFG); r8a66597_bset(r8a66597, USBE, SYSCFG0); r8a66597_bset(r8a66597, INTL, SOFCFG); @@ -170,9 +167,9 @@ static int enable_controller(struct r8a66597 *r8a66597) r8a66597_write(r8a66597, 0, INTENB1); r8a66597_write(r8a66597, 0, INTENB2); - r8a66597_bset(r8a66597, endian & BIGEND, CFIFOSEL); - r8a66597_bset(r8a66597, endian & BIGEND, D0FIFOSEL); - r8a66597_bset(r8a66597, endian & BIGEND, D1FIFOSEL); + r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, CFIFOSEL); + r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D0FIFOSEL); + r8a66597_bset(r8a66597, CONFIG_R8A66597_ENDIAN & BIGEND, D1FIFOSEL); r8a66597_bset(r8a66597, TRNENSEL, SOFCFG); for (port = 0; port < R8A66597_MAX_ROOT_HUB; port++) @@ -673,7 +670,6 @@ static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, int stat = 0; __u16 bmRType_bReq; __u16 wValue; - __u16 wIndex; __u16 wLength; unsigned char data[32]; @@ -686,7 +682,6 @@ static int r8a66597_submit_rh_msg(struct usb_device *dev, unsigned long pipe, bmRType_bReq = cmd->requesttype | (cmd->request << 8); wValue = cpu_to_le16 (cmd->value); - wIndex = cpu_to_le16 (cmd->index); wLength = cpu_to_le16 (cmd->length); switch (bmRType_bReq) { -- 1.7.9.1

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