January 2012 - U-Boot

[U-Boot] building tools/env
by Steve DeLaney 24 Jul '12

24 Jul '12

hi there, I'm attempting to build u-boot 1.1.1 tools/env and the build is failed. Any ideas on best way to enable it in the build. Here's what I did so far first, update tools/Makefile TOOLSUBDIRS = env then top level build make clobber mrproper make octeon_cn3010_evb_hs5_config make all the build in tools/env fails due to missing include files linux/mtd/mtd.h zlib.h add to tools/env/Makefile CPPFLAGS += ../../include and include CPPFLAGS here: fw_printenv : $(SOURCES) $(HEADERS) $(CROSS_COMPILE)gcc -Wall $(CPPFLAGS) -DUSE_HOSTCC $(SOURCES) -o fw_printenv but this leads to build error on definitions of uint32_t, phys_addr_t and erase_info_t Any ideas on preferred way to build tools/env? thanks in advance!

4 3

[U-Boot] [PATCH 1/2] NET: NE2000: Cleanup IO accessors
by Marek Vasut 13 Jul '12

13 Jul '12

Introduce ne2k_register_io(in, out), which allows user to supply two functions. One for reading data from the card, the other for writing data to the card. Then introduce drivers' private data, which carry pointers to these functions and are passed throughout the driver. The private data will carry more entries later. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- drivers/net/ne2000_base.c | 318 +++++++++++++++++++++++++++------------------ include/netdev.h | 2 + 2 files changed, 191 insertions(+), 129 deletions(-) NOTE: Formating not cleaned up, only relevant change made! diff --git a/drivers/net/ne2000_base.c b/drivers/net/ne2000_base.c index 88f2b37..35a8581 100644 --- a/drivers/net/ne2000_base.c +++ b/drivers/net/ne2000_base.c @@ -76,10 +76,7 @@ Add SNMP #include <command.h> #include <net.h> #include <malloc.h> - -/* forward definition of function used for the uboot interface */ -void uboot_push_packet_len(int len); -void uboot_push_tx_done(int key, int val); +#include <errno.h> /* NE2000 base header file */ #include "ne2000_base.h" @@ -94,12 +91,37 @@ void uboot_push_tx_done(int key, int val); static dp83902a_priv_data_t nic; /* just one instance of the card supported */ +uint32_t ne2k_default_in(uint8_t *addr, uint32_t offset) +{ + uint32_t ret; + DP_IN(addr, offset, ret); + return ret; +} + +void ne2k_default_out(uint8_t *addr, uint32_t offset, uint32_t val) +{ + DP_OUT(addr, offset, val); +} + +struct ne2k_io_accessors { + uint32_t (*in)(uint8_t *addr, uint32_t offset); + void (*out)(uint8_t *addr, uint32_t offset, uint32_t val); +}; + +struct ne2k_private_data { + struct ne2k_io_accessors io; +}; + +/* forward definition of function used for the uboot interface */ +void uboot_push_packet_len(struct ne2k_private_data *pdata, int len); +void uboot_push_tx_done(int key, int val); + /** * This function reads the MAC address from the serial EEPROM, * used if PROM read fails. Does nothing for ax88796 chips (sh boards) */ static bool -dp83902a_init(unsigned char *enetaddr) +dp83902a_init(struct eth_device *dev) { dp83902a_priv_data_t *dp = &nic; u8* base; @@ -116,13 +138,17 @@ dp83902a_init(unsigned char *enetaddr) DEBUG_LINE(); #if defined(NE2000_BASIC_INIT) + unsigned char *enetaddr = dev->enetaddr; + struct ne2k_private_data *pdata = dev->priv; + const struct ne2k_io_accessors *io = &pdata->io; + /* AX88796L doesn't need */ /* Prepare ESA */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ + io->out(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1); /* Select page 1 */ /* Use the address from the serial EEPROM */ for (i = 0; i < 6; i++) - DP_IN(base, DP_P1_PAR0+i, dp->esa[i]); - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ + dp->esa[i] = io->in(base, DP_P1_PAR0+i); + io->out(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0); /* Select page 0 */ printf("NE2000 - %s ESA: %02x:%02x:%02x:%02x:%02x:%02x\n", "eeprom", @@ -139,16 +165,18 @@ dp83902a_init(unsigned char *enetaddr) } static void -dp83902a_stop(void) +dp83902a_stop(struct eth_device *dev) { dp83902a_priv_data_t *dp = &nic; + struct ne2k_private_data *pdata = dev->priv; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; DEBUG_FUNCTION(); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ - DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ - DP_OUT(base, DP_IMR, 0x00); /* Disable all interrupts */ + io->out(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + io->out(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + io->out(base, DP_IMR, 0x00); /* Disable all interrupts */ dp->running = false; } @@ -160,9 +188,12 @@ dp83902a_stop(void) * the hardware ready to send/receive packets. */ static void -dp83902a_start(u8 * enaddr) +dp83902a_start(struct eth_device *dev) { dp83902a_priv_data_t *dp = &nic; + unsigned char *enaddr = dev->enetaddr; + struct ne2k_private_data *pdata = dev->priv; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; int i; @@ -170,37 +201,37 @@ dp83902a_start(u8 * enaddr) DEBUG_FUNCTION(); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ - DP_OUT(base, DP_DCR, DP_DCR_INIT); - DP_OUT(base, DP_RBCH, 0); /* Remote byte count */ - DP_OUT(base, DP_RBCL, 0); - DP_OUT(base, DP_RCR, DP_RCR_MON); /* Accept no packets */ - DP_OUT(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */ - DP_OUT(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */ + io->out(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_STOP); /* Brutal */ + io->out(base, DP_DCR, DP_DCR_INIT); + io->out(base, DP_RBCH, 0); /* Remote byte count */ + io->out(base, DP_RBCL, 0); + io->out(base, DP_RCR, DP_RCR_MON); /* Accept no packets */ + io->out(base, DP_TCR, DP_TCR_LOCAL); /* Transmitter [virtually] off */ + io->out(base, DP_TPSR, dp->tx_buf1); /* Transmitter start page */ dp->tx1 = dp->tx2 = 0; dp->tx_next = dp->tx_buf1; dp->tx_started = false; dp->running = true; - DP_OUT(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ - DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */ - DP_OUT(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ + io->out(base, DP_PSTART, dp->rx_buf_start); /* Receive ring start page */ + io->out(base, DP_BNDRY, dp->rx_buf_end - 1); /* Receive ring boundary */ + io->out(base, DP_PSTOP, dp->rx_buf_end); /* Receive ring end page */ dp->rx_next = dp->rx_buf_start - 1; dp->running = true; - DP_OUT(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ - DP_OUT(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ - DP_OUT(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ + io->out(base, DP_ISR, 0xFF); /* Clear any pending interrupts */ + io->out(base, DP_IMR, DP_IMR_All); /* Enable all interrupts */ + io->out(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE1 | DP_CR_STOP); /* Select page 1 */ + io->out(base, DP_P1_CURP, dp->rx_buf_start); /* Current page - next free page for Rx */ dp->running = true; for (i = 0; i < ETHER_ADDR_LEN; i++) { /* FIXME */ /*((vu_short*)( base + ((DP_P1_PAR0 + i) * 2) + * 0x1400)) = enaddr[i];*/ - DP_OUT(base, DP_P1_PAR0+i, enaddr[i]); + io->out(base, DP_P1_PAR0+i, enaddr[i]); } /* Enable and start device */ - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_OUT(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ - DP_OUT(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ + io->out(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + io->out(base, DP_TCR, DP_TCR_NORMAL); /* Normal transmit operations */ + io->out(base, DP_RCR, DP_RCR_AB); /* Accept broadcast, no errors, no multicast */ dp->running = true; } @@ -211,9 +242,10 @@ dp83902a_start(u8 * enaddr) */ static void -dp83902a_start_xmit(int start_page, int len) +dp83902a_start_xmit(struct ne2k_private_data *pdata, int start_page, int len) { dp83902a_priv_data_t *dp = (dp83902a_priv_data_t *) &nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; DEBUG_FUNCTION(); @@ -224,12 +256,12 @@ dp83902a_start_xmit(int start_page, int len) printf("TX already started?!?\n"); #endif - DP_OUT(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE)); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_OUT(base, DP_TBCL, len & 0xFF); - DP_OUT(base, DP_TBCH, len >> 8); - DP_OUT(base, DP_TPSR, start_page); - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + io->out(base, DP_ISR, (DP_ISR_TxP | DP_ISR_TxE)); + io->out(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + io->out(base, DP_TBCL, len & 0xFF); + io->out(base, DP_TBCH, len >> 8); + io->out(base, DP_TPSR, start_page); + io->out(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); dp->tx_started = true; } @@ -239,9 +271,10 @@ dp83902a_start_xmit(int start_page, int len) * that there is free buffer space (dp->tx_next). */ static void -dp83902a_send(u8 *data, int total_len, u32 key) +dp83902a_send(struct ne2k_private_data *pdata, u8 *data, int total_len, u32 key) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; int len, start_page, pkt_len, i, isr; #if DEBUG & 4 @@ -271,7 +304,7 @@ dp83902a_send(u8 *data, int total_len, u32 key) printf("TX prep page %d len %d\n", start_page, pkt_len); #endif - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + io->out(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ { /* * Dummy read. The manual sez something slightly different, @@ -279,15 +312,14 @@ dp83902a_send(u8 *data, int total_len, u32 key) * does (i.e., also read data). */ - u16 tmp; int len = 1; - DP_OUT(base, DP_RSAL, 0x100 - len); - DP_OUT(base, DP_RSAH, (start_page - 1) & 0xff); - DP_OUT(base, DP_RBCL, len); - DP_OUT(base, DP_RBCH, 0); - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); - DP_IN_DATA(dp->data, tmp); + io->out(base, DP_RSAL, 0x100 - len); + io->out(base, DP_RSAH, (start_page - 1) & 0xff); + io->out(base, DP_RBCL, len); + io->out(base, DP_RBCH, 0); + io->out(base, DP_CR, DP_CR_PAGE0 | DP_CR_RDMA | DP_CR_START); + io->in(dp->data, 0); } #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_TX_DMA @@ -299,11 +331,11 @@ dp83902a_send(u8 *data, int total_len, u32 key) #endif /* Send data to device buffer(s) */ - DP_OUT(base, DP_RSAL, 0); - DP_OUT(base, DP_RSAH, start_page); - DP_OUT(base, DP_RBCL, pkt_len & 0xFF); - DP_OUT(base, DP_RBCH, pkt_len >> 8); - DP_OUT(base, DP_CR, DP_CR_WDMA | DP_CR_START); + io->out(base, DP_RSAL, 0); + io->out(base, DP_RSAH, start_page); + io->out(base, DP_RBCL, pkt_len & 0xFF); + io->out(base, DP_RBCH, pkt_len >> 8); + io->out(base, DP_CR, DP_CR_WDMA | DP_CR_START); /* Put data into buffer */ #if DEBUG & 4 @@ -316,7 +348,7 @@ dp83902a_send(u8 *data, int total_len, u32 key) if (0 == (++dx % 16)) printf("\n "); #endif - DP_OUT_DATA(dp->data, *data++); + io->out(dp->data, 0, *data++); len--; } #if DEBUG & 4 @@ -329,7 +361,7 @@ dp83902a_send(u8 *data, int total_len, u32 key) /* Padding to 802.3 length was required */ for (i = total_len; i < pkt_len;) { i++; - DP_OUT_DATA(dp->data, 0); + io->out(dp->data, 0, 0); } } @@ -344,11 +376,11 @@ dp83902a_send(u8 *data, int total_len, u32 key) /* Wait for DMA to complete */ do { - DP_IN(base, DP_ISR, isr); + isr = io->in(base, DP_ISR); } while ((isr & DP_ISR_RDC) == 0); /* Then disable DMA */ - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + io->out(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); /* Start transmit if not already going */ if (!dp->tx_started) { @@ -357,7 +389,7 @@ dp83902a_send(u8 *data, int total_len, u32 key) } else { dp->tx_int = 2; /* Expecting interrupt from BUF2 */ } - dp83902a_start_xmit(start_page, pkt_len); + dp83902a_start_xmit(pdata, start_page, pkt_len); } } @@ -369,23 +401,23 @@ dp83902a_send(u8 *data, int total_len, u32 key) * 'dp83902a_recv' will be called to actually fetch it from the hardware. */ static void -dp83902a_RxEvent(void) +dp83902a_RxEvent(struct ne2k_private_data *pdata) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; - u8 rsr; u8 rcv_hdr[4]; int i, len, pkt, cur; DEBUG_FUNCTION(); - DP_IN(base, DP_RSR, rsr); + io->in(base, DP_RSR); while (true) { /* Read incoming packet header */ - DP_OUT(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START); - DP_IN(base, DP_P1_CURP, cur); - DP_OUT(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_IN(base, DP_BNDRY, pkt); + io->out(base, DP_CR, DP_CR_PAGE1 | DP_CR_NODMA | DP_CR_START); + cur = io->in(base, DP_P1_CURP); + io->out(base, DP_P1_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + pkt = io->in(base, DP_BNDRY); pkt += 1; if (pkt == dp->rx_buf_end) @@ -394,27 +426,27 @@ dp83902a_RxEvent(void) if (pkt == cur) { break; } - DP_OUT(base, DP_RBCL, sizeof(rcv_hdr)); - DP_OUT(base, DP_RBCH, 0); - DP_OUT(base, DP_RSAL, 0); - DP_OUT(base, DP_RSAH, pkt); + io->out(base, DP_RBCL, sizeof(rcv_hdr)); + io->out(base, DP_RBCH, 0); + io->out(base, DP_RSAL, 0); + io->out(base, DP_RSAH, pkt); if (dp->rx_next == pkt) { if (cur == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); + io->out(base, DP_BNDRY, dp->rx_buf_end - 1); else - DP_OUT(base, DP_BNDRY, cur - 1); /* Update pointer */ + io->out(base, DP_BNDRY, cur - 1); /* Update pointer */ return; } dp->rx_next = pkt; - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ - DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); + io->out(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + io->out(base, DP_CR, DP_CR_RDMA | DP_CR_START); #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA CYGACC_CALL_IF_DELAY_US(10); #endif /* read header (get data size)*/ for (i = 0; i < sizeof(rcv_hdr);) { - DP_IN_DATA(dp->data, rcv_hdr[i++]); + rcv_hdr[i++] = io->in(dp->data, 0); } #if DEBUG & 5 @@ -424,12 +456,12 @@ dp83902a_RxEvent(void) len = ((rcv_hdr[3] << 8) | rcv_hdr[2]) - sizeof(rcv_hdr); /* data read */ - uboot_push_packet_len(len); + uboot_push_packet_len(pdata, len); if (rcv_hdr[1] == dp->rx_buf_start) - DP_OUT(base, DP_BNDRY, dp->rx_buf_end - 1); + io->out(base, DP_BNDRY, dp->rx_buf_end - 1); else - DP_OUT(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */ + io->out(base, DP_BNDRY, rcv_hdr[1] - 1); /* Update pointer */ } } @@ -441,9 +473,10 @@ dp83902a_RxEvent(void) * efficient processing in the upper layers of the stack. */ static void -dp83902a_recv(u8 *data, int len) +dp83902a_recv(struct ne2k_private_data *pdata, u8 *data, int len) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; int i, mlen; u8 saved_char = 0; @@ -459,13 +492,13 @@ dp83902a_recv(u8 *data, int len) #endif /* Read incoming packet data */ - DP_OUT(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); - DP_OUT(base, DP_RBCL, len & 0xFF); - DP_OUT(base, DP_RBCH, len >> 8); - DP_OUT(base, DP_RSAL, 4); /* Past header */ - DP_OUT(base, DP_RSAH, dp->rx_next); - DP_OUT(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ - DP_OUT(base, DP_CR, DP_CR_RDMA | DP_CR_START); + io->out(base, DP_CR, DP_CR_PAGE0 | DP_CR_NODMA | DP_CR_START); + io->out(base, DP_RBCL, len & 0xFF); + io->out(base, DP_RBCH, len >> 8); + io->out(base, DP_RSAL, 4); /* Past header */ + io->out(base, DP_RSAH, dp->rx_next); + io->out(base, DP_ISR, DP_ISR_RDC); /* Clear end of DMA */ + io->out(base, DP_CR, DP_CR_RDMA | DP_CR_START); #ifdef CYGHWR_NS_DP83902A_PLF_BROKEN_RX_DMA CYGACC_CALL_IF_DELAY_US(10); #endif @@ -489,7 +522,7 @@ dp83902a_recv(u8 *data, int len) { u8 tmp; - DP_IN_DATA(dp->data, tmp); + tmp = io->in(dp->data, 0); #if DEBUG & 4 printf(" %02x", tmp); if (0 == (++dx % 16)) printf("\n "); @@ -506,16 +539,16 @@ dp83902a_recv(u8 *data, int len) } static void -dp83902a_TxEvent(void) +dp83902a_TxEvent(struct ne2k_private_data *pdata) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; - u8 tsr; u32 key; DEBUG_FUNCTION(); - DP_IN(base, DP_TSR, tsr); + io->in(base, DP_TSR); if (dp->tx_int == 1) { key = dp->tx1_key; dp->tx1 = 0; @@ -526,10 +559,10 @@ dp83902a_TxEvent(void) /* Start next packet if one is ready */ dp->tx_started = false; if (dp->tx1) { - dp83902a_start_xmit(dp->tx1, dp->tx1_len); + dp83902a_start_xmit(pdata, dp->tx1, dp->tx1_len); dp->tx_int = 1; } else if (dp->tx2) { - dp83902a_start_xmit(dp->tx2, dp->tx2_len); + dp83902a_start_xmit(pdata, dp->tx2, dp->tx2_len); dp->tx_int = 2; } else { dp->tx_int = 0; @@ -543,16 +576,16 @@ dp83902a_TxEvent(void) * interrupt. */ static void -dp83902a_ClearCounters(void) +dp83902a_ClearCounters(struct ne2k_private_data *pdata) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; - u8 cnt1, cnt2, cnt3; - DP_IN(base, DP_FER, cnt1); - DP_IN(base, DP_CER, cnt2); - DP_IN(base, DP_MISSED, cnt3); - DP_OUT(base, DP_ISR, DP_ISR_CNT); + io->in(base, DP_FER); + io->in(base, DP_CER); + io->in(base, DP_MISSED); + io->out(base, DP_ISR, DP_ISR_CNT); } /* @@ -560,55 +593,57 @@ dp83902a_ClearCounters(void) * out in section 7.0 of the datasheet. */ static void -dp83902a_Overflow(void) +dp83902a_Overflow(struct ne2k_private_data *pdata) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *)&nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; u8 isr; /* Issue a stop command and wait 1.6ms for it to complete. */ - DP_OUT(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); + io->out(base, DP_CR, DP_CR_STOP | DP_CR_NODMA); CYGACC_CALL_IF_DELAY_US(1600); /* Clear the remote byte counter registers. */ - DP_OUT(base, DP_RBCL, 0); - DP_OUT(base, DP_RBCH, 0); + io->out(base, DP_RBCL, 0); + io->out(base, DP_RBCH, 0); /* Enter loopback mode while we clear the buffer. */ - DP_OUT(base, DP_TCR, DP_TCR_LOCAL); - DP_OUT(base, DP_CR, DP_CR_START | DP_CR_NODMA); + io->out(base, DP_TCR, DP_TCR_LOCAL); + io->out(base, DP_CR, DP_CR_START | DP_CR_NODMA); /* * Read in as many packets as we can and acknowledge any and receive * interrupts. Since the buffer has overflowed, a receive event of * some kind will have occured. */ - dp83902a_RxEvent(); - DP_OUT(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); + dp83902a_RxEvent(pdata); + io->out(base, DP_ISR, DP_ISR_RxP|DP_ISR_RxE); /* Clear the overflow condition and leave loopback mode. */ - DP_OUT(base, DP_ISR, DP_ISR_OFLW); - DP_OUT(base, DP_TCR, DP_TCR_NORMAL); + io->out(base, DP_ISR, DP_ISR_OFLW); + io->out(base, DP_TCR, DP_TCR_NORMAL); /* * If a transmit command was issued, but no transmit event has occured, * restart it here. */ - DP_IN(base, DP_ISR, isr); + isr = io->in(base, DP_ISR); if (dp->tx_started && !(isr & (DP_ISR_TxP|DP_ISR_TxE))) { - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); + io->out(base, DP_CR, DP_CR_NODMA | DP_CR_TXPKT | DP_CR_START); } } static void -dp83902a_poll(void) +dp83902a_poll(struct ne2k_private_data *pdata) { struct dp83902a_priv_data *dp = (struct dp83902a_priv_data *) &nic; + const struct ne2k_io_accessors *io = &pdata->io; u8 *base = dp->base; u8 isr; - DP_OUT(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); - DP_IN(base, DP_ISR, isr); + io->out(base, DP_CR, DP_CR_NODMA | DP_CR_PAGE0 | DP_CR_START); + isr = io->in(base, DP_ISR); while (0 != isr) { /* * The CNT interrupt triggers when the MSB of one of the error @@ -616,7 +651,7 @@ dp83902a_poll(void) * we should read their values to reset them. */ if (isr & DP_ISR_CNT) { - dp83902a_ClearCounters(); + dp83902a_ClearCounters(pdata); } /* * Check for overflow. It's a special case, since there's a @@ -624,27 +659,27 @@ dp83902a_poll(void) * a running state.a */ if (isr & DP_ISR_OFLW) { - dp83902a_Overflow(); + dp83902a_Overflow(pdata); } else { /* * Other kinds of interrupts can be acknowledged simply by * clearing the relevant bits of the ISR. Do that now, then * handle the interrupts we care about. */ - DP_OUT(base, DP_ISR, isr); /* Clear set bits */ + io->out(base, DP_ISR, isr); /* Clear set bits */ if (!dp->running) break; /* Is this necessary? */ /* * Check for tx_started on TX event since these may happen * spuriously it seems. */ if (isr & (DP_ISR_TxP|DP_ISR_TxE) && dp->tx_started) { - dp83902a_TxEvent(); + dp83902a_TxEvent(pdata); } if (isr & (DP_ISR_RxP|DP_ISR_RxE)) { - dp83902a_RxEvent(); + dp83902a_RxEvent(pdata); } } - DP_IN(base, DP_ISR, isr); + isr = io->in(base, DP_ISR); } } @@ -655,13 +690,13 @@ static u8 *pbuf = NULL; static int pkey = -1; static int initialized = 0; -void uboot_push_packet_len(int len) { +void uboot_push_packet_len(struct ne2k_private_data *pdata, int len) { PRINTK("pushed len = %d\n", len); if (len >= 2000) { printf("NE2000: packet too big\n"); return; } - dp83902a_recv(&pbuf[0], len); + dp83902a_recv(pdata, &pbuf[0], len); /*Just pass it to the upper layer*/ NetReceive(&pbuf[0], len); @@ -717,7 +752,7 @@ static int ne2k_setup_driver(struct eth_device *dev) if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) { /* If the MAC address is not in the environment, get it: */ if (!get_prom(dev->enetaddr, nic.base)) /* get MAC from prom */ - dp83902a_init(dev->enetaddr); /* fallback: seeprom */ + dp83902a_init(dev); /* fallback: seeprom */ /* And write it into the environment otherwise eth_write_hwaddr * returns -1 due to eth_getenv_enetaddr_by_index() failing, * and this causes "Warning: failed to set MAC address", and @@ -729,7 +764,7 @@ static int ne2k_setup_driver(struct eth_device *dev) static int ne2k_init(struct eth_device *dev, bd_t *bd) { - dp83902a_start(dev->enetaddr); + dp83902a_start(dev); initialized = 1; return 0; } @@ -738,28 +773,30 @@ static void ne2k_halt(struct eth_device *dev) { debug("### ne2k_halt\n"); if(initialized) - dp83902a_stop(); + dp83902a_stop(dev); initialized = 0; } static int ne2k_recv(struct eth_device *dev) { - dp83902a_poll(); + struct ne2k_private_data *pdata = dev->priv; + dp83902a_poll(pdata); return 1; } static int ne2k_send(struct eth_device *dev, volatile void *packet, int length) { int tmo; + struct ne2k_private_data *pdata = dev->priv; debug("### ne2k_send\n"); pkey = -1; - dp83902a_send((u8 *) packet, length, 666); + dp83902a_send(pdata, (u8 *) packet, length, 666); tmo = get_timer (0) + TOUT * CONFIG_SYS_HZ; while(1) { - dp83902a_poll(); + dp83902a_poll(pdata); if (pkey != -1) { PRINTK("Packet sucesfully sent\n"); return 0; @@ -775,25 +812,48 @@ static int ne2k_send(struct eth_device *dev, volatile void *packet, int length) /** * Setup the driver for use and register it with the eth layer - * @return 0 on success, -1 on error (causing caller to print error msg) + * @return 0 on success, < 0 on error (causing caller to print error msg) */ -int ne2k_register(void) +int ne2k_register_io(uint32_t (*in)(uint8_t *addr, uint32_t offset), + void (*out)(uint8_t *addr, uint32_t offset, uint32_t value)) { struct eth_device *dev; + struct ne2k_private_data *pdata; dev = calloc(sizeof(*dev), 1); if (dev == NULL) - return -1; + return -ENOMEM; + + pdata = calloc(sizeof(struct ne2k_private_data), 1); + if (pdata == NULL) { + free(dev); + return -ENOMEM; + } if (ne2k_setup_driver(dev)) - return -1; + return -EINVAL; + + if (in == NULL) + in = ne2k_default_in; + + if (out == NULL) + out = ne2k_default_out; + + pdata->io.in = in; + pdata->io.out = out; dev->init = ne2k_init; dev->halt = ne2k_halt; dev->send = ne2k_send; dev->recv = ne2k_recv; + dev->priv = pdata; sprintf(dev->name, "NE2000"); return eth_register(dev); } + +int ne2k_register(void) +{ + return ne2k_register_io(NULL, NULL); +} diff --git a/include/netdev.h b/include/netdev.h index 150fa8e..7ea4642 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -81,6 +81,8 @@ int mpc82xx_scc_enet_initialize(bd_t *bis); int mvgbe_initialize(bd_t *bis); int natsemi_initialize(bd_t *bis); int ne2k_register(void); +int ne2k_register_io(uint32_t (*in)(uint8_t *addr, uint32_t offset), + void (*out)(uint8_t *addr, uint32_t offset, uint32_t value)); int npe_initialize(bd_t *bis); int ns8382x_initialize(bd_t *bis); int pcnet_initialize(bd_t *bis); -- 1.7.7.1

3 11

[U-Boot] [PATCH] pxe: get ethaddr from the current device instead of env
by Rob Herring 11 Jul '12

11 Jul '12

From: Rob Herring <rob.herring(a)calxeda.com> The env variable "ethaddr" may not be set, so get the address from the eth_device struct instead. This also enables pxe for secondary ethernet devices. Signed-off-by: Rob Herring <rob.herring(a)calxeda.com> --- common/cmd_pxe.c | 31 ++++++++++++------------------- 1 files changed, 12 insertions(+), 19 deletions(-) diff --git a/common/cmd_pxe.c b/common/cmd_pxe.c index 3efd700..f14ef89 100644 --- a/common/cmd_pxe.c +++ b/common/cmd_pxe.c @@ -56,38 +56,31 @@ static char *from_env(char *envvar) */ static int format_mac_pxe(char *outbuf, size_t outbuf_len) { - size_t ethaddr_len; - char *p, *ethaddr; - - ethaddr = from_env("ethaddr"); - - if (!ethaddr) - return -ENOENT; - - ethaddr_len = strlen(ethaddr); + char *p; + struct eth_device *dev; /* * ethaddr_len + 4 gives room for "01-", ethaddr, and a NUL byte at * the end. */ - if (outbuf_len < ethaddr_len + 4) { - printf("outbuf is too small (%d < %d)\n", - outbuf_len, ethaddr_len + 4); - + if (outbuf_len < 21) { + printf("outbuf is too small (%d < 21)\n", outbuf_len); return -EINVAL; } - strcpy(outbuf, "01-"); + eth_set_current(); + dev = eth_get_dev(); + if (!dev) + return -ENODEV; - for (p = outbuf + 3; *ethaddr; ethaddr++, p++) { - if (*ethaddr == ':') + sprintf(outbuf, "01-%pM", dev->enetaddr); + for (p = outbuf + 3; *p; p++) { + if (*p == ':') *p = '-'; else - *p = tolower(*ethaddr); + *p = tolower(*p); } - *p = '\0'; - return 1; } -- 1.7.5.4

4 13

[U-Boot] [PATCH] add new board vl_ma2sc
by Jens Scharsig 07 Jul '12

07 Jul '12

* add support for board VL+MA2SC * adds vl_ma2sc_config for standard NOR boot configuration * adds vl_ma2sc_ram_config for RAM load configuration Signed-off-by: Jens Scharsig <esw(a)bus-elektronik.de> --- MAINTAINERS | 1 + board/BuS/vl_ma2sc/Makefile | 54 ++++ board/BuS/vl_ma2sc/vl_ma2sc.c | 596 +++++++++++++++++++++++++++++++++++++++++ boards.cfg | 2 + include/configs/vl_ma2sc.h | 466 ++++++++++++++++++++++++++++++++ 5 files changed, 1119 insertions(+), 0 deletions(-) create mode 100644 board/BuS/vl_ma2sc/Makefile create mode 100644 board/BuS/vl_ma2sc/vl_ma2sc.c create mode 100644 include/configs/vl_ma2sc.h diff --git a/MAINTAINERS b/MAINTAINERS index a5b728e..12047fc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -819,6 +819,7 @@ Steve Sakoman <sakoman(a)gmail.com> Jens Scharsig <esw(a)bus-elektronik.de> eb_cpux9k2 ARM920T (AT91RM9200 SoC) + vl_ma2sc ARM926EJS (AT91SAM9263 SoC) Heiko Schocher <hs(a)denx.de> diff --git a/board/BuS/vl_ma2sc/Makefile b/board/BuS/vl_ma2sc/Makefile new file mode 100644 index 0000000..3f36a4d --- /dev/null +++ b/board/BuS/vl_ma2sc/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2009-2012 +# Jens Scharsig <esw(a)bus-elekronik.de> +# BuS Elektronik GmbH & Co. KG +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS += vl_ma2sc.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/BuS/vl_ma2sc/vl_ma2sc.c b/board/BuS/vl_ma2sc/vl_ma2sc.c new file mode 100644 index 0000000..dfaf2cb --- /dev/null +++ b/board/BuS/vl_ma2sc/vl_ma2sc.c @@ -0,0 +1,596 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig <esw(a)bus-elekronik.de> + * BuS Elektronik GmbH & Co. KG + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <asm/sizes.h> +#include <asm/io.h> +#include <asm/arch/hardware.h> +#include <asm/arch/clk.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91sam9263.h> +#include <asm/arch/gpio.h> +#include <asm/arch/at91_common.h> +#include <lcd.h> +#include <i2c.h> +#include <atmel_lcdc.h> +#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) +#include <net.h> +#endif +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ + +#ifdef CONFIG_CMD_NAND +static void vl_ma2sc_nand_hw_init(void) +{ + unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_matrix_t *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 12, 1); /* CAN_STB -> H */ + at91_set_pio_output(AT91_PIO_PORTA, 11, 1); /* CAN_EN -> H */ + + /* Enable CS3 */ + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); + + /* Configure SMC CS3 for NAND/SmartMedia */ +#if 1 + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); +#else +#warning SAMSUNG Timmings +#define NTM 1 + writel(AT91_SMC_SETUP_NWE(NTM * 2) | AT91_SMC_SETUP_NCS_WR(NTM * 1) | + AT91_SMC_SETUP_NRD(NTM * 2) | AT91_SMC_SETUP_NCS_RD(NTM * 1), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(NTM * 3) | AT91_SMC_PULSE_NCS_WR(NTM * 5) | + AT91_SMC_PULSE_NRD(NTM * 5) | AT91_SMC_PULSE_NCS_RD(NTM * 7), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(NTM * 7) | AT91_SMC_CYCLE_NRD(NTM * 10), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); +#endif + writel((1 << ATMEL_ID_PIOB) | (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + /* Configure RDY/BSY */ +#ifdef CONFIG_SYS_NAND_READY_PIN + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + /* Enable NandFlash */ + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void vl_ma2sc_macb_hw_init(void) +{ + unsigned long erstl; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC; + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PC25) => PHY normal mode (not Test mode) + * ERX0 (PE25) => PHY ADDR0 + * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0 + * + * PHY has internal pull-down + */ + + writel((1 << 25), &pio->pioc.pudr); + writel((1 << 25) | (1 << 26), &pio->pioe.pudr); + + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + + /* Need to reset PHY -> 500ms reset */ + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0x0D) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + /* Re-enable pull-up */ + writel((1 << 25), &pio->pioc.puer); + writel((1 << 25) | (1 << 26), &pio->pioe.puer); + + at91_macb_hw_init(); +} +#endif + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + vl_col: 320, + vl_row: 240, + vl_clk: 6500000, + vl_sync: ATMEL_LCDC_INVDVAL_INVERTED | + ATMEL_LCDC_INVLINE_INVERTED | + ATMEL_LCDC_INVVD_INVERTED | + ATMEL_LCDC_INVFRAME_INVERTED, + vl_bpix: (ATMEL_LCDC_PIXELSIZE_8 >> 5), + vl_tft: 1, + vl_hsync_len: 5, /* Horiz Sync Pulse Width */ + vl_left_margin: 68, /* horiz back porch */ + vl_right_margin: 20, /* horiz front porch */ + vl_vsync_len: 2, /* vert Sync Pulse Width */ + vl_upper_margin: 18, /* vert back porch */ + vl_lower_margin: 4, /* vert front porch */ + mmio: ATMEL_BASE_LCDC, +}; + +void lcd_enable(void) +{ +} + +void lcd_disable(void) +{ +} + +static void vl_ma2sc_lcd_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */ + at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */ + + at91_set_a_periph(AT91_PIO_PORTC, 4, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */ + at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTC, 20, 0); /* LCDD26 */ + at91_set_a_periph(AT91_PIO_PORTC, 21, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */ + at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */ + + at91_set_pio_output(AT91_PIO_PORTE, 0, 0); /* LCD QXH */ + + at91_set_pio_output(AT91_PIO_PORTE, 2, 0); /* LCD SHUT */ + at91_set_pio_output(AT91_PIO_PORTE, 3, 1); /* LCD TopBottom */ + at91_set_pio_output(AT91_PIO_PORTE, 4, 0); /* LCD REV */ + at91_set_pio_output(AT91_PIO_PORTE, 5, 1); /* LCD RightLeft */ + at91_set_pio_output(AT91_PIO_PORTE, 6, 0); /* LCD Color Mode CM */ + at91_set_pio_output(AT91_PIO_PORTE, 7, 0); /* LCD BGR */ + + at91_set_pio_output(AT91_PIO_PORTB, 9, 0); /* LCD CC */ + + writel(1 << ATMEL_ID_LCDC, &pmc->pcer); + gd->fb_base = ATMEL_BASE_SRAM0; +} + +#endif /* Config LCD */ + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOCDE), + &pmc->pcer); + + at91_seriald_hw_init(); + + return 0; +} +#endif + +int board_init(void) +{ + at91_smc_t *smc = (at91_smc_t *) ATMEL_BASE_SMC0; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + pin = 0x1F000001; + writel(pin, &pio->pioa.idr); + writel(pin, &pio->pioa.pudr); + writel(pin, &pio->pioa.per); + writel(pin, &pio->pioa.oer); + writel(pin, &pio->pioa.sodr); + writel((1 << 25), &pio->pioa.codr); + + pin = 0x1F000100; + writel(pin, &pio->piob.idr); + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.codr); + writel((1 << 24), &pio->piob.sodr); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + + pin = 0x0000000F; /* HWversion als Input */ + writel(pin, &pio->piod.idr); + writel(pin, &pio->piod.puer); + writel(pin, &pio->piod.per); + writel(pin, &pio->piod.odr); + writel(pin, &pio->piod.owdr); + + /* Enable Ctrlc */ + console_init_f(); + + gd->bd->bi_arch_number = MACH_TYPE_VL_MA2SC; + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + writel(CONFIG_SYS_SMC0_MODE0_VAL, &smc->cs[0].setup); + writel(CONFIG_SYS_SMC0_CYCLE0_VAL, &smc->cs[0].cycle); + writel(CONFIG_SYS_SMC0_PULSE0_VAL, &smc->cs[0].pulse); + writel(CONFIG_SYS_SMC0_SETUP0_VAL, &smc->cs[0].setup); + +#ifdef CONFIG_CMD_NAND + vl_ma2sc_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + vl_ma2sc_macb_hw_init(); +#endif +#ifdef CONFIG_USB_OHCI_NEW + at91_uhp_hw_init(); +#endif +#ifdef CONFIG_LCD + vl_ma2sc_lcd_hw_init(); +#endif + return 0; +} + +#ifdef CONFIG_MISC_INIT_R + +int misc_init_r(void) +{ + uchar buffer[8]; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin; + + buffer[0] = 0x04; + buffer[1] = 0x00; + if (i2c_write(0x68, 0x0E, 1, buffer, 2) != 0) + puts("error reseting rtc clock\n\0"); + + /* HWversion lesen */ + + pin = (readl(&pio->piod.pdsr) & 0x0F) + 0x44; + printf("Board: revision %c\n", pin); + buffer[0] = pin; + buffer[1] = 0; + setenv("revision", (char *) buffer); + + pin = 0x40000000; /* Pullup DRxD enbable */ + writel(pin, &pio->pioc.puer); + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_RESET_PHY_R +void reset_phy(void) +{ +#ifdef CONFIG_MACB + /* + * Initialize ethernet HW addr prior to starting Linux, + * needed for nfsroot + */ + eth_init(gd->bd); +#endif +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_MACB + rc = macb_eth_initialize(0, (void *) ATMEL_BASE_EMAC, 0x01); +#endif + return rc; +} + +#ifdef CONFIG_SOFT_I2C + +void i2c_init_board(void) +{ + u32 pin; + + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u8 sda = (1<<4); + u8 scl = (1<<5); + + writel(1 << ATMEL_ID_PIOB, &pmc->pcer); + pin = sda | scl; + writel(pin, &pio->piob.idr); /* Disable Interupt */ + writel(pin, &pio->piob.pudr); + writel(pin, &pio->piob.per); + writel(pin, &pio->piob.oer); + writel(pin, &pio->piob.sodr); +} + +#endif + +void watchdog_reset(void) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 pin = 0x1; /* PA0 */ + + if ((readl(&pio->pioa.odsr) & pin) > 0) + writel(pin, &pio->pioa.codr); + else + writel(pin, &pio->pioa.sodr); +} + +void enable_caches(void) +{ +#ifndef CONFIG_SYS_DCACHE_OFF + dcache_enable(); +#endif +} + +/*---------------------------------------------------------------------------*/ + +int do_ledtest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + int col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); /* LCD DIM */ + + pins = 0x1F000000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.oer); + writel(pins, &pio->pioa.sodr); + + pinz = 0x1F000000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.sodr); + + for (row = 0; row < 5; row++) { + for (col = 0; col < 5; col++) { + writel((0x01000000 << col), &pio->piob.sodr); + writel((0x01000000 << row), &pio->pioa.codr); + printf("LED Test %d x %d\n", row, col); + udelay(1000000); + writel(pinz, &pio->piob.codr); + writel(pins, &pio->pioa.sodr); + } + } + + return rcode; +} + +void poweroff(void) +{ + watchdog_reset(); + at91_set_pio_output(AT91_PIO_PORTA, 13, 1); /* CAN_TX -> H */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 12, 0); /* CAN_STB -> L */ + udelay(100); + at91_set_pio_output(AT91_PIO_PORTA, 11, 0); /* CAN_EN -> L */ + udelay(100); + while (1) + watchdog_reset(); +} + +int do_poweroff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + poweroff(); + return rcode; +} + +int do_beep(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int i; + u32 freq; + u32 durate; + int rcode = 1; + + freq = 1000; + durate = 2; + switch (argc) { + case 3: + durate = simple_strtoul(argv[2], NULL, 10); + case 2: + freq = simple_strtoul(argv[1], NULL, 10); + case 1: + break; + default: + cmd_usage(cmdtp); + rcode = 1; + break; + } + durate = durate * freq; + freq = 500000 / freq; + for (i = 0; i < durate; i++) { + at91_set_pio_output(AT91_PIO_PORTB, 29, 1); /* Sound On*/ + udelay(freq); + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + udelay(freq); + } + at91_set_pio_output(AT91_PIO_PORTB, 29, 0); /* Sound Off*/ + return rcode; +} + +int do_keytest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rcode = 1; + int row; + u32 col; + u32 pinz; + u32 pins; + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; + + writel((1 << ATMEL_ID_PIOA), &pmc->pcer); + + pins = 0x001F0000; + writel(pins, &pio->pioa.idr); + writel(pins, &pio->pioa.pudr); + writel(pins, &pio->pioa.per); + writel(pins, &pio->pioa.odr); + + pinz = 0x000F0000; + writel(pinz, &pio->piob.idr); + writel(pinz, &pio->piob.pudr); + writel(pinz, &pio->piob.per); + writel(pinz, &pio->piob.oer); + writel(pinz, &pio->piob.codr); + + while (1) { + col = 0; + for (row = 0; row < 4; row++) { + writel((0x00010000 << row), &pio->piob.sodr); + udelay(10000); + col <<= 4; + col |= ((readl(&pio->pioa.pdsr) >> 16) & 0xF) ^ 0xF ; + writel(pinz, &pio->piob.codr); + } + printf("Matix: "); + for (row = 0; row < 16; row++) { + printf("%1.1d", col & 1); + col >>= 1; + } + printf(" SP %d\r ", + 1 ^ (1 & (readl(&pio->piob.pdsr) >> 20))); + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) { + /* SHUTDOWN */ + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) == 0) + row++; + udelay(100); + } + udelay(100000); + row = 0; + while (row < 1000) { + if ((1 & (readl(&pio->pioa.pdsr) >> 1)) > 0) { + row++; + udelay(1000); + } + } + poweroff(); + while (1) + ; + } + } + return rcode; +} + +/*****************************************************************************/ + +U_BOOT_CMD( + ledtest, 1, 0, do_ledtest, + "test ledmatrix", + "\n" + ); + +U_BOOT_CMD( + keytest, 1, 0, do_keytest, + "test keymatix and special keys, poweroff on pressing ON key", + "\n" + ); + +U_BOOT_CMD( + poweroff, 1, 0, do_poweroff, + "power off", + "\n" + ); + +U_BOOT_CMD( + beep, 3, 0, do_beep, + "[freq [duration]]", + "freq frequence of beep\nduration duration of beep\n" + ); + +/*****************************************************************************/ diff --git a/boards.cfg b/boards.cfg index 576b392..2f7211f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,8 @@ at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91sam9xeek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_NANDFLASH snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 +vl_ma2sc arm arm926ejs vl_ma2sc BuS at91 +vl_ma2sc_ram arm arm926ejs vl_ma2sc BuS at91 vl_ma2sc:RAMLOAD sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH tny_a9260_eeprom arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9260,SYS_USE_EEPROM diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h new file mode 100644 index 0000000..d9c2a2d --- /dev/null +++ b/include/configs/vl_ma2sc.h @@ -0,0 +1,466 @@ +/* + * (C) Copyright 2009-2012 + * Jens Scharsig <esw(a)bus-elekronik.de> + * BuS Elektronik GmbH & Co. KG + * + * Configuation settings for the VL_MA2SC board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*--------------------------------------------------------------------------*/ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_ARM926EJS /* This is an ARM926EJS Core */ +#define CONFIG_AT91FAMILY +#define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */ +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_MISC_INIT_R + +#include <asm/hardware.h> + +#define MACH_TYPE_VL_MA2SC 2412 +#define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC + +#define CONFIG_SYS_DCACHE_OFF + +#ifdef CONFIG_RAMLOAD +#define CONFIG_SYS_TEXT_BASE 0x21000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x00000000 +#endif +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_IDENT_STRING " on MiS Activ 2" +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AT91_GPIO + +#if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD) +#define CONFIG_SYS_USE_NORFLASH +#define CONFIG_SYS_USE_BOOT_NORFLASH +#endif + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#ifndef CONFIG_SYS_USE_BOOT_NORFLASH +#define CONFIG_SKIP_LOWLEVEL_INIT +#endif + +/* + * Hardware drivers + */ + +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_WATCHDOG + +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS + +/* LCD */ +#define CONFIG_LCD +#define CONFIG_ATMEL_LCD +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SYS_BLACK_ON_WHITE +#define LCD_BPP LCD_COLOR8 +#define CONFIG_ATMEL_LCD_BGR555 + +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_BOOTDELAY 3 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_BMP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NAND +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_MD5SUM +#define CONFIG_CMD_SHA1SUM +/* +#define CONFIG_CMD_SPI +*/ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_LONGHELP +#define CONFIG_MD5 +#define CONFIG_SHA1 + +/*---------------------------------------------------------------------------- + * Hardware confuguration + *---------------------------------------------------------------------------*/ + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#define CONFIG_AT91C_PQFP_UHPBUG + +/* I2C-Bus */ + +#define CONFIG_SYS_I2C_SPEED 50000 +#define CONFIG_SYS_I2C_SLAVE 0 /* not used */ + +#ifndef CONFIG_HARD_I2C +#define CONFIG_SOFT_I2C + +/* Software I2C driver configuration */ + +#define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED) + +#define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */ +#define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */ + +#define I2C_INIT i2c_init_board(); +#define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr); +#define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder); +#define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0) +#define I2C_SDA(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SDA, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SDA, &pio->piob.codr); \ + } while (0); +#define I2C_SCL(bit) \ + do { \ + if (bit) \ + writel(AT91_PIN_SCL, &pio->piob.sodr); \ + else \ + writel(AT91_PIN_SCL, &pio->piob.codr); \ + } while (0); +#endif + +/* I2C-RTC */ + +#ifdef CONFIG_CMD_DATE +#define CONFIG_RTC_DS1338 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#endif + +/* EEPROM */ + +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 + +/* define PDC[31:16] as DATA[31:16] */ +#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 +#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 + +/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_MR_URSTEN | \ + AT91_RSTC_MR_ERSTL(15)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xFFF) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xFFF)) + +/* clocks */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */ + +#define MHZ180 +#if defined(MHZ199) +/* 199,8994 MHZ */ +#define MASTER_PLL_MUL 911 +#define MASTER_PLL_DIV 56 +#define MASTER_PLL_OUT 2 +#elif defined(MHZ180) +/* 180 MHZ */ +#define MASTER_PLL_MUL 1875 +#define MASTER_PLL_DIV 128 +#define MASTER_PLL_OUT 2 +#elif defined(MHZTEST) +/* Test MHZ */ +#define CONFIG_DISPLAY_CPUINFO +#define MASTER_PLL_MUL 8 +#define MASTER_PLL_DIV 1 +#define MASTER_PLL_OUT 2 +#else +/* 176.9472 MHZ */ +#define MASTER_PLL_MUL 72 +#define MASTER_PLL_DIV 5 +#define MASTER_PLL_OUT 2 +#endif + +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) + +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | \ + AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ + AT91_PMC_PLLXR_PLLCOUNT(63) | \ + AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ + AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* PCK/2 = MCK Master Clock from PLLA */ +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */ + +#define CONFIG_SYS_SDRC_MR_VAL1 0 +#define CONFIG_SYS_SDRC_TR_VAL1 700 +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_3 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* Write Recovery Delay */ \ + (7 << 12) | /* Row Cycle Delay */ \ + (2 << 16) | /* Row Precharge Delay */ \ + (2 << 20) | /* Row to Column Delay */ \ + (5 << 24) | /* Active to Precharge Delay */ \ + (8 << 28)) /* Exit Self Refresh to Active Delay */ + +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE +#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH +#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR +#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL +#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ +#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ +#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ + +/* NOR flash */ + +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define PHYS_FLASH_1 0x10000000 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) + +/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 0 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#endif + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 5 + +#define CONFIG_ETHADDR 00:4D:41:02:52:43 /* MA2SC */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE + +#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ + +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END 0x21e00000 + +/* Address and size of Primary Environment Sector */ +#ifdef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_SIZE 0x20000 +#else +#define CONFIG_ENV_SIZE 0x2000 +#endif + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \ + 38400, 57600, 9600 } + +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ +#define CONFIG_SYS_MAXARGS 32 /* max number of command args */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN \ + ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#ifndef CONFIG_RAMLOAD +#define CONFIG_BOOTCOMMAND "run nfsboot" +#endif +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_BOOT_RETRY_MIN 15 + +#define CONFIG_NFSBOOTCOMMAND \ + "dhcp $(copy_addr) $(kernelname);" \ + "run bootargsdefaults;" \ + "set bootargs $(bootargs) boot=nfs " \ + ";echo $(bootargs)" \ + ";bootm" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "ubootaddr=10000000\0" \ + "splashimage=10080000\0" \ + "kerneladdr=100A0000\0" \ + "kernelsize=00800000\0" \ + "minifsaddr=108A0000\0" \ + "minifssize=00060000\0" \ + "rootfsaddr=10900000\0" \ + "copy_addr=20200000\0" \ + "rootfssize=01700000\0" \ + "kernelname=uImage_vl_ma2sc\0" \ + "bootargsdefaults=set bootargs " \ + "console=ttyS0,115200 " \ + "video=atmel_lcdfb " \ + "mem=62M " \ + "panic=10 " \ + "boardrevison=\\\"${revision}\\\" " \ + "uboot=\\\"${ver}\\\" " \ + "\0" \ + "update_all=run update_kernel;run update_root;" \ + "run update_splash; run update_uboot\0" \ + "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \ + "dhcp $(copy_addr) $(kernelname);" \ + "erase $(kerneladdr) +$(kernelsize);" \ + "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \ + "protect on $(kerneladdr) +$(kernelsize)" \ + "\0" \ + "update_root=protect off $(rootfsaddr) +$(rootfssize);" \ + "dhcp $(copy_addr) vl_ma2sc.root;" \ + "erase $(rootfsaddr) +$(rootfssize);" \ + "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \ + "\0" \ + "update_splash=protect off $(splashimage) +20000;" \ + "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \ + "erase $(splashimage) +20000;" \ + "cp.b $(fileaddr) 10080000 $(filesize);" \ + "protect on $(splashimage) +20000\0" \ + "update_uboot=protect off 10000000 1005FFFF;" \ + "dhcp $(copy_addr) u-boot_vl_ma2sc;" \ + "erase 10000000 1005FFFF;" \ + "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \ + "protect on 10000000 1005FFFF;reset\0" \ + "emergency=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(kerneladdr)\0" \ + "netemergency=run bootargsdefaults;" \ + "dhcp $(copy_addr) $(kernelname);" \ + "set bootargs $(bootargs) root=initramfs boot=emergency " \ + ";bootm $(copy_addr)\0" \ + "norboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=local quiet " \ + ";bootm $(kerneladdr)\0" \ + "nandboot=run bootargsdefaults;" \ + "set bootargs $(bootargs) root=initramfs boot=nand " \ + ";bootm $(kerneladdr)\0" \ + "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \ + "clearenv=protect off 10060000 1007FFFF;" \ + "erase 10060000 1007FFFF;reset\0" \ + " " + +/*--------------------------------------------------------------------------*/ + +#ifdef CONFIG_USE_IRQ +#error CONFIG_USE_IRQ not supported +#endif + +#endif + +/* EOF */ -- 1.7.3.4

4 6

[U-Boot] [PATCH v4] at91: Add support for Bluewater Systems Snapper 9G45 module
by Simon Glass 30 Jun '12

30 Jun '12

Snapper 9G45 is a ARM9-based CPU module with 1GB NAND and 128MB DDR SDRAM. This patch includes NAND and Ethernet support. Signed-off-by: Simon Glass <sglass(a)bluewatersys.com> --- Changes in v2: - Removed unneeded i2c config - Added machine type define Changes in v3: - Use CONFIG_MACH_TYPE instead of custom code - Reduce PHY reset delay to minimum required Changes in v4: - Add MAINTAINERS entry and update Snapper boards since Ryan has moved - Fix ip= bootarg error - Remove I2C as this is not needed MAINTAINERS | 3 +- board/bluewater/snapper9g45/Makefile | 43 ++++++++ board/bluewater/snapper9g45/snapper9g45.c | 151 +++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/snapper9g45.h | 157 +++++++++++++++++++++++++++++ 5 files changed, 354 insertions(+), 1 deletions(-) create mode 100644 board/bluewater/snapper9g45/Makefile create mode 100644 board/bluewater/snapper9g45/snapper9g45.c create mode 100644 include/configs/snapper9g45.h diff --git a/MAINTAINERS b/MAINTAINERS index 576fea8..c12ee54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -300,10 +300,11 @@ Dan Malek <dan(a)embeddedalley.com> stxssa MPC85xx stxxtc MPC8xx -Ryan Mallon <ryan(a)bluewatersys.com> +Simon Glass <sglass(a)bluewatersys.com> snapper9260 ARM926EJS (AT91SAM9260 SoC) snapper9g20 ARM926EJS (AT91SAM9G20 SoC) + snapper9g45 ARM926EJS (AT91SAM9G45 SoC) Eran Man <eran(a)nbase.co.il> diff --git a/board/bluewater/snapper9g45/Makefile b/board/bluewater/snapper9g45/Makefile new file mode 100644 index 0000000..9016e5a --- /dev/null +++ b/board/bluewater/snapper9g45/Makefile @@ -0,0 +1,43 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += snapper9g45.o + +SRCS := $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/bluewater/snapper9g45/snapper9g45.c b/board/bluewater/snapper9g45/snapper9g45.c new file mode 100644 index 0000000..4e5afb1 --- /dev/null +++ b/board/bluewater/snapper9g45/snapper9g45.c @@ -0,0 +1,151 @@ +/* + * (C) Copyright 2011 Bluewater Systems Ltd + * Author: Andre Renaud <andre(a)bluewatersys.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/at91sam9g45_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hardware.h> +#include <net.h> +#include <netdev.h> + +DECLARE_GLOBAL_DATA_PTR; + +static void macb_hw_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + /* Enable clock */ + writel(1 << ATMEL_ID_EMAC, &pmc->pcer); + + /* + * Disable pull-up on: + * RXDV (PA15) => PHY normal mode (not Test mode) / CRSDV + * ERX0 (PA12) => PHY ADDR0 / RXD0 + * ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0 / RXD1 + * + * PHY has internal pull-down + */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + &pioa->pudr); + + /* Need to reset PHY -> needs 100us, so use minimum reset period */ + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(0) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); + + /* Wait for end hardware reset */ + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; + + /* Restore NRST value */ + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, &rstc->mr); + + /* The phy internal reset take 21ms */ + mdelay(21); + + /* Re-enable pull-up */ + writel(pin_to_mask(AT91_PIN_PA15) | + pin_to_mask(AT91_PIN_PA12) | + pin_to_mask(AT91_PIN_PA13), + &pioa->puer); + + at91_macb_hw_init(); +} + +static void nand_hw_init(void) +{ + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + unsigned long csa; + + /* Enable CS3 as NAND/SmartMedia */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) | + AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + /* Configure RDY/BSY */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} + +int board_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + + /* Enable PIO clocks */ + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC | + (1 << ATMEL_ID_PIODE)), &pmc->pcer); + + /* Address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Initialise peripherals */ + at91_seriald_hw_init(); + nand_hw_init(); + + macb_hw_init(); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x1b); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/boards.cfg b/boards.cfg index 604becf..b6123c2 100644 --- a/boards.cfg +++ b/boards.cfg @@ -94,6 +94,7 @@ at91sam9xeek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91sam9xeek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9XE,SYS_USE_DATAFLASH_CS1 snapper9260 arm arm926ejs - bluewater at91 snapper9260:AT91SAM9260 snapper9g20 arm arm926ejs snapper9260 bluewater at91 snapper9260:AT91SAM9G20 +snapper9g45 arm arm926ejs snapper9g45 bluewater at91 snapper9g45:AT91SAM9G45 sbc35_a9g20_nandflash arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH sbc35_a9g20_eeprom arm arm926ejs sbc35_a9g20 calao at91 sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM tny_a9g20_nandflash arm arm926ejs tny_a9260 calao at91 tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h new file mode 100644 index 0000000..30181ad --- /dev/null +++ b/include/configs/snapper9g45.h @@ -0,0 +1,157 @@ +/* + * Bluewater Systems Snapper 9G45 modules + * + * (C) Copyright 2011 Bluewater Systems + * Author: Andre Renaud <andre(a)bluewatersys.com> + * Author: Ryan Mallon <ryan(a)bluewatersys.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* SoC type is defined in boards.cfg */ +#include <asm/hardware.h> +#include <asm/sizes.h> + +#define CONFIG_SYS_TEXT_BASE 0x70000000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +/* CPU */ +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_SKIP_LOWLEVEL_INIT + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_FIT + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 +#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) /* 128MB */ +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +/* Mem test settings */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) + +/* NAND flash */ +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_NO_FLASH +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /*0x40000000*/ +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_TFTP_PORT +#define CONFIG_TFTP_TSIZE + +/* USB */ +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_DOS_PARTITION +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */ +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE + +/* GPIOs and IO expander */ +#define CONFIG_AT91_LEGACY +#define CONFIG_ATMEL_LEGACY +#define CONFIG_AT91_GPIO +#define CONFIG_AT91_GPIO_PULLUP 1 + +/* UARTs/Serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } +#define CONFIG_SYS_PROMPT "Snapper> " + +/* Boot options */ +#define CONFIG_SYS_LOAD_ADDR 0x71000000 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK + +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Environment settings */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET (512 << 10) +#define CONFIG_ENV_SIZE (256 << 10) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BOOTARGS "console=ttyS0,115200 ip=dhcp" + +/* Console settings */ +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_EXTBDINFO +#define CONFIG_CMDLINE_EDITING +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* U-Boot memory settings */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) +#define CONFIG_STACKSIZE (256 << 10) +#define CONFIG_MACH_TYPE 2817 + +/* Command line configuration */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#undef CONFIG_CMD_GPIO +#define CONFIG_CMD_USB +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND + +#endif -- 1.7.5.4

2 1

[U-Boot] [PATCH v2] skat91: add support for SK-AT91SAM9/SIM508 board
by Vladimir Zapolskiy 28 Jun '12

28 Jun '12

This change adds complete support for Starterkit SK-AT91SAM9/SIM508 board. Signed-off-by: Vladimir Zapolskiy <vz(a)mleia.com> Cc: Albert ARIBAUD <albert.u.boot(a)aribaud.net> Cc: Wolfgang Denk <wd(a)denx.de> --- Changes from v1 to v2: * make use of setbits_le32() and similar helpers * phy address is defined explicitly * removed CONFIG_EXTRA_ENV_SETTINGS MAINTAINERS | 4 + board/starterkit/skat91_sim508/Makefile | 44 ++++++ board/starterkit/skat91_sim508/partition.c | 39 +++++ board/starterkit/skat91_sim508/skat91_sim508.c | 122 ++++++++++++++++ boards.cfg | 2 + include/configs/skat91_sim508.h | 178 ++++++++++++++++++++++++ 6 files changed, 389 insertions(+), 0 deletions(-) create mode 100644 board/starterkit/skat91_sim508/Makefile create mode 100644 board/starterkit/skat91_sim508/partition.c create mode 100644 board/starterkit/skat91_sim508/skat91_sim508.c create mode 100644 include/configs/skat91_sim508.h diff --git a/MAINTAINERS b/MAINTAINERS index 4bf12b5..bcd330a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -914,6 +914,10 @@ Sughosh Ganu <urwithsughosh(a)gmail.com> hawkboard ARM926EJS (OMAP-L138) +Vladimir Zapolskiy <vz(a)mleia.com> + + skat91_sim508 ARM926EJS (AT91SAM9260 SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/board/starterkit/skat91_sim508/Makefile b/board/starterkit/skat91_sim508/Makefile new file mode 100644 index 0000000..77965f8 --- /dev/null +++ b/board/starterkit/skat91_sim508/Makefile @@ -0,0 +1,44 @@ +# +# Copyright (C) 2011 by Vladimir Zapolskiy <vz(a)mleia.com> +# Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := skat91_sim508.o partition.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/starterkit/skat91_sim508/partition.c b/board/starterkit/skat91_sim508/partition.c new file mode 100644 index 0000000..f82046d --- /dev/null +++ b/board/starterkit/skat91_sim508/partition.c @@ -0,0 +1,39 @@ +/* + * StarterKit SK-AT91SAM9/SIM508 board support, dataflash partitions + * + * Copyright (C) 2011 Vladimir Zapolskiy <vz(a)mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <config.h> +#include <asm/hardware.h> +#include <dataflash.h> + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + { CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0 }, +}; + +/* define the area offsets */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + { 0x00000000, 0x00003FFF, FLAG_PROTECT_SET, 0, "Bootstrap" }, + { 0x00004000, 0x00007FFF, FLAG_PROTECT_CLEAR, 0, "Environment" }, + { 0x00008000, 0x00037FFF, FLAG_PROTECT_SET, 0, "U-Boot" }, + { 0x00038000, 0x0041FFFF, FLAG_PROTECT_CLEAR, 0, "Kernel" }, +}; diff --git a/board/starterkit/skat91_sim508/skat91_sim508.c b/board/starterkit/skat91_sim508/skat91_sim508.c new file mode 100644 index 0000000..1ddafab --- /dev/null +++ b/board/starterkit/skat91_sim508/skat91_sim508.c @@ -0,0 +1,122 @@ +/* + * StarterKit SK-AT91SAM9/SIM508 board support + * + * Copyright (C) 2011 Vladimir Zapolskiy <vz(a)mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#include <common.h> +#include <netdev.h> + +#include <asm/arch/at91sam9260_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_pio.h> +#include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/gpio.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_CMD_NAND +static void skat91_sim508_nand_hw_init(void) +{ + struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + struct at91_smc *smc = (at91_smc_t *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; + + /* Assign CS3 to NAND/SmartMedia Interface */ + setbits_le32(&matrix->ebicsa, AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + + /* Configure SMC CS3 for NAND/SmartMedia */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + + writel(1 << ATMEL_ID_PIOC, &pmc->pcer); + + /* Configure RDY/BSY */ + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); + + /* Enable NandFlash */ + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +} +#endif + +#ifdef CONFIG_MACB +static void skat91_sim508_macb_hw_init(void) +{ + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; + + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); + + at91_macb_hw_init(); +} + +int board_eth_init(bd_t *bis) +{ + return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, + CONFIG_PHY_ADDR); +} +#endif + +int board_early_init_f(void) +{ + at91_seriald_hw_init(); + + return 0; +} + +int board_init(void) +{ + /* Enable Ctrlc */ + console_init_f(); + + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_CMD_NAND + skat91_sim508_nand_hw_init(); +#endif +#ifdef CONFIG_MACB + skat91_sim508_macb_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + + return 0; +} diff --git a/boards.cfg b/boards.cfg index 0b32532..6dd2269 100644 --- a/boards.cfg +++ b/boards.cfg @@ -118,6 +118,8 @@ cpu9G20_nand_128M arm arm926ejs cpu9260 eukrea pm9261 arm arm926ejs pm9261 ronetix at91 pm9261:AT91SAM9261 pm9263 arm arm926ejs pm9263 ronetix at91 pm9263:AT91SAM9263 pm9g45 arm arm926ejs pm9g45 ronetix at91 pm9g45:AT91SAM9G45 +skat91_sim508 arm arm926ejs skat91_sim508 starterkit at91 skat91_sim508:AT91SAM9260,SYS_USE_NANDFLASH +skat91_sim508_dataflash arm arm926ejs skat91_sim508 starterkit at91 skat91_sim508:AT91SAM9260,SYS_USE_DATAFLASH_CS0 cam_enc_4xx arm arm926ejs cam_enc_4xx ait davinci cam_enc_4xx da830evm arm arm926ejs da8xxevm davinci davinci da850_am18xxevm arm arm926ejs da8xxevm davinci davinci diff --git a/include/configs/skat91_sim508.h b/include/configs/skat91_sim508.h new file mode 100644 index 0000000..794b7d7 --- /dev/null +++ b/include/configs/skat91_sim508.h @@ -0,0 +1,178 @@ +/* + * Starterkit SK-AT91SAM9/SIM508 board configuration file + * + * Copyright (C) 2011 Vladimir Zapolskiy <vz(a)mleia.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301, USA. + */ + +#ifndef __CONFIG_SKAT91_SIM508_H__ +#define __CONFIG_SKAT91_SIM508_H__ + +#include <asm/sizes.h> +#include <asm/hardware.h> + +/* Define SK-AT91SAM9/SIM508 machine type by hand */ +#define MACH_TYPE_SKAT91_SIM508 2789 +#define CONFIG_MACH_TYPE MACH_TYPE_SKAT91_SIM508 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 +#define CONFIG_SYS_HZ 1000 + +/* SoC configurations */ +#define CONFIG_ARCH_CPU_INIT + +/* Memory configurations */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_STACKSIZE SZ_32K +#define CONFIG_SYS_MALLOC_LEN SZ_1M +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE SZ_64M +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) + +#define CONFIG_SYS_TEXT_BASE 0x23F00000 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_MEMTEST_START + SZ_32K) + +#define CONFIG_SYS_INIT_RAM_SIZE SZ_4K +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET + +/* Hardware drivers */ +#define CONFIG_AT91_GPIO + +/* Serial driver */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 , 57600, 38400, 19200, 9600 } + +/* DataFlash */ +#define CONFIG_CMD_FLASH +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_HAS_DATAFLASH +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define AT91_SPI_CLK 15000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x01 << 24) + +/* NOR flash - no real flash on this board */ +#define CONFIG_SYS_NO_FLASH + +/* NAND Flash */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_ATMEL +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_DBW_8 1 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTC, 13 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTC, 14 +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) + +/* Ethernet */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_PHY_ADDR 0x01 + +/* U-Boot General Configurations */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#if defined(CONFIG_SYS_USE_DATAFLASH_CS0) +#define CONFIG_ENV_IS_IN_DATAFLASH +#define CONFIG_SYS_MONITOR_BASE \ + (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8000) +#define CONFIG_ENV_OFFSET 0x4000 +#define CONFIG_ENV_ADDR \ + (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) +#define CONFIG_ENV_SIZE SZ_16K +#define CONFIG_BOOTCOMMAND "cp.b 0xC0038000 0x20400000 0x170000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + "mtdparts=atmel_nand:-(root) " \ + "rw rootfstype=jffs2" +#elif defined(CONFIG_SYS_USE_NANDFLASH) +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x020000 +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_BOOTCOMMAND "nand read 0x20400000 0x80000 0x200000; bootm" +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock5 " \ + "mtdparts=atmel_nand:128k(bootstrap)ro,"\ + "256k(uboot)ro,128k(env)ro," \ + "2M(linux),-(root) " \ + "rw rootfstype=jffs2" +#else +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_BOOTARGS "console=ttyS2,115200n8" +#endif + +/* U-Boot Commands */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Boot Linux */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_LOADADDR 0x20400000 + +#endif /* __CONFIG_SKAT91_SIM508_H__ */ -- 1.7.5.4

3 2

[U-Boot] [PATCH 1/3] cmd_mem: replace custom PRINTF() with debug()
by Mike Frysinger 19 Jun '12

19 Jun '12

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/cmd_mem.c | 12 +++--------- 1 files changed, 3 insertions(+), 9 deletions(-) diff --git a/common/cmd_mem.c b/common/cmd_mem.c index 9ad932c..5121b22 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -35,12 +35,6 @@ #include <watchdog.h> #include <asm/io.h> -#ifdef CMD_MEM_DEBUG -#define PRINTF(fmt,args...) printf (fmt ,##args) -#else -#define PRINTF(fmt,args...) -#endif - static int mod_mem(cmd_tbl_t *, int, int, int, char * const []); /* Display values from last command. @@ -681,7 +675,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_ALT_MEMTEST) printf ("Testing %08x ... %08x:\n", (uint)start, (uint)end); - PRINTF("%s:%d: start 0x%p end 0x%p\n", + debug("%s:%d: start 0x%p end 0x%p\n", __FUNCTION__, __LINE__, start, end); for (;;) { @@ -698,7 +692,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } printf("Iteration: %6d\r", iterations); - PRINTF("\n"); + debug("\n"); iterations++; /* @@ -789,7 +783,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) pattern = (vu_long) 0xaaaaaaaa; anti_pattern = (vu_long) 0x55555555; - PRINTF("%s:%d: length = 0x%.8lx\n", + debug("%s:%d: length = 0x%.8lx\n", __FUNCTION__, __LINE__, len); /* -- 1.7.7.3

2 5

[U-Boot] [PATCH 2/2] P4080/PBL: add tool to support pbl image build.
by Shaohui Xie 04 Jun '12

04 Jun '12

The tool can build u-boot image which can be used by PBL, run "make P4080DS_RAMBOOT_PBL" can make all works done, the default output image is u-boot.pbl, for more details please refer to doc/README.pblimage. Signed-off-by: Shaohui Xie <b21989(a)freescale.com> --- Makefile | 5 + board/freescale/corenet_ds/config.mk | 26 +++ board/freescale/corenet_ds/pblimage.cfg | 59 ++++++ common/image.c | 1 + doc/README.pblimage | 83 ++++++++ include/image.h | 1 + tools/Makefile | 2 + tools/mkimage.c | 5 + tools/mkimage.h | 2 + tools/pblimage.c | 329 +++++++++++++++++++++++++++++++ tools/pblimage.h | 36 ++++ 11 files changed, 549 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/config.mk create mode 100644 board/freescale/corenet_ds/pblimage.cfg create mode 100644 doc/README.pblimage create mode 100644 tools/pblimage.c create mode 100644 tools/pblimage.h diff --git a/Makefile b/Makefile index dc2e3d8..ca6078e 100644 --- a/Makefile +++ b/Makefile @@ -361,6 +361,10 @@ $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $< $@ +$(obj)u-boot.pbl: $(obj)u-boot.bin + $(obj)tools/mkimage -n $(PBL_CONFIG) -T pblimage \ + -d $< $@ + $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin @@ -1156,6 +1160,7 @@ clobber: clean $(obj)cscope.* $(obj)*.*~ @rm -f $(obj)u-boot $(obj)u-boot.map $(obj)u-boot.hex $(ALL) @rm -f $(obj)u-boot.kwb + @rm -f $(obj)u-boot.pbl @rm -f $(obj)u-boot.imx @rm -f $(obj)tools/{env/crc32.c,inca-swap-bytes} @rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c diff --git a/board/freescale/corenet_ds/config.mk b/board/freescale/corenet_ds/config.mk new file mode 100644 index 0000000..c94938f --- /dev/null +++ b/board/freescale/corenet_ds/config.mk @@ -0,0 +1,26 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +ifeq ($(CONFIG_RAMBOOT_PBL), y) +PBL_CONFIG = $(SRCTREE)/board/$(BOARDDIR)/pblimage.cfg +ALL += $(obj)u-boot.pbl +endif diff --git a/board/freescale/corenet_ds/pblimage.cfg b/board/freescale/corenet_ds/pblimage.cfg new file mode 100644 index 0000000..96c55ee --- /dev/null +++ b/board/freescale/corenet_ds/pblimage.cfg @@ -0,0 +1,59 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# Written-by: Shaohui Xie<b21989(a)freescale.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# +# Refer docs/README.pblimage for more details about how-to configure +# and create PBL boot image +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +4c580000 00000000 18185218 0000cccc +40464000 3c3c2000 58000000 61000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 diff --git a/common/image.c b/common/image.c index f63a2ff..76e493d 100644 --- a/common/image.c +++ b/common/image.c @@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = { { IH_TYPE_FLATDT, "flat_dt", "Flat Device Tree", }, { IH_TYPE_KWBIMAGE, "kwbimage", "Kirkwood Boot Image",}, { IH_TYPE_IMXIMAGE, "imximage", "Freescale i.MX Boot Image",}, + { IH_TYPE_PBLIMAGE, "pblimage", "Freescale PBL Boot Image",}, { -1, "", "", }, }; diff --git a/doc/README.pblimage b/doc/README.pblimage new file mode 100644 index 0000000..e7ebea0 --- /dev/null +++ b/doc/README.pblimage @@ -0,0 +1,83 @@ +------------------------------------------------------------------ +Freescale PBL(pre-boot loader) Boot Image generation using mkimage +------------------------------------------------------------------ + +This document describes the U-Boot feature as it +is implemented for the Freescale P4080. + +The P4080 SoC's can boot directly from eSPI FLASH. + +for more details refer section 5 Pre-boot loader specifications. + +Building PBL boot image and boot steps +-------------------------------------- + +1. To build the PBL boot image for P4080DS: + make P4080DS_RAMBOOT_PBL + The default image is u-boot.pbl. + +2. Command below provided a way to re-build the PBL boot image if the +configuration file needes to be modified while the u-boot.bin does not +need to be re-build. + +Command syntax: +-------------- +./tools/mkimage -n <board specific configuration file> \ + -T pblimage -d <input_raw_binary> <output_pblboot_file> + +for ex. +./tools/mkimage -n ./board/freescale/corenet_ds/pblimage.cfg \ + -T pblimage -d u-boot.bin u-boot.pbl + + +3. pblimage support available with mkimage utility will generate Freescale PBL +boot image that can be flashed on the board eSPI flash. After flashed the +image u-boot.pbl, Change SW1[2] = off, then power on, board will boot from +eSPI flash. + +Board specific configuration file specifications: +------------------------------------------------ +1. This file must present in the $(BOARDDIR) and the name should be + pblimage.cfg (since this is used in Makefile) +2. This file can have empty lines and lines starting with "#" as first + character to put comments + +Typical example of pblimage.cfg file: +----------------------------------- + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +4c580000 00000000 18185218 0000cccc +40464000 3c3c2000 58000000 61000000 +00000000 00000000 00000000 008b6000 +00000000 00000000 00000000 00000000 + +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +09010100 00000000 +09010104 fff0000b +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000d00 00000000 +09000d04 fff00000 +09000d08 81000013 +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Initialize eSPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +09138000 00000000 +091380c0 00000000 + +------------------------------------------------ +Author: Shaohui Xie<b21989(a)freescale.com> diff --git a/include/image.h b/include/image.h index 005e0d2..56b849e 100644 --- a/include/image.h +++ b/include/image.h @@ -157,6 +157,7 @@ #define IH_TYPE_FLATDT 8 /* Binary Flat Device Tree Blob */ #define IH_TYPE_KWBIMAGE 9 /* Kirkwood Boot Image */ #define IH_TYPE_IMXIMAGE 10 /* Freescale IMXBoot Image */ +#define IH_TYPE_PBLIMAGE 11 /* Freescale PBLBoot Image */ /* * Compression Types diff --git a/tools/Makefile b/tools/Makefile index 623f908..c068bc0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -83,6 +83,7 @@ OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-$(CONFIG_INCA_IP) += inca-swap-bytes.o NOPED_OBJ_FILES-y += kwbimage.o +NOPED_OBJ_FILES-y += pblimage.o NOPED_OBJ_FILES-y += imximage.o NOPED_OBJ_FILES-y += mkimage.o OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o @@ -181,6 +182,7 @@ $(obj)mkimage$(SFX): $(obj)crc32.o \ $(obj)image.o \ $(obj)imximage.o \ $(obj)kwbimage.o \ + $(obj)pblimage.o \ $(obj)md5.o \ $(obj)mkimage.o \ $(obj)os_support.o \ diff --git a/tools/mkimage.c b/tools/mkimage.c index f5859d7..a3e793a 100644 --- a/tools/mkimage.c +++ b/tools/mkimage.c @@ -149,6 +149,8 @@ main (int argc, char **argv) int retval = 0; struct image_type_params *tparams = NULL; + /* Init Freescale PBL Boot image generation/list support */ + init_pbl_image_type(); /* Init Kirkwood Boot image generation/list support */ init_kwb_image_type (); /* Init Freescale imx Boot image generation/list support */ @@ -421,6 +423,9 @@ NXTARG: ; break; } } + } else if (params.type == IH_TYPE_PBLIMAGE) { + /* the copy_file need to be re-write for PBL. */ + pbl_load_uboot(ifd, &params); } else { copy_file (ifd, params.datafile, 0); } diff --git a/tools/mkimage.h b/tools/mkimage.h index 9033a7d..597dcaf 100644 --- a/tools/mkimage.h +++ b/tools/mkimage.h @@ -139,6 +139,8 @@ void mkimage_register (struct image_type_params *tparams); * * Supported image types init functions */ +void pbl_load_uboot(int, struct mkimage_params *); +void init_pbl_image_type(void); void init_kwb_image_type (void); void init_imx_image_type (void); void init_default_image_type (void); diff --git a/tools/pblimage.c b/tools/pblimage.c new file mode 100644 index 0000000..d0c29a6 --- /dev/null +++ b/tools/pblimage.c @@ -0,0 +1,329 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#define _GNU_SOURCE + +#include "mkimage.h" +#include <image.h> +#include "pblimage.h" + +/* + * PBL can load 64 bytes each time in MAX, so the u-boot need to be splited into + * pieces of 64 bytes, PBL needs a command for each piece, the command looks + * like 81xxxxxx, the "xxxxxx" is offset, it starts from F80000 in our case. + */ +static unsigned int uboot_label = 0x81F80000; +/* + * need to store all bytes in memory for calculating crc32, then write the + * bytes to image file for PBL boot. + */ +static unsigned char mem_buf[600000]; +static unsigned char *pmem_buf = mem_buf; +static int mem_byte_cnt; +static char *fname = "Unknown"; +static int lineno = -1; +static struct pbl_header pblimage_header; + +static union +{ + char c[4]; + unsigned char l; +} endian_test = { {'l', '?', '?', 'b'} }; + +#define ENDIANNESS ((char)endian_test.l) + +static void generate_pbl_cmd(void) +{ + unsigned int val = uboot_label; + uboot_label += 0x40; + int i; + + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (val >> (i * 8)) & 0xff; + mem_byte_cnt++; + } +} + +static void pbl_fget(size_t size, FILE *stream) +{ + unsigned char c; + while (size) { + c = (unsigned char)fgetc(stream); + *pmem_buf++ = c; + mem_byte_cnt++; + size--; + } +} + +/* load splited u-boot with PBI command 81xxxxxx. */ +static void load_uboot(FILE *fp_uboot) +{ + while (uboot_label < 0x82000000) { + generate_pbl_cmd(); + pbl_fget(64, fp_uboot); + } +} + +static void check_get_hexval(char *token) +{ + uint32_t hexval; + int i; + + if (!sscanf(token, "%x", &hexval)) { + printf("Error:%s[%d] - Invalid hex data(%s)\n", fname, + lineno, token); + exit(EXIT_FAILURE); + } + for (i = 3; i >= 0; i--) { + *pmem_buf++ = (hexval >> (i * 8)) & 0xff; + mem_byte_cnt++; + } +} + +static void pbl_parser(char *name) +{ + FILE *fd = NULL; + char *line = NULL; + char *token, *saveptr1, *saveptr2; + size_t len = 0; + + fname = name; + fd = fopen(name, "r"); + if (fd == NULL) { + printf("Error:%s - Can't open\n", fname); + exit(EXIT_FAILURE); + } + + while ((getline(&line, &len, fd)) > 0) { + lineno++; + token = strtok_r(line, "\r\n", &saveptr1); + /* drop all lines with zero tokens (= empty lines) */ + if (token == NULL) + continue; + for (line = token;; line = NULL) { + token = strtok_r(line, " \t", &saveptr2); + if (token == NULL) + break; + /* Drop all text starting with '#' as comments */ + if (token[0] == '#') + break; + check_get_hexval(token); + } + } + if (line) + free(line); + fclose(fd); +} + +static uint32_t crc_table[256]; + +static void make_crc_table(void) +{ + uint32_t mask; + int i, j; + uint32_t poly; /* polynomial exclusive-or pattern */ + + /* + * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10 + * + x11 + x12 + x16 + x22 + x23 + x26 + x32. + */ + poly = 0x04c11db7; + + for (i = 0; i < 256; i++) { + mask = i << 24; + for (j = 0; j < 8; j++) { + if (mask & 0x80000000) + mask = (mask << 1) ^ poly; + else + mask <<= 1; + } + crc_table[i] = mask; + } +} + +unsigned long pbl_crc32(unsigned long crc, const char *buf, unsigned int len) +{ + unsigned int crc32_val = 0xffffffff; + unsigned int xor = 0x0; + int i; + + make_crc_table(); + + for (i = 0; i < len; i++) + crc32_val = (crc32_val << 8) ^ + crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)]; + + crc32_val = crc32_val ^ xor; + if (crc32_val < 0) { + crc32_val += 0xffffffff; + crc32_val += 1; + } + return crc32_val; +} + +static unsigned int reverse_byte(unsigned int val) +{ + unsigned int temp; + unsigned char *p1; + int j; + + temp = val; + p1 = (unsigned char *)&temp; + for (j = 3; j >= 0; j--) + *p1++ = (val >> (j * 8)) & 0xff; + return temp; +} + +/* write end command and crc command to memory. */ +static void add_end_cmd(void) +{ + unsigned int pbl_end_cmd[4] = {0x09138000, 0x00000000, + 0x091380c0, 0x00000000}; + unsigned int crc32_pbl; + int i; + unsigned char *p = (unsigned char *)&pbl_end_cmd; + + if (ENDIANNESS == 'l') { + for (i = 0; i < 4; i++) + pbl_end_cmd[i] = reverse_byte(pbl_end_cmd[i]); + } + + for (i = 0; i < 16; i++) { + *pmem_buf++ = *p++; + mem_byte_cnt++; + } + + /* Add PBI CRC command. */ + *pmem_buf++ = 0x08; + *pmem_buf++ = 0x13; + *pmem_buf++ = 0x80; + *pmem_buf++ = 0x40; + mem_byte_cnt += 4; + + /* calculated CRC32 and write it to memory. */ + crc32_pbl = pbl_crc32(0, (const char *)mem_buf, mem_byte_cnt); + *pmem_buf++ = (crc32_pbl >> 24) & 0xff; + *pmem_buf++ = (crc32_pbl >> 16) & 0xff; + *pmem_buf++ = (crc32_pbl >> 8) & 0xff; + *pmem_buf++ = (crc32_pbl) & 0xff; + mem_byte_cnt += 4; + + if (((mem_byte_cnt) % 16) != 0) { + for (i = 0; i < 8; i++) { + *pmem_buf++ = 0x0; + mem_byte_cnt++; + } + } + if ((mem_byte_cnt % 16 != 0)) { + printf("Error: Bad size of image file\n"); + exit(EXIT_FAILURE); + } + +} + +void pbl_load_uboot(int ifd, struct mkimage_params *params) +{ + FILE *fp_uboot; + int size; + + /* parse the pblimage.cfg file. */ + pbl_parser(params->imagename); + + fp_uboot = fopen(params->datafile, "r"); + if (fp_uboot == NULL) { + printf("Error: %s open failed\n", params->datafile); + exit(EXIT_FAILURE); + } + + load_uboot(fp_uboot); + add_end_cmd(); + fclose(fp_uboot); + lseek(ifd, 0, SEEK_SET); + + size = mem_byte_cnt; + if (write(ifd, (const void *)&mem_buf, size) != size) { + fprintf(stderr, "Write error on %s: %s\n", + params->imagefile, strerror(errno)); + exit(EXIT_FAILURE); + } +} + +static int pblimage_check_image_types(uint8_t type) +{ + if (type == IH_TYPE_PBLIMAGE) + return EXIT_SUCCESS; + else + return EXIT_FAILURE; +} + +static int pblimage_verify_header(unsigned char *ptr, int image_size, + struct mkimage_params *params) +{ + + struct pbl_header *pbl_hdr = (struct pbl_header *) ptr; + + /* Only a few checks can be done: search for magic numbers */ + if (ENDIANNESS == 'l') { + if (pbl_hdr->preamble != reverse_byte(RCW_PREAMBLE)) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != reverse_byte(RCW_HEADER)) + return -FDT_ERR_BADSTRUCTURE; + } else { + if (pbl_hdr->preamble != RCW_PREAMBLE) + return -FDT_ERR_BADSTRUCTURE; + + if (pbl_hdr->rcwheader != RCW_HEADER) + return -FDT_ERR_BADSTRUCTURE; + } + + return 0; +} + +static void pblimage_print_header(const void *ptr) +{ + printf("Image Type: Freescale pbl Boot Image\n"); +} + +static void pblimage_set_header(void *ptr, struct stat *sbuf, int ifd, + struct mkimage_params *params) +{ + /*nothing need to do, pbl_load_uboot takes care of whole file. */ +} + +/* + * pblimage parameters + */ +static struct image_type_params pblimage_params = { + .name = "Freescale PBL Boot Image support", + .header_size = sizeof(struct pbl_header), + .hdr = (void *)&pblimage_header, + .check_image_type = pblimage_check_image_types, + .verify_header = pblimage_verify_header, + .print_header = pblimage_print_header, + .set_header = pblimage_set_header, +}; + +void init_pbl_image_type(void) +{ + mem_byte_cnt = 0; + mkimage_register(&pblimage_params); +} diff --git a/tools/pblimage.h b/tools/pblimage.h new file mode 100644 index 0000000..887d4c9 --- /dev/null +++ b/tools/pblimage.h @@ -0,0 +1,36 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PBLIMAGE_H_ +#define _PBLIMAGE_H_ + +#define RCW_BYTES 64 +#define RCW_PREAMBLE 0xaa55aa55 +#define RCW_HEADER 0x010e0100 + +struct pbl_header { + uint32_t preamble; + uint32_t rcwheader; + uint8_t rcw_data[RCW_BYTES]; +}; + +#endif /* _PBLIMAGE_H_ */ -- 1.6.4

3 2

[U-Boot] [PATCH 00/28] Add link-local addressing support
by Joe Hershberger 30 May '12

30 May '12

Link-local support allows the bootloader to get a usable network address regardless of network environment. Given that bootloaders may not always have access to a DHCP server, this functionality makes accessing it in those environments easier. It is also referred to as zero-configuration IP. The following script allows the network to be configured for DHCP, link-local, and static IP addresses configurably by the environment using "dhcpenabled" and "linklocalenabled". #define CONFIG_EXTRA_ENV_SETTINGS \ "ipconfigcmd=if test \\\"$dhcpenabled\\\" -ne 0;" \ "then " \ "dhcpfail=0;dhcp || dhcpfail=1;" \ "else " \ "dhcpfail=-1;" \ "fi;" \ "if test \\\"$linklocalenabled\\\" -ne 0 -a " \ "\\\"$dhcpfail\\\" -ne 0;" \ "then " \ "linklocal;" \ "llfail=0;" \ "else " \ "llfail=-1;" \ "fi;" \ "if test \\\"$llfail\\\" -ne 0 -a " \ "\\\"$dhcpfail\\\" -ne 0; " \ "then " \ "setenv ipaddr $sipaddr; " \ "setenv netmask $snetmask; " \ "setenv gatewayip $sgatewayip; " \ "fi;\0" \ Some refactoring of net/ was done to make adding link-local support cleaner as well as generally improving the readability and organization of the code. Tested on da850_am18xxevm Tested on MPC8313ERDB_33 check-patch No warnings or errors (depends on ignoring CONSIDER_KSTRTO) MAKEALL -a powerpc No additional warnings or errors beyond master MAKEALL -a arm No additional warnings or errors beyond master git-test-sequence Cleanly bisectable Code-size affects on MPC8313ERDB_33 shown below > cat sizeofMCP8313 make BUILD_DIR=/tmp/u-boot-build/ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- USE_PRIVATE_LIBGG=yes distclean > /dev/null && \ make BUILD_DIR=/tmp/u-boot-build/ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- MPC8313ERDB_33_config > /dev/null && \ make BUILD_DIR=/tmp/u-boot-build/ ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnu- USE_PRIVATE_LIBGG=yes > /dev/null && \ powerpc-linux-gnu-size /tmp/u-boot-build/u-boot > git-test-sequence origin/master.. './sizeofMCP8313' Testing ./sizeofMCP8313 HEAD is now at 4dbe8d8 net: Remove volatile from all of net except the eth driver interface text data bss dec hex filename 264917 24880 42104 331901 5107d /tmp/u-boot-build/ppc/u-boot Passed: 90ea672853753b5a4244db60d095e5f99cdcfe7d. Testing ./sizeofMCP8313 HEAD is now at 92893c4 net: cosmetic: checkpatch compliance text data bss dec hex filename 264917 24880 42104 331901 5107d /tmp/u-boot-build/ppc/u-boot Passed: 12b0b6e953406a1ed98d1c4dd9701078d1dfe00d. Testing ./sizeofMCP8313 HEAD is now at d6c19a3 net: Move mv64x6x_eth_initialize() to board_eth_init() text data bss dec hex filename 264917 24880 42104 331901 5107d /tmp/u-boot-build/ppc/u-boot Passed: cf9f493ab5d08a282ec9905797fa58d82b15714d. Testing ./sizeofMCP8313 HEAD is now at 52403e8 net: Make the MAC-seeded random number generator available to /net text data bss dec hex filename 264917 24880 42104 331901 5107d /tmp/u-boot-build/ppc/u-boot Passed: a92c9c9e8f68337a78ee2d7c6775299d7c057b52. Testing ./sizeofMCP8313 HEAD is now at ff86c81 net: Move CDP out of net.c text data bss dec hex filename 264917 24880 42104 331901 5107d /tmp/u-boot-build/ppc/u-boot Passed: 9bf01065cb04c34e43cc5d56162aa2dac9d61f3e. Testing ./sizeofMCP8313 HEAD is now at da1998d net: Move ARP out of net.c text data bss dec hex filename 265045 24928 42104 332077 5112d /tmp/u-boot-build/ppc/u-boot Passed: 621d67b8c6126ef6510d0a2b2c06ce410cd60327. Testing ./sizeofMCP8313 HEAD is now at 408b8ab net: Move PING out of net.c text data bss dec hex filename 265237 24976 42096 332309 51215 /tmp/u-boot-build/ppc/u-boot Passed: e8aaa7382de39137c91809ba2e121f87338627d5. Testing ./sizeofMCP8313 HEAD is now at 1b3ed14 net: Move RARP receive logic out of net.c text data bss dec hex filename 265237 24976 42096 332309 51215 /tmp/u-boot-build/ppc/u-boot Passed: 7a8216874def295337178da67078758cbf909681. Testing ./sizeofMCP8313 HEAD is now at 50eb857 net: cosmetic: Un-typedef variables in net text data bss dec hex filename 265237 24976 42096 332309 51215 /tmp/u-boot-build/ppc/u-boot Passed: b679739af8ffc6f9a31264c175077f4ac96c236d. Testing ./sizeofMCP8313 HEAD is now at 22259f9 net: cosmetic: Improve variable names and code readability text data bss dec hex filename 265237 24976 42096 332309 51215 /tmp/u-boot-build/ppc/u-boot Passed: 834a569897337636fe861797625fbdbbe1373f75. Testing ./sizeofMCP8313 HEAD is now at 5340a18 net: Refactor IP, UPD, and ICMP header writing functions text data bss dec hex filename 265237 24972 42096 332305 51211 /tmp/u-boot-build/ppc/u-boot Passed: 20b84dcfa7d355010cacc3493e1e86521b00879f. Testing ./sizeofMCP8313 HEAD is now at 275e230 net: Refactor packet length computations text data bss dec hex filename 265221 24972 42096 332289 51201 /tmp/u-boot-build/ppc/u-boot Passed: d078d84d959dbb40a67baa16e8b0d210e6472c79. Testing ./sizeofMCP8313 HEAD is now at c1214f2 net: Refactor bootp packet length computations text data bss dec hex filename 265221 24972 42096 332289 51201 /tmp/u-boot-build/ppc/u-boot Passed: 3ff5dfd46c8f70ec2304a150a606871b7504cf42. Testing ./sizeofMCP8313 HEAD is now at 9cff376 net: Refactor ping recieve handler text data bss dec hex filename 265093 24968 42096 332157 5117d /tmp/u-boot-build/ppc/u-boot Passed: e531ec8d3986f45d30862eacce73b0db55e2fb13. Testing ./sizeofMCP8313 HEAD is now at e47e5ac net: Refactor to call NetSendPacket() instead of calling eth_send() text data bss dec hex filename 265093 24968 42096 332157 5117d /tmp/u-boot-build/ppc/u-boot Passed: 4a78d3ab2514c8d00bc18978f7a489a800a3a77b. Testing ./sizeofMCP8313 HEAD is now at 9bcb672 net: Refactor to protect access to the NetState variable text data bss dec hex filename 265109 24956 42096 332161 51181 /tmp/u-boot-build/ppc/u-boot Passed: 8ecfa86d86fe2624cb509c41fbaec8dcf13a9945. Testing ./sizeofMCP8313 HEAD is now at a2c79e3 net: Refactor to separate the UDP handler from the ARP handler text data bss dec hex filename 265317 24956 42112 332385 51261 /tmp/u-boot-build/ppc/u-boot Passed: f66f88edda9ec16b3de20a10faa1c6bb35f316c2. Testing ./sizeofMCP8313 HEAD is now at 502deaa net: Add NetUpdateEther() to handle ARP or Ping replies (VLAN or SNAP) text data bss dec hex filename 265429 24952 42112 332493 512cd /tmp/u-boot-build/ppc/u-boot Passed: 3daff36dc0b5b65b8df7a3a7011f1e5f89eb5a9d. Testing ./sizeofMCP8313 HEAD is now at 315bd4d net: Don't write the "serverip" env var if told not to in the config text data bss dec hex filename 265429 24952 42112 332493 512cd /tmp/u-boot-build/ppc/u-boot Passed: b0e7a73485c771eed710d6b9afd1e80e0ccc2cfa. Testing ./sizeofMCP8313 HEAD is now at 82b1968 net: Fix compile warning if CONFIG_BOOTP_SERVERIP is not defined text data bss dec hex filename 265429 24952 42112 332493 512cd /tmp/u-boot-build/ppc/u-boot Passed: 121eb763232d5cf6a4e66f6c100713537f6036cf. Testing ./sizeofMCP8313 HEAD is now at cebdefe net: Remove unneeded static allocation for MAC address in PingSend() text data bss dec hex filename 265397 24944 42104 332445 5129d /tmp/u-boot-build/ppc/u-boot Passed: 1366a9b1529e9752dd4a47d7c82545b13e11b461. Testing ./sizeofMCP8313 HEAD is now at 8f856ad net: Fix net buffer initialization text data bss dec hex filename 265605 24956 42104 332665 51379 /tmp/u-boot-build/ppc/u-boot Passed: 16cbef4189d5be4837c3de9dc2ac0bcf8d89fa75. Testing ./sizeofMCP8313 HEAD is now at 002991b net: Refactor NetSendUDPPacket to share more code text data bss dec hex filename 265557 24956 42104 332617 51349 /tmp/u-boot-build/ppc/u-boot Passed: 7f001d4025dc564fe2a96a1e32214e194b891bd1. Testing ./sizeofMCP8313 HEAD is now at 314902e net: Don't copy every packet that waits for an ARP text data bss dec hex filename 265573 24956 42104 332633 51359 /tmp/u-boot-build/ppc/u-boot Passed: 3be3cdd2224c88c88442e48c0f4f836d7be1d8ae. Testing ./sizeofMCP8313 HEAD is now at 2a43805 net: Add option CONFIG_BOOTP_CAN_FAIL text data bss dec hex filename 265573 24956 42104 332633 51359 /tmp/u-boot-build/ppc/u-boot Passed: 4d578ba84228e51a56249035207085f0845d3be8. Testing ./sizeofMCP8313 HEAD is now at defb33c net: Add link-local addressing support text data bss dec hex filename 265577 24956 42104 332637 5135d /tmp/u-boot-build/ppc/u-boot Passed: cb6b29e82f292b5b27aec6f51f2f9d50e1f8b0f8. Testing ./sizeofMCP8313 HEAD is now at 615c707 net: Work-around for brain-damaged Cisco routers with arp-proxy text data bss dec hex filename 265657 24956 42104 332717 513ad /tmp/u-boot-build/ppc/u-boot Passed: 63a3ddaf7e029bb7ec71b1edb42473ae6a208dec. Testing ./sizeofMCP8313 HEAD is now at 7d5229d net: Allow filtering on debug traces in the net subsystem text data bss dec hex filename 265594 24948 42104 332646 51366 /tmp/u-boot-build/ppc/u-boot Passed: 1cf14c686c5b60bfa48d8bfd6eb40e20ac0c378b. All's well. Joe Hershberger (28): net: Remove volatile from all of net except the eth driver interface net: cosmetic: checkpatch compliance net: Move mv64x6x_eth_initialize() to board_eth_init() net: Make the MAC-seeded random number generator available to /net net: Move CDP out of net.c net: Move ARP out of net.c net: Move PING out of net.c net: Move RARP receive logic out of net.c net: cosmetic: Un-typedef variables in net net: cosmetic: Improve variable names and code readability net: Refactor IP, UPD, and ICMP header writing functions net: Refactor packet length computations net: Refactor bootp packet length computations net: Refactor ping recieve handler net: Refactor to call NetSendPacket() instead of calling eth_send() net: Refactor to protect access to the NetState variable net: Refactor to separate the UDP handler from the ARP handler net: Add NetUpdateEther() to handle ARP or Ping replies (VLAN or SNAP) net: Don't write the "serverip" env var if told not to in the config net: Fix compile warning if CONFIG_BOOTP_SERVERIP is not defined net: Remove unneeded static allocation for MAC address in PingSend() net: Fix net buffer initialization net: Refactor NetSendUDPPacket to share more code net: Don't copy every packet that waits for an ARP net: Add option CONFIG_BOOTP_CAN_FAIL net: Add link-local addressing support net: Work-around for brain-damaged Cisco routers with arp-proxy net: Allow filtering on debug traces in the net subsystem README | 22 +- arch/powerpc/cpu/mpc8260/ether_fcc.c | 10 +- arch/powerpc/cpu/mpc8xx/fec.c | 2 +- board/Marvell/db64360/db64360.c | 12 +- board/Marvell/db64360/mv_eth.c | 78 ++- board/Marvell/db64360/mv_eth.h | 63 +-- board/Marvell/db64460/db64460.c | 12 +- board/Marvell/db64460/mv_eth.c | 78 ++- board/Marvell/db64460/mv_eth.h | 63 +-- board/esd/cpci750/cpci750.c | 6 + board/esd/cpci750/mv_eth.c | 78 ++- board/esd/cpci750/mv_eth.h | 63 +-- board/prodrive/p3mx/mv_eth.c | 78 ++- board/prodrive/p3mx/mv_eth.h | 63 +-- board/prodrive/p3mx/p3mx.c | 6 + common/cmd_net.c | 34 +- common/main.c | 1 - drivers/net/netconsole.c | 130 ++-- include/common.h | 4 + include/configs/am3517_crane.h | 2 +- include/configs/am3517_evm.h | 2 +- include/configs/origen.h | 2 +- include/net.h | 206 ++++--- net/Makefile | 8 +- net/arp.c | 242 +++++++ net/arp.h | 30 + net/bootp.c | 435 ++++++------- net/bootp.h | 60 +- net/cdp.c | 372 +++++++++++ net/cdp.h | 18 + net/dns.c | 12 +- net/eth.c | 75 +-- net/link_local.c | 340 ++++++++++ net/link_local.h | 21 + net/net.c | 1152 +++++++++------------------------- net/net_rand.c | 68 ++ net/net_rand.h | 18 + net/nfs.c | 306 +++++----- net/nfs.h | 2 +- net/ping.c | 119 ++++ net/ping.h | 20 + net/rarp.c | 77 ++- net/rarp.h | 5 +- net/sntp.c | 37 +- net/sntp.h | 2 +- net/tftp.c | 50 +- net/tftp.h | 2 +- 47 files changed, 2625 insertions(+), 1861 deletions(-) create mode 100644 net/arp.c create mode 100644 net/arp.h create mode 100644 net/cdp.c create mode 100644 net/cdp.h create mode 100644 net/link_local.c create mode 100644 net/link_local.h create mode 100644 net/net_rand.c create mode 100644 net/net_rand.h create mode 100644 net/ping.c create mode 100644 net/ping.h

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[U-Boot] Fastboot gadget, v2. repost
by Sebastian Andrzej Siewior 28 May '12

28 May '12

This is a repost of 19.10.2011. This series contains a small version of the fastboot gadget. I removed the flash/mmc/write to media part and re-add once I'm through with this basic thing :) This "basic" gadget supports the retrieval of variables (like serial number), reboot functionality, download of binary data and booting them in case the binary data is a bootable image. I did not include the fastboot client in this series. Remy asked about this. I could take it and stash it in tools if someone really wants this to have. This would include the fastboot and libzipfile folder from Andorid's system/core repository. An online version can be found at [0]. I haven't seen the library somewhere else than Android. For basic testing, the library could be excluded. v1..v2: fixed all issues that came up so far, including: - s/andoir_img_get_kload/android_img_get_kload/ spotted by Mike - adjusted Copyright message to GPLv2 or later for f_fastboot.c and removed "change" comments. - removed two header files in example patch 3/3 I believe that the "All rights reserved" problem got resolved. [0] http://www.netmite.com/android/mydroid/system/core/ Sebastian

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