January 2012 - U-Boot

[U-Boot] Help needed on Colibri T20 - Iris Board
by Stéphane Carvalho 13 Jan '12

13 Jan '12

We are 2 engineering students from Fribourg, Switzerland working on a embedded systems project. The fact is that we're looking to setup U-Boot on a Colibri Iris Board using the Colibri T20 module with NVIDIA Tegra 2 processor. Since the Iris board is a relatively new board, it is difficult for us to find information about it. We managed to install a recent uboot on the board but it is not very efficient. The major problem is that we aren't able to run the *saveenv*command in order to save the environnement. Does anyone have any ideas about the problem? Or patches to recommend us? We don't have much experience in embedded systems so a little help from you would be much appreciated. Thank you in advance

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[U-Boot] [PATCH v2] sdhc_boot: Introduce CONFIG_FSL_FIXED_MMC_LOCATION option
by Fabio Estevam 13 Jan '12

13 Jan '12

Since commit 97039ab98 (env_mmc: Allow board code to override the environment address) mmc_get_env_addr is a weak-aliased function in common/env_mmc.c The mmc_get_env_addr implementation that exists at board/freescale/common/sdhc_boot.c is meant to be used only for PowerPC boards, but currently it is being used for all platforms that have CONFIG_ENV_IS_IN_MMC defined. Introduce CONFIG_FSL_FIXED_MMC_LOCATION so that the boards that need to use the mmc_get_env_addr version from board/freescale/common/sdhc_boot.c could activate this config option on their board file. This fixes the retrieval of CONFIG_ENV_OFFSET on non-PowerPC boards. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Remove unneeded ifdef from board/freescale/common/sdhc_boot.c board/freescale/common/Makefile | 2 +- include/configs/MPC8536DS.h | 1 + include/configs/P1010RDB.h | 1 + include/configs/P1_P2_RDB.h | 1 + include/configs/P2020COME.h | 1 + include/configs/P2020DS.h | 1 + include/configs/P2041RDB.h | 1 + include/configs/corenet_ds.h | 1 + include/configs/p1_p2_rdb_pc.h | 1 + 9 files changed, 9 insertions(+), 1 deletions(-) diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 9077aaf..0b40dc7 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -39,7 +39,7 @@ COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o COBJS-$(CONFIG_ID_EEPROM) += sys_eeprom.o COBJS-$(CONFIG_FSL_SGMII_RISER) += sgmii_riser.o ifndef CONFIG_RAMBOOT_PBL -COBJS-$(CONFIG_ENV_IS_IN_MMC) += sdhc_boot.o +COBJS-$(CONFIG_FSL_FIXED_MMC_LOCATION) += sdhc_boot.o endif COBJS-$(CONFIG_MPC8541CDS) += cds_pci_ft.o diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 16db98f..c26cb63 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -659,6 +659,7 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #else diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index a9251b4..297cc0a 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -604,6 +604,7 @@ extern unsigned long get_sdram_size(void); #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_RAMBOOT_SPIFLASH) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 00fa74d..916b519 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -519,6 +519,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_RAMBOOT_SPIFLASH) diff --git a/include/configs/P2020COME.h b/include/configs/P2020COME.h index cf20d2b..365322c 100644 --- a/include/configs/P2020COME.h +++ b/include/configs/P2020COME.h @@ -350,6 +350,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #if defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_RAMBOOT_SPIFLASH) diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 2d9657a..f0eb029 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -596,6 +596,7 @@ */ #if defined(CONFIG_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_SPIFLASH) diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index a48055e..da98f8f 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -92,6 +92,7 @@ #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC + #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1097) diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 7925b95..77dd0a2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -88,6 +88,7 @@ #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1097) diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 9297dd0..57170da 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -726,6 +726,7 @@ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_RAMBOOT_SDCARD) #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 #elif defined(CONFIG_NAND_U_BOOT) -- 1.7.1

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[U-Boot] u-boot-imx on Freescale MX28EVK
by Matthias Fuchs 13 Jan '12

13 Jan '12

Hi Fabio, can you confirm that the current u-boot-imx tree runs fine on the MX28EVK? I tried it but the debug console stays dead. This is what I did: 1) make mx28evk 2) make u-boot.sb 3) ./tools/mxsboot sd u-boot.sb u-boot-sd.sb 4) prepare an SD card as described in doc/README.m28 (only one partition of type 53) 5) dd u-boot-sd.sb to above partition 6) install SD and press power button BTW: Did you ever try Freescales sd_loader to download u-boot into RAM? FYI: There also seems to be a Linux version of the USB loader (http://svn.rockbox.org/viewvc.cgi/trunk/utils/imxtools/). Best regards, Matthias

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[U-Boot] [PATCH 2/3] ARM: AM33XX: Add AM33XX I2C driver support
by Patil, Rachna 13 Jan '12

13 Jan '12

1. Compliant with Philips I2C specification version 2.1 2. Supports upto 100Kbps in standard mode. Signed-off-by: Chandan Nath <chandan.nath(a)ti.com> Signed-off-by: Patil, Rachna <rachna(a)ti.com> --- drivers/i2c/omap24xx_i2c.c | 20 +++++++++++++------- 1 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 88e26b2..ac381a5 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -142,7 +142,7 @@ static void flush_fifo(void) stat = readw(&i2c_base->stat); if (stat == I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ - defined(CONFIG_OMAP44XX) + defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) readb(&i2c_base->data); #else readw(&i2c_base->data); @@ -246,7 +246,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) switch (alen) { case 2: /* Send address MSByte */ -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_AM33XX) writew(((addr >> 8) & 0xFF), &i2c_base->data); /* Clearing XRDY event */ @@ -263,7 +264,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } #endif case 1: -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_AM33XX) /* Send address LSByte */ writew((addr & 0xFF), &i2c_base->data); #else @@ -313,7 +315,8 @@ int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) } if (status & I2C_STAT_RRDY) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_AM33XX) buffer[i] = readb(&i2c_base->data); #else *((u16 *)&buffer[i]) = @@ -404,7 +407,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) if (!i2c_error) { if (status & I2C_STAT_XRDY) { switch (alen) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_AM33XX) case 2: /* send out MSB byte */ writeb(((addr >> 8) & 0xFF), &i2c_base->data); @@ -424,7 +428,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) break; } case 1: -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_AM33XX) /* send out MSB byte */ writeb((addr & 0xFF), &i2c_base->data); #else @@ -446,7 +451,8 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) if (!i2c_error) { for (i = ((alen > 1) ? 0 : 1); i < len; i++) { if (status & I2C_STAT_XRDY) { -#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ + defined(CONFIG_AM33XX) writeb((buffer[i] & 0xFF), &i2c_base->data); #else -- 1.7.1

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Re: [U-Boot] [PATCH 7/7] tegra: Enable I2C on Seaboard
by Simon Glass 13 Jan '12

13 Jan '12

+U-Boot, which I seemed to have dropped by mistake Hi Stephen, On Thu, Jan 12, 2012 at 10:59 AM, Stephen Warren <swarren(a)nvidia.com> wrote: > Simon Glass wrote at Wednesday, January 11, 2012 8:00 PM: >> On Mon, Jan 9, 2012 at 1:45 PM, Stephen Warren <swarren(a)nvidia.com> wrote: >> > On 12/26/2011 11:11 AM, Simon Glass wrote: >> >> This enables I2C on Seaboard. >> > ... >> >> diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h >> > ... >> >> +#define CONFIG_SYS_I2C_INIT_BOARD >> > >> > I don't think that option is correct for Seaboard; the description in >> > the README indicates this causes a function named i2c_init_board() to be >> > called from boards/xxx/board.c, which is supposed to use GPIOs to unhang >> > the I2C bus. However, this raises a couple of issues: >> > >> > 1) Patch 5 in this series calls i2c_init_board() ifdef CONFIG_TEGRA2_I2C >> > rather than depending on this CONFIG option. >> > >> > 2) Tegra's i2c_init_board() doesn't appear to be anything to do with bus >> > unhanging, but is instead regular I2C initialization. Perhaps the >> > function should be renamed? >> >> I have had a bit of a look at this. From what I can see the problem is >> that i2c_init() is passed a bus speed, but this is just >> CONFIG_SYS_I2C_SPEED. We want to control the speed individually for >> each port. Yes would could use i2c_init() and ignore the speed, but >> that seems odd also. At least with the way it is we don't ignore the >> setting. >> >> We also don't define CONFIG_HARD_I2C which again seems odd, but I >> suppose is for the same reason (we don't want to call i2c_init()). > > Hmm. It sounds like we should replace CONFIG_TEGRA2_I2C with > CONFIG_HARD_I2C given the README description of the latter? Well we could, but we would need to ignore the speed argument. Do you think that is better? > >> Also U-Boot tends to call i2c_init() before every use of i2c, whereas >> we just want to init once and be done with it. >> >> I think the function name is correct, but perhaps I should change the >> #ifdef you mention in 1 above to CONFIG_SYS_I2C_INIT_BOARD. But for >> i2c to function on Tegra boards, this must be defined, so in fact this >> might be counterproductive. So perhaps a check that it is defined is >> best? > > But README explicitly says that i2c_init_board() is for bus unhanging > which isn't what the Tegra implementation does. How can the function > name be correct given that? > Well we should rename the function IMO. It seems to me that with a a name like that it is for initing i2c on the board. > Don't we just want to make i2c_init() use a global/static variable to > determine whether the device has already been initialized, and defer all > the init until first usage or something like that? That seems in line > with U-Boot's desire not to initialize drivers until they're actually > used. Actually that might work - if we keep i2c_init() a no-op, and wait until we get a request for a bus before we look up the fdt and init that port. But I suspect we might need to init port 0 immediately since there is no explicit call to i2c_set_bus_num() for that. It's a little wonky whatever we do. What do you think? (have just sent the series again with fdt changes, but can update once we sort this out). Regards, Simon

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[U-Boot] [PATCH 1/8] powerpc/srio: Correct the register defined errors in the struct ccsr_rio_t
by Liu Gang 13 Jan '12

13 Jan '12

Many registers were not defined in the struct ccsr_rio_t in the file arch/powerpc/include/asm/immap_85xx.h. For example it lacks registers from offset 0xc0600 to 0xd0160. Accordingly, some register's offset need to be modified in the struct. In addition, add the register's offset in the comments. Signed-off-by: Liu Gang <Gang.Liu(a)freescale.com> --- arch/powerpc/include/asm/immap_85xx.h | 338 ++++++++++++++++++++------------- 1 files changed, 202 insertions(+), 136 deletions(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 92da130..623be17 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -1355,168 +1355,234 @@ typedef struct ccsr_cpm { /* RapidIO Registers */ typedef struct ccsr_rio { - u32 didcar; /* Device Identity Capability */ - u32 dicar; /* Device Information Capability */ - u32 aidcar; /* Assembly Identity Capability */ - u32 aicar; /* Assembly Information Capability */ - u32 pefcar; /* Processing Element Features Capability */ - u32 spicar; /* Switch Port Information Capability */ - u32 socar; /* Source Operations Capability */ - u32 docar; /* Destination Operations Capability */ + u32 didcar; /* 0xc0000 - Device Identity CAR */ + u32 dicar; /* 0xc0004 - Device Information CAR */ + u32 aidcar; /* 0xc0008 - Assembly Identity CAR */ + u32 aicar; /* 0xc000c - Assembly Information CAR */ + u32 pefcar; /* 0xc0010 - Processing Element Features CAR */ + u32 spicar; /* 0xc0014 - Switch Port Information CAR */ + u32 socar; /* 0xc0018 - Source Operations CAR */ + u32 docar; /* 0xc001c - Destination Operations CAR */ u8 res1[32]; - u32 msr; /* Mailbox Cmd And Status */ - u32 pwdcsr; /* Port-Write & Doorbell Cmd And Status */ + u32 mcsr; /* 0xc0040 - Mailbox CSR */ + u32 pwdcsr; /* 0xc0044 - Port-Write and Doorbell CSR */ u8 res2[4]; - u32 pellccsr; /* Processing Element Logic Layer CCSR */ + u32 pellccsr; /* 0xc004c - Processing Element Logic Layer CCSR */ u8 res3[12]; - u32 lcsbacsr; /* Local Cfg Space Base Addr Cmd & Status */ - u32 bdidcsr; /* Base Device ID Cmd & Status */ + u32 lcsbacsr; /* 0xc005c - Local Configuration Space BACSR */ + u32 bdidcsr; /* 0xc0060 - Base Device ID CSR */ u8 res4[4]; - u32 hbdidlcsr; /* Host Base Device ID Lock Cmd & Status */ - u32 ctcsr; /* Component Tag Cmd & Status */ + u32 hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock CSR */ + u32 ctcsr; /* 0xc006c - Component Tag CSR */ u8 res5[144]; - u32 pmbh0csr; /* Port Maint. Block Hdr 0 Cmd & Status */ + u32 pmbh0csr; /* 0xc0100 - Port Maintenance Block Header 0 CSR */ u8 res6[28]; - u32 pltoccsr; /* Port Link Time-out Ctrl Cmd & Status */ - u32 prtoccsr; /* Port Response Time-out Ctrl Cmd & Status */ + u32 pltoccsr; /* 0xc0120 - Port Link Time-out CCSR */ + u32 prtoccsr; /* 0xc0124 - Port Response Time-out CCSR */ u8 res7[20]; - u32 pgccsr; /* Port General Cmd & Status */ - u32 plmreqcsr; /* Port Link Maint. Request Cmd & Status */ - u32 plmrespcsr; /* Port Link Maint. Response Cmd & Status */ - u32 plascsr; /* Port Local Ackid Status Cmd & Status */ + u32 pgccsr; /* 0xc013c - Port General CSR */ + u32 plmreqcsr; /* 0xc0140 - Port Link Maintenance Request CSR */ + u32 plmrespcsr; /* 0xc0144 - Port Link Maintenance Response CSR */ + u32 plascsr; /* 0xc0148 - Port Local Ackid Status CSR */ u8 res8[12]; - u32 pescsr; /* Port Error & Status Cmd & Status */ - u32 pccsr; /* Port Control Cmd & Status */ - u8 res9[65184]; - u32 cr; /* Port Control Cmd & Status */ - u8 res10[12]; - u32 pcr; /* Port Configuration */ - u32 peir; /* Port Error Injection */ - u8 res11[3048]; - u32 rowtar0; /* RIO Outbound Window Translation Addr 0 */ - u8 res12[12]; - u32 rowar0; /* RIO Outbound Attrs 0 */ + u32 pescsr; /* 0xc0158 - Port Error and Status CSR */ + u32 pccsr; /* 0xc015c - Port Control CSR */ + u8 res9[1184]; + u32 erbh; /* 0xc0600 - Error Reporting Block Header Register */ + u8 res10[4]; + u32 ltledcsr; /* 0xc0608 - Logical/Transport layer error DCSR */ + u32 ltleecsr; /* 0xc060c - Logical/Transport layer error ECSR */ + u8 res11[4]; + u32 ltlaccsr; /* 0xc0614 - Logical/Transport layer ACCSR */ + u32 ltldidccsr; /* 0xc0618 - Logical/Transport layer DID CCSR */ + u32 ltlcccsr; /* 0xc061c - Logical/Transport layer control CCSR */ + u8 res12[32]; + u32 edcsr; /* 0xc0640 - Port 0 error detect CSR */ + u32 erecsr; /* 0xc0644 - Port 0 error rate enable CSR */ + u32 ecacsr; /* 0xc0648 - Port 0 error capture attributes CSR */ + u32 pcseccsr0; /* 0xc064c - Port 0 packet/control symbol ECCSR 0 */ + u32 peccsr1; /* 0xc0650 - Port 0 error capture CSR 1 */ + u32 peccsr2; /* 0xc0654 - Port 0 error capture CSR 2 */ + u32 peccsr3; /* 0xc0658 - Port 0 error capture CSR 3 */ u8 res13[12]; - u32 rowtar1; /* RIO Outbound Window Translation Addr 1 */ - u8 res14[4]; - u32 rowbar1; /* RIO Outbound Window Base Addr 1 */ - u8 res15[4]; - u32 rowar1; /* RIO Outbound Attrs 1 */ + u32 ercsr; /* 0xc0668 - Port 0 error rate CSR */ + u32 ertcsr; /* 0xc066C - Port 0 error rate threshold CSR */ + u8 res14[63892]; + u32 llcr; /* 0xd0004 - Logical Layer Configuration Register */ + u8 res15[8]; + u32 epwisr; /* 0xd0010 - Error / Port-Write Interrupt SR */ u8 res16[12]; - u32 rowtar2; /* RIO Outbound Window Translation Addr 2 */ - u8 res17[4]; - u32 rowbar2; /* RIO Outbound Window Base Addr 2 */ - u8 res18[4]; - u32 rowar2; /* RIO Outbound Attrs 2 */ - u8 res19[12]; - u32 rowtar3; /* RIO Outbound Window Translation Addr 3 */ - u8 res20[4]; - u32 rowbar3; /* RIO Outbound Window Base Addr 3 */ - u8 res21[4]; - u32 rowar3; /* RIO Outbound Attrs 3 */ - u8 res22[12]; - u32 rowtar4; /* RIO Outbound Window Translation Addr 4 */ + u32 lretcr; /* 0xd0020 - Logical Retry Error Threshold CR */ + u8 res17[92]; + u32 pretcr; /* 0xd0080 - Physical Retry Erorr Threshold CR */ + u8 res18[124]; + u32 adidcsr; /* 0xd0100 - Port 0 Alt. Device ID CSR */ + u8 res19[28]; + u32 ptaacr; /* 0xd0120 - Port 0 Pass-Through/Accept-All CR */ + u8 res20[12]; + u32 iecsr; /* 0xd0130 - Port 0 Implementation Error CSR */ + u8 res21[12]; + u32 pcr; /* 0xd0140 - Port 0 Phsyical Configuration Register */ + u8 res22[20]; + u32 slcsr; /* 0xd0158 - Port 0 Serial Link CSR */ u8 res23[4]; - u32 rowbar4; /* RIO Outbound Window Base Addr 4 */ - u8 res24[4]; - u32 rowar4; /* RIO Outbound Attrs 4 */ - u8 res25[12]; - u32 rowtar5; /* RIO Outbound Window Translation Addr 5 */ - u8 res26[4]; - u32 rowbar5; /* RIO Outbound Window Base Addr 5 */ + u32 sleir; /* 0xd0160 - Port 0 Serial Link Error Injection */ + u8 res24[2716]; + u32 rowtar0; /* 0xd0c00 - RapidIO Outbound Window TAR 0 */ + u32 rowtear0; /* 0xd0c04 - RapidIO Outbound Window TEAR 0 */ + u8 res25[8]; + u32 rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ + u8 res26[12]; + u32 rowtar1; /* 0xd0c20 - RapidIO Outbound Window TAR 1 */ + u32 rowtear1; /* 0xd0c24 - RapidIO Outbound Window TEAR 1 */ + u32 rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base AR 1 */ u8 res27[4]; - u32 rowar5; /* RIO Outbound Attrs 5 */ - u8 res28[12]; - u32 rowtar6; /* RIO Outbound Window Translation Addr 6 */ + u32 rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ + u32 rows1r1; /* 0xd0c34 - RapidIO Outbound Window S 1 R1 */ + u32 rows2r1; /* 0xd0c38 - RapidIO Outbound Window S 2 R 1 */ + u32 rows3r1; /* 0xd0c3c - RapidIO Outbound Window S 3 R 1 */ + u32 rowtar2; /* 0xd0c40 - RapidIO Outbound Window TAR 2 */ + u32 rowtear2; /* 0xd0c44 - RapidIO Outbound Window TEAR 2 */ + u32 rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base AR 2 */ + u8 res28[4]; + u32 rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ + u32 rows1r2; /* 0xd0c54 - RapidIO Outbound Window S 1 R 2 */ + u32 rows2r2; /* 0xd0c58 - RapidIO Outbound Window S 2 R 2 */ + u32 rows3r2; /* 0xd0c5c - RapidIO Outbound Window S 3 R 2 */ + u32 rowtar3; /* 0xd0c60 - RapidIO Outbound Window TAR 3 */ + u32 rowtear3; /* 0xd0c64 - RapidIO Outbound Window TEAR 3 */ + u32 rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base AR 3 */ u8 res29[4]; - u32 rowbar6; /* RIO Outbound Window Base Addr 6 */ + u32 rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ + u32 rows1r3; /* 0xd0c74 - RapidIO Outbound Window S 1 R 3 */ + u32 rows2r3; /* 0xd0c78 - RapidIO Outbound Window S 2 R 3 */ + u32 rows3r3; /* 0xd0c7c - RapidIO Outbound Window S 3 R 3 */ + u32 rowtar4; /* 0xd0c80 - RapidIO Outbound Window TAR 4 */ + u32 rowtear4; /* 0xd0c84 - RapidIO Outbound Window TEAR 4 */ + u32 rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base AR 4 */ u8 res30[4]; - u32 rowar6; /* RIO Outbound Attrs 6 */ - u8 res31[12]; - u32 rowtar7; /* RIO Outbound Window Translation Addr 7 */ + u32 rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ + u32 rows1r4; /* 0xd0c94 - RapidIO Outbound Window S 1 R 4 */ + u32 rows2r4; /* 0xd0c98 - RapidIO Outbound Window S 2 R 4 */ + u32 rows3r4; /* 0xd0c9c - RapidIO Outbound Window S 3 R 4 */ + u32 rowtar5; /* 0xd0ca0 - RapidIO Outbound Window TAR 5 */ + u32 rowtear5; /* 0xd0ca4 - RapidIO Outbound Window TEAR 5 */ + u32 rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base AR 5 */ + u8 res31[4]; + u32 rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ + u32 rows1r5; /* 0xd0cb4 - RapidIO Outbound Window S 1 R 5 */ + u32 rows2r5; /* 0xd0cb8 - RapidIO Outbound Window S 2 R 5 */ + u32 rows3r5; /* 0xd0cbc - RapidIO Outbound Window S 3 R 5 */ + u32 rowtar6; /* 0xd0cc0 - RapidIO Outbound Window TAR 6 */ + u32 rowtear6; /* 0xd0cc4 - RapidIO Outbound Window TEAR 6 */ + u32 rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base AR 6 */ u8 res32[4]; - u32 rowbar7; /* RIO Outbound Window Base Addr 7 */ + u32 rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ + u32 rows1r6; /* 0xd0cd4 - RapidIO Outbound Window S 1 R 6 */ + u32 rows2r6; /* 0xd0cd8 - RapidIO Outbound Window S 2 R 6 */ + u32 rows3r6; /* 0xd0cdc - RapidIO Outbound Window S 3 R 6 */ + u32 rowtar7; /* 0xd0ce0 - RapidIO Outbound Window TAR 7 */ + u32 rowtear7; /* 0xd0ce4 - RapidIO Outbound Window TEAR 7 */ + u32 rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base AR 7 */ u8 res33[4]; - u32 rowar7; /* RIO Outbound Attrs 7 */ - u8 res34[12]; - u32 rowtar8; /* RIO Outbound Window Translation Addr 8 */ - u8 res35[4]; - u32 rowbar8; /* RIO Outbound Window Base Addr 8 */ + u32 rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ + u32 rows1r7; /* 0xd0cf4 - RapidIO Outbound Window S 1 R 7 */ + u32 rows2r7; /* 0xd0cf8 - RapidIO Outbound Window S 2 R 7 */ + u32 rows3r7; /* 0xd0cfc - RapidIO Outbound Window S 3 R 7 */ + u32 rowtar8; /* 0xd0d00 - RapidIO Outbound Window TAR 8 */ + u32 rowtear8; /* 0xd0d04 - RapidIO Outbound Window TEAR 8 */ + u32 rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base AR 8 */ + u8 res34[4]; + u32 rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ + u32 rows1r8; /* 0xd0d14 - RapidIO Outbound Window S 1 R 8 */ + u32 rows2r8; /* 0xd0d18 - RapidIO Outbound Window S 2 R 8 */ + u32 rows3r8; /* 0xd0d1c - RapidIO Outbound Window S 3 R 8 */ + u8 res35[64]; + u32 riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation AR 4 */ + u8 res59[4]; + u32 riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base AR 4 */ u8 res36[4]; - u32 rowar8; /* RIO Outbound Attrs 8 */ - u8 res37[76]; - u32 riwtar4; /* RIO Inbound Window Translation Addr 4 */ + u32 riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ + u8 res37[12]; + u32 riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation AR 3 */ u8 res38[4]; - u32 riwbar4; /* RIO Inbound Window Base Addr 4 */ + u32 riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base AR 3 */ u8 res39[4]; - u32 riwar4; /* RIO Inbound Attrs 4 */ + u32 riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ u8 res40[12]; - u32 riwtar3; /* RIO Inbound Window Translation Addr 3 */ + u32 riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation AR 2 */ u8 res41[4]; - u32 riwbar3; /* RIO Inbound Window Base Addr 3 */ + u32 riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base AR 2 */ u8 res42[4]; - u32 riwar3; /* RIO Inbound Attrs 3 */ + u32 riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ u8 res43[12]; - u32 riwtar2; /* RIO Inbound Window Translation Addr 2 */ + u32 riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation AR 1 */ u8 res44[4]; - u32 riwbar2; /* RIO Inbound Window Base Addr 2 */ + u32 riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base AR 1 */ u8 res45[4]; - u32 riwar2; /* RIO Inbound Attrs 2 */ + u32 riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ u8 res46[12]; - u32 riwtar1; /* RIO Inbound Window Translation Addr 1 */ - u8 res47[4]; - u32 riwbar1; /* RIO Inbound Window Base Addr 1 */ - u8 res48[4]; - u32 riwar1; /* RIO Inbound Attrs 1 */ - u8 res49[12]; - u32 riwtar0; /* RIO Inbound Window Translation Addr 0 */ - u8 res50[12]; - u32 riwar0; /* RIO Inbound Attrs 0 */ - u8 res51[12]; - u32 pnfedr; /* Port Notification/Fatal Error Detect */ - u32 pnfedir; /* Port Notification/Fatal Error Detect */ - u32 pnfeier; /* Port Notification/Fatal Error IRQ Enable */ - u32 pecr; /* Port Error Control */ - u32 pepcsr0; /* Port Error Packet/Control Symbol 0 */ - u32 pepr1; /* Port Error Packet 1 */ - u32 pepr2; /* Port Error Packet 2 */ - u8 res52[4]; - u32 predr; /* Port Recoverable Error Detect */ - u8 res53[4]; - u32 pertr; /* Port Error Recovery Threshold */ - u32 prtr; /* Port Retry Threshold */ - u8 res54[464]; - u32 omr; /* Outbound Mode */ - u32 osr; /* Outbound Status */ - u32 eodqtpar; /* Extended Outbound Desc Queue Tail Ptr Addr */ - u32 odqtpar; /* Outbound Desc Queue Tail Ptr Addr */ - u32 eosar; /* Extended Outbound Unit Source Addr */ - u32 osar; /* Outbound Unit Source Addr */ - u32 odpr; /* Outbound Destination Port */ - u32 odatr; /* Outbound Destination Attrs */ - u32 odcr; /* Outbound Doubleword Count */ - u32 eodqhpar; /* Extended Outbound Desc Queue Head Ptr Addr */ - u32 odqhpar; /* Outbound Desc Queue Head Ptr Addr */ - u8 res55[52]; - u32 imr; /* Outbound Mode */ - u32 isr; /* Inbound Status */ - u32 eidqtpar; /* Extended Inbound Desc Queue Tail Ptr Addr */ - u32 idqtpar; /* Inbound Desc Queue Tail Ptr Addr */ - u32 eifqhpar; /* Extended Inbound Frame Queue Head Ptr Addr */ - u32 ifqhpar; /* Inbound Frame Queue Head Ptr Addr */ - u8 res56[1000]; - u32 dmr; /* Doorbell Mode */ - u32 dsr; /* Doorbell Status */ - u32 edqtpar; /* Extended Doorbell Queue Tail Ptr Addr */ - u32 dqtpar; /* Doorbell Queue Tail Ptr Addr */ - u32 edqhpar; /* Extended Doorbell Queue Head Ptr Addr */ - u32 dqhpar; /* Doorbell Queue Head Ptr Addr */ - u8 res57[104]; - u32 pwmr; /* Port-Write Mode */ - u32 pwsr; /* Port-Write Status */ - u32 epwqbar; /* Extended Port-Write Queue Base Addr */ - u32 pwqbar; /* Port-Write Queue Base Addr */ - u8 res58[60176]; + u32 riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation AR 0 */ + u8 res47[12]; + u32 riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ + u8 res48[12]; + u32 pnfedr; /* 0xd0e00 - Port Notification/Fatal Error DR */ + u32 pnfedir; /* 0xd0e04 - Port Notification/Fatal Error DR */ + u32 pnfeier; /* 0xd0e08 - Port Notification/Fatal Error IER */ + u32 pecr; /* 0xd0e0c - Port Error Control Register */ + u32 pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol 0 */ + u32 pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ + u32 pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ + u8 res49[4]; + u32 predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ + u8 res50[4]; + u32 pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ + u32 prtr; /* 0xd0e2c - Port Retry Threshold Register */ + u8 res51[8656]; + u32 omr; /* 0xd3000 - Outbound Mode Register */ + u32 osr; /* 0xd3004 - Outbound Status Register */ + u32 eodqdpar; /* 0xd3008 - Extended Outbound DQ DPAR */ + u32 odqdpar; /* 0xd300c - Outbound Descriptor Queue DPAR */ + u32 eosar; /* 0xd3010 - Extended Outbound Unit Source AR */ + u32 osar; /* 0xd3014 - Outbound Unit Source AR */ + u32 odpr; /* 0xd3018 - Outbound Destination Port Register */ + u32 odatr; /* 0xd301c - Outbound Destination Attributes Register */ + u32 odcr; /* 0xd3020 - Outbound Doubleword Count Register */ + u32 eodqepar; /* 0xd3024 - Extended Outbound DQ EPAR */ + u32 odqepar; /* 0xd3028 - Outbound Descriptor Queue EPAR */ + u32 oretr; /* 0xd302C - Outbound Retry Error Threshold Register */ + u32 omgr; /* 0xd3030 - Outbound Multicast Group Register */ + u32 omlr; /* 0xd3034 - Outbound Multicast List Register */ + u8 res52[40]; + u32 imr; /* 0xd3060 - Outbound Mode Register */ + u32 isr; /* 0xd3064 - Inbound Status Register */ + u32 eidqdpar; /* 0xd3068 - Extended Inbound Descriptor Queue DPAR */ + u32 idqdpar; /* 0xd306c - Inbound Descriptor Queue DPAR */ + u32 eifqepar; /* 0xd3070 - Extended Inbound Frame Queue EPAR */ + u32 ifqepar; /* 0xd3074 - Inbound Frame Queue EPAR */ + u32 imirir; /* 0xd3078 - Inbound Maximum Interrutp RIR */ + u8 res53[900]; + u32 oddmr; /* 0xd3400 - Outbound Doorbell Mode Register */ + u32 oddsr; /* 0xd3404 - Outbound Doorbell Status Register */ + u8 res54[16]; + u32 oddpr; /* 0xd3418 - Outbound Doorbell Destination Port */ + u32 oddatr; /* 0xd341C - Outbound Doorbell Destination AR */ + u8 res55[12]; + u32 oddretr; /* 0xd342C - Outbound Doorbell Retry Threshold CR */ + u8 res56[48]; + u32 idmr; /* 0xd3460 - Inbound Doorbell Mode Register */ + u32 idsr; /* 0xd3464 - Inbound Doorbell Status Register */ + u32 iedqdpar; /* 0xd3468 - Extended Inbound Doorbell Queue DPAR */ + u32 iqdpar; /* 0xd346c - Inbound Doorbell Queue DPAR */ + u32 iedqepar; /* 0xd3470 - Extended Inbound Doorbell Queue EPAR */ + u32 idqepar; /* 0xd3474 - Inbound Doorbell Queue EPAR */ + u32 idmirir; /* 0xd3478 - Inbound Doorbell Max Interrupt RIR */ + u8 res57[100]; + u32 pwmr; /* 0xd34e0 - Port-Write Mode Register */ + u32 pwsr; /* 0xd34e4 - Port-Write Status Register */ + u32 epwqbar; /* 0xd34e8 - Extended Port-Write Queue BAR */ + u32 pwqbar; /* 0xd34ec - Port-Write Queue Base Address Register */ + u8 res58[51984]; } ccsr_rio_t; /* Quick Engine Block Pin Muxing Registers */ -- 1.7.3.1

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[U-Boot] [PATCH] cmd_source: introduce run_script()
by Michael Walle 12 Jan '12

12 Jan '12

Move actual script execution into a new function run_script(), which then can be called from other modules. Signed-off-by: Michael Walle <michael(a)walle.cc> Cc: Wolfgang Denk <wd(a)denx.de> --- common/cmd_source.c | 71 ++++++++++++++++++++++++++++---------------------- include/common.h | 1 + 2 files changed, 41 insertions(+), 31 deletions(-) diff --git a/common/cmd_source.c b/common/cmd_source.c index 16a627a..4b2740b 100644 --- a/common/cmd_source.c +++ b/common/cmd_source.c @@ -43,6 +43,45 @@ #include <hush.h> #endif +/* + * Run a series of commands, separated by '\n'. + * Beware, the contents of script may be modified while it is parsed. + */ +int run_script(char *script) +{ +#ifndef CONFIG_SYS_HUSH_PARSER /*?? */ + int rcode; + char *line = script; + char *next = script; + + /* + * break into individual lines and execute each line; + * terminate on error. + */ + while (*next) { + if (*next == '\n') { + *next = '\0'; + /* run only non-empty commands */ + if (*line) { + debug("** exec: \"%s\"\n", line); + if (run_command(line, 0) < 0) { + rcode = 1; + break; + } + } + line = next + 1; + } + ++next; + } + + if (rcode == 0 && *line) + rcode = (run_command(line, 0) >= 0); + return rcode; +#else + return parse_string_outer(script, FLAG_PARSE_SEMICOLON); +#endif +} + int source (ulong addr, const char *fit_uname) { @@ -160,38 +199,8 @@ source (ulong addr, const char *fit_uname) memmove (cmd, (char *)data, len); *(cmd + len) = 0; -#ifdef CONFIG_SYS_HUSH_PARSER /*?? */ - rcode = parse_string_outer (cmd, FLAG_PARSE_SEMICOLON); -#else - { - char *line = cmd; - char *next = cmd; + rcode = run_script(cmd); - /* - * break into individual lines, - * and execute each line; - * terminate on error. - */ - while (*next) { - if (*next == '\n') { - *next = '\0'; - /* run only non-empty commands */ - if (*line) { - debug ("** exec: \"%s\"\n", - line); - if (run_command (line, 0) < 0) { - rcode = 1; - break; - } - } - line = next + 1; - } - ++next; - } - if (rcode == 0 && *line) - rcode = (run_command(line, 0) >= 0); - } -#endif free (cmd); return rcode; } diff --git a/include/common.h b/include/common.h index 3df1def..dcfbed6 100644 --- a/include/common.h +++ b/include/common.h @@ -296,6 +296,7 @@ void board_pre_console_putc(int ch); void flash_perror (int); /* common/cmd_source.c */ +int run_script(char *script); int source (ulong addr, const char *fit_uname); extern ulong load_addr; /* Default Load Address */ -- 1.7.2.5

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[U-Boot] Please pull u-boot-ti/master
by Tom Rini 12 Jan '12

12 Jan '12

Hi Albert, This replaces the pull request I sent for u-boot-ti/next back around Dec 23rd that wasn't pulled. The following changes since commit a747cc0a8c55d69a56a6db80a35cdb48c853447d: Thierry Reding (1): tegra2: Optimize out-of-tree build for Ventana. are available in the git repository at: git://git.denx.de/u-boot-ti.git master Aneesh V (1): omap4: fix boot issue on ES2.0 Panda Christian Riesch (3): arm, davinci: Use a common configuration file for da850evm and da850_am18xxevm da850evm: Remove CONFIG_SYS_xxCACHE_OFF defines arm, davinci: Change byte order of RTC kick register values Peter Barada (1): ARMV7: Add support For Logic OMAP35x/DM37x modules Peter Meerwald (1): beagle: add eeprom expansion board info for bct brettl3 Thomas Weber (1): OMAP3: Remove unused define CONFIG_OMAP3_*_DDR MAINTAINERS | 4 + arch/arm/cpu/armv7/omap4/hwinit.c | 4 +- arch/arm/include/asm/arch-davinci/hardware.h | 4 +- arch/arm/include/asm/arch-omap4/omap.h | 2 +- board/enbw/enbw_cmc/enbw_cmc.c | 4 +- board/logicpd/omap3som/Makefile | 42 +++ board/logicpd/omap3som/omap3logic.c | 247 ++++++++++++++++++ board/logicpd/omap3som/omap3logic.h | 47 ++++ board/ti/beagle/beagle.c | 4 + boards.cfg | 3 +- include/configs/cm_t35.h | 3 - include/configs/da850_am18xxevm.h | 246 ----------------- include/configs/da850evm.h | 3 - include/configs/dig297.h | 3 - include/configs/igep0020.h | 3 - include/configs/igep0030.h | 3 - include/configs/omap3_logic.h | 362 ++++++++++++++++++++++++++ include/configs/omap3_mvblx.h | 3 - include/configs/omap3_overo.h | 3 - include/configs/omap3_pandora.h | 3 - include/configs/omap3_sdp3430.h | 3 - include/configs/omap3_zoom1.h | 3 - include/configs/omap3_zoom2.h | 3 - 23 files changed, 715 insertions(+), 287 deletions(-) create mode 100644 board/logicpd/omap3som/Makefile create mode 100644 board/logicpd/omap3som/omap3logic.c create mode 100644 board/logicpd/omap3som/omap3logic.h delete mode 100644 include/configs/da850_am18xxevm.h create mode 100644 include/configs/omap3_logic.h -- Tom

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[U-Boot] [GIT PULL] Pull request: u-boot-imx
by Stefano Babic 12 Jan '12

12 Jan '12

Hi Albert, please pull from u-boot-imx, thanks. The following changes since commit a747cc0a8c55d69a56a6db80a35cdb48c853447d: tegra2: Optimize out-of-tree build for Ventana. (2011-12-24 10:23:32 +0100) are available in the git repository at: git://www.denx.de/git/u-boot-imx.git master Eric Nelson (1): i.mx6q: mx6qarm2: Enable the usboh3 clock Fabio Estevam (6): net: imx: Add multi-FEC support for imx_get_mac_from_fuse mx28: Let imx_get_mac_from_fuse be common for mx28 mx28: Let dram_init be common for mx28 mx28evk: Add initial support for MX28EVK board mx28evk: Remove 'all' target from Makefile m28evk: Use GENERATED_GBL_DATA_SIZE Jason Liu (4): i.mx: i.mx6q: Add the enet clock function fec: add the i.mx6q enet driver support i.mx6q: arm2: Add the enet function support i.mx6:imx6q: allign MAC address with burned-in ordering Marek Vasut (1): MX28: Fix MXSBOOT segfault if no params specified Veli-Pekka Peltola (1): mx28: remove omap specific config options MAINTAINERS | 1 + arch/arm/cpu/arm1136/mx35/generic.c | 2 +- arch/arm/cpu/arm926ejs/mx25/generic.c | 2 +- arch/arm/cpu/arm926ejs/mx27/generic.c | 2 +- arch/arm/cpu/arm926ejs/mx28/mx28.c | 67 +++++++++++ arch/arm/cpu/arm926ejs/mx28/start.S | 6 - arch/arm/cpu/armv7/mx6/clock.c | 5 + arch/arm/cpu/armv7/mx6/soc.c | 16 ++- arch/arm/include/asm/arch-mx28/sys_proto.h | 2 + arch/arm/include/asm/arch-mx6/imx-regs.h | 4 +- board/denx/m28evk/m28evk.c | 53 +-------- board/freescale/mx28evk/Makefile | 47 ++++++++ board/freescale/mx28evk/iomux.c | 138 ++++++++++++++++++++++ board/freescale/mx28evk/mx28evk.c | 169 ++++++++++++++++++++++++++ board/freescale/mx28evk/u-boot.bd | 14 +++ board/freescale/mx6qarm2/imximage.cfg | 2 +- board/freescale/mx6qarm2/mx6qarm2.c | 90 ++++++++++++++ boards.cfg | 1 + drivers/net/fec_mxc.c | 19 +++- drivers/net/fec_mxc.h | 9 +- include/configs/m28evk.h | 9 ++- include/configs/mx28evk.h | 176 ++++++++++++++++++++++++++++ include/configs/mx6qarm2.h | 12 ++- tools/mxsboot.c | 3 + 24 files changed, 769 insertions(+), 80 deletions(-) create mode 100644 board/freescale/mx28evk/Makefile create mode 100644 board/freescale/mx28evk/iomux.c create mode 100644 board/freescale/mx28evk/mx28evk.c create mode 100644 board/freescale/mx28evk/u-boot.bd create mode 100644 include/configs/mx28evk.h -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot] LL TEMAC V7 refactored
by Stephan Linz 12 Jan '12

12 Jan '12

Back to the discussion from August and November I have refactored the LL TEMAC driver. Just in version V7 it is ready to next review. Thanks to Marek and Wolfgang to review V4..6. Note: To use the driver on Microblaze, you will need additional platform patches by Michal Simek: - http://patchwork.ozlabs.org/patch/112535/ - http://patchwork.ozlabs.org/patch/112534/ - http://patchwork.ozlabs.org/patch/112532/ I will collect all related patches on a public bundle: - http://patchwork.ozlabs.org/bundle/rexut/net-ll_temac/

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