August 2011 - U-Boot

[U-Boot] Problems using vxboot
by Reinhard Arlt 10 Aug '11

10 Aug '11

Hello, i run into a strange problem booting vxWorks on the cpci750 and vme8349 using u-boot 2011.06. The decrementer slot contains old code. The problem is starting vxWorks with the data cache enabled. The code below fix the problem. It disable (and flush) the data cache, and set the start parameter to cold boot for the vxWorks sysInit(int p0) routine. Is this code acceptable? diff --git a/common/cmd_elf.c b/common/cmd_elf.c index bf32612..c3f0986 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -230,7 +230,8 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) (char *) bootaddr); printf ("## Starting vxWorks at 0x%08lx ...\n", addr); - ((void (*)(void)) addr) (); + dcache_disable(); + ((void (*)(int)) addr) (0); puts ("## vxWorks terminated\n"); return 1; Kind regards Reinhard Arlt

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[U-Boot] [PATCH v4 1/2] gpio: Add GPIO driver framework for Marvell SoCs
by Ajay Bhargav 10 Aug '11

10 Aug '11

This patch adds generic GPIO driver framework support for Marvell SoCs. To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands define CONFIG_CMD_GPIO in your board configuration file. v3 - Added file mvgpio.h for common defines based on CPU core subversion. Arch related stuff should be added to arch/gpio.h Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- drivers/gpio/Makefile | 1 + drivers/gpio/mvgpio.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mvgpio.h | 77 +++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mvgpio.c create mode 100644 include/mvgpio.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 62ec97d..beca1da 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c new file mode 100644 index 0000000..0cc8ed7 --- /dev/null +++ b/drivers/gpio/mvgpio.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/gpio.h> + +#ifndef MV_MAX_GPIO +#define MV_MAX_GPIO 128 +#endif + +int gpio_request(int gp, const char *label) +{ + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO requested %d\n", __func__, gp); + return -EINVAL; + } + return 0; +} + +void gpio_free(int gp) +{ +} + +void gpio_toggle_value(int gp) +{ + gpio_set_value(gp, !gpio_get_value(gp)); +} + +int gpio_direction_input(int gp) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr); + return 0; +} + +int gpio_direction_output(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr); + gpio_set_value(gp, value); + return 0; +} + +int gpio_get_value(int gp) +{ + struct gpio_reg *gpio_reg_bank; + u32 gp_val; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + gp_val = readl(&gpio_reg_bank->gplr); + + return GPIO_VAL(gp, gp_val); +} + +void gpio_set_value(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr); + else + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr); +} diff --git a/include/mvgpio.h b/include/mvgpio.h new file mode 100644 index 0000000..768e94c --- /dev/null +++ b/include/mvgpio.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MVGPIO_H__ +#define __MVGPIO_H__ + +#include <common.h> + +#define GPIO_SET 1 +#define GPIO_CLR 0 + +#ifdef CONFIG_SHEEVA_88SV331xV5 +/* + * GPIO Register map for SHEEVA 88SV331xV5 + */ +struct gpio_reg { + u32 gplr; /* Pin Level Register - 0x0000 */ + u32 pad0[2]; + u32 gpdr; /* Pin Direction Register - 0x000C */ + u32 pad1[2]; + u32 gpsr; /* Pin Output Set Register - 0x0018 */ + u32 pad2[2]; + u32 gpcr; /* Pin Output Clear Register - 0x0024 */ + u32 pad3[2]; + u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ + u32 pad4[2]; + u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ + u32 pad5[2]; + u32 gedr; /* Edge Detect Status Register - 0x0048 */ + u32 pad6[2]; + u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ + u32 pad7[2]; + u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ + u32 pad8[2]; + u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable + Register - 0x006C */ + u32 pad9[2]; + u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable + Register - 0x0078 */ + u32 pad10[2]; + u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable + Register - 0x0084 */ + u32 pad11[2]; + u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable + Register - 0x0090 */ + u32 pad12[2]; + u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ +}; +#else +#error "CPU core subversion not defined" +#endif + +#endif /* __MVGPIO_H__ */ -- 1.7.0.4

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[U-Boot] [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
by Ajay Bhargav 10 Aug '11

10 Aug '11

This patch adds support for generic GPIO driver framework for Marvell SoC Armada100. Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- arch/arm/include/asm/arch-armada100/armada100.h | 4 ++ arch/arm/include/asm/arch-armada100/gpio.h | 54 +++++++++++++++++++++++ 2 files changed, 58 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-armada100/gpio.h diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h index d5d125a..aad3ed1 100644 --- a/arch/arm/include/asm/arch-armada100/armada100.h +++ b/arch/arm/include/asm/arch-armada100/armada100.h @@ -59,6 +59,10 @@ #define ARMD1_MPMU_BASE 0xD4050000 #define ARMD1_APMU_BASE 0xD4282800 #define ARMD1_CPU_BASE 0xD4282C00 +#define ARMD1_GPIO0_BASE 0xD4019000 +#define ARMD1_GPIO1_BASE 0xD4019004 +#define ARMD1_GPIO2_BASE 0xD4019008 +#define ARMD1_GPIO3_BASE 0xD4019100 /* * Main Power Management (MPMU) Registers diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h new file mode 100644 index 0000000..bd7d21a --- /dev/null +++ b/arch/arm/include/asm/arch-armada100/gpio.h @@ -0,0 +1,54 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _ASM_ARCH_GPIO_H +#define _ASM_ARCH_GPIO_H + +#include <asm/types.h> +#include <asm/arch/armada100.h> +#include <mvgpio.h> + +#define GPIO_TO_REG(gp) (gp >> 5) +#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F)) +#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01) + +static inline void *get_gpio_base(int bank) +{ + switch (bank) { + case 0: + return (struct gpio_reg *)ARMD1_GPIO0_BASE; + case 1: + return (struct gpio_reg *)ARMD1_GPIO1_BASE; + case 2: + return (struct gpio_reg *)ARMD1_GPIO2_BASE; + case 3: + return (struct gpio_reg *)ARMD1_GPIO3_BASE; + } + return 0; +} + +#endif /* _ASM_ARCH_GPIO_H */ -- 1.7.0.4

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Re: [U-Boot] [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC Armada100
by Ajay Bhargav 10 Aug '11

10 Aug '11

----- "Prafulla Wadaskar" <prafulla(a)marvell.com> wrote: > > -----Original Message----- > > From: Ajay Bhargav [mailto:ajay.bhargav@einfochips.com] > > Sent: Wednesday, August 10, 2011 1:37 PM > > To: Prafulla Wadaskar > > Cc: u-boot(a)lists.denx.de; Ashish Karkare; Prabhanjan Sarnaik > > Subject: Re: [PATCH v3 2/2] gpio: Add GPIO driver for Marvell SoC > > Armada100 > > > > > > ----- "Prafulla Wadaskar" <prafulla(a)marvell.com> wrote: > > > > > > > > I suggest below code for this function. > > > { > > > Const unsigned int offset[4] = {0, 4, 8, 0x100}; /* gpio > register > > > bank offsets */ > > > return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]); > > > } > > > > > > Again content in this file are SoC core specific and will > duplicate > > > for other SoC supports like pantheon. > > > > > > Can you please move them to mvgpio.h within #ifdef > > > CONFIG_SHEEVA_88SV331xV5? > > > I think this should be the final modification for this driver > > > support. > > > > > > Sorry for the rework. > > > > > > Regards.. > > > Prafulla . . > > > > > > > Hi Prafulla, > > > > Can you please tell me what part of code should be moved to > mvgpio.h? > > You should move entire contents of gpio.h in mvgpio.h within #ifdef > CONFIG_SHEEVA_88SV331xV5, so just mvgpio.c,mvgpio.h,Makefile will add > armada100 gpio driver support in more generic way. > > > I have no idea about number of banks in other SOCs with same core. > > No need to worry, at this moment this driver will be supporting > 88SV331xv5 core only. > > Regards.. > Prafulla . . > I feel it is important to keep gpio.h in arch folder, 'coz if someone enables GPIO command support, generic library header (asm/gpio.h) will look for asm/arch/gpio.h file. we can simply include mvgpio.h in gpio.h incase of armada100. Regards, Ajay Bhargav

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[U-Boot] [PATCH v3 1/2] gpio: Add GPIO driver framework for Marvell SoCs
by Ajay Bhargav 10 Aug '11

10 Aug '11

This patch adds generic GPIO driver framework support for Marvell SoCs. To enable GPIO driver define CONFIG_MARVELL_GPIO and for GPIO commands define CONFIG_CMD_GPIO in your board configuration file. v3 - Added file mvgpio.h for common defines based on CPU core subversion. Arch related stuff should be added to arch/gpio.h Signed-off-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> --- drivers/gpio/Makefile | 1 + drivers/gpio/mvgpio.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++ include/mvgpio.h | 77 +++++++++++++++++++++++++++++++++ 3 files changed, 192 insertions(+), 0 deletions(-) create mode 100644 drivers/gpio/mvgpio.c create mode 100644 include/mvgpio.h diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 62ec97d..beca1da 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libgpio.o COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o COBJS-$(CONFIG_PCA953X) += pca953x.o diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c new file mode 100644 index 0000000..0cc8ed7 --- /dev/null +++ b/drivers/gpio/mvgpio.c @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/gpio.h> + +#ifndef MV_MAX_GPIO +#define MV_MAX_GPIO 128 +#endif + +int gpio_request(int gp, const char *label) +{ + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO requested %d\n", __func__, gp); + return -EINVAL; + } + return 0; +} + +void gpio_free(int gp) +{ +} + +void gpio_toggle_value(int gp) +{ + gpio_set_value(gp, !gpio_get_value(gp)); +} + +int gpio_direction_input(int gp) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr); + return 0; +} + +int gpio_direction_output(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr); + gpio_set_value(gp, value); + return 0; +} + +int gpio_get_value(int gp) +{ + struct gpio_reg *gpio_reg_bank; + u32 gp_val; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return -EINVAL; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + gp_val = readl(&gpio_reg_bank->gplr); + + return GPIO_VAL(gp, gp_val); +} + +void gpio_set_value(int gp, int value) +{ + struct gpio_reg *gpio_reg_bank; + + if (gp >= MV_MAX_GPIO) { + printf("%s: Invalid GPIO %d\n", __func__, gp); + return; + } + + gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp)); + if (value) + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpsr); + else + writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gpcr); +} diff --git a/include/mvgpio.h b/include/mvgpio.h new file mode 100644 index 0000000..768e94c --- /dev/null +++ b/include/mvgpio.h @@ -0,0 +1,77 @@ +/* + * (C) Copyright 2011 + * eInfochips Ltd. <www.einfochips.com> + * Written-by: Ajay Bhargav <ajay.bhargav(a)einfochips.com> + * + * (C) Copyright 2010 + * Marvell Semiconductor <www.marvell.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __MVGPIO_H__ +#define __MVGPIO_H__ + +#include <common.h> + +#define GPIO_SET 1 +#define GPIO_CLR 0 + +#ifdef CONFIG_SHEEVA_88SV331xV5 +/* + * GPIO Register map for SHEEVA 88SV331xV5 + */ +struct gpio_reg { + u32 gplr; /* Pin Level Register - 0x0000 */ + u32 pad0[2]; + u32 gpdr; /* Pin Direction Register - 0x000C */ + u32 pad1[2]; + u32 gpsr; /* Pin Output Set Register - 0x0018 */ + u32 pad2[2]; + u32 gpcr; /* Pin Output Clear Register - 0x0024 */ + u32 pad3[2]; + u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */ + u32 pad4[2]; + u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */ + u32 pad5[2]; + u32 gedr; /* Edge Detect Status Register - 0x0048 */ + u32 pad6[2]; + u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */ + u32 pad7[2]; + u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */ + u32 pad8[2]; + u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable + Register - 0x006C */ + u32 pad9[2]; + u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable + Register - 0x0078 */ + u32 pad10[2]; + u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable + Register - 0x0084 */ + u32 pad11[2]; + u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable + Register - 0x0090 */ + u32 pad12[2]; + u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */ +}; +#else +#error "CPU core subversion not defined" +#endif + +#endif /* __MVGPIO_H__ */ -- 1.7.0.4

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[U-Boot] [PATCH] mmc: Fix mmc_send_status()
by Marek Vasut 10 Aug '11

10 Aug '11

The mmc_send_status() function sets cmd.arg = 0. That's incorrect, so fix it. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- drivers/mmc/mmc.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cbd7567..c9ff023 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -115,7 +115,7 @@ int mmc_send_status(struct mmc *mmc, int timeout) cmd.cmdidx = MMC_CMD_SEND_STATUS; cmd.resp_type = MMC_RSP_R1; - cmd.cmdarg = 0; + cmd.cmdarg = mmc->rca << 16; cmd.flags = 0; do { -- 1.7.5.4

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[U-Boot] MBR emulation
by Steven Barker 10 Aug '11

10 Aug '11

I have a Tegra 2 device that stores its configuration data in the spot that the MBR is meant to sit on the device this is immobile and cannot be moved, The device has a GPT partition table but no MBR, is there a way to either make u-boot just read the GPT from the end of the emmc or, emulate the mbr either statically or by loading an "MBR.bin" from elsewhere on the emmc device. At the moment u-boot does see the emmc but cannot read the partition table

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[U-Boot] [PATCH] omap4_panda: Enable command-line editing and hush shell by default on panda board
by Joe Hershberger 10 Aug '11

10 Aug '11

Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Sandeep Paulraj <s-paulraj(a)ti.com> --- include/configs/omap4_panda.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index e313231..a3f13e5 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -192,6 +192,12 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +#define CONFIG_CMDLINE_EDITING 1 + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + /* * memtest setup */ -- 1.6.0.2

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[U-Boot] [PATCH] ARM926ejs: Add routines to invalidate D-Cache
by Hong Xu 10 Aug '11

10 Aug '11

After DMA operation, we need to maintain D-Cache coherency. So that the DCache must be invalidated (hence CPU will fetch data written by DMA controller from RAM). Tested on AT91SAM9261EK with Peripheral DMA controller. Signed-off-by: Hong Xu <hong.xu(a)atmel.com> Tested-by: Elen Song <elen.song(a)atmel.com> CC: Albert Aribaud <albert.u.boot(a)aribaud.net> CC: Aneesh V <aneesh(a)ti.com> CC: Reinhard Meyer <u-boot(a)emk-elektronik.de> CC: Heiko Schocher <hs(a)denx.de> --- V2: Per Albert's suggestion, add invalidate_dcache_range V3: invalidate_dcache_range emits warning when detecting unaligned buffer invalidate_dcache_range won't clean any adjacent cache line when detecting unaligned buffer and only round up/down the buffer address arch/arm/lib/cache.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 54 insertions(+), 0 deletions(-) diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 92b61a2..9e6aa47 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -53,3 +53,57 @@ void __flush_dcache_all(void) } void flush_dcache_all(void) __attribute__((weak, alias("__flush_dcache_all"))); + +/* + * The buffer range to be invalidated is [start, stop) + */ +void __invalidate_dcache_range(unsigned long start, unsigned long stop) +{ + int cache_line_len; + unsigned long mva; + +#ifdef CONFIG_ARM926EJS +#ifdef CONFIG_SYS_CACHELINE_SIZE + cache_line_len = CONFIG_SYS_CACHELINE_SIZE; +#else + /* + * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9 + * only b'10, aka. 32 bytes cache line len is valid + */ + cache_line_len = 32; +#endif + mva = start; + if ((mva & (cache_line_len - 1)) != 0) { + printf("WARNING: %s - unaligned buffer detected, starting " + "address: 0x%08x\n", __FUNCTION__, start); + mva &= ~(cache_line_len - 1); + } + if ((stop & (cache_line_len - 1)) != 0) { + printf("WARNING: %s - unaligned buffer detected, ending " + "address: 0x%08x\n", __FUNCTION__, stop); + stop = (stop | (cache_line_len - 1)) + 1; + } + + while (mva < stop) { + asm("mcr p15, 0, %0, c7, c6, 1" : : "r"(mva)); + mva += cache_line_len; + } + + /* Drain the WB */ + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +#endif + + return; +} +void invalidate_dcache_range(unsigned long start, unsigned long stop) + __attribute__((weak, alias("__invalidate_dcache_range"))); + +void __invalidate_dcache_all(void) +{ +#ifdef CONFIG_ARM926EJS + asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0)); +#endif + return; +} +void invalidate_dcache_all(void) + __attribute__((weak, alias("__invalidate_dcache_all"))); -- 1.7.6

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[U-Boot] [PATCH V3] NAND: Allow per-buffer allocation
by Marek Vasut 10 Aug '11

10 Aug '11

Don't allocate NAND buffers as one block, but allocate them separately. This can be beneficial for example for systems, which need DMA buffers to be aligned. With this patch, such systems can allocate aligned buffers and avoid memcpy()ing data in place. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- drivers/mtd/nand/nand_base.c | 30 +++++++++++++++++++++++------- include/linux/mtd/nand.h | 7 ++++--- 2 files changed, 27 insertions(+), 10 deletions(-) V2: Fix the chip->buffers->buffer condition V3: Fix compiler warning due to bad cast in chip->buffers->buffer and patch description diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 1a95a91..a5f872e 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2749,13 +2749,27 @@ int nand_scan_ident(struct mtd_info *mtd, int maxchips, */ int nand_scan_tail(struct mtd_info *mtd) { - int i; + int i, bufsize; + uint8_t *buf; struct nand_chip *chip = mtd->priv; - if (!(chip->options & NAND_OWN_BUFFERS)) - chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); - if (!chip->buffers) - return -ENOMEM; + if (!(chip->options & NAND_OWN_BUFFERS)) { + chip->buffers = malloc(sizeof(struct nand_buffers)); + if (!chip->buffers) + return -ENOMEM; + + bufsize = NAND_MAX_PAGESIZE + (3 * NAND_MAX_OOBSIZE); + buf = malloc(bufsize); + if (!buf) { + free(chip->buffers); + return -ENOMEM; + } + + chip->buffers->buffer = buf; + chip->buffers->ecccalc = buf; + chip->buffers->ecccode = buf + NAND_MAX_OOBSIZE; + chip->buffers->databuf = buf + (2 * NAND_MAX_OOBSIZE); + } /* Set the internal oob buffer location, just after the page data */ chip->oob_poi = chip->buffers->databuf + mtd->writesize; @@ -2996,6 +3010,8 @@ void nand_release(struct mtd_info *mtd) /* Free bad block table memory */ kfree(chip->bbt); - if (!(chip->options & NAND_OWN_BUFFERS)) - kfree(chip->buffers); + if (!(chip->options & NAND_OWN_BUFFERS)) { + free(chip->buffers->buffer); + free(chip->buffers); + } } diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h index 987a2ec..c3449a9 100644 --- a/include/linux/mtd/nand.h +++ b/include/linux/mtd/nand.h @@ -370,9 +370,10 @@ struct nand_ecc_ctrl { * consecutive order. */ struct nand_buffers { - uint8_t ecccalc[NAND_MAX_OOBSIZE]; - uint8_t ecccode[NAND_MAX_OOBSIZE]; - uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE]; + uint8_t *buffer; + uint8_t *ecccalc; + uint8_t *ecccode; + uint8_t *databuf; }; /** -- 1.7.5.4

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