August 2011 - U-Boot

[U-Boot] [PATCH 1/3] arm: add CONFIG_MACH_TYPE option and documentation
by Igor Grinberg 11 Aug '11

11 Aug '11

CONFIG_MACH_TYPE can be used to set the machine type number in the common arm code instead of setting it in the board code. Signed-off-by: Igor Grinberg <grinberg(a)compulab.co.il> --- README | 12 ++++++++++++ arch/arm/lib/board.c | 5 +++++ 2 files changed, 17 insertions(+), 0 deletions(-) diff --git a/README b/README index 446966d..a9ccb0a 100644 --- a/README +++ b/README @@ -442,6 +442,18 @@ The following options need to be configured: crash. This is needed for buggy hardware (uc101) where no pull down resistor is connected to the signal IDE5V_DD7. + CONFIG_MACH_TYPE [relevant for ARM only] + + This option can be used to specify the machine type number + as it appears in the ARM machine registry + (see http://www.arm.linux.org.uk/developer/machines/). + If this option is not defined, then your board code + will have to set this up like: + gd->bd->bi_arch_number = <mach type>; + Note: This option is not suitable if you have multiple + boards supported in a single configuration file and the + machine type is runtime discoverable. + - vxWorks boot parameters: bootvx constructs a valid bootline using the following diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 169dfeb..ee77d05 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -451,6 +451,11 @@ void board_init_r (gd_t *id, ulong dest_addr) monitor_flash_len = _end_ofs; debug ("monitor flash len: %08lX\n", monitor_flash_len); + +#ifdef CONFIG_MACH_TYPE + bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */ +#endif + board_init(); /* Setup chipselects */ #ifdef CONFIG_SERIAL_MULTI -- 1.7.3.4

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[U-Boot] [PATCH] gpio: Expand cmd_gpio functionality and script friendliness
by Joe Hershberger 11 Aug '11

11 Aug '11

Add quiet parameter to cmd_gpio for use when part of a script Enable repeat... especially useful when used with input and toggle Add "outstate" command that will return and print the state of an output Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Mike Frysinger <vapier(a)gentoo.org> --- common/cmd_gpio.c | 39 ++++++++++++++++++++++++--------------- 1 files changed, 24 insertions(+), 15 deletions(-) diff --git a/common/cmd_gpio.c b/common/cmd_gpio.c index 9cc790a..0acb93e 100644 --- a/common/cmd_gpio.c +++ b/common/cmd_gpio.c @@ -20,6 +20,7 @@ enum gpio_cmd { GPIO_SET, GPIO_CLEAR, GPIO_TOGGLE, + GPIO_OUTSTATE, }; static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -27,7 +28,7 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) int gpio; enum gpio_cmd sub_cmd; ulong value; - const char *str_cmd, *str_gpio; + const char *str_cmd, *str_gpio, *str_quiet = "0"; #ifdef gpio_status if (argc == 2 && !strcmp(argv[1], "status")) { @@ -36,18 +37,22 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif - if (argc != 3) + if (argc != 3 && argc != 4) show_usage: return cmd_usage(cmdtp); + str_cmd = argv[1]; str_gpio = argv[2]; + if (argc == 4) + str_quiet = argv[3]; /* parse the behavior */ switch (*str_cmd) { - case 'i': sub_cmd = GPIO_INPUT; break; - case 's': sub_cmd = GPIO_SET; break; - case 'c': sub_cmd = GPIO_CLEAR; break; - case 't': sub_cmd = GPIO_TOGGLE; break; + case 'i': sub_cmd = GPIO_INPUT; break; + case 's': sub_cmd = GPIO_SET; break; + case 'c': sub_cmd = GPIO_CLEAR; break; + case 't': sub_cmd = GPIO_TOGGLE; break; + case 'o': sub_cmd = GPIO_OUTSTATE; break; default: goto show_usage; } @@ -68,22 +73,26 @@ static int do_gpio(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) value = gpio_get_value(gpio); } else { switch (sub_cmd) { - case GPIO_SET: value = 1; break; - case GPIO_CLEAR: value = 0; break; - case GPIO_TOGGLE: value = !gpio_get_value(gpio); break; + case GPIO_SET: value = 1; break; + case GPIO_CLEAR: value = 0; break; + case GPIO_TOGGLE: value = !gpio_get_value(gpio); break; + case GPIO_OUTSTATE: value = gpio_get_value(gpio); break; default: goto show_usage; } gpio_direction_output(gpio, value); } - printf("gpio: pin %s (gpio %i) value is %lu\n", - str_gpio, gpio, value); + + if (*str_quiet == '0') + printf("gpio: pin %s (gpio %i) value is %lu\n", + str_gpio, gpio, value); gpio_free(gpio); return value; } -U_BOOT_CMD(gpio, 3, 0, do_gpio, - "input/set/clear/toggle gpio pins", - "<input|set|clear|toggle> <pin>\n" - " - input/set/clear/toggle the specified pin"); +U_BOOT_CMD(gpio, 4, 1, do_gpio, + "input/set/clear/toggle/outstate gpio pins", + "<input|set|clear|toggle|outstate> <pin> [quiet]\n" + " - input/set/clear/toggle/outstate the specified pin\n" + " - quiet: if 1, do not print"); -- 1.6.0.2

3 3

[U-Boot] 2011 HONDA PROMOTION
by HONDA COMPANY 11 Aug '11

11 Aug '11

Your email address has luckily won you 1,750,000.00 GBP.

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[U-Boot] mailbox storage limit/quota exceeded‏
by Street, James (Referee) 11 Aug '11

11 Aug '11

Your mailbox storage limit/quota has been exceeded until you re-validate your mailbox you cannot send or recieve e-mail.To re-validate your mailbox please CLICK HERE<http://augty.weebly.com/> Thanks System Administrator

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[U-Boot] MII - Incorrect type specified for offset addr
by Hebbar, Gururaja 11 Aug '11

11 Aug '11

Hi, We have an upcoming SOC with Ethernet controller which has registers with offsets crossing 0x110. In order to access these registers, we use miiphy_read() & miiphy_write() api provided by Standard u-boot mii phy util code (common/miiphyutil.c). However the syntax of miiphy_read() & miiphy_write() is as below int miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned short *value); int miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); Here the "reg" argument is of type "unsigned char" which limits the offset to a max of 0xff. In linux, they are using u32 as type. Right now we have modified the type to short and using it. Is this correct? If yes, can we send a patch for the same? If not, what is the alternative? Thanks & Regards Gururaja

3 3

[U-Boot] [PATCH 1/3] add mcf5307 support
by Angelo Dureghello 10 Aug '11

10 Aug '11

Cpu architecture files. # new file: arch/m68k/cpu/mcf530x/Makefile # new file: arch/m68k/cpu/mcf530x/config.mk # new file: arch/m68k/cpu/mcf530x/cpu.c # new file: arch/m68k/cpu/mcf530x/cpu.h # new file: arch/m68k/cpu/mcf530x/cpu_init.c # new file: arch/m68k/cpu/mcf530x/interrupts.c # new file: arch/m68k/cpu/mcf530x/speed.c # new file: arch/m68k/cpu/mcf530x/start.S Signed-off-by: Angelo Dureghello <sysamfw(a)gmail.com> --- diff --git a/arch/m68k/cpu/mcf530x/Makefile b/arch/m68k/cpu/mcf530x/Makefile new file mode 100644 index 0000000..3c5a1c2 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/Makefile @@ -0,0 +1,48 @@ +# +# Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +# CFLAGS += -DET_DEBUG + +LIB = $(obj)lib$(CPU).o + +START = start.o +COBJS = interrupts.o cpu.o speed.o cpu_init.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/m68k/cpu/mcf530x/config.mk b/arch/m68k/cpu/mcf530x/config.mk new file mode 100644 index 0000000..2ba1644 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/config.mk @@ -0,0 +1,25 @@ +# +# Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +PLATFORM_RELFLAGS += -ffixed-d7 -msep-data + +PLATFORM_CPPFLAGS += -m5307 -fPIC diff --git a/arch/m68k/cpu/mcf530x/cpu.c b/arch/m68k/cpu/mcf530x/cpu.c new file mode 100644 index 0000000..efd9cbd --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu.c @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <command.h> +#include <asm/immap.h> + +#include "cpu.h" + +int checkcpu(void) +{ + char buf[32]; + + printf("CPU: Freescale Coldfire MCF5307 at %s MHz\n", + strmhz(buf, CONFIG_SYS_CLK)); + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + /* enable watchdog, set timeout to 0 and wait */ + mbar_writeByte(MCFSIM_SYPCR, 0xc0); + while (1) ; + + /* we don't return! */ + return 0; +} + diff --git a/arch/m68k/cpu/mcf530x/cpu.h b/arch/m68k/cpu/mcf530x/cpu.h new file mode 100644 index 0000000..c1227eb --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu.h @@ -0,0 +1,33 @@ +/* + * cpu.h + * + * Copyright (c) 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _CPU_H_ +#define _CPU_H_ + +#include <command.h> + +/* Use this to create board specific reset functions */ +void board_reset(void) __attribute__((__weak__)); + +#endif /* _CPU_H_ */ diff --git a/arch/m68k/cpu/mcf530x/cpu_init.c b/arch/m68k/cpu/mcf530x/cpu_init.c new file mode 100644 index 0000000..5e1c9f0 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/cpu_init.c @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/immap.h> + +/* + * Simple mcf5307 chip select module init. + * + * Note: this chip has an issue reported in the device "errata": + * MCF5307ER Rev 4.2 reports @ section 35: + * Corrupted Return PC in Exception Stack Frame + * When processing an autovectored interrupt an error can occur that + * causes 0xFFFFFFFF to be written as the return PC value in the + * exception stack frame. The problem is caused by a conflict between + * an internal autovector access and a chip select mapped to the IACK + * address space (0xFFFFXXXX). + * Workaround: + * Set the C/I bit in the chip select mask register (CSMR) for the + * chip select that is mapped to 0xFFFFXXXX. + * This will prevent the chip select from asserting for IACK accesses. + */ +#define MCF5307_SP_ERR_FIX(cs_base,mask) \ + if((cs_base+(mask&0xffff0000))>=0xffff0000)mask|=0x20 + +void init_csm(void) +{ + volatile csm_t *csm = (csm_t *) (MMAP_CSM); + +#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \ + && defined(CONFIG_SYS_CS0_CTRL)) + csm->csar0 = (CONFIG_SYS_CS0_BASE>>16); + csm->cscr0 = CONFIG_SYS_CS0_CTRL; + csm->csmr0 = CONFIG_SYS_CS0_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS0_BASE,csm->csmr0); +#else +#warning "Chip Select 0 are not initialized/used" +#endif +#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \ + && defined(CONFIG_SYS_CS1_CTRL)) + csm->csar1 = (CONFIG_SYS_CS1_BASE>>16); + csm->cscr1 = CONFIG_SYS_CS1_CTRL; + csm->csmr1 = CONFIG_SYS_CS1_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS1_BASE,csm->csmr1); +#endif +#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \ + && defined(CONFIG_SYS_CS2_CTRL)) + csm->csar2 = (CONFIG_SYS_CS2_BASE>>16); + csm->cscr2 = CONFIG_SYS_CS2_CTRL; + csm->csmr2 = CONFIG_SYS_CS2_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS2_BASE,csm->csmr2); +#endif +#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \ + && defined(CONFIG_SYS_CS3_CTRL)) + csm->csar3 =(CONFIG_SYS_CS3_BASE>>16); + csm->cscr3 = CONFIG_SYS_CS3_CTRL; + csm->csmr3 = CONFIG_SYS_CS3_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS3_BASE,csm->csmr3); +#endif +#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \ + && defined(CONFIG_SYS_CS4_CTRL)) + csm->csar4 = (CONFIG_SYS_CS4_BASE>>16); + csm->cscr4 = CONFIG_SYS_CS4_CTRL; + csm->csmr4 = CONFIG_SYS_CS4_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS4_BASE,csm->csmr4); +#endif +#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \ + && defined(CONFIG_SYS_CS5_CTRL)) + csm->csar5 = (CONFIG_SYS_CS5_BASE>>16); + csm->cscr5 = CONFIG_SYS_CS5_CTRL; + csm->csmr5 = CONFIG_SYS_CS5_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS5_BASE,csm->csmr5); +#endif +#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) \ + && defined(CONFIG_SYS_CS6_CTRL)) + csm->csar6 = (CONFIG_SYS_CS6_BASE>>16); + csm->cscr6 = CONFIG_SYS_CS6_CTRL; + csm->csmr6 = CONFIG_SYS_CS6_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS6_BASE,csm->csmr6); +#endif +#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) \ + && defined(CONFIG_SYS_CS7_CTRL)) + csm->csar7 = (CONFIG_SYS_CS7_BASE>>16); + csm->cscr7 = CONFIG_SYS_CS7_CTRL; + csm->csmr7 = CONFIG_SYS_CS7_MASK; + MCF5307_SP_ERR_FIX(CONFIG_SYS_CS7_BASE,csm->csmr7); +#endif +} + +/* + * Breath some life into the CPU... + * + * Set up the memory map, + * initialize a bunch of registers, + */ +void cpu_init_f(void) +{ + /* 5307 Internal Core takes priority over DMA */ + mbar_writeByte(MCFSIM_MPARK, 0x30); + + mbar_writeByte(MCFSIM_SYPCR, 0x00); + mbar_writeByte(MCFSIM_SWIVR, 0x0f); + mbar_writeByte(MCFSIM_SWSR, 0x00); + mbar_writeLong(MCFSIM_IMR, 0xfffffbff); + mbar_writeByte(MCFSIM_SWDICR, 0x00); + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); + mbar_writeByte(MCFSIM_I2CICR, 0x00); + mbar_writeByte(MCFSIM_UART1ICR, 0x00); + mbar_writeByte(MCFSIM_UART2ICR, 0x00); + mbar_writeByte(MCFSIM_ICR6, 0x00); + mbar_writeByte(MCFSIM_ICR7, 0x00); + mbar_writeByte(MCFSIM_ICR8, 0x00); + mbar_writeByte(MCFSIM_ICR9, 0x00); + + /* Chipselect Init */ + init_csm(); + + /* enable instruction cache now */ + icache_enable(); +} + +/* + * initialize higher level parts of CPU like timers + */ +int cpu_init_r(void) +{ + return (0); +} + +void uart_port_conf(int port) +{ +} + +void arch_preboot_os(void) +{ + /* + * OS can change interrupt offsets and are about to boot the OS so + * we need to make sure we disable all async interrupts. + */ + mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); + mbar_writeByte(MCFSIM_TIMER2ICR, 0x00); +} + diff --git a/arch/m68k/cpu/mcf530x/interrupts.c b/arch/m68k/cpu/mcf530x/interrupts.c new file mode 100644 index 0000000..f743d1e --- /dev/null +++ b/arch/m68k/cpu/mcf530x/interrupts.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/processor.h> +#include <asm/immap.h> + +int interrupt_init(void) +{ + enable_interrupts(); + + return 0; +} + +void dtimer_intr_setup(void) +{ + /* clearing TIMER2 mask, so enabling the related interrupt */ + mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); + /* set TIMER2 interrupt priority */ + mbar_writeByte(MCFSIM_TIMER2ICR, CONFIG_SYS_TMRINTR_PRI); +} + diff --git a/arch/m68k/cpu/mcf530x/speed.c b/arch/m68k/cpu/mcf530x/speed.c new file mode 100644 index 0000000..426bd9e --- /dev/null +++ b/arch/m68k/cpu/mcf530x/speed.c @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* get_clocks() fills in gd->cpu_clock and gd->bus_clk */ +int get_clocks (void) +{ + gd->cpu_clk = CONFIG_SYS_CLK; + gd->bus_clk = gd->cpu_clk / 2; + + return (0); +} diff --git a/arch/m68k/cpu/mcf530x/start.S b/arch/m68k/cpu/mcf530x/start.S new file mode 100644 index 0000000..d717080 --- /dev/null +++ b/arch/m68k/cpu/mcf530x/start.S @@ -0,0 +1,253 @@ +/* + * Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm-offsets.h> +#include <config.h> +#include <timestamp.h> +#include "version.h" +#include <asm/cache.h> + +#ifndef CONFIG_IDENT_STRING +#define CONFIG_IDENT_STRING "" +#endif + +#define _START _start +#define _FAULT _fault + +#define SAVE_ALL \ + move.w #0x2700,%sr; /* disable intrs */ \ + subl #60,%sp; /* space for 15 regs */ \ + moveml %d0-%d7/%a0-%a6,%sp@; \ + +#define RESTORE_ALL \ + moveml %sp@,%d0-%d7/%a0-%a6; \ + addl #60,%sp; /* space for 15 regs */ \ + rte + +/* If we come from a pre-loader we don't need an initial exception + * table. + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + +.text +/* + * Vector table. This is used for initial platform startup. + * These vectors are to catch any un-intended traps. + */ +_vectors: + +.long 0x00000000 /* Flash offset is 0 until we setup CS0 */ +.long _START + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT + +#endif + + .text + .globl _start +_start: + nop + nop + move.w #0x2700,%sr + + move.l #(CONFIG_SYS_MBAR + 1), %d0 /* set MBAR address + valid flag */ + move.c %d0, %MBAR + + move.l #(CONFIG_SYS_INIT_RAM_ADDR + 1), %d0 + movec %d0, %RAMBAR + + /* if we come from a pre-loader we have no exception table and + * therefore no VBR to set + */ +#if !defined(CONFIG_MONITOR_IS_IN_RAM) + move.l #CONFIG_SYS_FLASH_BASE, %d0 + movec %d0, %VBR +#endif + + /* initialize general use internal ram */ + move.l #0, %d0 + move.l #(ICACHE_STATUS), %a1 /* icache */ + move.l #(DCACHE_STATUS), %a2 /* icache */ + move.l %d0, (%a1) + move.l %d0, (%a2) + + /* set stackpointer to internal sram end - 80 (global data struct size + some bytes) + * get some stackspace for the first c-code, + */ + move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET), %sp + clr.l %sp@- + + move.l #__got_start, %a5 /* put relocation table address to a5 */ + + bsr cpu_init_f /* run low-level CPU init code (from flash) */ + bsr board_init_f /* run low-level board init code (from flash) */ + + /* board_init_f() does not return */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + * r3 = dest + * r4 = src + * r5 = length in bytes + * r6 = cachelinesize + */ + .globl relocate_code +relocate_code: + link.w %a6,#0 + move.l 8(%a6), %sp /* set new stack pointer */ + move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ + move.l 16(%a6), %a0 /* Save copy of Destination Address */ + + move.l #CONFIG_SYS_MONITOR_BASE, %a1 + move.l #__init_end, %a2 + move.l %a0, %a3 + + /* copy the code to RAM */ +1: + move.l (%a1)+, (%a3)+ + cmp.l %a1,%a2 + bgt.s 1b + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + move.l %a0, %a1 + add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1 + jmp (%a1) + +in_ram: + +clear_bss: + /* + * Now clear BSS segment + */ + move.l %a0, %a1 + add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a0, %d1 + add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1 +6: + clr.l (%a1)+ + cmp.l %a1,%d1 + bgt.s 6b + + /* + * fix got table in RAM + */ + move.l %a0, %a1 + add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1 + move.l %a1,%a5 /* * fix got pointer register a5 */ + + move.l %a0, %a2 + add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2 + +7: + move.l (%a1),%d1 + sub.l #_start,%d1 + add.l %a0,%d1 + move.l %d1,(%a1)+ + cmp.l %a2, %a1 + bne 7b + + /* calculate relative jump to board_init_r in ram */ + move.l %a0, %a1 + add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1 + + /* set parameters for board_init_r */ + move.l %a0,-(%sp) /* dest_addr */ + move.l %d0,-(%sp) /* gd */ +#if defined(DEBUG) && (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE) && \ + defined(CONFIG_SYS_HALT_BEFOR_RAM_JUMP) + halt +#endif + jsr (%a1) + +/*------------------------------------------------------------------------------*/ +/* exception code */ + .globl _fault +_fault: + jmp _fault + + .globl _exc_handler +_exc_handler: + SAVE_ALL + movel %sp,%sp@- + bsr exc_handler + addql #4,%sp + RESTORE_ALL + + .globl _int_handler +_int_handler: + SAVE_ALL + movel %sp,%sp@- + bsr int_handler + addql #4,%sp + RESTORE_ALL + +/*------------------------------------------------------------------------------*/ + + .globl version_string +version_string: + .ascii U_BOOT_VERSION + .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")" + .ascii CONFIG_IDENT_STRING, "\0" + .align 4

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[U-Boot] [PATCH V2] mmc: Fix mmc_send_status()
by Marek Vasut 10 Aug '11

10 Aug '11

The mmc_send_status() function sets cmd.arg = 0. That's incorrect, so fix it. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- drivers/mmc/mmc.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) V2: Take SPI mode into account diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index cbd7567..00687d6 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -115,7 +115,8 @@ int mmc_send_status(struct mmc *mmc, int timeout) cmd.cmdidx = MMC_CMD_SEND_STATUS; cmd.resp_type = MMC_RSP_R1; - cmd.cmdarg = 0; + if (!mmc_host_is_spi(mmc)) + cmd.cmdarg = mmc->rca << 16; cmd.flags = 0; do { -- 1.7.5.4

4 4

[U-Boot] [PATCH 0/3] add mcf5307 support
by Angelo Dureghello 10 Aug '11

10 Aug '11

The following patches add support for Freescale MCF5307 cpu. Below a brief of the changes: # On branch master # Changes to be committed: # (use "git reset HEAD <file>..." to unstage) # # new file: arch/m68k/cpu/mcf530x/Makefile # new file: arch/m68k/cpu/mcf530x/config.mk # new file: arch/m68k/cpu/mcf530x/cpu.c # new file: arch/m68k/cpu/mcf530x/cpu.h # new file: arch/m68k/cpu/mcf530x/cpu_init.c # new file: arch/m68k/cpu/mcf530x/interrupts.c # new file: arch/m68k/cpu/mcf530x/speed.c # new file: arch/m68k/cpu/mcf530x/start.S # new file: arch/m68k/include/asm/immap_5307.h # new file: arch/m68k/include/asm/m5307.h # # Changed but not updated: # (use "git add <file>..." to update what will be committed) # (use "git checkout -- <file>..." to discard changes in working directory) # # modified: arch/m68k/include/asm/cache.h # modified: arch/m68k/include/asm/immap.h # modified: arch/m68k/include/asm/timer.h # modified: include/common.h # Best Regards, Angelo Dureghello Sysam

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[U-Boot] [PATCH 3/3] add mcf5307 support
by Angelo Dureghello 10 Aug '11

10 Aug '11

Other modified files: # modified: arch/m68k/include/asm/cache.h # modified: arch/m68k/include/asm/immap.h # modified: arch/m68k/include/asm/timer.h # modified: include/common.h Signed-off-by: Angelo Dureghello <sysamfw(a)gmail.com> --- diff --git a/arch/m68k/include/asm/cache.h b/arch/m68k/include/asm/cache.h index 7c84e48..e447f3c 100644 --- a/arch/m68k/include/asm/cache.h +++ b/arch/m68k/include/asm/cache.h @@ -31,7 +31,7 @@ #define CONFIG_CF_V2 #endif -#if defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) +#if defined(CONFIG_MCF530x) || defined(CONFIG_MCF532x) || defined(CONFIG_MCF5301x) #define CONFIG_CF_V3 #endif diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index e83ce08..bc43f13 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -256,6 +256,28 @@ #endif #endif /* CONFIG_M5282 */ +#ifdef CONFIG_M5307 +#include <asm/immap_5307.h> +#include <asm/m5307.h> + +#define CONFIG_SYS_UART_BASE (MMAP_UART0 + (CONFIG_SYS_UART_PORT * 0x40)) + +#define CONFIG_SYS_INTR_BASE (MMAP_INTC) +#define CONFIG_SYS_NUM_IRQS (64) + +/* Timer */ +#ifdef CONFIG_MCFTMR +#define CONFIG_SYS_UDELAY_BASE (MMAP_DTMR0) +#define CONFIG_SYS_TMR_BASE (MMAP_DTMR1) +#define CONFIG_SYS_TMRPND_REG (mbar_readLong(MCFSIM_IPR)) +#define CONFIG_SYS_TMRINTR_NO (31) +#define CONFIG_SYS_TMRINTR_MASK (0x00000400) +#define CONFIG_SYS_TMRINTR_PEND (CONFIG_SYS_TMRINTR_MASK) +#define CONFIG_SYS_TMRINTR_PRI (MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3) +#define CONFIG_SYS_TIMER_PRESCALER (((gd->bus_clk / 1000000) - 1) << 8) +#endif +#endif /* CONFIG_M5307 */ + #if defined(CONFIG_MCF5301x) #include <asm/immap_5301x.h> #include <asm/m5301x.h> diff --git a/arch/m68k/include/asm/timer.h b/arch/m68k/include/asm/timer.h index 1a5de05..8516c8f 100644 --- a/arch/m68k/include/asm/timer.h +++ b/arch/m68k/include/asm/timer.h @@ -33,7 +33,7 @@ /****************************************************************************/ /* DMA Timer module registers */ typedef struct dtimer_ctrl { -#if defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272) +#if defined(CONFIG_M5307) || defined(CONFIG_M5249) || defined(CONFIG_M5253) || defined(CONFIG_M5272) u16 tmr; /* 0x00 Mode register */ u16 res1; /* 0x02 */ u16 trr; /* 0x04 Reference register */ diff --git a/include/common.h b/include/common.h index 12a1074..40bfbe9 100644 --- a/include/common.h +++ b/include/common.h @@ -574,7 +574,7 @@ void get_sys_info ( sys_info_t * ); #if defined(CONFIG_8xx) || defined(CONFIG_8260) void cpu_init_f (volatile immap_t *immr); #endif -#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) ||defined(CONFIG_MPC86xx) +#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MCF52x2) || defined (CONFIG_MCF5307) || defined(CONFIG_MPC86xx) void cpu_init_f (void); #endif

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[U-Boot] [PATCH 2/3] add mcf5307 support
by Angelo Dureghello 10 Aug '11

10 Aug '11

Architecture includes. # new file: arch/m68k/include/asm/immap_5307.h # new file: arch/m68k/include/asm/m5307.h Signed-off-by: Angelo Dureghello <sysamfw(a)gmail.com> --- diff --git a/arch/m68k/include/asm/immap_5307.h b/arch/m68k/include/asm/immap_5307.h new file mode 100644 index 0000000..cb58297 --- /dev/null +++ b/arch/m68k/include/asm/immap_5307.h @@ -0,0 +1,78 @@ +/* + * MCF5307 Internal Memory Map + * + * Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __IMMAP_5307__ +#define __IMMAP_5307__ + +#define MMAP_INTC (CONFIG_SYS_MBAR + 0x00000040) +#define MMAP_CSM (CONFIG_SYS_MBAR + 0x00000080) +#define MMAP_DTMR0 (CONFIG_SYS_MBAR + 0x00000140) +#define MMAP_DTMR1 (CONFIG_SYS_MBAR + 0x00000180) +#define MMAP_UART0 (CONFIG_SYS_MBAR + 0x000001C0) +#define MMAP_UART1 (CONFIG_SYS_MBAR + 0x00000200) + +typedef struct csm { + u16 csar0; /* Chip-select Address */ + u16 res0a; + u32 csmr0; /* Chip-select Mask */ + u16 res0b; + u16 cscr0; /* Chip-select Control */ + u16 csar1; + u16 res1a; + u32 csmr1; + u16 res1b; + u16 cscr1; + u16 csar2; + u16 res2a; + u32 csmr2; + u16 res2b; + u16 cscr2; + u16 csar3; + u16 res3a; + u32 csmr3; + u16 res3b; + u16 cscr3; + u16 csar4; + u16 res4a; + u32 csmr4; + u16 res4b; + u16 cscr4; + u16 csar5; + u16 res5a; + u32 csmr5; + u16 res5b; + u16 cscr5; + u16 csar6; + u16 res6a; + u32 csmr6; + u16 res6b; + u16 cscr6; + u16 csar7; + u16 res7a; + u32 csmr7; + u16 res7b; + u16 cscr7; +} csm_t; + +#endif /* __IMMAP_5307__ */ diff --git a/arch/m68k/include/asm/m5307.h b/arch/m68k/include/asm/m5307.h new file mode 100644 index 0000000..edb1bf2 --- /dev/null +++ b/arch/m68k/include/asm/m5307.h @@ -0,0 +1,119 @@ +/* + * mcf5307.h -- Definitions for Motorola Coldfire 5307 + * + * Copyright (c) 2011 Angelo Dureghello <sysamfw(a)gmail.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef mcf5307_h +#define mcf5307_h +/****************************************************************************/ + +/* + * useful definitions for reading/writing MBAR offset memory + */ +#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) +#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y +#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y + +/* + * Size of internal RAM + */ + +#define INT_RAM_SIZE 4096 /* RAMBAR - 4k */ + +/* + * Define the 5249 SIM register set addresses. + */ + +/***************** + ***** MBAR ***** + *****************/ +#define MCFSIM_RSR 0x00 /* Reset Status reg (r/w) */ +#define MCFSIM_SYPCR 0x01 /* System Protection reg (r/w) */ +#define MCFSIM_SWIVR 0x02 /* SW Watchdog intr reg (r/w) */ +#define MCFSIM_SWSR 0x03 /* SW Watchdog service (r/w) */ +#define MCFSIM_PLLCR 0x08 /* PLL Control register */ +#define MCFSIM_MPARK 0x0c /* Bus master park register (r/w) */ + +#define MCFSIM_SIMR 0x00 /* SIM Config reg (r/w) */ +#define MCFSIM_ICR0 0x4c /* Intr Ctrl reg 0 (r/w) */ +#define MCFSIM_ICR1 0x4d /* Intr Ctrl reg 1 (r/w) */ +#define MCFSIM_ICR2 0x4e /* Intr Ctrl reg 2 (r/w) */ +#define MCFSIM_ICR3 0x4f /* Intr Ctrl reg 3 (r/w) */ +#define MCFSIM_ICR4 0x50 /* Intr Ctrl reg 4 (r/w) */ +#define MCFSIM_ICR5 0x51 /* Intr Ctrl reg 5 (r/w) */ +#define MCFSIM_ICR6 0x52 /* Intr Ctrl reg 6 (r/w) */ +#define MCFSIM_ICR7 0x53 /* Intr Ctrl reg 7 (r/w) */ +#define MCFSIM_ICR8 0x54 /* Intr Ctrl reg 8 (r/w) */ +#define MCFSIM_ICR9 0x55 /* Intr Ctrl reg 9 (r/w) */ +#define MCFSIM_ICR10 0x56 /* Intr Ctrl reg 10 (r/w) */ +#define MCFSIM_ICR11 0x57 /* Intr Ctrl reg 11 (r/w) */ + +#define MCFSIM_IPR 0x40 /* Interrupt Pend reg (r/w) */ +#define MCFSIM_IMR 0x44 /* Interrupt Mask reg (r/w) */ + +#define MCFSIM_DCR 0x100 /* DRAM Control reg (r/w) */ +#define MCFSIM_DACR0 0x108 /* DRAM 0 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR0 0x10c /* DRAM 0 Mask reg (r/w) */ +#define MCFSIM_DACR1 0x110 /* DRAM 1 Addr and Ctrl (r/w) */ +#define MCFSIM_DMR1 0x114 /* DRAM 1 Mask reg (r/w) */ + +/* + * Some symbol defines for the above... + */ +#define MCFSIM_SWDICR MCFSIM_ICR0 /* Watchdog timer ICR */ +#define MCFSIM_TIMER1ICR MCFSIM_ICR1 /* Timer 1 ICR */ +#define MCFSIM_TIMER2ICR MCFSIM_ICR2 /* Timer 2 ICR */ +#define MCFSIM_I2CICR MCFSIM_ICR3 /* I2C ICR */ +#define MCFSIM_UART1ICR MCFSIM_ICR4 /* UART 1 ICR */ +#define MCFSIM_UART2ICR MCFSIM_ICR5 /* UART 2 ICR */ +/* XXX - If needed, DMA ICRs go here */ + +/* + * Bit definitions for the ICR family of registers. + */ +#define MCFSIM_ICR_AUTOVEC 0x80 /* Auto-vectored intr */ +#define MCFSIM_ICR_LEVEL0 0x00 /* Level 0 intr */ +#define MCFSIM_ICR_LEVEL1 0x04 /* Level 1 intr */ +#define MCFSIM_ICR_LEVEL2 0x08 /* Level 2 intr */ +#define MCFSIM_ICR_LEVEL3 0x0c /* Level 3 intr */ +#define MCFSIM_ICR_LEVEL4 0x10 /* Level 4 intr */ +#define MCFSIM_ICR_LEVEL5 0x14 /* Level 5 intr */ +#define MCFSIM_ICR_LEVEL6 0x18 /* Level 6 intr */ +#define MCFSIM_ICR_LEVEL7 0x1c /* Level 7 intr */ + +#define MCFSIM_ICR_PRI0 0x00 /* Priority 0 intr */ +#define MCFSIM_ICR_PRI1 0x01 /* Priority 1 intr */ +#define MCFSIM_ICR_PRI2 0x02 /* Priority 2 intr */ +#define MCFSIM_ICR_PRI3 0x03 /* Priority 3 intr */ + +/* + * Macros to read/set IMR register. It is 32 bits on the 5307. + */ + +#define mcf_getimr() \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) + +#define mcf_setimr(imr) \ + *((volatile unsigned long *) (MCF_MBAR + MCFSIM_IMR)) = (imr); + +#endif /* mcf5307_h */

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