July 2011 - U-Boot

[U-Boot] N/A
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07 Jul '11

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[U-Boot] [Patch] MPC83XX: Fix PCI express clock setup
by Bill Cook 07 Jul '11

07 Jul '11

On a 8308 based board it was found that the PEX_GLK_RATIO register (programmed in arch/powerpc/cpu/mpc83xx/pcie.c) was getting set to 0, This was tracked to the fact that the pci express clock frequency was not being assigned to the pciexp1_clk entry in the global data structure in file arch/powerpc/cpu/mpc83xx/speed.c. Fix this and a similiar issue in 'do_clocks' command. Signed-off-by: Bill Cook <cook(a)isgchips.com> --- This also points to another problem. The description of the PEX_CLK_RATIO for the various SOCs in question (I checked the RMs for 8308, 8315, and 8378) shows a different maximum freqency for the PCIe core. So the divider in the equation on line 271 should reflect these differences. This seems to be the only mention of a maximum core frequency though, so I hesitate to patch pcie.c without feedback from Freescale. As I'm not a PCI expert, I would rather someone at Freescale look at this and provide appropriate patches. Also, if the max PCIe core frequency on the 8308 is really 125MHz, shouldn't the SCCR PCIEXPCM field of the SCCR be programmed with a 2 instead of 1, this is given by the definition of CONFIG_SYS_SCCR_PCIEXP1CM in the board config file. arch/powerpc/cpu/mpc83xx/speed.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 5e616dd..86d2e18 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -481,7 +481,8 @@ int get_clocks(void) gd->qe_clk = qe_clk; gd->brg_clk = brg_clk; #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) gd->pciexp1_clk = pciexp1_clk; gd->pciexp2_clk = pciexp2_clk; #endif @@ -541,7 +542,8 @@ int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_MPC834x) printf(" USB MPH: %-4s MHz\n", strmhz(buf, gd->usbmph_clk)); #endif -#if defined(CONFIG_MPC837x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \ + defined(CONFIG_MPC837x) printf(" PCIEXP1: %-4s MHz\n", strmhz(buf, gd->pciexp1_clk)); printf(" PCIEXP2: %-4s MHz\n", strmhz(buf, gd->pciexp2_clk)); #endif -- 1.7.2.3

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[U-Boot] powerpc/83xx: remove empty board_early_init_f()
by Timur Tabi 07 Jul '11

07 Jul '11

Remove an empty board_early_init_f() from the MPC8323ERD and MPC360ERDK boards. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- board/freescale/mpc8323erdb/mpc8323erdb.c | 5 ----- board/freescale/mpc8360erdk/mpc8360erdk.c | 5 ----- include/configs/MPC8323ERDB.h | 2 -- include/configs/MPC8360ERDK.h | 1 - 4 files changed, 0 insertions(+), 13 deletions(-) diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 7a0ff18..f29b2f4 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -66,11 +66,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ }; -int board_early_init_f(void) -{ - return 0; -} - int fixed_sdram(void); phys_size_t initdram(int board_type) diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 2baa11a..99c0fbb 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -207,11 +207,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { {0, 0, 0, 0, QE_IOP_TAB_END}, }; -int board_early_init_f(void) -{ - return 0; -} - int board_early_init_r(void) { void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8); diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index e25d5ac..4d4c758 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -59,8 +59,6 @@ */ #define CONFIG_SYS_SICRL 0x00000000 -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ - /* * IMMR new address */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f42cf..851872a 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -72,7 +72,6 @@ #define CONFIG_SYS_SICRH 0x00000000 #define CONFIG_SYS_SICRL 0x40000000 -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_R /* -- 1.7.3.4

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[U-Boot] [PATCH 0/4] MPC83xx: Add MergerBox support.
by Andre Schwarz 07 Jul '11

07 Jul '11

This patch adds support for Matrix Vision MergerBox. It is a Freescale MPC8377 based 3D image preocessing platform utilizing Altera Cyclone IV FPGA and Silicon Motion SM107 embedded graphics connected via PCI. See doc/README.mergerbox for details. MAKEALL -c mpc83xx shows no errors/warnings introduced by this patchset. Files have been checked using checkpatch. Andre Schwarz (4): MergerBox: Add board config file. MergerBox: add documentation. MergerBox: add maintainer and boards.cfg entries. MergerBox: add board specific files in vendor dir. MAINTAINERS | 1 + board/matrix_vision/mergerbox/Makefile | 51 +++ board/matrix_vision/mergerbox/fpga.c | 175 ++++++++ board/matrix_vision/mergerbox/fpga.h | 30 ++ board/matrix_vision/mergerbox/mergerbox.c | 241 +++++++++++ board/matrix_vision/mergerbox/mergerbox.h | 67 +++ board/matrix_vision/mergerbox/pci.c | 134 +++++++ board/matrix_vision/mergerbox/sm107.c | 126 ++++++ boards.cfg | 1 + doc/README.mergerbox | 59 +++ include/configs/MERGERBOX.h | 619 +++++++++++++++++++++++++++++ 11 files changed, 1504 insertions(+), 0 deletions(-) create mode 100644 board/matrix_vision/mergerbox/Makefile create mode 100644 board/matrix_vision/mergerbox/fpga.c create mode 100644 board/matrix_vision/mergerbox/fpga.h create mode 100644 board/matrix_vision/mergerbox/mergerbox.c create mode 100644 board/matrix_vision/mergerbox/mergerbox.h create mode 100644 board/matrix_vision/mergerbox/pci.c create mode 100644 board/matrix_vision/mergerbox/sm107.c create mode 100644 doc/README.mergerbox create mode 100644 include/configs/MERGERBOX.h

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[U-Boot] [PATCH] MPC83xx: add config options for memory setup.
by Andre Schwarz 07 Jul '11

07 Jul '11

CPO value and driver strength settings are board specifc. Also allow SPD data fetch from any accessible I2C EEPROM. Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 19 ++++++++++++++++++- 1 files changed, 18 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 44aaa9a..9b01f0d 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -68,6 +68,12 @@ void board_add_ram_info(int use_default) #ifndef CONFIG_SYS_READ_SPD #define CONFIG_SYS_READ_SPD i2c_read #endif +#ifndef SPD_EEPROM_OFFSET +#define SPD_EEPROM_OFFSET 0 +#endif +#ifndef SPD_EEPROM_ADDR_LEN +#define SPD_EEPROM_ADDR_LEN 1 +#endif /* * Convert picoseconds into clock cycles (rounding up if needed). @@ -160,7 +166,8 @@ long int spd_sdram() isync(); /* Read SPD parameters with I2C */ - CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd)); + CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, SPD_EEPROM_OFFSET, + SPD_EEPROM_ADDR_LEN, (uchar *) &spd, sizeof(spd)); #ifdef SPD_DEBUG spd_debug(&spd); #endif @@ -562,6 +569,9 @@ long int spd_sdram() * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266. */ wr_data_delay = 2; +#ifdef CONFIG_SYS_DDR_WRITE_DATA_DELAY + wr_data_delay = CONFIG_SYS_DDR_WRITE_DATA_DELAY; +#endif /* * Write Latency @@ -601,6 +611,9 @@ long int spd_sdram() */ cpo = 0; if (spd.mem_type == SPD_MEMTYPE_DDR2) { +#ifdef CONFIG_SYS_DDR_CPO + cpo = CONFIG_SYS_DDR_CPO; +#else if (effective_data_rate == 266) { cpo = 0x4; /* READ_LAT + 1/2 */ } else if (effective_data_rate == 333) { @@ -611,6 +624,7 @@ long int spd_sdram() /* Automatic calibration */ cpo = 0x1f; } +#endif } ddr->timing_cfg_2 = (0 @@ -679,6 +693,9 @@ long int spd_sdram() ddr->sdram_mode = (0 | (1 << (16 + 10)) /* DQS Differential disable */ +#ifdef CONFIG_SYS_DDR_MODE_WEAK + | (1 << (16 + 1)) /* weak driver (~60%) */ +#endif | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */ | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */ | ((twr_clk - 1) << 9) /* Write Recovery Autopre */ -- 1.7.0.4

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[U-Boot] [PATCH] MPC83xx: add define for global half-strength enable (HSE)
by Andre Schwarz 07 Jul '11

07 Jul '11

Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- include/mpc83xx.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ea137c7..8292018 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -1000,6 +1000,7 @@ #define SDRAM_CFG_8_BE 0x00040000 #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 +#define SDRAM_CFG_HSE 0x00000008 #define SDRAM_CFG_BI 0x00000001 /* DDR_SDRAM_MODE - DDR SDRAM Mode Register -- 1.7.0.4

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[U-Boot] [PATCH v2] MPC837x: set i2c1_clk
by Andre Schwarz 07 Jul '11

07 Jul '11

Running on mpc837x without CONFIG_FSL_ESDHC leads to i2c1_clk not being set at all. It is bound to clock of encryption module. fix this. Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- Changes for v2: - fix commit message mangling in subject line. arch/powerpc/cpu/mpc83xx/speed.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/speed.c b/arch/powerpc/cpu/mpc83xx/speed.c index 5e616dd..1eca1a8 100644 --- a/arch/powerpc/cpu/mpc83xx/speed.c +++ b/arch/powerpc/cpu/mpc83xx/speed.c @@ -327,6 +327,8 @@ int get_clocks(void) i2c1_clk = enc_clk; #elif defined(CONFIG_FSL_ESDHC) i2c1_clk = sdhc_clk; +#elif defined(CONFIG_MPC837x) + i2c1_clk = enc_clk; #endif #if !defined(CONFIG_MPC832x) i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */ -- 1.7.0.4

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[U-Boot] [PATCH] fsl_dma: fix support for 83xx DMA engine
by Ira W. Snyder 07 Jul '11

07 Jul '11

Commit 359ec4931944adb885882deb9b781e4095eabc94 broke support for the Freescale DMA engine on the 83xx parts. This is due to using registers which do not exist on 83xx. Remove the attribute register accesses from the 83xx build. Signed-off-by: Ira W. Snyder <iws(a)ovro.caltech.edu> Cc: York Sun <yorksun(a)freescale.com> Cc: Peter Tyser <ptyser(a)xes-inc.com> Cc: Kumar Gala <galak(a)kernel.crashing.org> --- drivers/dma/fsl_dma.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 09c18c1..30785ec 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -116,10 +116,12 @@ int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) { out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF)); out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF)); +#if !defined(CONFIG_MPC83xx) out_dma32(&dma->satr, in_dma32(&dma->satr) | (u32)((u64)src >> 32)); out_dma32(&dma->datr, in_dma32(&dma->datr) | (u32)((u64)dest >> 32)); +#endif out_dma32(&dma->bcr, xfer_size); dma_sync(); -- 1.7.3.4

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[U-Boot] [Patch 1/1] Spi Flash: Allow auto-booting of images from spi flash load
by Andre Renaud 07 Jul '11

07 Jul '11

This allows intelligent booting of FIT (& the legacy style) images from SPI flash. Basically it means that you don't have to guess at the image length, so data reads are more optimal (& hopefully faster). Signed-off-by: Andre Renaud <andre(a)bluewatersys.com> --- Index: common/cmd_sf.c =================================================================== --- common/cmd_sf.c (revision 31) +++ common/cmd_sf.c (working copy) @@ -109,6 +109,96 @@ return 0; } +static int do_spi_flash_boot(cmd_tbl_t *cmdtp, int argc, char * const argv[]) +{ + char *ep; + size_t cnt; + image_header_t *hdr; +#if defined(CONFIG_FIT) + const void *fit_hdr = NULL; +#endif + unsigned long addr; + unsigned long offset; + char *endp; + int ret; + + if (argc < 3) + return -1; + + addr = simple_strtoul(argv[1], &endp, 16); + if (*argv[1] == 0 || *endp != 0) + return -1; + offset = simple_strtoul(argv[2], &endp, 16); + if (*argv[2] == 0 || *endp != 0) + return -1; + + printf("\nLoading from offset 0x%lx\n", offset); + + ret = spi_flash_read(flash, offset, 1024, (u_char *)addr); + if (ret) { + printf("SPI flash boot failed\n"); + return 1; + } + + switch (genimg_get_format((void *)addr)) { + case IMAGE_FORMAT_LEGACY: + hdr = (image_header_t *)addr; + + image_print_contents(hdr); + + cnt = image_get_image_size(hdr); + break; +#if defined(CONFIG_FIT) + case IMAGE_FORMAT_FIT: + fit_hdr = (const void *)addr; + puts("Fit image detected...\n"); + + cnt = fit_get_size(fit_hdr); + break; +#endif + default: + puts("** Unknown image type\n"); + return 1; + } + + ret = spi_flash_read(flash, offset, cnt, (u_char *)addr); + if (ret) { + printf("SPI flash boot failed\n"); + return 1; + } + +#if defined(CONFIG_FIT) + /* This cannot be done earlier, + * we need complete FIT image in RAM first */ + if (genimg_get_format((void *)addr) == IMAGE_FORMAT_FIT) { + if (!fit_check_format(fit_hdr)) { + puts("** Bad FIT image format\n"); + return 1; + } + fit_print_contents(fit_hdr); + } +#endif + + /* Loading ok, update default load address */ + + load_addr = addr; + + /* Check if we should attempt an auto-start */ + if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) { + char *local_args[2]; + + local_args[0] = "bootm"; + local_args[1] = NULL; + + printf("Automatic boot of image at addr 0x%08lx ...\n", addr); + + do_bootm(cmdtp, 0, 1, local_args); + return 1; + } + return 0; +} + + static int do_spi_flash_read_write(int argc, char * const argv[]) { unsigned long addr; @@ -207,6 +297,8 @@ ret = do_spi_flash_read_write(argc, argv); else if (strcmp(cmd, "erase") == 0) ret = do_spi_flash_erase(argc, argv); + else if (strcmp(cmd, "boot") == 0) + ret = do_spi_flash_boot(cmdtp, argc, argv); else ret = -1; @@ -229,4 +321,7 @@ " at `addr' to flash at `offset'\n" "sf erase offset [+]len - erase `len' bytes from `offset'\n" " `+len' round up `len' to block size" + "sf boot addr offset - read a boot image starting at\n" + " `offset' to memory at `addr' and\n" + " execute it\n" );

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[U-Boot] [PATCH] ARM: Update maintainer of board scb9328
by Torsten Koschorrek 06 Jul '11

06 Jul '11

Signed-off-by: Torsten Koschorrek <koschorrek(a)synertronixx.de> --- MAINTAINERS | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index c462ae2..fe578ef 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -684,7 +684,7 @@ Matthias Kaehlcke <matthias(a)kaehlcke.net> edb9315 ARM920T (EP9315) edb9315a ARM920T (EP9315) -Konstantin Kletschke <kletschke(a)synertronixx.de> +Torsten Koschorrek <koschorrek(a)synertronixx.de> scb9328 ARM920T Nishant Kamat <nskamat(a)ti.com> -- 1.7.2.5

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