July 2011 - U-Boot

[U-Boot] [PATCH] STx AMC8548: initial support for Silicon Turnkey Express AMC8548 board
by Alex Dubov 18 Oct '11

18 Oct '11

AMC8548 is a RapidIO development board in AMC form factor, featuring MPC8548E processor, DDR2 SO-DIMM slot, 16MB of hardwired NAND flash memory, real time clock and additional serial EEPROM on i2c bus (enabled). USB controller is available, but not presently enabled. Additional board information is available at: http://www.silicontkx.com/AMC8548.htm Signed-off-by: Alex Dubov <oakad(a)yahoo.com> --- This is really a patch repost from Fall, 2009. The board is old and never was that good, but I still got those running, so I propped up an u-boot config as well. Nothing fancy here, just a fairly standard config. MAINTAINERS | 1 + board/stx/stxamc8548/Makefile | 53 ++++++ board/stx/stxamc8548/law.c | 50 +++++ board/stx/stxamc8548/stxamc8548.c | 120 ++++++++++++ board/stx/stxamc8548/tlb.c | 82 ++++++++ boards.cfg | 1 + include/configs/stxamc8548.h | 374 +++++++++++++++++++++++++++++++++++++ 7 files changed, 681 insertions(+), 0 deletions(-) create mode 100644 board/stx/stxamc8548/Makefile create mode 100644 board/stx/stxamc8548/law.c create mode 100644 board/stx/stxamc8548/stxamc8548.c create mode 100644 board/stx/stxamc8548/tlb.c create mode 100644 include/configs/stxamc8548.h diff --git a/MAINTAINERS b/MAINTAINERS index 14d06ca..787db07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -141,6 +141,7 @@ Jon Diekema <jon.diekema(a)smiths-aerospace.com> Alex Dubov <oakad(a)yahoo.com> mpq101 MPC8548 + stxamc8548 MPC8548 Dirk Eibach <eibach(a)gdsys.de> diff --git a/board/stx/stxamc8548/Makefile b/board/stx/stxamc8548/Makefile new file mode 100644 index 0000000..58bc1b3 --- /dev/null +++ b/board/stx/stxamc8548/Makefile @@ -0,0 +1,53 @@ +# +# Copyright 2007 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/stx/stxamc8548/law.c b/board/stx/stxamc8548/law.c new file mode 100644 index 0000000..0a435d9 --- /dev/null +++ b/board/stx/stxamc8548/law.c @@ -0,0 +1,50 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +/* + * LAW(Local Access Window) configuration: + * + * 0x0000_0000 0x1fff_ffff DDR (set elsewhere) autodetect + * 0xc000_0000 0xdfff_ffff RapidIO (set elsewhere) 512M + * 0xe000_0000 0xe000_ffff CCSR (set elsewhere) 1M + * 0xf000_0000 0xffff_ffff LBC options + FLASH 256M + * + * Notes: + * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. + * If flash is 8M at default position (last 8M), no LAW needed. + * + * LAW 0 is reserved for boot mapping + */ + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE_PHYS, LAW_SIZE_256M, + LAW_TRGT_IF_LBC) +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stx/stxamc8548/stxamc8548.c b/board/stx/stxamc8548/stxamc8548.c new file mode 100644 index 0000000..e0c4f9c --- /dev/null +++ b/board/stx/stxamc8548/stxamc8548.c @@ -0,0 +1,120 @@ +/* + * (C) Copyright 2011 Alex Dubov <oakad(a)yahoo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <i2c.h> + +/* + * Initialize Local Bus + */ +void local_bus_init(void) +{ + fsl_lbc_t *lbc = LBC_BASE_ADDR; + + out_be32(&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ + out_be32(&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ +} + +int checkboard(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + + puts("Board: Silicon Turnkey Express AMC8548 "); +#ifdef CONFIG_PHYS_64BIT + puts("(36-bit addrmap) "); +#endif + putc('\n'); + + /* + * Initialize local bus. + */ + local_bus_init(); + + /* + * Hack TSEC 3 and 4 IO voltages. + */ + out_be32(&gur->tsec34ioovcr, 0xe7e0); /* 1110 0111 1110 0xxx */ + + out_be32(&ecm->eedr, 0xffffffff); /* clear ecm errors */ + out_be32(&ecm->eeer, 0xffffffff); /* enable ecm errors */ + return 0; +} + +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) +{ + int rc = 0; + + if (ctrl_num == 0) { + rc = i2c_read(SPD_EEPROM_ADDRESS, 0, 1, (uchar *)ctrl_dimms_spd, + sizeof(ddr2_spd_eeprom_t)); + if (rc) { + debug("DDR: failed to read SPD from address %u\n", + SPD_EEPROM_ADDRESS); + memset(ctrl_dimms_spd, 0, sizeof(ddr2_spd_eeprom_t)); + } + } +} + +unsigned int fsl_ddr_get_mem_data_rate(void) +{ + return get_ddr_freq(0); +} + +void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + popts->clk_adjust = 6; + popts->cpo_override = 7; + popts->write_data_delay = 3; + popts->half_strength_driver_enable = 0; +} + +void pci_init_board(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* PCI is disabled */ + out_be32(&gur->devdisr, in_be32(&gur->devdisr) + | MPC85xx_DEVDISR_PCI1 + | MPC85xx_DEVDISR_PCI2 + | MPC85xx_DEVDISR_PCIE); +} + +#if defined(CONFIG_OF_BOARD_SETUP) + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); +} + +#endif diff --git a/board/stx/stxamc8548/tlb.c b/board/stx/stxamc8548/tlb.c new file mode 100644 index 0000000..fd2eaec --- /dev/null +++ b/board/stx/stxamc8548/tlb.c @@ -0,0 +1,82 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* + * TLB 0: 256M Non-cacheable, guarded + * 0xf0000000 256M LBC (FLASH included) + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, + CONFIG_SYS_LBC_OPTION_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 1: 1M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + +#ifdef CONFIG_SYS_SRIO1_MEM_PHYS + /* + * TLB 2: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 3: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, + CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 141b143..2096cc3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -497,6 +497,7 @@ P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freesca P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020,SPIFLASH P4080DS powerpc mpc85xx corenet_ds freescale mpq101 powerpc mpc85xx mpq101 mercury - mpq101 +stxamc8548 powerpc mpc85xx stxamc8548 stx - stxamc8548 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M diff --git a/include/configs/stxamc8548.h b/include/configs/stxamc8548.h new file mode 100644 index 0000000..e6eb799 --- /dev/null +++ b/include/configs/stxamc8548.h @@ -0,0 +1,374 @@ +/* + * Copyright 2011 Alex Dubov <oakad(a)yahoo.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Merury Computers MPQ101 board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#ifdef CONFIG_36BIT +# define CONFIG_PHYS_64BIT +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */ +#define CONFIG_MPC8548 /* MPC8548 specific */ +#define CONFIG_MPQ101 /* MPQ101 board specific */ + +#define CONFIG_SYS_SRIO /* enable serial RapidIO */ +#define CONFIG_TSEC_ENET /* tsec ethernet support */ +#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_PANIC_HANG + +/* + * Only possible on E500 Version 2 or newer cores. + */ +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_ADDR_MAP +# define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ +#endif + + +#define CONFIG_SYS_CLK_FREQ 33000000 /* sysclk for MPC85xx */ + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 +#define CONFIG_SYS_CCSRBAR 0xe0000000 + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_CCSRBAR_PHYS 0xfe0000000ull +#else +# define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR +#endif + +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR + +/* DDR Setup */ +#define CONFIG_FSL_DDR2 +#define CONFIG_DDR_SPD +#define CONFIG_SPD_EEPROM +#define CONFIG_DDR_2T_TIMING +#define SPD_EEPROM_ADDRESS 0x50 + +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ + +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) + + +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_START 0x0ff00000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0ffffffc + +/* + * RAM definitions + */ +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* + * Local Bus Definitions + */ +#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ + + +/* + * FLASH on the Local Bus + * One bank, 16M, using the CFI driver. + */ +#define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 128M */ + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_FLASH_BASE_PHYS 0xfff000000ull +#else +# define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +/* 0xff001801 */ +#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ + | BR_PS_32 | BR_V) + +/* 0xff006e65 */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(16) | OR_GPCM_XAM | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 | OR_GPCM_SCY_6 \ + | OR_GPCM_TRLX | OR_GPCM_EAD) + +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ + +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 +/* + * When initializing flash, if we cannot find the manufacturer ID, + * assume this is the AMD flash. + */ +#define CONFIG_ASSUME_AMD_FLASH + +/* + * Environment parameters + */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K boot sector */ +#define CONFIG_ENV_SIZE 0x4000 + +/* Environment at the start of flash sector, before text. */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x58000) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_TEXT_BASE 0xfffA0000 + +/* + * Cypress CY7C67200 USB controller on the Local Bus. + * Not supported by u-boot at present. + */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 + +#ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_LBC_OPTION_BASE_PHYS 0xff0000000ull +#else +# define CONFIG_SYS_LBC_OPTION_BASE_PHYS CONFIG_SYS_LBC_OPTION_BASE +#endif + +/* 0xf0001001 */ +#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBC_OPTION_BASE_PHYS) \ + | BR_PS_16 | BR_V) + +/* fffff002 */ +#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(0x8000) | OR_GPCM_XAM \ + | OR_GPCM_BCTLD | OR_GPCM_EHTR) + +/* + * Serial Ports + */ +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE {300, 600, 1200, 2400, 4800, 9600, \ + 19200, 38400, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* + * I2C buses and peripherals + */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support*/ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C RTC - DS1339 */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +/* I2C EEPROM - 24C32 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_BUS_NUM 0 + +/* + * RapidIO MMU + */ +#ifdef CONFIG_SYS_SRIO +# define CONFIG_SRIO1 +# define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000 +# define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +# ifdef CONFIG_PHYS_64BIT +# define CONFIG_SYS_SRIO1_MEM_PHYS 0xfc0000000ull +# else +# define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_VIRT +# endif +#endif + +/* + * Ethernet + */ +#ifdef CONFIG_TSEC_ENET + +# ifndef CONFIG_NET_MULTI +# define CONFIG_NET_MULTI +# endif + +# define CONFIG_MII /* MII PHY management */ +# define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ + +# define CONFIG_TSEC1 +# define CONFIG_TSEC1_NAME "eTSEC0" +# define TSEC1_PHY_ADDR 0x10 +# define TSEC1_PHYIDX 0 +# define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +# define CONFIG_TSEC2 +# define CONFIG_TSEC2_NAME "eTSEC1" +# define TSEC2_PHY_ADDR 0x11 +# define TSEC2_PHYIDX 0 +# define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +# define CONFIG_TSEC3 +# define CONFIG_TSEC3_NAME "eTSEC2" +# define TSEC3_PHY_ADDR 0x12 +# define TSEC3_PHYIDX 0 +# define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +# define CONFIG_TSEC4 +# define CONFIG_TSEC4_NAME "eTSEC3" +# define TSEC4_PHY_ADDR 0x13 +# define TSEC4_PHYIDX 0 +# define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +/* Options are: eTSEC[0-3] */ +# define CONFIG_ETHPRIME "eTSEC0" +# define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_MII +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_JFFS2 + +/* + * Miscellaneous configurable options + */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +#define CONFIG_FIT /* new uImage format support */ +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER + +#ifdef CONFIG_SYS_HUSH_PARSER +# define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ + +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "AMC8548=> " /* Monitor Command Prompt */ + +/* Console I/O Buffer Size */ +#ifdef CONFIG_CMD_KGDB +# define CONFIG_SYS_CBSIZE 1024 +#else +# define CONFIG_SYS_CBSIZE 256 +#endif + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) + +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 16 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +# define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +# define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Basic Environment Configuration + */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +/*default location for tftp and bootm*/ +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR + +#endif /* __CONFIG_H */ -- 1.7.3.2

3 6

[U-Boot] [PATCH] tools: make it possible to build tools unconfigured
by Ilya Yanok 17 Oct '11

17 Oct '11

Sometimes we want to build common tools without configuring for specific target. Currently top Makefile has some support for this but it doesn't work. This patch tries to fix this. Things changed: - config.mk disable 'ld script not found error' in case if we are building tools only. - Makefile mkimage relies on autogenerated version so we need to move $(VERSION_FILE) rule out of ifeq and make tools rule depend on it. - tools/Makefile put common/env_embedded.o and envcrc.o to object list conditionally. This fixes errors during dependency generation. Signed-off-by: Ilya Yanok <yanok(a)emcraft.com> --- Makefile | 34 +++++++++++++++++----------------- config.mk | 2 ++ tools/Makefile | 19 ++++++++++++++++--- 3 files changed, 35 insertions(+), 20 deletions(-) diff --git a/Makefile b/Makefile index dcf5d93..4f7326e 100644 --- a/Makefile +++ b/Makefile @@ -140,7 +140,7 @@ SUBDIRS = tools \ examples/standalone \ examples/api -.PHONY : $(SUBDIRS) +.PHONY : $(SUBDIRS) $(VERSION_FILE) ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) @@ -422,19 +422,6 @@ mmc_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend $(obj)mmc_spl/u-boot-mmc-spl.bin: mmc_spl -$(VERSION_FILE): - @( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \ - printf '#define PLAIN_VERSION "%s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \ - "$(U_BOOT_VERSION)" "$${localvers}" ; \ - ) > $@.tmp - @( printf '#define CC_VERSION_STRING "%s"\n' \ - '$(shell $(CC) --version | head -n 1)' )>> $@.tmp - @( printf '#define LD_VERSION_STRING "%s"\n' \ - '$(shell $(LD) -v | head -n 1)' )>> $@.tmp - @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ - $(TIMESTAMP_FILE): @LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@ @LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@ @@ -509,20 +496,33 @@ $(obj)lib/asm-offsets.s: $(obj)include/autoconf.mk.dep \ else # !config.mk all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ -$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) \ +$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) \ updater depend dep tags ctags etags cscope $(obj)System.map: @echo "System not configured - see README" >&2 @ exit 1 -tools: +tools: $(VERSION_FILE) $(MAKE) -C $@ all endif # config.mk +$(VERSION_FILE): + @( localvers='$(shell $(TOPDIR)/tools/setlocalversion $(TOPDIR))' ; \ + printf '#define PLAIN_VERSION "%s%s"\n' \ + "$(U_BOOT_VERSION)" "$${localvers}" ; \ + printf '#define U_BOOT_VERSION "U-Boot %s%s"\n' \ + "$(U_BOOT_VERSION)" "$${localvers}" ; \ + ) > $@.tmp + @( printf '#define CC_VERSION_STRING "%s"\n' \ + '$(shell $(CC) --version | head -n 1)' )>> $@.tmp + @( printf '#define LD_VERSION_STRING "%s"\n' \ + '$(shell $(LD) -v | head -n 1)' )>> $@.tmp + @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ + easylogo env gdb: $(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION} gdbtools: gdb -tools-all: easylogo env gdb +tools-all: easylogo env gdb $(VERSION_FILE) $(MAKE) -C tools HOST_TOOLS_ALL=y .PHONY : CHANGELOG diff --git a/config.mk b/config.mk index 7ce554e..51994f2 100644 --- a/config.mk +++ b/config.mk @@ -180,7 +180,9 @@ ifndef LDSCRIPT LDSCRIPT := $(TOPDIR)/$(CPUDIR)/u-boot.lds endif ifeq ($(wildcard $(LDSCRIPT)),) + ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) $(error could not find linker script) + endif endif endif diff --git a/tools/Makefile b/tools/Makefile index 623f908..30ae0b5 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -67,7 +67,14 @@ BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) # Source files which exist outside the tools directory -EXT_OBJ_FILES-y += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_IN_DATAFLASH) += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_IN_EEPROM) += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_IN_FLASH) += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_IN_ONENAND) += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_IN_NAND) += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_IN_NVRAM) += common/env_embedded.o +EXT_OBJ_FILES-$(CONFIG_ENV_IS_IN_SPI_FLASH) += common/env_embedded.o EXT_OBJ_FILES-y += common/image.o EXT_OBJ_FILES-y += lib/crc32.o EXT_OBJ_FILES-y += lib/md5.o @@ -77,7 +84,14 @@ EXT_OBJ_FILES-y += lib/sha1.o OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o NOPED_OBJ_FILES-y += default_image.o -OBJ_FILES-y += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_IN_DATAFLASH) += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_IN_EEPROM) += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_IN_FLASH) += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_IN_ONENAND) += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_IN_NAND) += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_IN_NVRAM) += envcrc.o +OBJ_FILES-$(CONFIG_ENV_IS_IN_SPI_FLASH) += envcrc.o NOPED_OBJ_FILES-y += fit_image.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o @@ -149,7 +163,6 @@ HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \ -DUSE_HOSTCC \ -D__KERNEL_STRICT_NAMES - all: $(obj).depend $(BINS) $(LOGO-y) subdirs $(obj)bin2header$(SFX): $(obj)bin2header.o -- 1.7.4.4

4 12

[U-Boot] [PATCH] cmd_bmp: fix very long uncompressing time of gzipped bitmaps
by Anatolij Gustschin 17 Oct '11

17 Oct '11

If a compressed bitmap is located in sectors at the end of the flash and it's offset + CONFIG_SYS_VIDEO_LOGO_MAX_SIZE > 0xFFFFFFFF, the uncompressing time is very long, since processing the stream is done bytewise (and not blockwise) due to overflow in inflate_fast() while calculation and checking for enough input available. Fix available bitmap data input size for gunzip() to match the actually available data size to prevent the observed misbehaviour. Reported-by: Werner Pfister <werner.pfister(a)intercontrol.de> Signed-off-by: Anatolij Gustschin <agust(a)denx.de> --- common/cmd_bmp.c | 9 +++++++++ drivers/video/cfb_console.c | 10 ++++++++++ 2 files changed, 19 insertions(+), 0 deletions(-) diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index 23fc82f..0640a95 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -32,6 +32,8 @@ #include <asm/byteorder.h> #include <malloc.h> +DECLARE_GLOBAL_DATA_PTR; + static int bmp_info (ulong addr); static int bmp_display (ulong addr, int x, int y); @@ -47,6 +49,7 @@ static int bmp_display (ulong addr, int x, int y); #ifdef CONFIG_VIDEO_BMP_GZIP bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) { + unsigned long flash_end; void *dst; unsigned long len; bmp_image_t *bmp; @@ -55,6 +58,12 @@ bmp_image_t *gunzip_bmp(unsigned long addr, unsigned long *lenp) * Decompress bmp image */ len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + flash_end = gd->bd->bi_flashstart + gd->bd->bi_flashsize - 1; + if (addr >= gd->bd->bi_flashstart && addr <= flash_end) { + if (flash_end - addr < CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) + len = flash_end - addr + 1; + } + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { puts("Error: malloc in gunzip failed!\n"); diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index b427c84..42b4b21 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -334,6 +334,7 @@ void console_cursor (int state); #define PRINTD(x) #endif +DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_CONSOLE_EXTRA_INFO extern void video_get_info_str ( /* setup a board string: type, speed, etc. */ @@ -1043,7 +1044,16 @@ int video_display_bitmap (ulong bmp_image, int x, int y) /* * Could be a gzipped bmp image, try to decrompress... */ + unsigned long addr = (unsigned long)bmp; + unsigned long flash_end; + len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE; + flash_end = gd->bd->bi_flashstart + gd->bd->bi_flashsize - 1; + if (addr >= gd->bd->bi_flashstart && addr <= flash_end) { + if (flash_end - addr < CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) + len = flash_end - addr + 1; + } + dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE); if (dst == NULL) { printf("Error: malloc in gunzip failed!\n"); -- 1.7.1

3 4

[U-Boot] [PATCH V2] Ethernut 5 board support
by Harald Kipp 17 Oct '11

17 Oct '11

Add support for the Ethernut 5 open hardware design, based on Atmel's AT91SAM9XE512 SoC. Signed-off-by: Harald Kipp <harald.kipp(a)egnite.de> --- V2: - Fix several coding style issues. - Remove Ethernet MAC address from default environment. MAINTAINERS | 3 + board/egnite/ethernut5/Makefile | 54 +++++ board/egnite/ethernut5/ethernut5.c | 259 ++++++++++++++++++++++ board/egnite/ethernut5/ethernut5_pwrman.c | 339 +++++++++++++++++++++++++++++ board/egnite/ethernut5/ethernut5_pwrman.h | 68 ++++++ boards.cfg | 1 + include/configs/ethernut5.h | 281 ++++++++++++++++++++++++ 7 files changed, 1005 insertions(+), 0 deletions(-) create mode 100644 board/egnite/ethernut5/Makefile create mode 100644 board/egnite/ethernut5/ethernut5.c create mode 100644 board/egnite/ethernut5/ethernut5_pwrman.c create mode 100644 board/egnite/ethernut5/ethernut5_pwrman.h create mode 100644 include/configs/ethernut5.h diff --git a/MAINTAINERS b/MAINTAINERS index 4756f14..8b8aa49 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -616,6 +616,9 @@ Wolfgang Denk <wd(a)denx.de> imx27lite i.MX27 qong i.MX31 +egnite GmbH <info(a)egnite.de> + ethernut5 ARM926EJS (AT91SAM9XE SoC) + Thomas Elste <info(a)elste.org> modnet50 ARM720T (NET+50) diff --git a/board/egnite/ethernut5/Makefile b/board/egnite/ethernut5/Makefile new file mode 100644 index 0000000..d8e485f --- /dev/null +++ b/board/egnite/ethernut5/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2003-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# (C) Copyright 2010 +# egnite GmbH +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += $(BOARD)_pwrman.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/egnite/ethernut5/ethernut5.c b/board/egnite/ethernut5/ethernut5.c new file mode 100644 index 0000000..ab6d28a --- /dev/null +++ b/board/egnite/ethernut5/ethernut5.c @@ -0,0 +1,259 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info(a)egnite.de> + * + * (C) Copyright 2010 + * Ole Reinhardt <ole.reinhardt(a)thermotemp.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 general board support + * + * Ethernut is an open source hardware and software project for + * embedded Ethernet devices. Hardware layouts and CAD files are + * freely available under BSD-like license. + * + * Ethernut 5 is the first member of the Ethernut board family + * with U-Boot and Linux support. This implementation is based + * on the original work done by Ole Reinhardt, but heavily modified + * to support additional features and the latest board revision 5.0F. + * + * Main board components are by default: + * + * Atmel AT91SAM9XE512 CPU with 512 kBytes NOR Flash + * 2 x 64 MBytes Micron MT48LC32M16A2P SDRAM + * 512 MBytes Micron MT29F4G08ABADA NAND Flash + * 4 MBytes Atmel AT45DB321D DataFlash + * SMSC LAN8710 Ethernet PHY + * Atmel ATmega168 MCU used for power management + * Linear Technology LTC4411 PoE controller + * + * U-Boot relevant board interfaces are: + * + * 100 Mbit Ethernet with IEEE 802.3af PoE + * RS-232 serial port + * USB host and device + * MMC/SD-Card slot + * Expansion port with I2C, SPI and more... + * + * Typically the U-Boot image is loaded from serial DataFlash into + * SDRAM by the samboot boot loader, which is located in internal + * NOR Flash and provides all essential initializations like CPU + * and peripheral clocks and, of course, the SDRAM configuration. + * + * For testing purposes it is also possibly to directly transfer + * the image into SDRAM via JTAG. A tested configuration exists + * for the Turtelizer 2 hardware dongle and the OpenOCD software. + * In this case the latter will do the basic hardware configuration + * via its reset-init script. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +#include <common.h> +#include <net.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include <spi.h> +#include <dataflash.h> +#include <mmc.h> + +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91sam9_matrix.h> +#include <asm/arch/at91sam9_smc.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_pmc.h> +#include <asm/arch/at91_spi.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> + +#include "ethernut5_pwrman.h" + +DECLARE_GLOBAL_DATA_PTR; + +AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS]; + +struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = { + {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0} +}; + +/* + * In fact we have 7 partitions, but u-boot supports 5 only. This is + * no big deal, because the first partition is reserved for applications + * and the last one is used by Nut/OS. Both need not to be visible here. + */ +dataflash_protect_t area_list[NB_DATAFLASH_AREA] = { + { 0x00021000, 0x00041FFF, FLAG_PROTECT_SET, 0, "setup" }, + { 0x00042000, 0x000C5FFF, FLAG_PROTECT_SET, 0, "uboot" }, + { 0x000C6000, 0x00359FFF, FLAG_PROTECT_SET, 0, "kernel" }, + { 0x0035A000, 0x003DDFFF, FLAG_PROTECT_SET, 0, "nutos" }, + { 0x003DE000, 0x003FEFFF, FLAG_PROTECT_CLEAR, 0, "env" } +}; + +/* + * This is called last during early initialization. Most of the basic + * hardware interfaces are up and running. + * + * The SDRAM hardware has been configured by the first stage boot loader. + * We only need to announce its size, using u-boot's memory check. + */ +int dram_init(void) +{ + gd->ram_size = get_ram_size( + (volatile long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +/* + * This is called first during late initialization. + */ +int board_init(void) +{ + /* Enable all GPIO clocks. */ + at91_sys_write(AT91_PMC_PCER, + (1 << AT91SAM9260_ID_PIOA) | + (1 << AT91SAM9260_ID_PIOB) | + (1 << AT91SAM9260_ID_PIOC)); + /* Enable ctrl+c. */ + console_init_f(); + /* Set our official architecture number. */ + gd->bd->bi_arch_number = MACH_TYPE_ETHERNUT5; + /* Set adress of boot parameters. */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + /* Initialize UARTs and power management. */ + at91_serial_hw_init(); + ethernut5_power_init(); + +#ifdef CONFIG_CMD_NAND + /* Enable NAND flash chip select. */ + at91_sys_write(AT91_MATRIX_EBICSA, + at91_sys_read(AT91_MATRIX_EBICSA) | + AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Configure SMC for Micron NAND Flash. */ + at91_sys_write(AT91_SMC_SETUP(3), + AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC_PULSE(3), + AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | + AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); + at91_sys_write(AT91_SMC_CYCLE(3), + AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); + at91_sys_write(AT91_SMC_MODE(3), + AT91_SMC_READMODE | AT91_SMC_WRITEMODE | + AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8 | + AT91_SMC_TDF_(2)); +#ifdef CONFIG_SYS_NAND_READY_PIN + /* Ready pin is optional. */ + at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); +#endif + at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); +#endif + +#ifdef CONFIG_HAS_DATAFLASH + at91_spi0_hw_init(1 << 0); +#endif + return 0; +} + +#ifdef CONFIG_MACB +/* + * This is optionally called last during late initialization. + */ +int board_eth_init(bd_t *bis) +{ + const char *devname; + unsigned short mode; + + /* Enable on-chip EMAC clock. */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); + /* Need to reset PHY via power management. */ + ethernut5_phy_reset(); + /* Set peripheral pins. */ + at91_macb_hw_init(); + /* Basic EMAC initialization. */ + if (macb_eth_initialize(0, (void *)AT91_EMAC_BASE, CONFIG_PHY_ID)) + return -1; + /* + * Early board revisions have a pull-down at the PHY's MODE0 + * strap pin, which forces the PHY into power down. Here we + * switch to all-capable mode. + */ + devname = miiphy_get_current_dev(); + if (miiphy_read(devname, 0, 18, &mode) == 0) { + /* Set mode[2:0] to 0b111. */ + mode |= 0x00E0; + miiphy_write(devname, 0, 18, mode); + /* Soft reset overrides strap pins. */ + miiphy_write(devname, 0, MII_BMCR, BMCR_RESET); + } + /* Sync environment with network devices, needed for nfsroot. */ + return eth_init(gd->bd); +} +#endif + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bd) +{ + /* Enable MCI clock. */ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + /* Initialize MCI hardware. */ + at91_mci_hw_init(); + /* Register the device. */ + return atmel_mci_init((void *)AT91_BASE_MCI); +} + +int board_mmc_getcd(u8 *cd, struct mmc *mmc) +{ + *cd = at91_get_gpio_value(CONFIG_SYS_MMC_CD_PIN) ? 1 : 0; + return 0; +} +#endif + +#ifdef CONFIG_ATMEL_SPI +/* + * Note, that u-boot uses different code for SPI bus access. While + * memory routines use automatic chip select control, the serial + * flash support requires 'manual' GPIO control. Thus, we switch + * modes. + */ +void spi_cs_activate(struct spi_slave *slave) +{ + /* Enable NPCS0 in GPIO mode. This disables peripheral control. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 0); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + /* Disable NPCS0 in GPIO mode. */ + at91_set_pio_output(AT91_PIO_PORTA, 3, 1); + /* Switch back to peripheral chip select control. */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 1); +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs == 0; +} +#endif diff --git a/board/egnite/ethernut5/ethernut5_pwrman.c b/board/egnite/ethernut5/ethernut5_pwrman.c new file mode 100644 index 0000000..01d7744 --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.c @@ -0,0 +1,339 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info(a)egnite.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * This board may be supplied via USB, IEEE 802.3af PoE or an + * auxiliary DC input. An on-board ATmega168 microcontroller, + * the so called power management controller or PMC, is used + * to select the supply source and to switch on and off certain + * energy consuming board components. This allows to reduce the + * total stand-by consumption to less than 70mW. + * + * The main CPU communicates with the PMC via I2C. When + * CONFIG_CMD_BSP is defined in the board configuration file, + * then the board specific command 'pwrman' becomes available, + * which allows to manually deal with the PMC. + * + * Two distinct registers are provided by the PMC for enabling + * and disabling specific features. This avoids the often seen + * read-modify-write cycle or shadow register requirement. + * Additional registers are available to query the board + * status and temperature, the auxiliary voltage and to control + * the green user LED that is integrated in the reset switch. + * + * Note, that the AVR firmware of the PMC is released under BSDL. + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ +#include <common.h> +#include <asm/arch/at91sam9260.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#include <i2c.h> + +#include "ethernut5_pwrman.h" + +/* PMC firmware version */ +static int pwrman_major; +static int pwrman_minor; + +/* + * Enable Ethernut 5 power management. + * + * This function must be called during board initialization. + * While we are using u-boot's I2C subsystem, it may be required + * to enable the serial port before calling this function, + * in particular when debugging is enabled. + * + * If board specific commands are not available, we will activate + * all board components. + */ +void ethernut5_power_init(void) +{ + pwrman_minor = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VERS); + pwrman_major = pwrman_minor >> 4; + pwrman_minor &= 15; + +#ifndef CONFIG_CMD_BSP + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major == 2) { + /* Without board specific commands we enable all features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, ~PWRMAN_ETHRST); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + } +#endif +} + +/* + * Reset Ethernet PHY. + * + * This function allows the re-configure the PHY after + * changing its strap pins. + */ +void ethernut5_phy_reset(void) +{ + /* Do not modify anything, if we do not have a known version. */ + if (pwrman_major != 2) + return; + + /* + * Make sure that the Ethernet clock is enabled and the PHY reset + * is disabled for at least 100 us. + */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHCLK); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + udelay(100); + + /* + * LAN8710 strap pins are + * PA14 => PHY MODE0 + * PA15 => PHY MODE1 + * PA17 => PHY MODE2 => 111b all capable + * PA18 => PHY ADDR0 => 0b + */ + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); + at91_set_pio_input(AT91_PIO_PORTA, 15, 1); + at91_set_pio_input(AT91_PIO_PORTA, 17, 1); + at91_set_pio_input(AT91_PIO_PORTA, 18, 0); + + /* Activate PHY reset for 100 us. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, PWRMAN_ETHRST); + udelay(100); + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, PWRMAN_ETHRST); + + at91_set_pio_input(AT91_PIO_PORTA, 14, 1); +} + +/* + * Output the firmware version we got during initialization. + */ +void ethernut5_print_version(void) +{ + printf("%u.%u\n", pwrman_major, pwrman_minor); +} + +/* + * All code below this point is optional and implements + * the 'pwrman' command. + */ +#ifdef CONFIG_CMD_BSP + +/* Human readable names of PMC features */ +char *pwrman_feat[8] = { + "board", "vbin", "vbout", "mmc", + "rs232", "ethclk", "ethrst", "wakeup" +}; + +/* + * Print all feature names, that have its related flags enabled. + */ +static void print_flagged_features(u8 flags) +{ + int i; + + for (i = 0; i < 8; i++) { + if (flags & (1 << i)) + printf("%s ", pwrman_feat[i]); + } +} + +/* + * Return flags of a given list of feature names. + * + * The function stops at the first unknown list entry and + * returns the number of detected names as a function result. + */ +static int feature_flags(char * const names[], int num, u8 *flags) +{ + int i, j; + + *flags = 0; + for (i = 0; i < num; i++) { + for (j = 0; j < 8; j++) { + if (strcmp(pwrman_feat[j], names[i]) == 0) { + *flags |= 1 << j; + break; + } + } + if (j > 7) + break; + } + return i; +} + +void ethernut5_print_power(void) +{ + u8 flags; + int i; + + flags = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA); + for (i = 0; i < 2; i++) { + if (flags) { + print_flagged_features(flags); + printf("%s\n", i ? "off" : "on"); + } + flags = ~flags; + } +} + +void ethernut5_print_celsius(void) +{ + int val; + + /* Read ADC value from LM50 and return Celsius degrees. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_TEMP); + val *= 5000; /* 100mV/degree with 5V reference */ + val += 128; /* 8 bit resolution */ + val /= 256; + val -= 450; /* Celsius offset, still x10 */ + /* Output full degrees. */ + printf("%d\n", (val + 5) / 10); +} + +void ethernut5_print_voltage(void) +{ + int val; + + /* Read ADC value from divider and return voltage. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_VAUX); + /* Resistors are 100k and 12.1k */ + val += 5; + val *= 180948; + val /= 100000; + val++; + /* Calculation was done in 0.1V units. */ + printf("%d\n", (val + 5) / 10); +} + +/* + * Process the board specific 'pwrman' command. + */ +int do_pwrman(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + u8 val; + int i; + + if (argc == 1) { + ethernut5_print_power(); + } else if (argc == 2 && strcmp(argv[1], "reset") == 0) { + at91_set_pio_output(AT91_PIO_PORTB, 8, 1); + udelay(100); + at91_set_pio_output(AT91_PIO_PORTB, 8, 0); + udelay(100000); + } else if (argc == 2 && strcmp(argv[1], "temp") == 0) { + ethernut5_print_celsius(); + } else if (argc == 2 && strcmp(argv[1], "vaux") == 0) { + ethernut5_print_voltage(); + } else if (argc == 2 && strcmp(argv[1], "version") == 0) { + ethernut5_print_version(); + } else if (strcmp(argv[1], "led") == 0) { + /* Control the green status LED. Blink frequency unit + ** is 0.1s, very roughly. */ + if (argc == 2) { + /* No more arguments, output current settings. */ + val = i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL); + printf("led %u %u\n", val >> 4, val & 15); + } else { + /* First argument specifies the on-time. */ + val = (u8) simple_strtoul(argv[2], NULL, 0); + val <<= 4; + if (argc > 3) { + /* Second argument specifies the off-time. */ + val |= (u8) (simple_strtoul(argv[3], NULL, 0) + & 15); + } + /* Update the LED control register. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_LEDCTL, val); + } + } else { + /* We expect a list of features followed an optional status. */ + argc--; + i = feature_flags(&argv[1], argc, &val); + if (argc == i) { + /* We got a list only, print status. */ + val &= i2c_reg_read(PWRMAN_I2C_ADDR, PWRMAN_REG_STA); + if (val) { + if (i > 1) + print_flagged_features(val); + printf("active\n"); + } else { + printf("inactive\n"); + } + } else { + /* More arguments. */ + if (i == 0) { + /* No given feature, use despensibles. */ + val = PWRMAN_DISPENSIBLE; + } + if (strcmp(argv[i + 1], "on") == 0) { + /* Enable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_ENA, + val); + } else if (strcmp(argv[i + 1], "off") == 0) { + /* Disable features. */ + i2c_reg_write(PWRMAN_I2C_ADDR, PWRMAN_REG_DIS, + val); + } else { + printf("Bad parameter %s\n", argv[i + 1]); + return 1; + } + } + } + return 0; +} + +U_BOOT_CMD( + pwrman, CONFIG_SYS_MAXARGS, 1, do_pwrman, + "power management", + "- print settings\n" + "pwrman feature ...\n" + " - print status\n" + "pwrman [feature ...] on|off\n" + " - enable/disable specified or all dispensible features\n" + "pwrman led [on-time [off-time]]\n" + " - print or set led blink timer\n" + "pwrman temp\n" + " - print board temperature (Celsius)\n" + "pwrman vaux\n" + " - print auxiliary input voltage\n" + "pwrman reset\n" + " - reset power management controller\n" + "pwrman version\n" + " - print firmware version\n" + "\n" + " features, (*)=dispensible:\n" + " board - 1.8V and 3.3V supply\n" + " vbin - supply via USB device connector\n" + " vbout - USB host connector supply(*)\n" + " mmc - MMC slot supply(*)\n" + " rs232 - RS232 driver\n" + " ethclk - Ethernet PHY clock(*)\n" + " ethrst - Ethernet PHY reset\n" + " wakeup - RTC alarm" +); +#endif /* CONFIG_CMD_BSP */ diff --git a/board/egnite/ethernut5/ethernut5_pwrman.h b/board/egnite/ethernut5/ethernut5_pwrman.h new file mode 100644 index 0000000..0541884 --- /dev/null +++ b/board/egnite/ethernut5/ethernut5_pwrman.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info(a)egnite.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Ethernut 5 power management support + * + * For additional information visit the project home page at + * http://www.ethernut.de/ + */ + +/* I2C address of the PMC */ +#define PWRMAN_I2C_ADDR 0x22 + +/* PMC registers */ +#define PWRMAN_REG_VERS 0 /* Version register */ +#define PWRMAN_REG_STA 1 /* Feature status register */ +#define PWRMAN_REG_ENA 2 /* Feature enable register */ +#define PWRMAN_REG_DIS 3 /* Feature disable register */ +#define PWRMAN_REG_TEMP 4 /* Board temperature */ +#define PWRMAN_REG_VAUX 6 /* Auxiliary input voltage */ +#define PWRMAN_REG_LEDCTL 8 /* LED blinking timer. */ + +/* Feature flags used in status, enable and disable registers */ +#define PWRMAN_BOARD 0x01 /* 1.8V and 3.3V supply */ +#define PWRMAN_VBIN 0x02 /* VBUS input at device connector */ +#define PWRMAN_VBOUT 0x04 /* VBUS output at host connector */ +#define PWRMAN_MMC 0x08 /* Memory card supply */ +#define PWRMAN_RS232 0x10 /* RS-232 driver shutdown */ +#define PWRMAN_ETHCLK 0x20 /* Ethernet clock enable */ +#define PWRMAN_ETHRST 0x40 /* Ethernet PHY reset */ +#define PWRMAN_WAKEUP 0x80 /* RTC wake-up */ + +/* Features, which are not essential to keep u-boot alive */ +#define PWRMAN_DISPENSIBLE (PWRMAN_VBOUT | PWRMAN_MMC | PWRMAN_ETHCLK) + +/* Enable Ethernut 5 power management. */ +extern void ethernut5_power_init(void); + +/* Reset Ethernet PHY. */ +extern void ethernut5_phy_reset(void); + +extern void ethernut5_print_version(void); + +#ifdef CONFIG_CMD_BSP +extern void ethernut5_print_power(void); +extern void ethernut5_print_celsius(void); +extern void ethernut5_print_voltage(void); +#endif diff --git a/boards.cfg b/boards.cfg index 45c3102..8b5d5a5 100644 --- a/boards.cfg +++ b/boards.cfg @@ -73,6 +73,7 @@ omap1510inn arm arm925t - ti aspenite arm arm926ejs - Marvell armada100 afeb9260 arm arm926ejs - - at91 at91cap9adk arm arm926ejs - atmel at91 +ethernut5 arm arm926ejs ethernut5 egnite at91 top9000eval_xe arm arm926ejs top9000 emk at91 top9000:EVAL9000 top9000su_xe arm arm926ejs top9000 emk at91 top9000:SU9000 meesc arm arm926ejs - esd at91 diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h new file mode 100644 index 0000000..efd5121 --- /dev/null +++ b/include/configs/ethernut5.h @@ -0,0 +1,281 @@ +/* + * (C) Copyright 2011 + * egnite GmbH <info(a)egnite.de> + * + * Configuation settings for Ethernut 5 with AT91SAM9XE. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* The first stage boot loader expects u-boot running at this address. */ +#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */ + +/* The first stage boot loader takes care of low level initialization. */ +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* CPU information */ +#define CONFIG_ARM926EJS +#define CONFIG_AT91FAMILY +#define CONFIG_AT91SAM9260 +#define CONFIG_AT91SAM9XE /* Special variant. */ +#define CONFIG_DISPLAY_CPUINFO /* Display at console. */ +#define CONFIG_ARCH_CPU_INIT + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ +#define CONFIG_SYS_HZ 1000 +#undef CONFIG_USE_IRQ /* Running w/o interrupts */ + +/* 32kB internal SRAM */ +#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */ +#define CONFIG_SRAM_SIZE (32 << 10) +#define CONFIG_STACKSIZE (CONFIG_SRAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_STACKSIZE) + +/* 128MB SDRAM in 1 bank */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE (128 << 20) +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \ + - CONFIG_SYS_MALLOC_LEN) + +/* 512kB on-chip NOR flash */ +# define CONFIG_SYS_MAX_FLASH_BANKS 1 +# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */ +# define CONFIG_AT91_EFLASH +# define CONFIG_SYS_MAX_FLASH_SECT 32 +# define CONFIG_SYS_FLASH_PROTECTION /* First stage loader in sector 0 */ +# define CONFIG_EFLASH_PROTSECTORS 1 + +/* 512kB DataFlash at NPCS0 */ +#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 +#define CONFIG_HAS_DATAFLASH +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_ATMEL +#define CONFIG_ATMEL_DATAFLASH_SPI +#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 +#define DATAFLASH_TCSS (0x1a << 16) +#define DATAFLASH_TCHS (0x1 << 24) + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x3DE000 +#define CONFIG_ENV_SECT_SIZE (132 << 10) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ + + CONFIG_ENV_OFFSET) +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \ + + 0x042000) + +/* SPI */ +#define CONFIG_ATMEL_SPI +#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ) +#define AT91_SPI_CLK 15000000 + +/* Serial port */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART3 /* USART 3 is DBGU */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } + +/* Misc. hardware drivers */ +#define CONFIG_AT91_GPIO + +/* Command line configuration */ +#include <config_cmd_default.h> +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_LOADS + +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_SPI + +#ifdef MINIMAL_LOADER +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_IMI +#undef CONFIG_CMD_ITEST +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_XIMG +#else +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_BSP +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CDP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DNS +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MMC +#define CONFIG_CMD_PING +#define CONFIG_CMD_RARP +#define CONFIG_CMD_REISER +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SNTP +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_UNZIP +#define CONFIG_CMD_USB +#endif + +/* NAND flash */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_DBW_8 +#define CONFIG_NAND_ATMEL +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 +#define CONFIG_AT91_LEGACY +#endif + +/* JFFS2 */ +#ifdef CONFIG_CMD_JFFS2 +#define CONFIG_MTD_NAND_ECC_JFFS2 +#define CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_NAND +#endif + +/* Ethernet */ +#define CONFIG_NET_MULTI +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_PHY_ID 0 +#define CONFIG_MACB_SEARCH_PHY + +/* MMC */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define CONFIG_SYS_MMC_CD_PIN AT91_PIN_PC8 +#endif + +/* USB */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_STORAGE +#endif + +/* RTC */ +#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP) +#define CONFIG_RTC_PCF8563 +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 +#endif + +/* I2C */ +#define CONFIG_SYS_MAX_I2C_BUS 1 +#define CONFIG_SYS_I2C_SLAVE 0 +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_SOFT_I2C +#define I2C_SOFT_DECLARATIONS + +#define GPIO_I2C_SCL AT91_PIN_PA24 +#define GPIO_I2C_SDA AT91_PIN_PA23 + +#define I2C_INIT { \ + at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ + at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \ + at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \ + at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ +} + +#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0) +#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0) +#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) +#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit) +#define I2C_DELAY udelay(100) +#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23) + +/* DHCP/BOOTP options */ +#ifdef CONFIG_CMD_DHCP +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_SYS_AUTOLOAD "n" +#endif + +/* File systems */ +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND) +#define MTDIDS_DEFAULT "nand0=atmel_nand" +#define MTDPARTS_DEFAULT "mtdparts=atmel_nand:-(root)" +#endif +#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \ + defined(CONFIG_CMD_USB) || defined(CONFIG_MMC) +#define CONFIG_DOS_PARTITION +#endif +#define CONFIG_LZO +#define CONFIG_RBTREE + +/* Boot command */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_BOOTCOMMAND "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm" +#if defined(CONFIG_CMD_NAND) +#define CONFIG_BOOTARGS "console=ttyS0,115200 " \ + "root=/dev/mtdblock0 " \ + MTDPARTS_DEFAULT \ + " rw rootfstype=jffs2" +#endif + +/* Misc. u-boot settings */ +#define CONFIG_SYS_PROMPT "U-Boot> " +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + 16 \ + + sizeof(CONFIG_SYS_PROMPT)) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#endif -- 1.7.0.4

3 5

[U-Boot] [PATCH v7 0/4] Board support series for the eXMeritus HWW-1U-1A
by Kyle Moffett 16 Oct '11

16 Oct '11

This is the final respin of the eXMeritus HWW-1U-1A board support patches, rebased onto the 'next' branch of git://git.denx.de/u-boot-mpc85xx.git This code conforms to the Linux kernel coding style. It passes checkpatch with only a few false positives. I believe these 4 patches are ready to be merged. Cheers, Kyle Moffett

2 8

[U-Boot] [PATCH 0/5] mpc5200: digsy_mtc: update for next
by Anatolij Gustschin 15 Oct '11

15 Oct '11

This patch series mainly updates digsy_mtc board to initialize graphic extention hardware and add splash screen support. The last patch is an update for "mtc appreg" command. Anatolij Gustschin (5): video: mb862xx: support Coral-PA controller pci: option for configurable delay between pci reset and pci bus scan mpc5200: digsy_mtc: enable pci_scan_delay option mpc5200: digsy_mtc: add support for graphic extension board mpc5200: digsy_mtc: add support for writing 'appreg' value board/digsy_mtc/Makefile | 7 +++-- board/digsy_mtc/cmd_disp.c | 54 +++++++++++++++++++++++++++++++++++++++++++ board/digsy_mtc/cmd_mtc.c | 46 +++++++++++++++++++++++++++++++---- board/digsy_mtc/digsy_mtc.c | 49 +++++++++++++++++++++++++++++++++++++++ board/digsy_mtc/exbo.h | 17 +++++++++++++ drivers/pci/pci.c | 14 +++++++++++ drivers/video/mb862xx.c | 32 +++++++++++++++++++++---- include/configs/digsy_mtc.h | 28 ++++++++++++++++++++++ 8 files changed, 233 insertions(+), 14 deletions(-) create mode 100644 board/digsy_mtc/cmd_disp.c create mode 100644 board/digsy_mtc/exbo.h -- 1.7.4.4

6 34

[U-Boot] [PATCH 1/2] NS16550: buffer reads
by Scott Wood 15 Oct '11

15 Oct '11

This improves the performance of U-Boot when accepting rapid input, such as pasting a sequence of commands. Without this patch, on P4080DS I see a maximum of around 5 mw.l lines can be pasted. With this patch, it handles around 70 lines before lossage, long enough for most things you'd paste. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- README | 8 ++++ drivers/serial/ns16550.c | 96 +++++++++++++++++++++++++++++++++++++++++++-- drivers/serial/serial.c | 4 +- include/ns16550.h | 4 +- 4 files changed, 103 insertions(+), 9 deletions(-) diff --git a/README b/README index bd03523..d21ea9c 100644 --- a/README +++ b/README @@ -2682,6 +2682,14 @@ use the "saveenv" command to store a valid environment. space for already greatly restricted images, including but not limited to NAND_SPL configurations. +- CONFIG_NS16550_BUFFER_READS: + Instead of reading directly from the receive register + every time U-Boot is ready for another byte, keep a + buffer and fill it from the hardware fifo every time + U-Boot reads a character. This helps U-Boot keep up with + a larger amount of rapid input, such as happens when + pasting text into the terminal. + Low Level (hardware related) configuration options: --------------------------------------------------- diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 8eeb48f..ed3428d 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -4,12 +4,15 @@ * modified to use CONFIG_SYS_ISA_MEM and new defines */ +#include <common.h> #include <config.h> #include <ns16550.h> #include <watchdog.h> #include <linux/types.h> #include <asm/io.h> +DECLARE_GLOBAL_DATA_PTR; + #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ UART_MCR_RTS) /* RTS/DTR */ @@ -86,21 +89,104 @@ void NS16550_putc (NS16550_t com_port, char c) } #ifndef CONFIG_NS16550_MIN_FUNCTIONS -char NS16550_getc (NS16550_t com_port) + +static char NS16550_raw_getc(NS16550_t regs) { - while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) { + while ((serial_in(&regs->lsr) & UART_LSR_DR) == 0) { #ifdef CONFIG_USB_TTY extern void usbtty_poll(void); usbtty_poll(); #endif WATCHDOG_RESET(); } - return serial_in(&com_port->rbr); + return serial_in(&regs->rbr); +} + +static int NS16550_raw_tstc(NS16550_t regs) +{ + return ((serial_in(&regs->lsr) & UART_LSR_DR) != 0); +} + + +#ifdef CONFIG_NS16550_BUFFER_READS + +#define BUF_SIZE 256 +#define NUM_PORTS 4 + +struct ns16550_priv { + char buf[BUF_SIZE]; + unsigned int head, tail; +}; + +static struct ns16550_priv rxstate[NUM_PORTS]; + +static void enqueue(unsigned int port, char ch) +{ + /* If queue is full, drop the character. */ + if ((rxstate[port].head - rxstate[port].tail - 1) % BUF_SIZE == 0) + return; + + rxstate[port].buf[rxstate[port].tail] = ch; + rxstate[port].tail = (rxstate[port].tail + 1) % BUF_SIZE; +} + +static int dequeue(unsigned int port, char *ch) +{ + /* Empty queue? */ + if (rxstate[port].head == rxstate[port].tail) + return 0; + + *ch = rxstate[port].buf[rxstate[port].head]; + rxstate[port].head = (rxstate[port].head + 1) % BUF_SIZE; + return 1; +} + +static void fill_rx_buf(NS16550_t regs, unsigned int port) +{ + while ((serial_in(&regs->lsr) & UART_LSR_DR) != 0) + enqueue(port, serial_in(&regs->rbr)); +} + +char NS16550_getc(NS16550_t regs, unsigned int port) +{ + char ch; + + if (port >= NUM_PORTS || !(gd->flags & GD_FLG_RELOC)) + return NS16550_raw_getc(regs); + + do { +#ifdef CONFIG_USB_TTY + extern void usbtty_poll(void); + usbtty_poll(); +#endif + fill_rx_buf(regs, port); + WATCHDOG_RESET(); + } while (!dequeue(port, &ch)); + + return ch; +} + +int NS16550_tstc(NS16550_t regs, unsigned int port) +{ + if (port >= NUM_PORTS || !(gd->flags & GD_FLG_RELOC)) + return NS16550_raw_tstc(regs); + + fill_rx_buf(regs, port); + + return rxstate[port].head != rxstate[port].tail; +} + +#else /* CONFIG_NS16550_BUFFER_READS */ + +char NS16550_getc(NS16550_t regs, unsigned int port) +{ + return NS16550_raw_getc(regs); } -int NS16550_tstc (NS16550_t com_port) +int NS16550_tstc(NS16550_t regs, unsigned int port) { - return ((serial_in(&com_port->lsr) & UART_LSR_DR) != 0); + return NS16550_raw_tstc(regs); } +#endif /* CONFIG_NS16550_BUFFER_READS */ #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 4032dfd..3fc80b1 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -219,13 +219,13 @@ _serial_puts (const char *s,const int port) int _serial_getc(const int port) { - return NS16550_getc(PORT); + return NS16550_getc(PORT, port); } int _serial_tstc(const int port) { - return NS16550_tstc(PORT); + return NS16550_tstc(PORT, port); } void diff --git a/include/ns16550.h b/include/ns16550.h index 9ea81e9..fa3e62e 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -160,6 +160,6 @@ typedef volatile struct NS16550 *NS16550_t; void NS16550_init (NS16550_t com_port, int baud_divisor); void NS16550_putc (NS16550_t com_port, char c); -char NS16550_getc (NS16550_t com_port); -int NS16550_tstc (NS16550_t com_port); +char NS16550_getc (NS16550_t regs, unsigned int port); +int NS16550_tstc (NS16550_t regs, unsigned int port); void NS16550_reinit (NS16550_t com_port, int baud_divisor); -- 1.7.1

4 8

[U-Boot] [PATCH v2 0/5] usb:gadget USB Gadget support
by Lukasz Majewski 11 Oct '11

11 Oct '11

Presented patches provide Linux USB Gadget support for U-boot running on the Samsung's SoC family of processors. This patch series include UDC driver and example USB Mass Storage gadger implementation. --- Changes for v2: - Patches have been divided in a more logical way - Some #define registers definitions (in the UDC) have been replaced with structures - Detailed information about Kernel origin for USB Mass Storage Gadget files - Code cleanup and fixes Lukasz Majewski (5): usb:gadget:s5p USB Device Controller (UDC) implementation usb:gadget:s5p Enabling the USB Gadget framework at GONI usb:gadget: USB Mass Storage - files from Linux kernel usb:gadget: USB Mass Storage Gadget support usb:gadget:s5p Support for USB Mass Storage Gadget on GONI arch/arm/include/asm/arch-s5pc1xx/cpu.h | 4 + arch/arm/include/asm/arch-s5pc1xx/hs_otg.h | 32 + board/samsung/goni/goni.c | 139 ++ common/Makefile | 1 + common/cmd_usb_mass_storage.c | 78 + drivers/usb/gadget/Makefile | 7 +- drivers/usb/gadget/file_storage.c | 3536 ++++++++++++++++++++++++++++ drivers/usb/gadget/regs-otg.h | 209 ++ drivers/usb/gadget/s3c_udc_otg.c | 892 +++++++ drivers/usb/gadget/s3c_udc_otg_xfer_dma.c | 1419 +++++++++++ drivers/usb/gadget/storage_common.c | 765 ++++++ include/configs/s5p_goni.h | 10 + include/usb/lin_gadget_compat.h | 66 + include/usb/s3c_udc.h | 160 ++ include/usb_mass_storage.h | 56 + 15 files changed, 7371 insertions(+), 3 deletions(-) create mode 100644 arch/arm/include/asm/arch-s5pc1xx/hs_otg.h create mode 100644 common/cmd_usb_mass_storage.c create mode 100644 drivers/usb/gadget/file_storage.c create mode 100644 drivers/usb/gadget/regs-otg.h create mode 100644 drivers/usb/gadget/s3c_udc_otg.c create mode 100644 drivers/usb/gadget/s3c_udc_otg_xfer_dma.c create mode 100644 drivers/usb/gadget/storage_common.c create mode 100644 include/usb/lin_gadget_compat.h create mode 100644 include/usb/s3c_udc.h create mode 100644 include/usb_mass_storage.h -- 1.7.2.3

4 18

[U-Boot] [PATCH 0/1 v4] RFC: Dreamplug support
by u-boot＠lakedaemon.net 07 Oct '11

07 Oct '11

From: Jason Cooper <u-boot(a)lakedaemon.net> It compiles clean, and I've loaded it via JTAG and used it to dump the existing bootloader out of the SPI flash. I have _not_ used it to burn itself to the flash yet. I'm looking for comments before I try that. ;-) Some concerns: - The SPI flash chip is a Macronix MX25L1606, however it has the identical chip idcode to the MX25L1605. How is that properly handled? The 06 does have some new features [1]. [1] http://www.macronix.com/QuickPlace/hq/PageLibrary4825740B00298A3B.nsf/h_Ind… Changes from v1 to v2: - resorted series to move 'make all' support last. Changes from v2 to v3: - Use MACH_TYPE_GURUPLUG for now until dreamplug support is in Linux. - Update MAINTAINERS. - Collapse into one patch. Changes from v3 to v4: - update copyright info as recommended by Prafulla Wadaskar. - maintain proper order in boards.cfg, MAINTAINERS, etc. - label MPP's - change back to MACH_TYPE_DREAMPLUG. This patch is just RFC until the Dreamplug is supported in Linux (and MACH_TYPE_ added). Jason Cooper (1): dreamplug: Initial support. MAINTAINERS | 4 + MAKEALL | 1 + board/Marvell/dreamplug/Makefile | 54 +++++++++++ board/Marvell/dreamplug/dreamplug.c | 157 ++++++++++++++++++++++++++++++++ board/Marvell/dreamplug/dreamplug.h | 42 +++++++++ board/Marvell/dreamplug/kwbimage.cfg | 163 ++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/dreamplug.h | 114 ++++++++++++++++++++++++ 8 files changed, 536 insertions(+), 0 deletions(-) create mode 100644 board/Marvell/dreamplug/Makefile create mode 100644 board/Marvell/dreamplug/dreamplug.c create mode 100644 board/Marvell/dreamplug/dreamplug.h create mode 100644 board/Marvell/dreamplug/kwbimage.cfg create mode 100644 include/configs/dreamplug.h

10 59

[U-Boot] [PATCH] powerpc/p2040rdb: Add p2040rdb board support
by Mingkai Hu 07 Oct '11

07 Oct '11

P2040RDB Specification: ----------------------- Memory subsystem: * 4Gbyte unbuffered DDR3 SDRAM SO-DIMM(64bit bus) * 128 Mbyte NOR flash single-chip memory * 256 Kbit M24256 I2C EEPROM * 16 Mbyte SPI memory * SD connector to interface with the SD memory card Ethernet: * dTSEC1: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC2: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC3: connected to the Vitesse SGMII PHY (VSC8221) * dTSEC4: connected to the Vitesse RGMII PHY (VSC8641) * dTSEC5: connected to the Vitesse RGMII PHY (VSC8641) PCIe: * Lanes E, F, G and H of Bank1 are connected to one x4 PCIe SLOT1 * Lanes C and Land D of Bank2 are connected to one x4 PCIe SLOT2 SATA: Lanes C and Land D of Bank2 are connected to two SATA connectors USB 2.0: connected via a internal UTMI PHY to two TYPE-A interfaces I2C: * I2C1: Real time clock, Temperature sensor, Memory module * I2C2: Vcore Regulator, 256Kbit I2C Bus EEPROM, PCIe slot1/2 UART: supports two UARTs up to 115200 bps for console Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> --- Based on http://git.denx.de/?p=u-boot/u-boot-mpc85xx.git;a=shortlog;h=refs/heads/next board/freescale/p2040rdb/Makefile | 56 ++++ board/freescale/p2040rdb/cpld.c | 171 ++++++++++ board/freescale/p2040rdb/cpld.h | 53 +++ board/freescale/p2040rdb/ddr.c | 115 +++++++ board/freescale/p2040rdb/law.c | 37 ++ board/freescale/p2040rdb/p2040rdb.c | 204 ++++++++++++ board/freescale/p2040rdb/pci.c | 39 +++ board/freescale/p2040rdb/tlb.c | 119 +++++++ boards.cfg | 3 + doc/README.p2040rdb | 123 +++++++ include/configs/P2040RDB.h | 617 +++++++++++++++++++++++++++++++++++ 11 files changed, 1537 insertions(+), 0 deletions(-) create mode 100644 board/freescale/p2040rdb/Makefile create mode 100644 board/freescale/p2040rdb/cpld.c create mode 100644 board/freescale/p2040rdb/cpld.h create mode 100644 board/freescale/p2040rdb/ddr.c create mode 100644 board/freescale/p2040rdb/law.c create mode 100644 board/freescale/p2040rdb/p2040rdb.c create mode 100644 board/freescale/p2040rdb/pci.c create mode 100644 board/freescale/p2040rdb/tlb.c create mode 100644 doc/README.p2040rdb create mode 100644 include/configs/P2040RDB.h diff --git a/board/freescale/p2040rdb/Makefile b/board/freescale/p2040rdb/Makefile new file mode 100644 index 0000000..65f348f --- /dev/null +++ b/board/freescale/p2040rdb/Makefile @@ -0,0 +1,56 @@ +# +# Copyright 2011 Freescale Semiconductor, Inc. +# (C) Copyright 2001-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += cpld.o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o +COBJS-$(CONFIG_PCI) += pci.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(OBJS) $(SOBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/p2040rdb/cpld.c b/board/freescale/p2040rdb/cpld.c new file mode 100644 index 0000000..8e1f46e --- /dev/null +++ b/board/freescale/p2040rdb/cpld.c @@ -0,0 +1,171 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CPLD_BASE - The virtual address of the base of the CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +static u8 __cpld_read(unsigned int reg) +{ + void *p = (void *)CPLD_BASE; + + return in_8(p + reg); +} +u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); + +static void __cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CPLD_BASE; + + out_8(p + reg, value); +} +void cpld_write(unsigned int reg, u8 value) + __attribute__((weak, alias("__cpld_write"))); + +/* + * Reset the board. This honors the por_cfg registers. + */ +void __cpld_reset(void) +{ + CPLD_WRITE(system_rst, 1); +} +void cpld_reset(void) __attribute__((weak, alias("__cpld_reset"))); + +/** + * Set the boot bank to the alternate bank + */ +void __cpld_set_altbank(void) +{ + CPLD_WRITE(fbank_sel, 1); +} +void cpld_set_altbank(void) + __attribute__((weak, alias("__cpld_set_altbank"))); + +/** + * Set the boot bank to the default bank + */ +void __cpld_clear_altbank(void) +{ + CPLD_WRITE(fbank_sel, 0); +} +void cpld_clear_altbank(void) + __attribute__((weak, alias("__cpld_clear_altbank"))); + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver)); + printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub)); + printf("pcba_ver = 0x%02x\n", CPLD_READ(pcba_ver)); + printf("system_rst = 0x%02x\n", CPLD_READ(system_rst)); + printf("wd_cfg = 0x%02x\n", CPLD_READ(wd_cfg)); + printf("sw_ctl_on = 0x%02x\n", CPLD_READ(sw_ctl_on)); + printf("por_cfg = 0x%02x\n", CPLD_READ(por_cfg)); + printf("switch_strobe = 0x%02x\n", CPLD_READ(switch_strobe)); + printf("jtag_sel = 0x%02x\n", CPLD_READ(jtag_sel)); + printf("sdbank1_clk = 0x%02x\n", CPLD_READ(sdbank1_clk)); + printf("sdbank2_clk = 0x%02x\n", CPLD_READ(sdbank2_clk)); + printf("fbank_sel = 0x%02x\n", CPLD_READ(fbank_sel)); + printf("serdes_mux = 0x%02x\n", CPLD_READ(serdes_mux)); + printf("SW[2] = 0x%02x\n", in_8(&CPLD_SW(2))); + putc('\n'); +} +#endif + +int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + unsigned int i; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (strcmp(argv[2], "altbank") == 0) + cpld_set_altbank(); + else + cpld_clear_altbank(); + + cpld_reset(); + } else if (strcmp(argv[1], "watchdog") == 0) { + static char *period[8] = {"1ms", "10ms", "30ms", "disable", + "100ms", "1s", "10s", "60s"}; + for (i = 0; i < ARRAY_SIZE(period); i++) { + if (strcmp(argv[2], period[i]) == 0) + CPLD_WRITE(wd_cfg, i); + } + } else if (strcmp(argv[1], "lane_mux") == 0) { + u32 lane = simple_strtoul(argv[2], NULL, 16); + u8 val = (u8)simple_strtoul(argv[3], NULL, 16); + u8 reg = CPLD_READ(serdes_mux); + + switch (lane) { + case 0x6: + reg &= ~SERDES_MUX_LANE_6_MASK; + reg |= val << SERDES_MUX_LANE_6_SHIFT; + break; + case 0xa: + reg &= ~SERDES_MUX_LANE_A_MASK; + reg |= val << SERDES_MUX_LANE_A_SHIFT; + break; + case 0xc: + reg &= ~SERDES_MUX_LANE_C_MASK; + reg |= val << SERDES_MUX_LANE_C_SHIFT; + break; + case 0xd: + reg &= ~SERDES_MUX_LANE_D_MASK; + reg |= val << SERDES_MUX_LANE_D_SHIFT; + break; + default: + printf("Invalid value\n"); + break; + } + + CPLD_WRITE(serdes_mux, reg); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board or pin mulexing selection using the CPLD sequencer", + "reset - hard reset to default bank\n" + "cpld_cmd reset altbank - reset to alternate bank\n" + "cpld_cmd watchdog <watchdog_period> - set the watchdog period\n" + " period: 1ms 10ms 30ms 100ms 1s 10s 60s disable\n" + "cpld_cmd lane_mux <lane> <mux_value> - set multiplexed lane pin\n" + " lane 6: 0 -> slot1 (Default)\n" + " 1 -> SGMII\n" + " lane a: 0 -> slot2 (Default)\n" + " 1 -> AURORA\n" + " lane c: 0 -> slot2 (Default)\n" + " 1 -> SATA0\n" + " lane d: 0 -> slot2 (Default)\n" + " 1 -> SATA1\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/p2040rdb/cpld.h b/board/freescale/p2040rdb/cpld.h new file mode 100644 index 0000000..3b24cb0 --- /dev/null +++ b/board/freescale/p2040rdb/cpld.h @@ -0,0 +1,53 @@ +/** + * Copyright 2011 Freescale Semiconductor + * Author: Mingkai Hu <Mingkai.hu(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +typedef struct cpld_data { + u8 cpld_ver; /* 0x0 - CPLD Major Revision Register */ + u8 cpld_ver_sub; /* 0x1 - CPLD Minor Revision Register */ + u8 pcba_ver; /* 0x2 - PCBA Revision Register */ + u8 system_rst; /* 0x3 - system reset register */ + u8 wd_cfg; /* 0x4 - Watchdog Period Setting Register */ + u8 sw_ctl_on; /* 0x5 - Switch Control Enable Register */ + u8 por_cfg; /* 0x6 - POR Control Register */ + u8 switch_strobe; /* 0x7 - Multiplexed pin Select Register */ + u8 jtag_sel; /* 0x8 - JTAG or AURORA Selection */ + u8 sdbank1_clk; /* 0x9 - SerDes Bank1 Reference clock */ + u8 sdbank2_clk; /* 0xa - SerDes Bank2 Reference clock */ + u8 fbank_sel; /* 0xb - Flash bank selection */ + u8 serdes_mux; /* 0xc - Multiplexed pin Select Register */ + u8 sw[1]; /* 0xd - SW2 Status */ +} __attribute__ ((packed)) cpld_data_t; + +#define SERDES_MUX_LANE_6_MASK 0x2 +#define SERDES_MUX_LANE_6_SHIFT 1 +#define SERDES_MUX_LANE_A_MASK 0x1 +#define SERDES_MUX_LANE_A_SHIFT 0 +#define SERDES_MUX_LANE_C_MASK 0x4 +#define SERDES_MUX_LANE_C_SHIFT 2 +#define SERDES_MUX_LANE_D_MASK 0x8 +#define SERDES_MUX_LANE_D_SHIFT 3 + +/* Pointer to the CPLD register set */ +#define cpld ((cpld_data_t *)CPLD_BASE) + +/* The CPLD SW register that corresponds to board switch X, where x >= 1 */ +#define CPLD_SW(x) (cpld->sw[(x) - 2]) + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_READ(reg) cpld_read(offsetof(cpld_data_t, reg)) +#define CPLD_WRITE(reg, value) cpld_write(offsetof(cpld_data_t, reg), value) diff --git a/board/freescale/p2040rdb/ddr.c b/board/freescale/p2040rdb/ddr.c new file mode 100644 index 0000000..46de910 --- /dev/null +++ b/board/freescale/p2040rdb/ddr.c @@ -0,0 +1,115 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <i2c.h> +#include <hwconfig.h> +#include <asm/mmu.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> +#include <asm/fsl_law.h> + +typedef struct { + u32 datarate_mhz_low; + u32 datarate_mhz_high; + u32 n_ranks; + u32 clk_adjust; + u32 wrlvl_start; + u32 cpo; + u32 write_data_delay; + u32 force_2T; +} board_specific_parameters_t; + +/* + * ranges for parameters: + * wr_data_delay = 0-6 + * clk adjust = 0-8 + * cpo 2-0x1E (30) + */ +const board_specific_parameters_t board_specific_parameters[] = { + /* + * memory controller 0 + * lo| hi| num| clk| wrlvl | cpo |wrdata|2T + * mhz| mhz|ranks|adjst| start | delay| + */ + { 1017, 1116, 2, 4, 6, 0xff, 2, 0}, +}; + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + const board_specific_parameters_t *pbsp = + &board_specific_parameters[0]; + u32 num_params = ARRAY_SIZE(board_specific_parameters); + u32 i; + ulong ddr_freq; + + /* + * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr + * freqency and n_banks specified in board_specific_parameters table. + */ + ddr_freq = get_ddr_freq(0) / 1000000; + for (i = 0; i < num_params; i++) { + if (ddr_freq >= pbsp->datarate_mhz_low && + ddr_freq <= pbsp->datarate_mhz_high && + pdimm[0].n_ranks == pbsp->n_ranks) { + popts->cpo_override = pbsp->cpo; + popts->write_data_delay = pbsp->write_data_delay; + popts->clk_adjust = pbsp->clk_adjust; + popts->wrlvl_start = pbsp->wrlvl_start; + popts->twoT_en = pbsp->force_2T; + break; + } + pbsp++; + } + + if (i == num_params) { + printf("Warning: board specific timing not found " + "for data rate %lu MT/s!\n", ddr_freq); + } + + /* + * Factors to consider for half-strength driver enable: + * - number of DIMMs installed + */ + popts->half_strength_driver_enable = 0; + /* Write leveling override */ + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + + /* Rtt and Rtt_WR override */ + popts->rtt_override = 0; + + /* Enable ZQ calibration */ + popts->zq_en = 1; + + /* DHC_EN =1, ODT = 60 Ohm */ + popts->ddr_cdr1 = DDR_CDR1_DHC_EN; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing...."); + + if (fsl_use_spd()) { + puts("using SPD\n"); + dram_size = fsl_ddr_sdram(); + } else { + puts("no SPD and fixed parameters\n"); + return dram_size; + } + + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + + puts(" DDR: "); + return dram_size; +} diff --git a/board/freescale/p2040rdb/law.c b/board/freescale/p2040rdb/law.c new file mode 100644 index 0000000..127a478 --- /dev/null +++ b/board/freescale/p2040rdb/law.c @@ -0,0 +1,37 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN), + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN), + SET_LAW(CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR), +#endif +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/p2040rdb/p2040rdb.c b/board/freescale/p2040rdb/p2040rdb.c new file mode 100644 index 0000000..1311a7a --- /dev/null +++ b/board/freescale/p2040rdb/p2040rdb.c @@ -0,0 +1,204 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <netdev.h> +#include <linux/compiler.h> +#include <asm/mmu.h> +#include <asm/processor.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_law.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_portals.h> +#include <asm/fsl_liodn.h> + +extern void pci_of_setup(void *blob, bd_t *bd); + +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + u8 sw; + struct cpu_type *cpu = gd->cpu; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + unsigned int i; + + printf("Board: %sRDB, ", cpu->name); + printf("CPLD version: %d.%d ", CPLD_READ(cpld_ver), + CPLD_READ(cpld_ver_sub)); + + sw = CPLD_READ(fbank_sel); + printf("vBank: %d\n", sw & 0x1); + +#ifdef CONFIG_PHYS_64BIT + puts("36-bit Addressing\n"); +#endif + + /* + * Display the RCW, so that no one gets confused as to what RCW + * we're actually using for this boot. + */ + puts("Reset Configuration Word (RCW):"); + for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { + u32 rcw = in_be32(&gur->rcwsr[i]); + + if ((i % 4) == 0) + printf("\n %08x:", i * 4); + printf(" %08x", rcw); + } + puts("\n"); + + /* + * Display the actual SERDES reference clocks as configured by the + * dip switches on the board. Note that the SWx registers could + * technically be set to force the reference clocks to match the + * values that the SERDES expects (or vice versa). For now, however, + * we just display both values and hope the user notices when they + * don't match. + */ + puts("SERDES Reference Clocks: "); + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < 2; i++) { + static const char *freq[] = {"0", "100", "125"}; + unsigned int clock = (sw >> (2 * i)) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); + + return 0; +} + +int board_early_init_f(void) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* + * P2040 RDB board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 + */ + setbits_be32(&gur->ddrclkdr, 0x000f000f); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash + PROMJET region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash + promjet */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */ + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */ + 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */ + + set_liodns(); + setup_portals(); + + return 0; +} + +static const char *serdes_clock_to_string(u32 clock) +{ + switch (clock) { + case SRDS_PLLCR0_RFCK_SEL_100: + return "100"; + case SRDS_PLLCR0_RFCK_SEL_125: + return "125"; + case SRDS_PLLCR0_RFCK_SEL_156_25: + return "156.25"; + default: + return "150"; + } +} + +#define NUM_SRDS_BANKS 2 + +int misc_init_r(void) +{ + serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + u32 actual[NUM_SRDS_BANKS]; + unsigned int i; + u8 sw; + + sw = in_8(&CPLD_SW(2)) >> 2; + for (i = 0; i < NUM_SRDS_BANKS; i++) { + unsigned int clock = (sw >> (2 * i)) & 3; + switch (clock) { + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '11' is " + "unsupported\n", i + 1); + break; + } + } + + for (i = 0; i < NUM_SRDS_BANKS; i++) { + u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; + if (expected != actual[i]) { + printf("Warning: SERDES bank %u expects reference clock" + " %sMHz, but actual is %sMHz\n", i + 1, + serdes_clock_to_string(expected), + serdes_clock_to_string(actual[i])); + } + } + + return 0; +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + + fdt_fixup_memory(blob, (u64)base, (u64)size); + +#ifdef CONFIG_PCI + pci_of_setup(blob, bd); +#endif + + fdt_fixup_liodn(blob); +} diff --git a/board/freescale/p2040rdb/pci.c b/board/freescale/p2040rdb/pci.c new file mode 100644 index 0000000..1ab4cdf --- /dev/null +++ b/board/freescale/p2040rdb/pci.c @@ -0,0 +1,39 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <pci.h> +#include <asm/fsl_pci.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <asm/fsl_serdes.h> + +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} + +void pci_of_setup(void *blob, bd_t *bd) +{ + FT_FSL_PCI_SETUP; +} diff --git a/board/freescale/p2040rdb/tlb.c b/board/freescale/p2040rdb/tlb.c new file mode 100644 index 0000000..43f28ed --- /dev/null +++ b/board/freescale/p2040rdb/tlb.c @@ -0,0 +1,119 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, + CONFIG_SYS_INIT_RAM_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR) + /* + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the + * SRAM is at 0xfff00000, it covered the 0xfffff000. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_1M, 1), +#else + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), +#endif + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_16M, 1), + + /* *I*G* - Flash, localbus */ + /* This will be changed to *I*G* after relocation to RAM. */ + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_1G, 1), + + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000, + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256K, 1), + + /* Bman/Qman */ + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 10, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 11, BOOKE_PAGESZ_1M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000, + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_1M, 1), +#ifdef CONFIG_SYS_DCSRBAR_PHYS + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 13, BOOKE_PAGESZ_4M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index e1bb9e0..903c65b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -575,6 +575,9 @@ P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH +P2040RDB powerpc mpc85xx p2040rdb freescale +P2040RDB_SDCARD powerpc mpc85xx p2040rdb freescale - P2040RDB:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 +P2040RDB_SPIFLASH powerpc mpc85xx p2040rdb freescale - P2040RDB:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000 P3041DS powerpc mpc85xx corenet_ds freescale P3041DS_NAND powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000 P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000 diff --git a/doc/README.p2040rdb b/doc/README.p2040rdb new file mode 100644 index 0000000..63cfb7c --- /dev/null +++ b/doc/README.p2040rdb @@ -0,0 +1,123 @@ +Overview +========= +The P2040 Processor combines four Power Architecture processor cores +with high-performance datapath acceleration architecture(DPAA), CoreNet +fabric infrastructure, as well as network and peripheral bus interfaces +required for networking, telecom/datacom, wireless infrastructure, and +military/aerospace applications. + +P2040RDB board is a quad core platform supporting the P2040 processor +of QorIQ DPAA series. + +Boot from NOR flash +=================== +1. Build image + make P2040RDB_config + make all + +2. Program image + => tftp 1000000 u-boot.bin + => protect off all + => erase eff80000 efffffff + => cp.b 1000000 eff80000 80000 + +3. Program RCW + => tftp 1000000 rcw.bin + => protect off all + => erase e8000000 e801ffff + => cp.b 1000000 e8000000 50 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => protect off all + => erase ef000000 ef0fffff + => cp.b 1000000 ef000000 2000 + +5. Change DIP-switch + SW1[1-5] = 10110 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SDCard +=================== +1. Build image + make P2040RDB_SDCARD_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SDCard which contains RCW and U-Boot image. + +3. Program the PBL image to SDCard + => tftp 1000000 pbl_sd.bin + => mmcinfo + => mmc write 1000000 8 441 + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => mmc write 1000000 46a 10 + +5. Change DIP-switch + SW1[1-5] = 01100 + Note: 1 stands for 'on', 0 stands for 'off' + +Boot from SPI flash +=================== +1. Build image + make P2040RDB_SPIFLASH_config + make all + +2. Generate PBL imge + Use PE tool to produce a image used to be programed to + SPI flash which contains RCW and U-Boot image. + +3. Program the PBL image to SPI flash + => tftp 1000000 pbl_spi.bin + => spi probe 0 + => sf erase 0 100000 + => sf write 1000000 0 $filesize + +4. Program FMAN Firmware ucode + => tftp 1000000 ucode.bin + => sf erase 110000 10000 + => sf write 1000000 110000 $filesize + +5. Change DIP-switch + SW1[1-5] = 10100 + Note: 1 stands for 'on', 0 stands for 'off' + +CPLD command +============ +The CPLD is used to control the power sequence and some serdes lane +mux function. + +cpld reset - hard reset to default bank +cpld reset altbank - reset to alternate bank +cpld lane_mux <lane> <mux_value> - set multiplexed lane pin + lane 6: 0 -> slot1 (Default) + 1 -> SGMII + lane a: 0 -> slot2 (Default) + 1 -> AURORA + lane c: 0 -> slot2 (Default) + 1 -> SATA0 + lane d: 0 -> slot2 (Default) + 1 -> SATA1 + +Using the Device Tree Source File +================================= +To create the DTB (Device Tree Binary) image file, use a command +similar to this: + dtc -O dtb -b 0 -p 1024 p2040rdb.dts > p2040rdb.dtb + +Or use the following command: + {linux-2.6}/make p2040rdb.dtb ARCH=powerpc + +then the dtb file will be generated under the following directory: + {linux-2.6}/arch/powerpc/boot/p2040rdb.dtb + +Booting Linux +============= +Place a linux uImage in the TFTP disk area. + tftp 1000000 uImage + tftp 2000000 rootfs.ext2.gz.uboot + tftp 3000000 p2040rdb.dtb + bootm 1000000 2000000 3000000 diff --git a/include/configs/P2040RDB.h b/include/configs/P2040RDB.h new file mode 100644 index 0000000..a1cbdbb --- /dev/null +++ b/include/configs/P2040RDB.h @@ -0,0 +1,617 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P2040 RDB board configuration file + * + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_P2040RDB +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P2040 + +#ifdef CONFIG_RAMBOOT_PBL +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_E500MC /* BOOKE e500mc family */ +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ +#define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ +#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ +#define CONFIG_MP /* support multiple processors */ + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + +#define CONFIG_FSL_LAW /* Use common FSL init code */ + +#define CONFIG_ENV_OVERWRITE + +#ifdef CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#else +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#endif + +#if defined(CONFIG_SPIFLASH) + #define CONFIG_SYS_EXTRA_ENV_RELOC + #define CONFIG_ENV_IS_IN_SPI_FLASH + #define CONFIG_ENV_SPI_BUS 0 + #define CONFIG_ENV_SPI_CS 0 + #define CONFIG_ENV_SPI_MAX_HZ 10000000 + #define CONFIG_ENV_SPI_MODE 0 + #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ + #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ + #define CONFIG_ENV_SECT_SIZE 0x10000 +#elif defined(CONFIG_SDCARD) + #define CONFIG_SYS_EXTRA_ENV_RELOC + #define CONFIG_ENV_IS_IN_MMC + #define CONFIG_SYS_MMC_ENV_DEV 0 + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_OFFSET (512 * 1097) +#else + #define CONFIG_ENV_IS_IN_FLASH + #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) + #define CONFIG_ENV_SIZE 0x2000 + #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif + +#define CONFIG_SYS_CLK_FREQ 66666666 + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_SYS_CACHE_STASHING +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_ADDR_MAP +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ +#endif + +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_PANIC_HANG /* do not reset board on panic */ + +/* + * Config the L3 Cache as L3 SRAM + */ +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) +#else +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR +#endif +#define CONFIG_SYS_L3_SIZE (1024 << 10) +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) + +/* + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + */ +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ +#else +#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#endif +#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ + +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_DCSRBAR 0xf0000000 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull +#endif + +/* EEPROM */ +#define CONFIG_ID_EEPROM +#define CONFIG_SYS_I2C_EEPROM_NXID +#define CONFIG_SYS_EEPROM_BUS_NUM 0 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 + +/* + * DDR Setup + */ +#define CONFIG_VERY_BIG_RAM +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) + +#define CONFIG_DDR_SPD +#define CONFIG_FSL_DDR3 + +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x52 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ + +/* + * Local Bus Definitions + */ + +/* Set the local bus clock 1/8 of platform clock */ +#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 + +#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* Start of PromJet */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull +#else +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE +#endif + +#define CONFIG_SYS_BR0_PRELIM \ + (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) +#define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ + | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) + +#define CONFIG_FSL_CPLD +#define CPLD_BASE 0xffdf0000 /* CPLD registers */ +#ifdef CONFIG_PHYS_64BIT +#define CPLD_BASE_PHYS 0xfffdf0000ull +#else +#define CPLD_BASE_PHYS CPLD_BASE +#endif + +#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V) +#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ + +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x40 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ + +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ + +#if defined(CONFIG_RAMBOOT_PBL) +#define CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_HWCONFIG + +/* define to use L1 as initial stack */ +#define CONFIG_L1_INIT_RAM +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ + +/* Serial Port - controlled on board with jumper J8 + * open - index 2 + * shorted - index 1 + */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +/* I2C */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x118000 +#define CONFIG_SYS_I2C2_OFFSET 0x118100 + +/* + * RapidIO + */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ + +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ + +/* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE 0 + +/* + * General PCI + * Memory space is mapped 1-1, but I/O space must start from 0. + */ + +/* controller 1, direct to uli, tgtid 3, Base address 20000 */ +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull +#else +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 +#endif +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ + +/* controller 2, Slot 2, tgtid 2, Base address 201000 */ +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull +#else +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 +#endif +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +/* controller 3, Slot 1, tgtid 1, Base address 202000 */ +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull +#else +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 +#endif +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ + +/* Qman/Bman */ +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ +#define CONFIG_SYS_BMAN_NUM_PORTALS 10 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull +#else +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE +#endif +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull +#else +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE +#endif +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 + +#define CONFIG_SYS_DPAA_FMAN +#define CONFIG_SYS_DPAA_PME +/* Default address of microcode for the Linux Fman driver */ +#define CONFIG_SYS_FMAN_FW +#if defined(CONFIG_SPIFLASH) +/* + * env is stored at 0x100000, sector size is 0x10000, ucode is stored after + * env, so we got 0x110000. + */ +#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#elif defined(CONFIG_SDCARD) +/* + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is + * about 545KB (1089 blocks), Env is stored after the image, and the env size is + * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. + */ +#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#elif defined(CONFIG_NAND) +#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#else +#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#endif +#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) + +#ifdef CONFIG_SYS_DPAA_FMAN +#define CONFIG_FMAN_ENET +#endif + +#ifdef CONFIG_PCI +#define CONFIG_NET_MULTI +#define CONFIG_PCI_PNP /* do pci plug-and-play */ +#define CONFIG_E1000 + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif /* CONFIG_PCI */ + +#ifdef CONFIG_FMAN_ENET +#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 +#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3 +#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4 +#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1 +#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0 + +#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c +#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d +#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e +#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f + +#define CONFIG_SYS_TBIPA_VALUE 8 +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_ETHPRIME "FM1@DTSEC1" +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ +#endif + +/* + * Environment + */ +#define CONFIG_LOADS_ECHO /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_ELF +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_GREPENV +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR + +#ifdef CONFIG_PCI +#define CONFIG_CMD_PCI +#define CONFIG_CMD_NET +#endif + +/* +* USB +*/ +#define CONFIG_CMD_USB +#define CONFIG_USB_STORAGE +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_FSL +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_CMD_EXT2 + +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Environment Configuration + */ +#define CONFIG_ROOTPATH /opt/nfsroot +#define CONFIG_BOOTFILE uImage +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define __USB_PHY_TYPE utmi + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ + "bank_intlv=cs0_cs1\0" \ + "netdev=eth0\0" \ + "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ + "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot && " \ + "protect off $ubootaddr +$filesize && " \ + "erase $ubootaddr +$filesize && " \ + "cp.b $loadaddr $ubootaddr $filesize && " \ + "protect on $ubootaddr +$filesize && " \ + "cmp.b $loadaddr $ubootaddr $filesize\0" \ + "consoledev=ttyS0\0" \ + "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \ + "usb_dr_mode=host\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=p2040rdb/ramdisk.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=p2040rdb/p2040rdb.dtb\0" \ + "bdev=sda3\0" \ + "c=ffe\0" + +#define CONFIG_HDBOOT \ + "setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT + +#ifdef CONFIG_SECURE_BOOT +#include <asm/fsl_secure_boot.h> +#endif + +#endif /* __CONFIG_H */ -- 1.7.5.1

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