June 2011 - U-Boot

[U-Boot] [PATCH 1/2] [V2] AT91: Makes AT91SAM9RL SoC build correctly against u-boot-atmel/master
by Hong Xu 14 Jun '11

14 Jun '11

Rework for AT91SAM9RL SoC, makes it build again. Based on the work for AT91SAM9260-EK. Signed-off-by: Hong Xu <hong.xu(a)atmel.com> --- arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c | 26 ++-- arch/arm/include/asm/arch-at91/at91_spi.h | 2 +- arch/arm/include/asm/arch-at91/at91sam9rl.h | 176 ++++++++++---------- arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h | 121 +++++--------- 4 files changed, 141 insertions(+), 184 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c index 4f570f4..c8d19f8 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -23,45 +23,45 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 6, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* RXD0 */ - writel(1 << AT91SAM9RL_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_US0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 11, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* RXD1 */ - writel(1 << AT91SAM9RL_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_US1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 13, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* RXD2 */ - writel(1 << AT91SAM9RL_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_US2, &pmc->pcer); } -void at91_serial3_hw_init(void) +void at91_seriald_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 22, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } void at91_serial_hw_init(void) @@ -79,21 +79,21 @@ void at91_serial_hw_init(void) #endif #ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); + at91_seriald_hw_init(); #endif } #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 25, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9RL_ID_SPI, &pmc->pcer); + writel(1 << ATMEL_ID_SPI, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 28, 1); diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h index c520e89..afe724d 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/include/asm/arch-at91/at91_spi.h @@ -33,7 +33,7 @@ typedef struct at91_spi { at91_pdc_t pdc; } at91_spi_t; -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl.h b/arch/arm/include/asm/arch-at91/at91sam9rl.h index 8eb0d4f..7e3a029 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl.h +++ b/arch/arm/include/asm/arch-at91/at91sam9rl.h @@ -14,117 +14,109 @@ #ifndef AT91SAM9RL_H #define AT91SAM9RL_H +#define CONFIG_ARM926EJS /* ARM926EJS Core */ +#define CONFIG_AT91FAMILY /* it's a member of AT91 */ /* * Peripheral identifiers/interrupts. */ -#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91_ID_SYS 1 /* System Controller */ -#define AT91SAM9RL_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91SAM9RL_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91SAM9RL_ID_PIOC 4 /* Parallel IO Controller C */ -#define AT91SAM9RL_ID_PIOD 5 /* Parallel IO Controller D */ -#define AT91SAM9RL_ID_US0 6 /* USART 0 */ -#define AT91SAM9RL_ID_US1 7 /* USART 1 */ -#define AT91SAM9RL_ID_US2 8 /* USART 2 */ -#define AT91SAM9RL_ID_US3 9 /* USART 3 */ -#define AT91SAM9RL_ID_MCI 10 /* Multimedia Card Interface */ -#define AT91SAM9RL_ID_TWI0 11 /* TWI 0 */ -#define AT91SAM9RL_ID_TWI1 12 /* TWI 1 */ -#define AT91SAM9RL_ID_SPI 13 /* Serial Peripheral Interface */ -#define AT91SAM9RL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ -#define AT91SAM9RL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ -#define AT91SAM9RL_ID_TC0 16 /* Timer Counter 0 */ -#define AT91SAM9RL_ID_TC1 17 /* Timer Counter 1 */ -#define AT91SAM9RL_ID_TC2 18 /* Timer Counter 2 */ -#define AT91SAM9RL_ID_PWMC 19 /* Pulse Width Modulation Controller */ -#define AT91SAM9RL_ID_TSC 20 /* Touch Screen Controller */ -#define AT91SAM9RL_ID_DMA 21 /* DMA Controller */ -#define AT91SAM9RL_ID_UDPHS 22 /* USB Device HS */ -#define AT91SAM9RL_ID_LCDC 23 /* LCD Controller */ -#define AT91SAM9RL_ID_AC97C 24 /* AC97 Controller */ -#define AT91SAM9RL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ - -#define AT91_SDRAMC_BASE 0xffffea00 -#define AT91_SMC_BASE 0xffffec00 -#define AT91_MATRIX_BASE 0xffffee00 -#define AT91_PIO_BASE 0xfffff400 -#define AT91_PMC_BASE 0xfffffc00 -#define AT91_RSTC_BASE 0xfffffd00 -#define AT91_PIT_BASE 0xfffffd30 -#define AT91_WDT_BASE 0xfffffd40 - -#ifdef CONFIG_AT91_LEGACY +#define ATMEL_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define ATMEL_ID_SYS 1 /* System Controller */ +#define ATMEL_ID_PIOA 2 /* Parallel IO Controller A */ +#define ATMEL_ID_PIOB 3 /* Parallel IO Controller B */ +#define ATMEL_ID_PIOC 4 /* Parallel IO Controller C */ +#define ATMEL_ID_PIOD 5 /* Parallel IO Controller D */ +#define ATMEL_ID_US0 6 /* USART 0 */ +#define ATMEL_ID_US1 7 /* USART 1 */ +#define ATMEL_ID_US2 8 /* USART 2 */ +#define ATMEL_ID_US3 9 /* USART 3 */ +#define ATMEL_ID_MCI 10 /* Multimedia Card Interface */ +#define ATMEL_ID_TWI0 11 /* TWI 0 */ +#define ATMEL_ID_TWI1 12 /* TWI 1 */ +#define ATMEL_ID_SPI 13 /* Serial Peripheral Interface */ +#define ATMEL_ID_SSC0 14 /* Serial Synchronous Controller 0 */ +#define ATMEL_ID_SSC1 15 /* Serial Synchronous Controller 1 */ +#define ATMEL_ID_TC0 16 /* Timer Counter 0 */ +#define ATMEL_ID_TC1 17 /* Timer Counter 1 */ +#define ATMEL_ID_TC2 18 /* Timer Counter 2 */ +#define ATMEL_ID_PWMC 19 /* Pulse Width Modulation Controller */ +#define ATMEL_ID_TSC 20 /* Touch Screen Controller */ +#define ATMEL_ID_DMA 21 /* DMA Controller */ +#define ATMEL_ID_UDPHS 22 /* USB Device HS */ +#define ATMEL_ID_LCDC 23 /* LCD Controller */ +#define ATMEL_ID_AC97C 24 /* AC97 Controller */ +#define ATMEL_ID_IRQ0 31 /* Advanced Interrupt Controller (IRQ0) */ /* * User Peripheral physical base addresses. */ -#define AT91SAM9RL_BASE_TCB0 0xfffa0000 -#define AT91SAM9RL_BASE_TC0 0xfffa0000 -#define AT91SAM9RL_BASE_TC1 0xfffa0040 -#define AT91SAM9RL_BASE_TC2 0xfffa0080 -#define AT91SAM9RL_BASE_MCI 0xfffa4000 -#define AT91SAM9RL_BASE_TWI0 0xfffa8000 -#define AT91SAM9RL_BASE_TWI1 0xfffac000 -#define AT91SAM9RL_BASE_US0 0xfffb0000 -#define AT91SAM9RL_BASE_US1 0xfffb4000 -#define AT91SAM9RL_BASE_US2 0xfffb8000 -#define AT91SAM9RL_BASE_US3 0xfffbc000 -#define AT91SAM9RL_BASE_SSC0 0xfffc0000 -#define AT91SAM9RL_BASE_SSC1 0xfffc4000 -#define AT91SAM9RL_BASE_PWMC 0xfffc8000 -#define AT91SAM9RL_BASE_SPI 0xfffcc000 -#define AT91SAM9RL_BASE_TSC 0xfffd0000 -#define AT91SAM9RL_BASE_UDPHS 0xfffd4000 -#define AT91SAM9RL_BASE_AC97C 0xfffd8000 -#define AT91_BASE_SYS 0xffffc000 +#define ATMEL_BASE_TCB0 0xfffa0000 +#define ATMEL_BASE_TC0 0xfffa0000 +#define ATMEL_BASE_TC1 0xfffa0040 +#define ATMEL_BASE_TC2 0xfffa0080 +#define ATMEL_BASE_MCI 0xfffa4000 +#define ATMEL_BASE_TWI0 0xfffa8000 +#define ATMEL_BASE_TWI1 0xfffac000 +#define ATMEL_BASE_US0 0xfffb0000 +#define ATMEL_BASE_US1 0xfffb4000 +#define ATMEL_BASE_US2 0xfffb8000 +#define ATMEL_BASE_US3 0xfffbc000 +#define ATMEL_BASE_SSC0 0xfffc0000 +#define ATMEL_BASE_SSC1 0xfffc4000 +#define ATMEL_BASE_PWMC 0xfffc8000 +#define ATMEL_BASE_SPI 0xfffcc000 +#define ATMEL_BASE_SPI0 0xfffcc000 +#define ATMEL_BASE_TSC 0xfffd0000 +#define ATMEL_BASE_UDPHS 0xfffd4000 +#define ATMEL_BASE_AC97C 0xfffd8000 +#define ATMEL_BASE_SYS 0xffffc000 /* - * System Peripherals (offset from AT91_BASE_SYS) + * System Peripherals */ -#define AT91_DMA (0xffffe600 - AT91_BASE_SYS) -#define AT91_ECC (0xffffe800 - AT91_BASE_SYS) -#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS) -#define AT91_SMC (0xffffec00 - AT91_BASE_SYS) -#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS) -#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS) -#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) -#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) -#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) -#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) -#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) -#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) -#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) -#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS) -#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS) -#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS) -#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS) -#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS) -#define AT91_SCKCR (0xfffffd50 - AT91_BASE_SYS) -#define AT91_GPBR (0xfffffd60 - AT91_BASE_SYS) -#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) - -#define AT91_USART0 AT91SAM9RL_BASE_US0 -#define AT91_USART1 AT91SAM9RL_BASE_US1 -#define AT91_USART2 AT91SAM9RL_BASE_US2 -#define AT91_USART3 AT91SAM9RL_BASE_US3 - -#endif /* CONFIG_AT91_LEGACY */ +#define ATMEL_BASE_DMA 0xffffe600 +#define ATMEL_BASE_ECC 0xffffe800 +#define ATMEL_BASE_SDRAMC 0xffffea00 +#define ATMEL_BASE_SMC 0xffffec00 +#define ATMEL_BASE_MATRIX 0xffffee00 +#define ATMEL_BASE_CCFG 0xffffef10 +#define ATMEL_BASE_AIC 0xfffff000 +#define ATMEL_BASE_DBGU 0xfffff200 +#define ATMEL_BASE_PIOA 0xfffff400 +#define ATMEL_BASE_PIOB 0xfffff600 +#define ATMEL_BASE_PIOC 0xfffff800 +#define ATMEL_BASE_PIOD 0xfffffa00 +#define ATMEL_BASE_PMC 0xfffffc00 +#define ATMEL_BASE_RSTC 0xfffffd00 +#define ATMEL_BASE_SHDWC 0xfffffd10 +#define ATMEL_BASE_RTT 0xfffffd20 +#define ATMEL_BASE_PIT 0xfffffd30 +#define ATMEL_BASE_WDT 0xfffffd40 +#define ATMEL_BASE_SCKCR 0xfffffd50 +#define ATMEL_BASE_GPBR 0xfffffd60 +#define ATMEL_BASE_RTC 0xfffffe00 /* * Internal Memory. */ -#define AT91SAM9RL_SRAM_BASE 0x00300000 /* Internal SRAM base address */ -#define AT91SAM9RL_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */ +#define ATMEL_BASE_SRAM 0x00300000 /* Internal SRAM base address */ +#define ATMEL_SRAM_SIZE SZ_64K /* Internal SRAM size (64Kb) */ -#define AT91SAM9RL_ROM_BASE 0x00400000 /* Internal ROM base address */ -#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ +#define ATMEL_BASE_ROM 0x00400000 /* Internal ROM base address */ +#define ATMEL_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */ -#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ -#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ +#define ATMEL_BASE_LCDC 0x00500000 /* LCD Controller */ +#define ATMEL_UHP_BASE 0x00600000 /* USB Device HS controller */ + +/* + * External memory + */ +#define ATMEL_BASE_CS1 0x20000000 /* SDRAM */ +#define ATMEL_BASE_CS3 0x40000000 /* typically NAND */ +#define ATMEL_PIO_PORTS 4 /* * Cpu Name */ -#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9RL" +#define ATMEL_CPU_NAME "AT91SAM9RL" #endif diff --git a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h index af8d914..295f768 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9rl_matrix.h @@ -14,83 +14,48 @@ #ifndef AT91SAM9RL_MATRIX_H #define AT91SAM9RL_MATRIX_H -#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */ -#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */ -#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */ -#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */ -#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */ -#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */ -#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */ -#define AT91_MATRIX_ULBT_INFINITE (0 << 0) -#define AT91_MATRIX_ULBT_SINGLE (1 << 0) -#define AT91_MATRIX_ULBT_FOUR (2 << 0) -#define AT91_MATRIX_ULBT_EIGHT (3 << 0) -#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) - -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */ -#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ -#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) -#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) - -#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */ -#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */ -#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */ -#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */ -#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */ -#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */ -#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */ -#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */ -#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */ -#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */ -#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */ -#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */ - -#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91_MATRIX_RCB2 (1 << 2) -#define AT91_MATRIX_RCB3 (1 << 3) -#define AT91_MATRIX_RCB4 (1 << 4) -#define AT91_MATRIX_RCB5 (1 << 5) - -#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) - -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ -#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */ -#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) -#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) - +#ifndef __ASSEMBLY__ + +struct at91_matrix { + u32 mcfg[16]; /* Master Configuration Registers */ + u32 scfg[16]; /* Slave Configuration Registers */ + u32 pras[16][2]; /* Priority Assignment Slave Registers */ + u32 mrcr; /* Master Remap Control Register */ + u32 filler[7]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; + +#endif /* __ASSEMBLY__ */ + +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) + +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) + +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 + +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) + +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif -- 1.7.3.3

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by China Daily (European Edition Weekly) 14 Jun '11

14 Jun '11

Hi there We know how busy you are, so just a quick note, if we may, to let you know about China Daily European Edition, advertising in which is now available for the first time ever! From China Daily, now 30 years old, as you might see it's a brand new and exciting opportunity, especially if your organisation is intending to reach European CEOs/CFOs/Senior Executives interested in China, and full page advertisements are now invited (flyer link below). It's weekly, it's in English, it's a business tabloid-size newspaper, it's distributed to its 41,000 C-level subscription base each week, and also offers some private distribution to corporate receptions, business hotels and airlines (approx 10,000 per week also). In addition, the online edition (included) at the European section of the website benefits from 2.5 million unique visitors per week. You might also like to know that the European edition is now already a year old, and we have spent the entire year building the subscription base and distribution, now available for your advertising. AND, if you would like to reach the Chinese market itself in English (with Chinese subscript), China Daily (daily broadsheet) will do this effectively for you, as, indeed, will the China Daily website, now benefiting from 3.6 million unique visitors per day, media pack links here: China Daily China Edition (daily, broadsheet) - http://sksassociates.co.uk/cd/2011ChinaDailyChinaADRATE.pdf (large file) China Daily website - http://sksassociates.co.uk/cd/2011ChinaDailyWebsiteMediaKit.pdf You may decide that, for a new opportunity such as China Daily European Weekly, you might like to try a 'test' advertisement. We appreciate this sentiment, and therefore, until 1st July 2011 we would like to offer you a full page (tabloid size) in CDEW, including the online edition, at a special introduction rate of £1999.00 (usual list £2500)! To book for this attractive introductory test appearance in CDEW for your organisation, please simply reply to this email with the phrase 'Yes please!', and we will forward specs and confirmation by return. We hope to hear from you soon! Best wishes, Chris Brown @ SKS London for China Daily Europe T: +44 (0) 845 428 9350 / or via accts team +44 (0) 207 607 0717 ddi W: http://europe.chinadaily.com.cn Links section: China Daily European Weekly Flyer - http://www.sksassociates.co.uk/cd/ChinaDailyEuropeanWeeklyMediaFlyerJune201… China Daily China Edition (daily, broadsheet) - http://sksassociates.co.uk/cd/2011ChinaDailyChinaADRATE.pdf China Daily website - http://sksassociates.co.uk/cd/2011ChinaDailyWebsiteMediaKit.pdf ________________________________________________________________________________________________________________________ Additional Notes FYI: China Daily is China's national English-language newspaper, which was founded in 1981. China Daily European Edition Edition (Weekly), is the European offering. For readers at home and abroad, China Daily is a popular choice among English-language media in China. It is the only Chinese newspaper that has effectively entered Western mainstream society and is the newspaper most quoted by the foreign press. The paper also has published the largest number of supplements for international meetings in China among all media outlets. Global readers recognize China Daily as the most authoritative and influential English-language media in the country. It serves as an important window for "China to understand the world and be understood by the world". China Daily Media Group rides the tide of the times and drives innovations. It believes that "content is king". While reporting on China and commenting on the world, it is also accelerating efforts to become "localized" overseas, to improve reporting, editing and distribution networks worldwide, and to march toward being a world-class multiple-platform media group. Contracted exclusively by: SKS/Enhanced Media & Communications Ltd 1 Farnham Road, Guildford, Surrey GU2 4RG UK "Bringing the top drawer to you!" ** It's our intention to only contact you with interesting opportunities you might otherwise overlook from the cream of the "top drawer"! ** If you feel you have received this email in error, simply REPLY and SEND with the subject line intact. Thanks.

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[U-Boot] DSN: failed (Error)
by Mailbot for etexusa.com 14 Jun '11

14 Jun '11

This is a Delivery Status Notification (DSN). I was unable to deliver your message to userid(a)sancharnet.in. I said RCPT TO:<userid(a)sancharnet.in> And they gave me the error; 550 Recipient Suspended

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[U-Boot] Latest u-boot-atmel git hangs on AVR32 board
by Mark Jackson 14 Jun '11

14 Jun '11

Hi Our MIMC200 board has been using 2009.08 for some time, so I thought I would take a look at the latest git version to keep our boards more up-to-date. I have checked out the u-boot-atmel branch, and done:- $ make mimc200_config $ make Everything compiles, but when I try the image, I only get:- U-Boot 2011.06-rc2-02816-g5f2e176 (Jun 13 2011 - 12:50:29) U-Boot code: 00000000 -> 00012668 data: 0001ae38 -> 00050840 LCD: Frame buffer allocated at preset 0x10600000 VMR table @ 0x11fca7f4 I have traced through the code to see where things stop, and it seems to be in:- arch/avr32/cpu/at32ap700x/mmu.c void mmu_init_r(unsigned long dest_addr) { ... printf("VMR table @ 0x%08x\n", vmr_table_addr); /* Enable paging */ puts("a"); sysreg_write(MMUCR, SYSREG_BF(DRP, 1) | SYSREG_BF(DLA, 1) | SYSREG_BIT(MMUCR_S) | SYSREG_BIT(M) | SYSREG_BIT(E)); puts("b"); } I get the "VMR table ..." string, as well as "a", but I never get "b". Can anyone help ? Regards Mark

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[U-Boot] [PATCH] vision2: Fix build due to WEIM registers name change
by Fabio Estevam 14 Jun '11

14 Jun '11

commit 0015de1a (MX5: Make the weim structure complete) fixed the name for the WEIM registers in order to match with the MX51/MX53 manuals. Fix the WEIM register for vision2 board so that it can build again. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- board/ttcontrol/vision2/vision2.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index 8e6ad74..565c4d0 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -169,11 +169,11 @@ static void setup_weim(void) { struct weim *pweim = (struct weim *)WEIM_BASE_ADDR; - pweim->csgcr1 = 0x004100b9; - pweim->csgcr2 = 0x00000001; - pweim->csrcr1 = 0x0a018000; - pweim->csrcr2 = 0; - pweim->cswcr1 = 0x0704a240; + pweim->cs0gcr1 = 0x004100b9; + pweim->cs0gcr2 = 0x00000001; + pweim->cs0rcr1 = 0x0a018000; + pweim->cs0rcr2 = 0; + pweim->cs0wcr1 = 0x0704a240; } static void setup_uart(void) -- 1.7.1

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[U-Boot] [PATCH] mx1ads: Fix build by using new relocation scheme
by Fabio Estevam 14 Jun '11

14 Jun '11

Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Build tested only. Don't have access to this hardware. board/mx1ads/config.mk | 25 ------------------------- board/mx1ads/mx1ads.c | 27 +++++++++++++++++++-------- include/configs/mx1ads.h | 10 ++++++++++ 3 files changed, 29 insertions(+), 33 deletions(-) delete mode 100644 board/mx1ads/config.mk diff --git a/board/mx1ads/config.mk b/board/mx1ads/config.mk deleted file mode 100644 index 2bc5b15..0000000 --- a/board/mx1ads/config.mk +++ /dev/null @@ -1,25 +0,0 @@ -# -# board/mx1ads/config.mk -# -# (c) Copyright 2004 -# Techware Information Technology, Inc. -# http://www.techware.com.tw/ -# -# Ming-Len Wu <minglen_wu(a)techware.com.tw> -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA - -CONFIG_SYS_TEXT_BASE = 0x08400000 diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c index f8ce210..0685518 100644 --- a/board/mx1ads/mx1ads.c +++ b/board/mx1ads/mx1ads.c @@ -78,7 +78,7 @@ void SetAsynchMode (void) static u32 mc9328sid; -int board_init (void) +int board_early_init_f(void) { volatile unsigned int tmp; @@ -112,10 +112,6 @@ int board_init (void) SetAsynchMode (); - gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; - - gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ - icache_enable (); dcache_enable (); @@ -133,6 +129,15 @@ int board_init (void) return 0; } +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_MX1ADS; + + gd->bd->bi_boot_params = 0x08000100; /* adress of boot parameters */ + + return 0; +} + int board_late_init (void) { @@ -161,12 +166,18 @@ int board_late_init (void) return 0; } -int dram_init (void) +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return 0; } #ifdef CONFIG_CMD_NET diff --git a/include/configs/mx1ads.h b/include/configs/mx1ads.h index 166da6c..7b68ec5 100644 --- a/include/configs/mx1ads.h +++ b/include/configs/mx1ads.h @@ -156,6 +156,16 @@ #define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define CONFIG_SYS_TEXT_BASE 0x10000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x00300000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x000FFFFF +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ #define CONFIG_SYS_FLASH_BASE 0x0C000000 /* SyncFlash on CSD1 */ #define FLASH_BANK_SIZE 0x01000000 /* 16 MB Total */ -- 1.7.1

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[U-Boot] [PATCH] imx31_phycore: Fix build by using new relocation scheme
by Fabio Estevam 14 Jun '11

14 Jun '11

Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Build tested only. Don't have access to this hardware. board/imx31_phycore/config.mk | 1 - board/imx31_phycore/imx31_phycore.c | 22 ++++++++++++++-------- include/configs/imx31_phycore.h | 12 ++++++++++++ 3 files changed, 26 insertions(+), 9 deletions(-) delete mode 100644 board/imx31_phycore/config.mk diff --git a/board/imx31_phycore/config.mk b/board/imx31_phycore/config.mk deleted file mode 100644 index 0131edf..0000000 --- a/board/imx31_phycore/config.mk +++ /dev/null @@ -1 +0,0 @@ -CONFIG_SYS_TEXT_BASE = 0x87f00000 diff --git a/board/imx31_phycore/imx31_phycore.c b/board/imx31_phycore/imx31_phycore.c index 82daaa3..87b04d9 100644 --- a/board/imx31_phycore/imx31_phycore.c +++ b/board/imx31_phycore/imx31_phycore.c @@ -30,15 +30,24 @@ DECLARE_GLOBAL_DATA_PTR; -int dram_init (void) +int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} + +int board_init(void) +{ + + gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ + gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ return 0; } -int board_init (void) +int board_early_init_f(void) { __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */ __REG(CSCR_L(0)) = 0x10000d03; @@ -61,10 +70,7 @@ int board_init (void) /* setup pins for I2C2 (for EEPROM, RTC) */ mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL); mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA); - - gd->bd->bi_arch_number = MACH_TYPE_PCM037; /* board id for linux */ - gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ - + return 0; } diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 4d11f97..a0c0f1b 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -28,6 +28,8 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/imx-regs.h> + /* High Level Configuration Options */ #define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ #define CONFIG_MX31 1 /* in a mx31 */ @@ -143,6 +145,16 @@ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_GBL_DATA_OFFSET) /*----------------------------------------------------------------------- * FLASH and environment organization -- 1.7.1

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Re: [U-Boot] [PATCH v2 4/5] arm/km: replace suenx targets with km_kirkwood
by Prafulla Wadaskar 14 Jun '11

14 Jun '11

> -----Original Message----- > From: Prafulla Wadaskar > Sent: Saturday, June 11, 2011 9:53 AM > To: 'Holger Brunck'; u-boot(a)lists.denx.de > Cc: Valentin Longchamp; Heiko Schocher > Subject: RE: [PATCH v2 4/5] arm/km: replace suenx targets with > km_kirkwood > > > > > -----Original Message----- > > From: Holger Brunck [mailto:holger.brunck@keymile.com] > > Sent: Wednesday, June 08, 2011 5:13 PM > > To: u-boot(a)lists.denx.de > > Cc: Holger Brunck; Valentin Longchamp; Prafulla Wadaskar; Heiko > Schocher > > Subject: [PATCH v2 4/5] arm/km: replace suenx targets with km_kirkwood > > > > suen3 and suen8 were in first HW version quite different, but > > now they are from a u-boot point of view similar. So these > > two boards can use the same header file. Other keymile boards > > differ only in the usage of the PCI interface. Therefore > > a target km_kirkwood_pci was introduced. All targets use > > the same header file. > > > > Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> > > Signed-off-by: Valentin Longchamp <valentin.longchamp(a)keymile.com> > > cc: Prafulla Wadaskar <prafulla(a)marvell.com> > > cc: Heiko Schocher <hs(a)denx.de> > > --- > > Changes for v2: > > - squashed together with 5/6 from previous serie, because > > the pci defines belongs logically to this patch > > - change typo in board maintainers name > > > > MAINTAINERS | 6 ++- > > MAKEALL | 2 +- > > boards.cfg | 4 +- > > include/configs/km/km_arm.h | 1 - > > include/configs/{suen3.h => km_kirkwood.h} | 18 +++++++--- > > include/configs/mgcoge3un.h | 5 +++ > > include/configs/suen8.h | 50 ------------------- > -- > > ------- > > Applied to u-boot-marvell.git next branch > Regards.. > Prafulla . . Hi Holger, Valentin During this pull check I observed that u-boot.kwb image generation gives build errors for all Kirkwood based keymile boards. Please kindly check on this and provide a fix. Regards.. Prafulla . .

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[U-Boot] Re-validate your mailbox
by Priya Prabhakaran, M.D. 14 Jun '11

14 Jun '11

Your mailbox storage limit has been exceeded until you re-validate your mailbox you cannot send or recieve e-mail.To re-validate your mailbox please CLICK HERE <http://fecch.weebly.com/>

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[U-Boot] CONGRATULATIONS,YOU HAVE WON ONE Million Dollars ATM Card, send mail to markrollins1965@live.com‏ ‏
by Free Internet Lottery 13 Jun '11

13 Jun '11

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