June 2011 - U-Boot

[U-Boot] Information regarding load address, execute address and image load address
by Hebbar, Gururaja 15 Jun '11

15 Jun '11

Hi, I need one clarification regarding load address, entry point inside the Kernel image & the address to where we load the image. Assume, the image header is as below. Image Name: Linux-2.6.38-10700-g846a497 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 2064396 Bytes = 2 MiB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK And I load the image using loadb to address 0x80008000. Will this work?. Because here Image->load_address == Load_address for u-boot. Now u-boot considers this as XIP Image and will not move os data which actually will be at 0x80008040 to 0x80008000 Please correct me if I am wrong I have attached the console output for reference. Thanks & regards Gururaja CON_SOLE#iminfo ## Checking Image at 80008000 ... Legacy image found Image Name: Linux-2.6.38-10700-g846a497 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 2064396 Bytes = 2 MiB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK CON_SOLE #bootm 0x80008000 * kernel: cmdline image address = 0x80008000 Boot reached stage 1 ## Booting kernel from Legacy Image at 80008000 ... Boot reached stage 2 Boot reached stage 3 Image Name: Linux-2.6.38-10700-g846a497 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 2064396 Bytes = 2 MiB Load Address: 80008000 Entry Point: 80008000 Verifying Checksum ... OK Boot reached stage 4 Boot reached stage 5 Boot reached stage 6 kernel data at 0x80008040, len = 0x001f800c (2064396) Boot reached stage 14 ## No init Ramdisk ramdisk start = 0x00000000, ramdisk end = 0x00000000 XIP Kernel Image ... OK OK kernel loaded at 0x80008000, end = 0x8020000c Boot reached stage 7 images.os.start = 0x80008000, images.os.end = 0x8020004c images.os.load = 0x80008000, load_end = 0x8020000c Boot reached stage 8 Boot reached stage 15 ## Transferring control to Linux (at address 80008000) ... Starting kernel ...

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Re: [U-Boot] [STATUS] Release delayed by two weeks
by Wolfgang Denk 15 Jun '11

15 Jun '11

Dear Albert, In message <4DF853C3.9080605(a)discworld.dascon.de> Michael Schwingen wrote: > > what about the IXP patches? > > Marek sent a pull request on 2011-05-27, but I can't find them in a > freshly pulled master. Could you please comment? Thanks! Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Imitation is the sincerest form of plagarism.

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[U-Boot] OMAP3/devkit8000 division/multiplication function problems
by Simon Schwarz 15 Jun '11

15 Jun '11

Hi List, as some may know I'am working on an SPL for the devkit8000. Now I have a problem with the UART init where I hope someone on the list can help. My problem is in drivers/serial/serial.c with the function calc_divisor. With my defines this function is essentially just this: return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) / (MODE_X_DIV * gd->baudrate); (Where MODE_X_DIV=16) If i try to execute this line (with the step instruction of gdb/openOCD) the debugger just does not return and I have to use Strg+c to get a prompt. Then the PC is 0x4020ffd4 (upper region of SRAM) and the CPSR is 0x600001d7 I think I have some problem with the division/multiplication functions as there is nothing else in this line which may cause trouble (returns and function calls worked before). U-boot is running in SRAM no SDRAM init yet. Has someone an idea where I can start looking? Maybe a known pitfall for beginners? More information needed? Thanks! Simon

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[U-Boot] OMAP3 clocks initialization not consistent with x-loader?
by Igor Grinberg 15 Jun '11

15 Jun '11

Hi, x-loader has the following comment and if statement for all boards supporting omap36xx SoC: ----------------------cut---------------------------------------- /* * On OMAP3630, DDR data corruption has been observed on OFF mode * exit if the sys clock was lower than 26M. As a work around, * OMAP3630 is operated at 26M sys clock and this internal division * is not performed. */ if((is_cpu_family() != CPU_OMAP36XX) && (sys_clkin_sel > 2)) { sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */ clk_index = sys_clkin_sel/2; } else { sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */ clk_index = sys_clkin_sel; } ----------------------cut---------------------------------------- U-Boot's omap3 clock initialization does not have that check for omap36xx. Shouldn't we have it also in U-Boot to workaround that DDR data corruption issue? -- Regards, Igor.

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[U-Boot] Warning Notice E-mail User
by Webmail Help Desk 15 Jun '11

15 Jun '11

Dear Webmail Account User To complete your Account Verification process, you are to reply this message and enter your ID and PASSWORD in the space provided (**********), you are required to do this before the next 48hrs of receipt of this e-mail, or your Webmail Account will be de-activated and erased from our database. Full Name: Webmail User ID: webmail Password: Date of Birth Warning!!! Account owners that refuses to update his or her account within Four days of receiving this warning will lose his or her account permanently. Thanks, Webmail Administrator ---------------------------------------------------------------- This message was sent using IMP, the Internet Messaging Program.

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by ** Gain Control Of Your Health With 7 Ancient Health Secrets ** 14 Jun '11

14 Jun '11

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[U-Boot] ARM/ATMEL/AT91: rework SoCs 9261/9263 and others
by Reinhard Meyer 14 Jun '11

14 Jun '11

Dear Friends, I have received several different patches reworking "at91sam*_devices.c" and "at91sam9*.h". Lokking at them, none of them is completely done the way the files for at91sam9260 are done. Examples: 9260, 9263: ATMEL_ID_USART0 9261: ATMEL_ID_US0 9260 uses the CONFIG_AT91_GPIO_PULLUP define, the others do not. 9261 still uses the CONFIG_USARTx defines. Please have a look at at91sam9260 as a reference. We do need a properly fixed SoC port for 9261, 9263 and the others before individual board ports can be fixed. Just because there is a sudden rush to get things fixed for the next release should NOT tempt us to get in interim versions. With Best Regards, Reinhard

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[U-Boot] [PATCH v2][ARM][AT91] Build fix/update of AFEB9260
by Sergey Lapin 14 Jun '11

14 Jun '11

Make AFEB9260 build again. Based on fix for AT91SAM9260EK. Signed-off-by: Sergey Lapin <slapin(a)ossfans.org> --- Cleaned-up a bit board/afeb9260/afeb9260.c | 103 ++++++++++++++++++++++++------------------- boards.cfg | 2 +- include/configs/afeb9260.h | 28 +++++++++--- 3 files changed, 79 insertions(+), 54 deletions(-) diff --git a/board/afeb9260/afeb9260.c b/board/afeb9260/afeb9260.c index 3c37557..0269140 100644 --- a/board/afeb9260/afeb9260.c +++ b/board/afeb9260/afeb9260.c @@ -31,7 +31,7 @@ #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> #include <asm/arch/hardware.h> #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB) #include <netdev.h> @@ -48,29 +48,29 @@ DECLARE_GLOBAL_DATA_PTR; static void afeb9260_nand_hw_init(void) { unsigned long csa; + struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; + struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; - /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBICSA); - at91_sys_write(AT91_MATRIX_EBICSA, - csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA); + /* Assign CS3 to NAND/SmartMedia Interface */ + csa = readl(&matrix->ebicsa); + csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; + writel(csa, &matrix->ebicsa); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | - AT91_SMC_DBW_8 | - AT91_SMC_TDF_(2)); - - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC); - + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); + /* Configure RDY/BSY */ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); @@ -81,10 +81,15 @@ static void afeb9260_nand_hw_init(void) #ifdef CONFIG_MACB static void afeb9260_macb_hw_init(void) { - unsigned long rstc; + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA; + struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC; + unsigned long erstl; + + + /* Enable EMAC clock */ + writel(1 << ATMEL_ID_EMAC0, &pmc->pcer); - /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC); /* * Disable pull-up on: @@ -103,24 +108,22 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUDR); + &pioa->pudr); - rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL; + erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK; /* Need to reset PHY -> 500ms reset */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | - AT91_RSTC_URSTEN); - - at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); + writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) | + AT91_RSTC_MR_URSTEN, &rstc->mr); + writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr); /* Wait for end hardware reset */ - while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); - + while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) + ; /* Restore NRST value */ - at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - (rstc) | - AT91_RSTC_URSTEN); + writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN, + &rstc->mr); + /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PA14) | @@ -129,23 +132,29 @@ static void afeb9260_macb_hw_init(void) pin_to_mask(AT91_PIN_PA25) | pin_to_mask(AT91_PIN_PA26) | pin_to_mask(AT91_PIN_PA28), - pin_to_controller(AT91_PIN_PA0) + PIO_PUER); + &pioa->puer); at91_macb_hw_init(); } #endif - +int board_early_init_f(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + /* Enable clocks for all PIOs */ + writel((1 << ATMEL_ID_PIOA) | + (1 << ATMEL_ID_PIOB) | + (1 << ATMEL_ID_PIOC), + &pmc->pcer); + return 0; +} int board_init(void) { - /* Enable Ctrlc */ - console_init_f(); - /* arch number of AT91SAM9260EK-Board */ gd->bd->bi_arch_number = MACH_TYPE_AFEB9260; /* adress of boot parameters */ - gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; - at91_serial_hw_init(); + at91_seriald_hw_init(); #ifdef CONFIG_CMD_NAND afeb9260_nand_hw_init(); #endif @@ -159,8 +168,10 @@ int board_init(void) int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + gd->ram_size = get_ram_size( + (void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; } @@ -174,7 +185,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x01); + rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x01); #endif return rc; } diff --git a/boards.cfg b/boards.cfg index ac20c81..a187a9f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -72,7 +72,7 @@ netstar arm arm925t voiceblue arm arm925t omap1510inn arm arm925t - ti aspenite arm arm926ejs - Marvell armada100 -afeb9260 arm arm926ejs - - at91 +afeb9260 arm arm926ejs - - at91 afeb9260:AT91SAM9260 at91cap9adk arm arm926ejs - atmel at91 at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0 diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index 36a2a46..9114a52 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -25,12 +25,19 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/arch/hardware.h> -#define CONFIG_AT91_LEGACY +#define CONFIG_SYS_TEXT_BASE 0x21f00000 /* ARM asynchronous clock */ #define CONFIG_SYS_AT91_MAIN_CLOCK 18429952 /* from 18.432 MHz crystal */ -#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + + #define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/ #define CONFIG_AFEB9260 1 /* on an AFEB9260 Board */ @@ -46,8 +53,14 @@ /* * Hardware drivers */ +#define CONFIG_ATMEL_LEGACY #define CONFIG_AT91_GPIO 1 +#define CONFIG_AT91_PULLUP 1 + + #define CONFIG_ATMEL_USART 1 +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS #undef CONFIG_USART0 #undef CONFIG_USART1 #undef CONFIG_USART2 @@ -82,8 +95,8 @@ /* SDRAM */ #define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM 0x20000000 -#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 +#define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */ /* DataFlash */ #define CONFIG_ATMEL_DATAFLASH_SPI @@ -100,7 +113,7 @@ #ifdef CONFIG_CMD_NAND #define CONFIG_NAND_ATMEL #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) @@ -134,12 +147,14 @@ #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* load address */ -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x21e00000 #undef CONFIG_SYS_USE_DATAFLASH_CS0 #define CONFIG_SYS_USE_DATAFLASH_CS1 1 #undef CONFIG_SYS_USE_NANDFLASH +#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 -\ + GENERATED_GBL_DATA_SIZE) /* bootstrap + u-boot + env + linux in dataflash on CS1 */ #define CONFIG_ENV_IS_IN_DATAFLASH 1 -- 1.7.2.3

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[U-Boot] [PATCH 1/1] usb: Some EHCI chipsets are slow to respond.
by u-boot＠lakedaemon.net 14 Jun '11

14 Jun '11

From: Jason Cooper <u-boot(a)lakedaemon.net> This fixes 'EHCI timed out on TD...' on the dreamplug board. Signed-off-by: Jason Cooper <u-boot(a)lakedaemon.net> --- include/usb.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/usb.h b/include/usb.h index 53603a5..168e2b2 100644 --- a/include/usb.h +++ b/include/usb.h @@ -46,7 +46,7 @@ * This is the timeout to allow for submitting an urb in ms. We allow more * time for a BULK device to react - some are slow. */ -#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 100) +#define USB_TIMEOUT_MS(pipe) (usb_pipebulk(pipe) ? 5000 : 500) /* device request (setup) */ struct devrequest { -- 1.7.0.4

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[U-Boot] [PATCH 1/2] [V2] AT91: Makes AT91SAM9261(9G10) SoC build correctly against u-boot-atmel/master
by Hong Xu 14 Jun '11

14 Jun '11

Rework for AT91SAM9261(9G10) SoC, makes it build again. Based on the work for AT91SAM9260-EK. Signed-off-by: Hong Xu <hong.xu(a)atmel.com> --- arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c | 45 +++++------- arch/arm/include/asm/arch-at91/at91_spi.h | 2 +- arch/arm/include/asm/arch-at91/at91sam9261.h | 1 + .../arm/include/asm/arch-at91/at91sam9261_matrix.h | 77 +++++++++----------- 4 files changed, 56 insertions(+), 69 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c index b4353ef..3db2b20 100644 --- a/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -26,74 +26,65 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/gpio.h> -#include <asm/arch/io.h> +#include <asm/io.h> void at91_serial0_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */ - writel(1 << AT91SAM9261_ID_US0, &pmc->pcer); + writel(1 << ATMEL_ID_USART0, &pmc->pcer); } void at91_serial1_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */ at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */ - writel(1 << AT91SAM9261_ID_US1, &pmc->pcer); + writel(1 << ATMEL_ID_USART1, &pmc->pcer); } void at91_serial2_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */ - writel(1 << AT91SAM9261_ID_US2, &pmc->pcer); + writel(1 << ATMEL_ID_USART2, &pmc->pcer); } void at91_serial3_hw_init(void) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */ at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */ - writel(1 << AT91_ID_SYS, &pmc->pcer); + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } -void at91_serial_hw_init(void) +void at91_seriald_hw_init(void) { -#ifdef CONFIG_USART0 - at91_serial0_hw_init(); -#endif + at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; -#ifdef CONFIG_USART1 - at91_serial1_hw_init(); -#endif + at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* DRXD */ + at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */ -#ifdef CONFIG_USART2 - at91_serial2_hw_init(); -#endif - -#ifdef CONFIG_USART3 /* DBGU */ - at91_serial3_hw_init(); -#endif + writel(1 << ATMEL_ID_SYS, &pmc->pcer); } #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* SPI0_MISO */ at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* SPI0_MOSI */ at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* SPI0_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9261_ID_SPI0, &pmc->pcer); + writel(1 << ATMEL_ID_SPI0, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTA, 3, 1); @@ -123,14 +114,14 @@ void at91_spi0_hw_init(unsigned long cs_mask) void at91_spi1_hw_init(unsigned long cs_mask) { - at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC; at91_set_a_periph(AT91_PIO_PORTB, 30, 0); /* SPI1_MISO */ at91_set_a_periph(AT91_PIO_PORTB, 31, 0); /* SPI1_MOSI */ at91_set_a_periph(AT91_PIO_PORTB, 29, 0); /* SPI1_SPCK */ /* Enable clock */ - writel(1 << AT91SAM9261_ID_SPI1, &pmc->pcer); + writel(1 << ATMEL_ID_SPI1, &pmc->pcer); if (cs_mask & (1 << 0)) { at91_set_a_periph(AT91_PIO_PORTB, 28, 1); diff --git a/arch/arm/include/asm/arch-at91/at91_spi.h b/arch/arm/include/asm/arch-at91/at91_spi.h index c520e89..afe724d 100644 --- a/arch/arm/include/asm/arch-at91/at91_spi.h +++ b/arch/arm/include/asm/arch-at91/at91_spi.h @@ -33,7 +33,7 @@ typedef struct at91_spi { at91_pdc_t pdc; } at91_spi_t; -#ifdef CONFIG_AT91_LEGACY +#ifdef CONFIG_ATMEL_LEGACY #define AT91_SPI_CR 0x00 /* Control Register */ #define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */ diff --git a/arch/arm/include/asm/arch-at91/at91sam9261.h b/arch/arm/include/asm/arch-at91/at91sam9261.h index c85fd29..afd7bd9 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261.h @@ -126,6 +126,7 @@ */ #define ATMEL_PIO_PORTS 3 /* theese SoCs have 3 PIO */ #define ATMEL_BASE_PIO ATMEL_BASE_PIOA +#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP /* * SoC specific defines diff --git a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h index e2bfc4b..913b4d7 100644 --- a/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h +++ b/arch/arm/include/asm/arch-at91/at91sam9261_matrix.h @@ -15,50 +15,45 @@ #ifndef AT91SAM9261_MATRIX_H #define AT91SAM9261_MATRIX_H -#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */ -#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */ -#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ +#ifndef __ASSEMBLY__ -#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */ -#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */ -#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */ -#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */ -#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */ -#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */ -#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */ -#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) -#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) -#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ +struct at91_matrix { + u32 mcfg; /* Master Configuration Registers */ + u32 scfg[5]; /* Slave Configuration Registers */ + u32 filler[6]; + u32 ebicsa; /* EBI Chip Select Assignment Register */ +}; +#endif /* __ASSEMBLY__ */ -#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */ -#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */ -#define AT91_MATRIX_ITCM_0 (0 << 0) -#define AT91_MATRIX_ITCM_16 (5 << 0) -#define AT91_MATRIX_ITCM_32 (6 << 0) -#define AT91_MATRIX_ITCM_64 (7 << 0) -#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */ -#define AT91_MATRIX_DTCM_0 (0 << 4) -#define AT91_MATRIX_DTCM_16 (5 << 4) -#define AT91_MATRIX_DTCM_32 (6 << 4) -#define AT91_MATRIX_DTCM_64 (7 << 4) +#define AT91_MATRIX_ULBT_INFINITE (0 << 0) +#define AT91_MATRIX_ULBT_SINGLE (1 << 0) +#define AT91_MATRIX_ULBT_FOUR (2 << 0) +#define AT91_MATRIX_ULBT_EIGHT (3 << 0) +#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0) -#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */ -#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */ -#define AT91_MATRIX_CS1A_SMC (0 << 1) -#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) -#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */ -#define AT91_MATRIX_CS3A_SMC (0 << 3) -#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) -#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ -#define AT91_MATRIX_CS4A_SMC (0 << 4) -#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) -#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */ -#define AT91_MATRIX_CS5A_SMC (0 << 5) -#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) -#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ +#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) +#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) +#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18 +#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) +#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) -#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */ -#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */ +#define AT91_MATRIX_M0PR_SHIFT 0 +#define AT91_MATRIX_M1PR_SHIFT 4 +#define AT91_MATRIX_M2PR_SHIFT 8 +#define AT91_MATRIX_M3PR_SHIFT 12 +#define AT91_MATRIX_M4PR_SHIFT 16 +#define AT91_MATRIX_M5PR_SHIFT 20 + +#define AT91_MATRIX_RCB0 (1 << 0) +#define AT91_MATRIX_RCB1 (1 << 1) + +#define AT91_MATRIX_CS1A_SDRAMC (1 << 1) +#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3) +#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) +#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) +#define AT91_MATRIX_DBPUC (1 << 8) +#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16) +#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16) #endif -- 1.7.3.3

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