April 2011 - U-Boot

[U-Boot] [PATCH 1/2] powerpc/85xx: fsl_corenet_serdes code rework
by Kumar Gala 29 Apr '11

29 Apr '11

From: Emil Medve <Emilian.Medve(a)freescale.com> Rework and add some new APIs to the fsl_corenet_serdes code for use by erratum and drivers. * Rename serdes_get_bank() to serdes_get_bank_by_lane() * Add serdes_get_first_lane returns which SERDES lane is used by device Signed-off-by: Emil Medve <Emilian.Medve(a)Freescale.com> Signed-off-by: Timur Tabi <timur(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 40 +++++++++++++++++++++++- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h | 2 +- arch/powerpc/include/asm/fsl_serdes.h | 4 ++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index f58d6d6..1177247 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -29,6 +29,7 @@ #include <asm/io.h> #include <asm/processor.h> #include <asm/fsl_law.h> +#include <asm/errno.h> #include "fsl_corenet_serdes.h" static u32 serdes_prtcl_map; @@ -91,7 +92,7 @@ int serdes_get_lane_idx(int lane) return lanes[lane].idx; } -int serdes_get_bank(int lane) +int serdes_get_bank_by_lane(int lane) { return lanes[lane].bank; } @@ -132,6 +133,41 @@ int is_serdes_configured(enum srds_prtcl device) return (1 << device) & serdes_prtcl_map; } +static int __serdes_get_first_lane(uint32_t prtcl, enum srds_prtcl device) +{ + int i; + + for (i = 0; i < SRDS_MAX_LANES; i++) { + if (serdes_get_prtcl(prtcl, i) == device) + return i; + } + + return -ENODEV; +} + +/* + * Returns the SERDES lane (0..SRDS_MAX_LANES-1) that routes to the given + * device. This depends on the current SERDES protocol, as defined in the RCW. + * + * Returns a negative error code if SERDES is disabled or the given device is + * not supported in the current SERDES protocol. + */ +int serdes_get_first_lane(enum srds_prtcl device) +{ + u32 prtcl; + const ccsr_gur_t *gur; + + gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + + /* Is serdes enabled at all? */ + if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) + return -ENODEV; + + prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + return __serdes_get_first_lane(prtcl, device); +} + #ifndef CONFIG_SYS_DCSRBAR_PHYS #define CONFIG_SYS_DCSRBAR_PHYS 0x80000000 /* Must be 1GB-aligned for rev1.0 */ #define CONFIG_SYS_DCSRBAR 0x80000000 @@ -325,7 +361,7 @@ void fsl_serdes_init(void) for (lane = 0; lane < SRDS_MAX_LANES; lane++) { enum srds_prtcl lane_prtcl = serdes_get_prtcl(cfg, lane); if (serdes_lane_enabled(lane)) { - have_bank[serdes_get_bank(lane)] = 1; + have_bank[serdes_get_bank_by_lane(lane)] = 1; serdes_prtcl_map |= (1 << lane_prtcl); } } diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h index 42d771e..f261351 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.h @@ -33,7 +33,7 @@ enum srds_bank { int is_serdes_prtcl_valid(u32 prtcl); int serdes_get_lane_idx(int lane); -int serdes_get_bank(int lane); +int serdes_get_bank_by_lane(int lane); int serdes_lane_enabled(int lane); enum srds_prtcl serdes_get_prtcl(int cfg, int lane); diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index 85518eb..9d9f2e4 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -53,4 +53,8 @@ enum srds_prtcl { int is_serdes_configured(enum srds_prtcl device); void fsl_serdes_init(void); +#ifdef CONFIG_FSL_CORENET +int serdes_get_first_lane(enum srds_prtcl device); +#endif + #endif /* __FSL_SERDES_H */ -- 1.7.3.4

1 3

[U-Boot] [PATCH] powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)
by Kumar Gala 29 Apr '11

29 Apr '11

The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur(a)freescale.com> Signed-off-by: Shaohui Xie <b21989(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/immap_85xx.h | 1 + board/freescale/common/Makefile | 2 + board/freescale/common/ngpixis.h | 7 ++-- board/freescale/corenet_ds/Makefile | 2 + board/freescale/corenet_ds/corenet_ds.c | 45 ++++++++++++++++++++++++++---- board/freescale/corenet_ds/law.c | 5 ++- board/freescale/corenet_ds/p3041ds_ddr.c | 14 +++++++++ board/freescale/corenet_ds/p5020ds_ddr.c | 18 ++++++++++++ board/freescale/corenet_ds/tlb.c | 10 ++++++ boards.cfg | 2 + include/configs/P3041DS.h | 37 ++++++++++++++++++++++++ include/configs/P5020DS.h | 37 ++++++++++++++++++++++++ include/configs/corenet_ds.h | 38 +++++++++++++++++++++++++ 13 files changed, 208 insertions(+), 10 deletions(-) create mode 100644 board/freescale/corenet_ds/p3041ds_ddr.c create mode 100644 board/freescale/corenet_ds/p5020ds_ddr.c create mode 100644 include/configs/P3041DS.h create mode 100644 include/configs/P5020DS.h diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index d6ac61a..c39c95f 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2101,6 +2101,7 @@ typedef struct serdes_corenet { #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 +#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000 diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 8ea5acb..dbf1da8 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -46,7 +46,9 @@ COBJS-$(CONFIG_MPC8536DS) += ics307_clk.o COBJS-$(CONFIG_MPC8572DS) += ics307_clk.o COBJS-$(CONFIG_P1022DS) += ics307_clk.o COBJS-$(CONFIG_P2020DS) += ics307_clk.o +COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o +COBJS-$(CONFIG_P5020DS) += ics307_clk.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 681b0d0..1d4483d 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -20,16 +20,17 @@ typedef struct ngpixis { u8 scver; u8 csr; u8 rst; - u8 res1; + u8 serclk; u8 aux; u8 spd; u8 brdcfg0; u8 brdcfg1; /* On some boards, this register is called 'dma' */ u8 addr; - u8 res2[2]; + u8 brdcfg2; + u8 gpiodir; u8 data; u8 led; - u8 res3; + u8 tag; u8 vctl; u8 vstat; u8 vcfgen0; diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 1047d78..69e81a4 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -28,7 +28,9 @@ LIB = $(obj)lib$(BOARD).o COBJS-y += $(BOARD).o COBJS-y += ddr.o +COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o +COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o COBJS-$(CONFIG_PCI) += pci.o COBJS-y += law.o COBJS-y += tlb.o diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index 3db93c3..9324125 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -87,10 +87,21 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) + sw = in_8(&PIXIS_SW(5)); + for (i = 0; i < 3; i++) { + static const char *freq[] = {"100", "125", "156.25", "212.5" }; + unsigned int clock = (sw >> (6 - (2 * i))) & 3; + + printf("Bank%u=%sMhz ", i+1, freq[clock]); + } + puts("\n"); +#else sw = in_8(&PIXIS_SW(3)); printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); +#endif return 0; } @@ -146,7 +157,7 @@ static const char *serdes_clock_to_string(u32 clock) case SRDS_PLLCR0_RFCK_SEL_156_25: return "156.25"; default: - return "???"; + return "150"; } } @@ -157,19 +168,41 @@ int misc_init_r(void) serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; u32 actual[NUM_SRDS_BANKS]; unsigned int i; - u8 sw3; + u8 sw; +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) + sw = in_8(&PIXIS_SW(5)); + for (i = 0; i < 3; i++) { + unsigned int clock = (sw >> (6 - (2 * i))) & 3; + switch (clock) { + case 0: + actual[i] = SRDS_PLLCR0_RFCK_SEL_100; + break; + case 1: + actual[i] = SRDS_PLLCR0_RFCK_SEL_125; + break; + case 2: + actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25; + break; + default: + printf("Warning: SDREFCLK%u switch setting of '11' is " + "unsupported\n", i + 1); + break; + } + } +#else /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ - sw3 = in_8(&PIXIS_SW(3)); - actual[0] = (sw3 & 0x40) ? + sw = in_8(&PIXIS_SW(3)); + actual[0] = (sw & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; - actual[1] = (sw3 & 0x20) ? + actual[1] = (sw & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; - actual[2] = (sw3 & 0x10) ? + actual[2] = (sw & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; +#endif for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; diff --git a/board/freescale/corenet_ds/law.c b/board/freescale/corenet_ds/law.c index 43b4b97..d2ba556 100644 --- a/board/freescale/corenet_ds/law.c +++ b/board/freescale/corenet_ds/law.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2010 Freescale Semiconductor, Inc. + * Copyright 2008-2011 Freescale Semiconductor, Inc. * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. @@ -35,6 +35,9 @@ struct law_entry law_table[] = { #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR), #endif +#ifdef CONFIG_SYS_NAND_BASE_PHYS + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), +#endif }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/corenet_ds/p3041ds_ddr.c b/board/freescale/corenet_ds/p3041ds_ddr.c new file mode 100644 index 0000000..5a8ed94 --- /dev/null +++ b/board/freescale/corenet_ds/p3041ds_ddr.c @@ -0,0 +1,14 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {0, 0, NULL} +}; diff --git a/board/freescale/corenet_ds/p5020ds_ddr.c b/board/freescale/corenet_ds/p5020ds_ddr.c new file mode 100644 index 0000000..e65de36 --- /dev/null +++ b/board/freescale/corenet_ds/p5020ds_ddr.c @@ -0,0 +1,18 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {0, 0, NULL} +}; + +fixed_ddr_parm_t fixed_ddr_parm_1[] = { + {0, 0, NULL} +}; diff --git a/board/freescale/corenet_ds/tlb.c b/board/freescale/corenet_ds/tlb.c index 2fbb33c..5e6620a 100644 --- a/board/freescale/corenet_ds/tlb.c +++ b/board/freescale/corenet_ds/tlb.c @@ -116,6 +116,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 13, BOOKE_PAGESZ_4M, 1), #endif +#ifdef CONFIG_SYS_NAND_BASE + /* + * *I*G - NAND + * entry 14 and 15 has been used hard coded, they will be disabled + * in cpu_init_f, so we use entry 16 for nand. + */ + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 16, BOOKE_PAGESZ_1M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index 6ffcd96..6454ac1 100644 --- a/boards.cfg +++ b/boards.cfg @@ -543,9 +543,11 @@ P2020RDB_36BIT_SPIFLASH powerpc mpc85xx p1_p2_rdb freesca P2020RDB_NAND powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,NAND P2020RDB_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SDCARD P2020RDB_SPIFLASH powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,SPIFLASH +P3041DS powerpc mpc85xx corenet_ds freescale P4080DS powerpc mpc85xx corenet_ds freescale P4080DS_RAMBOOT_PBL powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF80000 P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT +P5020DS powerpc mpc85xx corenet_ds freescale mpq101 powerpc mpc85xx mpq101 mercury - mpq101 stxgp3 powerpc mpc85xx stxgp3 stx stxssa powerpc mpc85xx stxssa stx - stxssa diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h new file mode 100644 index 0000000..46f91cc --- /dev/null +++ b/include/configs/P3041DS.h @@ -0,0 +1,37 @@ +/* + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P3041 DS board configuration file + * + */ +#define CONFIG_P3041DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P3041 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" + diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h new file mode 100644 index 0000000..6d279b3 --- /dev/null +++ b/include/configs/P5020DS.h @@ -0,0 +1,37 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * P5020 DS board configuration file + * + */ +#define CONFIG_P5020DS +#define CONFIG_PHYS_64BIT +#define CONFIG_PPC_P5020 + +#define CONFIG_FSL_SATA_V2 +#define CONFIG_PCIE4 + +#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ + +#include "corenet_ds.h" + diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index 9bc9017..080a5a7 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -164,6 +164,7 @@ #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 +#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ /* @@ -220,6 +221,43 @@ #define CONFIG_SYS_RAMBOOT #endif +/* Nand Flash */ +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#define CONFIG_NAND_FSL_ELBC +#ifdef CONFIG_NAND_FSL_ELBC +#define CONFIG_SYS_NAND_BASE 0xffa00000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull +#else +#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE +#endif + +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* NAND flash config */ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ + | OR_FCM_PGS /* Large Page*/ \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) + +#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ +#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ +#endif /* CONFIG_NAND_FSL_ELBC */ +#endif + #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} -- 1.7.3.4

1 1

[U-Boot] [PATCH] powerpc/85xx: Enable Internal USB PHY for p2040, p3041, p5010 and p5020
by Kumar Gala 29 Apr '11

29 Apr '11

From: Roy Zang <tie-fei.zang(a)freescale.com> The P2040, P3041, P5010, and P5020 all have internal USB PHYs that we need to enable for them to function. Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/cpu_init.c | 17 +++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 8 ++++++++ arch/powerpc/include/asm/immap_85xx.h | 13 +++++++++++++ 3 files changed, 38 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 174b031..856d69e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -444,6 +444,23 @@ int cpu_init_r(void) isync(); #endif +#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy1 = + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + out_be32(&usb_phy1->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif +#ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE + { + ccsr_usb_phy_t *usb_phy2 = + (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; + out_be32(&usb_phy2->usb_enable_override, + CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE); + } +#endif + #ifdef CONFIG_FMAN_ENET fman_enet_init(); #endif diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 92d825a..78fd677 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -269,6 +269,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -281,6 +283,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -325,6 +329,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -337,6 +343,8 @@ #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_ERRATUM_COP_A001 +#define CONFIG_SYS_FSL_USB1_PHY_ENABLE +#define CONFIG_SYS_FSL_USB2_PHY_ENABLE #else #error Processor type not defined for this platform diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index caa3c59..75ee506 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2304,6 +2304,13 @@ typedef struct ccsr_pme { u8 res4[0x400]; } ccsr_pme_t; +typedef struct ccsr_usb_phy { + u8 res0[0x18]; + u32 usb_enable_override; + u8 res[0xe4]; +} ccsr_usb_phy_t; +#define CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE 1 + #ifdef CONFIG_SECURE_BOOT typedef struct ccsr_sfp_regs { u8 reserved0[0x40]; @@ -2350,6 +2357,8 @@ typedef struct ccsr_snvs_regs { #define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 #define CONFIG_SYS_MPC85xx_USB_OFFSET CONFIG_SYS_MPC85xx_USB1_OFFSET +#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 +#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 @@ -2475,6 +2484,10 @@ typedef struct ccsr_snvs_regs { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_MPC85xx_USB_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB_OFFSET) +#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) +#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_FM1_ADDR \ -- 1.7.3.4

1 1

[U-Boot] [PATCH] powerpc/85xx: Change timebase divisor to be defined per processor
by Kumar Gala 29 Apr '11

29 Apr '11

Introduce new CONFIG_SYS_FSL_TBCLK_DIV on 85xx platforms because different SoCs have different divisor amounts. All the PQ3 parts are /8, the P4080/P4080 is /16, and P2040/P3041/P5020 are /32. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/cpu.c | 11 ++++++----- arch/powerpc/include/asm/config_mpc85xx.h | 6 ++++++ 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f5b39c0..f863f4a 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -234,13 +234,14 @@ int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* * Get timebase clock frequency */ +#ifndef CONFIG_SYS_FSL_TBCLK_DIV +#define CONFIG_SYS_FSL_TBCLK_DIV 8 +#endif unsigned long get_tbclk (void) { -#ifdef CONFIG_FSL_CORENET - return (gd->bus_clk + 8) / 16; -#else - return (gd->bus_clk + 4UL)/8UL; -#endif + unsigned long tbclk_div = CONFIG_SYS_FSL_TBCLK_DIV; + + return (gd->bus_clk + (tbclk_div >> 1)) / tbclk_div; } diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index da2e998..d71c3fc 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -264,6 +264,7 @@ #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -278,6 +279,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -288,6 +290,7 @@ #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #elif defined(CONFIG_PPC_P4080) #define CONFIG_MAX_CPUS 8 @@ -301,6 +304,7 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 16 #define CONFIG_SYS_FSL_ERRATUM_CPC_A002 #define CONFIG_SYS_FSL_ERRATUM_CPC_A003 #define CONFIG_SYS_FSL_ERRATUM_DDR_A003 @@ -323,6 +327,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 @@ -337,6 +342,7 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 +#define CONFIG_SYS_FSL_TBCLK_DIV 32 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_ERRATUM_ESDHC111 -- 1.7.3.4

4 8

[U-Boot] [PATCH] powerpc/85xx: handle both "secX.Y" and "sec-vX.Y" properties
by Kumar Gala 29 Apr '11

29 Apr '11

From: Kim Phillips <kim.phillips(a)freescale.com> versioned SEC properties changed names during development, so for now search and update LIODNs for both "secX.Y" and "sec-vX.Y" based properties. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/fsl_liodn.h | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 0ec5c0a..801571f 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -115,10 +115,18 @@ extern void fdt_fixup_liodn(void *blob); FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) \ +/* + * handle both old and new versioned SEC properties: + * "fsl,secX.Y" became "fsl,sec-vX.Y" during development + */ #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ + SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ + offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) /* This is a bit evil since we treat rtic param as both a string & hex value */ @@ -127,6 +135,11 @@ extern void fdt_fixup_liodn(void *blob); liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ CONFIG_SYS_FSL_SEC_OFFSET, \ + CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ + liodnA, \ + offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ + CONFIG_SYS_FSL_SEC_OFFSET, \ CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ -- 1.7.3.4

1 1

[U-Boot] [PATCH] powerpc/85xx: Enable ESDHC111 erratum on P2040/P3041/P5010/P5020 SoCs
by Kumar Gala 29 Apr '11

29 Apr '11

From: Lei Xu <B33228(a)freescale.com> The workaround for ESDHC111 should also be applied on P2040/P3041/P5010/P5020 SoCs. Signed-off-by: Lei Xu <B33228(a)freescale.com> Signed-off-by: Roy Zang <tie-fei.zang(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/config_mpc85xx.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d93586a..da2e998 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -266,6 +266,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 @@ -279,6 +280,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -323,6 +325,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 @@ -336,6 +339,7 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 #else #error Processor type not defined for this platform -- 1.7.3.4

1 1

[U-Boot] [PATCH 1/4] powerpc/85xx: Implement work-around for P4080 erratum SERDES-A005
by Kumar Gala 29 Apr '11

29 Apr '11

From: Timur Tabi <timur(a)freescale.com> SerDes PLL bandwidth default setting is incorrect when no lanes are configured as PCI Express. Signed-off-by: Timur Tabi <timur(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 ++ arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 48 +++++++++++++++++++++++++ arch/powerpc/include/asm/config_mpc85xx.h | 1 + 3 files changed, 52 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index 0564816..7b9f773 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -47,6 +47,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) puts("Work-around for Erratum SERDES9 enabled\n"); #endif +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005) + puts("Work-around for Erratum SERDES-A005 enabled\n"); +#endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index d39f963..edacdb8 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -386,6 +386,52 @@ static void p4080_erratum_serdes8(serdes_corenet_t *regs, ccsr_gur_t *gur, } #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 +/* + * If PCIe is not selected as a protocol for any lanes driven by a given PLL, + * that PLL should have SRDSBnPLLCR1[PLLBW_SEL] = 0. + */ +static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) +{ + enum srds_prtcl device; + + switch (cfg) { + case 0x13: + case 0x16: + /* + * If SRDS_PRTCL = 0x13 or 0x16, set SRDSB1PLLCR1[PLLBW_SEL] + * to 0. + */ + clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + case 0x19: + /* + * If SRDS_PRTCL = 0x19, set SRDSB1PLLCR1[PLLBW_SEL] to 0 and + * SRDSB3PLLCR1[PLLBW_SEL] to 1. + */ + clrbits_be32(&regs->bank[FSL_SRDS_BANK_1].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + setbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + break; + } + + /* + * Set SRDSBnPLLCR1[PLLBW_SEL] to 0 for each bank that selects XAUI + * before XAUI is initialized. + */ + for (device = XAUI_FM1; device <= XAUI_FM2; device++) { + if (is_serdes_configured(device)) { + int bank = serdes_get_bank_by_device(cfg, device); + + clrbits_be32(&regs->bank[bank].pllcr1, + SRDS_PLLCR1_PLL_BWSEL); + } + } +} +#endif + void fsl_serdes_init(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -570,6 +616,8 @@ void fsl_serdes_init(void) puts("\n"); #endif +#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A005 + p4080_erratum_serdes_a005(srds_regs, cfg); #endif for (idx = 0; idx < SRDS_MAX_BANK; idx++) { diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d71c3fc..207f717 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -315,6 +315,7 @@ #define CONFIG_SYS_P4080_ERRATUM_CPU22 #define CONFIG_SYS_P4080_ERRATUM_SERDES8 #define CONFIG_SYS_P4080_ERRATUM_SERDES9 +#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005 /* P5010 is single core version of P5020 */ #elif defined(CONFIG_PPC_P5010) -- 1.7.3.4

2 9

[U-Boot] [PATCH 1/3] powerpc/85xx: Enable eSPI controller & SPI bootsupport on P2020DS
by Kumar Gala 29 Apr '11

29 Apr '11

From: Jerry Huang <Chang-Ming.Huang(a)freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> Signed-off-by: Zhao Chenhui <b35336(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- boards.cfg | 1 + include/configs/P2020DS.h | 28 ++++++++++++++++++++++++++++ 2 files changed, 29 insertions(+), 0 deletions(-) diff --git a/boards.cfg b/boards.cfg index be5f83d..39f15f6 100644 --- a/boards.cfg +++ b/boards.cfg @@ -537,6 +537,7 @@ P2020DS powerpc mpc85xx p2020ds freesca P2020DS_36BIT powerpc mpc85xx p2020ds freescale - P2020DS:36BIT P2020DS_DDR2 powerpc mpc85xx p2020ds freescale - P2020DS:DDR2 P2020DS_SDCARD powerpc mpc85xx p2020ds freescale - P2020DS:SDCARD +P2020DS_SPIFLASH powerpc mpc85xx p2020ds freescale - P2020DS:SPIFLASH P2020RDB powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB P2020RDB_36BIT powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT P2020RDB_36BIT_SDCARD powerpc mpc85xx p1_p2_rdb freescale - P1_P2_RDB:P2020RDB,36BIT,SDCARD diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 47f1f18..cee9fd4 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -40,6 +40,13 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc #endif +#ifdef CONFIG_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -418,6 +425,18 @@ #define CONFIG_SYS_EEPROM_BUS_NUM 0 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ @@ -594,6 +613,15 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 #else #define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 -- 1.7.3.4

2 6

[U-Boot] [PATCH][v5] powerpc: eSPI and eSPI controller support
by Shaohui Xie 29 Apr '11

29 Apr '11

From: Mingkai Hu <Mingkai.hu(a)freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> Singed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> Signed-off-by: Shaohui Xie <b21989(a)freescale.com> Cc: Mike Frysinger <vapier(a)gentoo.org> --- changes for v2: remove #ifdef wrapper and refactor spi_xfer by use SPI_XFER(BEGIN | END). remove 'volatile' use I/O accessors instead. changes for v3: move powerpc specific code to asm/config.h. use spi_claim_bus() to setup hardware rather than spi_setup_slave(). use slave data rather than global. drop useless return. changes for v4: use controller specific struct rather than put in common header. merge read more than 0xfffa bytes patch. changes for v5: fix code style. drop flag check. drop unnecessary copy right. arch/powerpc/include/asm/config.h | 7 + drivers/spi/Makefile | 1 + drivers/spi/fsl_espi.c | 334 +++++++++++++++++++++++++++++++++++++ include/spi.h | 7 - 4 files changed, 342 insertions(+), 7 deletions(-) create mode 100644 drivers/spi/fsl_espi.c diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h index 624d8c2..9aad9be 100644 --- a/arch/powerpc/include/asm/config.h +++ b/arch/powerpc/include/asm/config.h @@ -29,6 +29,13 @@ #include <asm/config_mpc86xx.h> #endif +/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ +#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI) +# ifndef CONFIG_HARD_SPI +# define CONFIG_HARD_SPI +# endif +#endif + #define CONFIG_LMB #define CONFIG_SYS_BOOT_RAMDISK_HIGH #define CONFIG_SYS_BOOT_GET_CMDLINE diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index d582fbb..74f1293 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o COBJS-$(CONFIG_SH_SPI) += sh_spi.o +COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c new file mode 100644 index 0000000..f872cd8 --- /dev/null +++ b/drivers/spi/fsl_espi.c @@ -0,0 +1,334 @@ +/* + * eSPI controller driver. + * + * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Author: Mingkai Hu (Mingkai.hu(a)freescale.com) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <malloc.h> +#include <spi.h> +#include <asm/immap_85xx.h> + +struct fsl_spi_slave { + struct spi_slave slave; + unsigned int div16; + unsigned int pm; + unsigned int mode; + size_t cmd_len; + u8 cmd_buf[16]; + size_t data_len; + unsigned int max_transfer_length; +}; + +#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) + +#define ESPI_MAX_CS_NUM 4 + +#define ESPI_EV_RNE (1 << 9) +#define ESPI_EV_TNF (1 << 8) + +#define ESPI_MODE_EN (1 << 31) /* Enable interface */ +#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ +#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ + +#define ESPI_COM_CS(x) ((x) << 30) +#define ESPI_COM_TRANLEN(x) ((x) << 0) + +#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31) +#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30) +#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29) +#define ESPI_CSMODE_DIV16 (1 << 28) +#define ESPI_CSMODE_PM(x) ((x) << 24) +#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20) +#define ESPI_CSMODE_LEN(x) ((x) << 16) +#define ESPI_CSMODE_CSBEF(x) ((x) << 12) +#define ESPI_CSMODE_CSAFT(x) ((x) << 8) +#define ESPI_CSMODE_CSCG(x) ((x) << 3) + +#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \ + ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \ + ESPI_CSMODE_CSCG(1)) + +#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0 + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_spi_slave *fsl; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned char pm = 0; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = malloc(sizeof(struct fsl_spi_slave)); + if (!fsl) + return NULL; + + fsl->slave.bus = bus; + fsl->slave.cs = cs; + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + + /* Set eSPI BRG clock source */ + get_sys_info(&sysinfo); + spibrg = sysinfo.freqSystemBus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("Requested speed is too low: %d Hz, " + "%d Hz is used.\n", max_hz, spibrg / (32 * 16)); + } + } else + pm = spibrg / (max_hz * 2); + if (pm) + pm--; + fsl->pm = pm; + + return &fsl->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + free(fsl); +} + +void spi_init(void) +{ + +} + +int spi_claim_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + unsigned char pm = fsl->pm; + unsigned int cs = slave->cs; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, + void *data_in, unsigned long flags) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + unsigned int tmpdout, tmpdin, event; + const void *dout = NULL; + void *din = NULL; + int len = 0; + int num_blks, num_chunks, max_tran_len, tran_len; + int num_bytes; + unsigned char *ch; + unsigned char *buffer = NULL; + size_t buf_len; + u8 *cmd_buf = fsl->cmd_buf; + size_t cmd_len = fsl->cmd_len; + size_t data_len = bitlen / 8; + size_t rx_offset = 0; + + max_tran_len = fsl->max_transfer_length; + switch (flags) { + case SPI_XFER_BEGIN: + cmd_len = fsl->cmd_len = data_len; + memcpy(cmd_buf, data_out, cmd_len); + return 0; + case 0: + case SPI_XFER_END: + if (bitlen == 0) { + spi_cs_deactivate(slave); + return 0; + } + buf_len = 2 * cmd_len + min(data_len, max_tran_len); + len = cmd_len + data_len; + rx_offset = cmd_len; + buffer = (unsigned char *)malloc(buf_len); + if (!buffer) { + debug("SF: Failed to malloc memory.\n"); + return 1; + } + memcpy(buffer, cmd_buf, cmd_len); + if (cmd_len != 1) { + if (data_in == NULL) + memcpy(buffer + cmd_len, data_out, data_len); + } + break; + case SPI_XFER_BEGIN | SPI_XFER_END: + len = data_len; + buffer = (unsigned char *)malloc(len * 2); + if (!buffer) { + debug("SF: Failed to malloc memory.\n"); + return 1; + } + memcpy(buffer, data_out, len); + rx_offset = len; + cmd_len = 0; + break; + } + + debug("spi_xfer: slave %u:%u dout %08X(%08x) din %08X(%08x) len %u\n", + slave->bus, slave->cs, *(uint *) dout, + dout, *(uint *) din, din, len); + + num_chunks = data_len / max_tran_len + + (data_len % max_tran_len ? 1 : 0); + while (num_chunks--) { + if (data_in) + din = buffer + rx_offset; + dout = buffer; + tran_len = min(data_len , max_tran_len); + num_blks = (tran_len + cmd_len) / 4 + + ((tran_len + cmd_len) % 4 ? 1 : 0); + num_bytes = (tran_len + cmd_len) % 4; + fsl->data_len = tran_len + cmd_len; + spi_cs_activate(slave); + + /* Clear all eSPI events */ + out_be32(&espi->event , 0xffffffff); + /* handle data in 32-bit chunks */ + while (num_blks--) { + + event = in_be32(&espi->event); + if (event & ESPI_EV_TNF) { + tmpdout = *(u32 *)dout; + + /* Set up the next iteration */ + if (len > 4) { + len -= 4; + dout += 4; + } + + out_be32(&espi->tx, tmpdout); + out_be32(&espi->event, ESPI_EV_TNF); + debug("***spi_xfer:...%08x written\n", tmpdout); + } + + /* Wait for eSPI transmit to get out */ + udelay(80); + + event = in_be32(&espi->event); + if (event & ESPI_EV_RNE) { + tmpdin = in_be32(&espi->rx); + if (num_blks == 0 && num_bytes != 0) { + ch = (unsigned char *)&tmpdin; + while (num_bytes--) + *(unsigned char *)din++ = *ch++; + } else { + *(u32 *) din = tmpdin; + din += 4; + } + + out_be32(&espi->event, in_be32(&espi->event) + | ESPI_EV_RNE); + debug("***spi_xfer:...%08x readed\n", tmpdin); + } + } + if (data_in) { + memcpy(data_in, buffer + 2 * cmd_len, tran_len); + if (*buffer == 0x0b) { + data_in += tran_len; + data_len -= tran_len; + *(int *)buffer += tran_len; + } + } + spi_cs_deactivate(slave); + } + + free(buffer); + return 0; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < ESPI_MAX_CS_NUM; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + unsigned int com = 0; + size_t data_len = fsl->data_len; + + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(slave->cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + + /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); +} diff --git a/include/spi.h b/include/spi.h index 320e50e..1eb31d9 100644 --- a/include/spi.h +++ b/include/spi.h @@ -26,13 +26,6 @@ /* Controller-specific definitions: */ -/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */ -#ifdef CONFIG_MPC8XXX_SPI -# ifndef CONFIG_HARD_SPI -# define CONFIG_HARD_SPI -# endif -#endif - /* SPI mode flags */ #define SPI_CPHA 0x01 /* clock phase */ #define SPI_CPOL 0x02 /* clock polarity */ -- 1.6.4

2 1

[U-Boot] DSN: failed (Delivery reports about your e-mail)
by Mailbot for fineweavetextile.com 29 Apr '11

29 Apr '11

This is a Delivery Status Notification (DSN). I was unable to deliver your message to vjsyntex(a)vsnl.com. I said RCPT TO:<vjsyntex(a)vsnl.com> And they gave me the error; 550 5.1.1 unknown or illegal alias: vjsyntex(a)vsnl.com

1 0