November 2011 - U-Boot

[U-Boot] sandbox: I2C EEPROM support
by Wolfgang Denk 04 Nov '11

04 Nov '11

Dear Simon, I just ran over this old posting again: 09/10/2008 Ricardo Ribalda D [PATCH] I2C EEPROM simulator v2 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/46964 We never accepted this for U-Boot mainline, but in the context of the Sandbox environment it might be interesting again. What do you think? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de I often quote myself; it adds spice to my conversation. - G. B. Shaw

3 2

[U-Boot] [PATCH v2 3/3] sandbox: Fix warnings in hashtable.c
by Simon Glass 04 Nov '11

04 Nov '11

This fixes a few printf() strings for size_t which are missing the 'z' modifier. Signed-off-by: Simon Glass <sjg(a)chromium.org> --- Changes in v2: - Fix another warning in the same file lib/hashtable.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/lib/hashtable.c b/lib/hashtable.c index 6895550..fca9d6e 100644 --- a/lib/hashtable.c +++ b/lib/hashtable.c @@ -491,8 +491,8 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, return (-1); } - debug("EXPORT table = %p, htab.size = %d, htab.filled = %d, size = %d\n", - htab, htab->size, htab->filled, size); + debug("EXPORT table = %p, htab.size = %d, htab.filled = %d, " + "size = %zu\n", htab, htab->size, htab->filled, size); /* * Pass 1: * search used entries, @@ -539,7 +539,7 @@ ssize_t hexport_r(struct hsearch_data *htab, const char sep, /* Check if the user supplied buffer size is sufficient */ if (size) { if (size < totlen + 1) { /* provided buffer too small */ - debug("### buffer too small: %d, but need %d\n", + debug("### buffer too small: %zu, but need %zu\n", size, totlen + 1); __set_errno(ENOMEM); return (-1); @@ -640,7 +640,7 @@ int himport_r(struct hsearch_data *htab, /* we allocate new space to make sure we can write to the array */ if ((data = malloc(size)) == NULL) { - debug("himport_r: can't malloc %d bytes\n", size); + debug("himport_r: can't malloc %zu bytes\n", size); __set_errno(ENOMEM); return 0; } -- 1.7.3.1

2 1

[U-Boot] [PATCH] Reduce build times
by Wolfgang Denk 04 Nov '11

04 Nov '11

U-Boot Makefiles contain a number of tests for compiler features etc. which so far are executed again and again. On some architectures (especially ARM) this results in a large number of calls to gcc. This patch makes sure to run such tests only once, thus largely reducing the number of "execve" system calls. Example: number of "execve" system calls for building the "P2020DS" (Power Architecture) and "qong" (ARM) boards, measured as: -> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board> -> grep execve /tmp/foo | wc -l Before: After: Reduction: ================================== P2020DS 20555 15205 -26% qong 31692 14490 -54% As a result, built times are significantly reduced, typically by 30...50%. Signed-off-by: Wolfgang Denk <wd(a)denx.de> Cc: Andy Fleming <afleming(a)gmail.com> Cc: Kumar Gala <galak(a)kernel.crashing.org> Cc: Albert Aribaud <albert.aribaud(a)free.fr> cc: Graeme Russ <graeme.russ(a)gmail.com> cc: Mike Frysinger <vapier(a)gentoo.org> --- More detailled build results: 1) Number of "execve" system calls for two exemplary boards: "P2020DS" for Power Architecture, and "qong" for ARM. Measured as: -> strace -f -e trace=execve -o /tmp/foo ./MAKEALL <board> -> grep execve /tmp/foo | wc -l Before: After: Reduction: ======================================= P2020DS 20555 15205 -26% qong 31692 14490 -54% 2) Build time for single boards: Measured as "time ./MAKEALL <board>" (average over 3 runs after a dummy run to populate the file system; using ELDK 4.2 tool chain; measured for "P2020DS" and "qong" on a Core2 Quad CPU at 2.83GHz, for "m28evk" on a i.MX28 at 454MHz over NFS) Before: After: Reduction: ======================================= P2020DS real 29.429s 19.494s -34% user 64.035s 48.621s -24% sys 16.188s 9.203s -43% qong: real 34.274s 16.263s -53% user 65.014s 39.516s -39% sys 27.606s 9.551s -65% m28evk: real 45.752m 27.606m -40% user 24.868m 17.511m -30% sys 17.017m 6.642m -61% 3) Build time for MAKEALL: Measured as "time MAKEALL_LOGDIR=/work/wd/tmp-LOG BUILD_DIR=/work/wd/tmp ./MAKEALL <arch>" (using ELDK 4.2 tool chain; measured for "ppc" and "arm" on a Core i7 at 3.07GHz) Before: After: Reduction: ======================================= ppc real 82.063m 66.595m -19% user 261.710m 231.429m -12% sys 61.739m 49.193m -20% arm real 55.269m 20.763m -62% user 84.302m 49.154m -42% sys 38.933m 15.028m -61% Note: There is further potential for build time reductions by performing similar optimizations for a number of $(shell ...) constructs in the Makefiles, but I have no good ways to test these at the moment so this is left as exercise for the respective architecture maintainers (mostly blackfin and coldfire, AFAICT) -- wd Makefile | 2 +- arch/arm/config.mk | 19 ++++++++++--------- arch/arm/cpu/arm1136/config.mk | 3 ++- arch/arm/cpu/arm1176/config.mk | 4 +++- arch/arm/cpu/arm1176/s3c64xx/config.mk | 4 +++- arch/arm/cpu/arm720t/config.mk | 4 +++- arch/arm/cpu/arm920t/config.mk | 3 ++- arch/arm/cpu/arm925t/config.mk | 3 ++- arch/arm/cpu/arm926ejs/at91/config.mk | 3 ++- arch/arm/cpu/arm926ejs/config.mk | 3 ++- arch/arm/cpu/arm946es/config.mk | 3 ++- arch/arm/cpu/arm_intcm/config.mk | 3 ++- arch/arm/cpu/armv7/config.mk | 4 ++-- arch/arm/cpu/armv7/omap-common/config.mk | 5 +++-- arch/arm/cpu/ixp/config.mk | 3 ++- arch/arm/cpu/lh7a40x/config.mk | 3 ++- arch/arm/cpu/pxa/config.mk | 3 ++- arch/arm/cpu/s3c44b0/config.mk | 3 ++- arch/arm/cpu/sa1100/config.mk | 3 ++- arch/powerpc/cpu/mpc824x/Makefile | 3 +-- arch/powerpc/cpu/mpc85xx/config.mk | 5 +++-- arch/x86/config.mk | 10 ++++++---- board/siemens/SCM/Makefile | 3 +-- config.mk | 8 +++++--- examples/standalone/Makefile | 3 ++- 25 files changed, 67 insertions(+), 43 deletions(-) diff --git a/Makefile b/Makefile index 9ef33f9..82de62b 100644 --- a/Makefile +++ b/Makefile @@ -320,7 +320,7 @@ else PLATFORM_LIBGCC = -L $(USE_PRIVATE_LIBGCC) -lgcc endif else -PLATFORM_LIBGCC = -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc +PLATFORM_LIBGCC := -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc endif PLATFORM_LIBS += $(PLATFORM_LIBGCC) export PLATFORM_LIBS diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 9b4e581..45f9dca 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -34,7 +34,7 @@ endif PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: -PLATFORM_CPPFLAGS += $(call cc-option,-marm,) +PF_CPPFLAGS_ARM := $(call cc-option,-marm,) # Try if EABI is supported, else fall back to old API, # i. e. for example: @@ -44,15 +44,16 @@ PLATFORM_CPPFLAGS += $(call cc-option,-marm,) # -mabi=apcs-gnu -mno-thumb-interwork # - with ELDK 3.1 (gcc 3.x), use: # -mapcs-32 -mno-thumb-interwork -PLATFORM_CPPFLAGS += $(call cc-option,\ - -mabi=aapcs-linux -mno-thumb-interwork,\ +PF_CPPFLAGS_ABI := $(call cc-option,\ + -mabi=aapcs-linux -mno-thumb-interwork,\ + $(call cc-option,\ + -mapcs-32,\ $(call cc-option,\ - -mapcs-32,\ - $(call cc-option,\ - -mabi=apcs-gnu,\ - )\ - ) $(call cc-option,-mno-thumb-interwork,)\ - ) + -mabi=apcs-gnu,\ + )\ + ) $(call cc-option,-mno-thumb-interwork,)\ + ) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARM) $(PF_CPPFLAGS_ABI) # For EABI, make sure to provide raise() ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS))) diff --git a/arch/arm/cpu/arm1136/config.mk b/arch/arm/cpu/arm1136/config.mk index 3e68535..efee0d1 100644 --- a/arch/arm/cpu/arm1136/config.mk +++ b/arch/arm/cpu/arm1136/config.mk @@ -29,4 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv5 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm1176/config.mk b/arch/arm/cpu/arm1176/config.mk index 14346cf..222d352 100644 --- a/arch/arm/cpu/arm1176/config.mk +++ b/arch/arm/cpu/arm1176/config.mk @@ -29,4 +29,6 @@ PLATFORM_CPPFLAGS += -march=armv5t # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm1176/s3c64xx/config.mk b/arch/arm/cpu/arm1176/s3c64xx/config.mk index 14346cf..222d352 100644 --- a/arch/arm/cpu/arm1176/s3c64xx/config.mk +++ b/arch/arm/cpu/arm1176/s3c64xx/config.mk @@ -29,4 +29,6 @@ PLATFORM_CPPFLAGS += -march=armv5t # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm720t/config.mk b/arch/arm/cpu/arm720t/config.mk index 3844c62..210c6dc 100644 --- a/arch/arm/cpu/arm720t/config.mk +++ b/arch/arm/cpu/arm720t/config.mk @@ -30,4 +30,6 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm920t/config.mk b/arch/arm/cpu/arm920t/config.mk index 8f6c1a3..f03030a 100644 --- a/arch/arm/cpu/arm920t/config.mk +++ b/arch/arm/cpu/arm920t/config.mk @@ -29,4 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm925t/config.mk b/arch/arm/cpu/arm925t/config.mk index 8f6c1a3..f03030a 100644 --- a/arch/arm/cpu/arm925t/config.mk +++ b/arch/arm/cpu/arm925t/config.mk @@ -29,4 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm926ejs/at91/config.mk b/arch/arm/cpu/arm926ejs/at91/config.mk index 19296fd..370630d 100644 --- a/arch/arm/cpu/arm926ejs/at91/config.mk +++ b/arch/arm/cpu/arm926ejs/at91/config.mk @@ -1 +1,2 @@ -PLATFORM_CPPFLAGS += $(call cc-option,-mtune=arm926ejs,) +PF_CPPFLAGS_TUNE := $(call cc-option,-mtune=arm926ejs,) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_TUNE) diff --git a/arch/arm/cpu/arm926ejs/config.mk b/arch/arm/cpu/arm926ejs/config.mk index f8ef90f..ffb2e6c 100644 --- a/arch/arm/cpu/arm926ejs/config.mk +++ b/arch/arm/cpu/arm926ejs/config.mk @@ -29,4 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv5te # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm946es/config.mk b/arch/arm/cpu/arm946es/config.mk index e783f69..c2354ba 100644 --- a/arch/arm/cpu/arm946es/config.mk +++ b/arch/arm/cpu/arm946es/config.mk @@ -29,4 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/arm_intcm/config.mk b/arch/arm/cpu/arm_intcm/config.mk index e783f69..c2354ba 100644 --- a/arch/arm/cpu/arm_intcm/config.mk +++ b/arch/arm/cpu/arm_intcm/config.mk @@ -29,4 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/armv7/config.mk b/arch/arm/cpu/armv7/config.mk index 49ac9c7..83ddf10 100644 --- a/arch/arm/cpu/armv7/config.mk +++ b/arch/arm/cpu/armv7/config.mk @@ -29,5 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv5 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk index 49ac9c7..c400dcc 100644 --- a/arch/arm/cpu/armv7/omap-common/config.mk +++ b/arch/arm/cpu/armv7/omap-common/config.mk @@ -29,5 +29,6 @@ PLATFORM_CPPFLAGS += -march=armv5 # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ - $(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/ixp/config.mk b/arch/arm/cpu/ixp/config.mk index 5868cba..9149665 100644 --- a/arch/arm/cpu/ixp/config.mk +++ b/arch/arm/cpu/ixp/config.mk @@ -37,4 +37,5 @@ LDFLAGS_u-boot += --gc-sections # Supply options according to compiler version # # ========================================================================= -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/lh7a40x/config.mk b/arch/arm/cpu/lh7a40x/config.mk index 47b2b7b..1c4aa97 100644 --- a/arch/arm/cpu/lh7a40x/config.mk +++ b/arch/arm/cpu/lh7a40x/config.mk @@ -29,4 +29,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # Supply options according to compiler version # # ======================================================================== -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/pxa/config.mk b/arch/arm/cpu/pxa/config.mk index a05d69c..0bbe295 100644 --- a/arch/arm/cpu/pxa/config.mk +++ b/arch/arm/cpu/pxa/config.mk @@ -30,4 +30,5 @@ PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale # Supply options according to compiler version # # ======================================================================== -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/s3c44b0/config.mk b/arch/arm/cpu/s3c44b0/config.mk index 7454d72..f6f6398 100644 --- a/arch/arm/cpu/s3c44b0/config.mk +++ b/arch/arm/cpu/s3c44b0/config.mk @@ -30,4 +30,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float # Supply options according to compiler version # # ======================================================================== -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/arm/cpu/sa1100/config.mk b/arch/arm/cpu/sa1100/config.mk index 6f21f41..06af160 100644 --- a/arch/arm/cpu/sa1100/config.mk +++ b/arch/arm/cpu/sa1100/config.mk @@ -30,4 +30,5 @@ PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100 # Supply options according to compiler version # # ======================================================================== -PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) +PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT) diff --git a/arch/powerpc/cpu/mpc824x/Makefile b/arch/powerpc/cpu/mpc824x/Makefile index 2bfcd85..ebf4cb2 100644 --- a/arch/powerpc/cpu/mpc824x/Makefile +++ b/arch/powerpc/cpu/mpc824x/Makefile @@ -23,8 +23,7 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)drivers/epic) -$(shell mkdir -p $(obj)drivers/i2c) +$(shell mkdir -p $(obj)drivers/epic $(obj)drivers/i2c) endif LIB = $(obj)lib$(CPU).o diff --git a/arch/powerpc/cpu/mpc85xx/config.mk b/arch/powerpc/cpu/mpc85xx/config.mk index 68ac57d..f36d823 100644 --- a/arch/powerpc/cpu/mpc85xx/config.mk +++ b/arch/powerpc/cpu/mpc85xx/config.mk @@ -28,5 +28,6 @@ PLATFORM_CPPFLAGS += -ffixed-r2 -Wa,-me500 -msoft-float -mno-string # -mspe=yes is needed to have -mno-spe accepted by a buggy GCC; # see "[PATCH,rs6000] make -mno-spe work as expected" on # http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html -PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=yes) -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) +PF_CPPFLAGS_SPE := $(call cc-option,-mspe=yes) \ + $(call cc-option,-mno-spe) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_SPE) diff --git a/arch/x86/config.mk b/arch/x86/config.mk index ee23c9f..fe9083f 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -27,10 +27,12 @@ PLATFORM_CPPFLAGS += -fno-strict-aliasing PLATFORM_CPPFLAGS += -Wstrict-prototypes PLATFORM_CPPFLAGS += -mregparm=3 PLATFORM_CPPFLAGS += -fomit-frame-pointer -PLATFORM_CPPFLAGS += $(call cc-option, -ffreestanding) -PLATFORM_CPPFLAGS += $(call cc-option, -fno-toplevel-reorder, $(call cc-option, -fno-unit-at-a-time)) -PLATFORM_CPPFLAGS += $(call cc-option, -fno-stack-protector) -PLATFORM_CPPFLAGS += $(call cc-option, -mpreferred-stack-boundary=2) +PF_CPPFLAGS_X86 := $(call cc-option, -ffreestanding) \ + $(call cc-option, -fno-toplevel-reorder, \ + $(call cc-option, -fno-unit-at-a-time)) \ + $(call cc-option, -fno-stack-protector) \ + $(call cc-option, -mpreferred-stack-boundary=2) +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0 diff --git a/board/siemens/SCM/Makefile b/board/siemens/SCM/Makefile index 07cc5a6..07db9d4 100644 --- a/board/siemens/SCM/Makefile +++ b/board/siemens/SCM/Makefile @@ -24,8 +24,7 @@ include $(TOPDIR)/config.mk ifneq ($(OBJTREE),$(SRCTREE)) -$(shell mkdir -p $(obj)../common) -$(shell mkdir -p $(obj)../../tqc/tqm8xx) +$(shell mkdir -p $(obj)../common $(obj)../../tqc/tqm8xx) endif LIB = $(obj)lib$(BOARD).o diff --git a/config.mk b/config.mk index 11b67e5..918cffe 100644 --- a/config.mk +++ b/config.mk @@ -209,11 +209,13 @@ else CFLAGS := $(CPPFLAGS) -Wall -Wstrict-prototypes endif -CFLAGS += $(call cc-option,-fno-stack-protector) +CFLAGS_SSP := $(call cc-option,-fno-stack-protector) +CFLAGS += $(CFLAGS_SSP) # Some toolchains enable security related warning flags by default, # but they don't make much sense in the u-boot world, so disable them. -CFLAGS += $(call cc-option,-Wno-format-nonliteral) -CFLAGS += $(call cc-option,-Wno-format-security) +CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \ + $(call cc-option,-Wno-format-security) +CFLAGS += $(CFLAGS_WARN) # $(CPPFLAGS) sets -g, which causes gcc to pass a suitable -g<format> # option to the assembler. diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile index b1e33fb..e23865b 100644 --- a/examples/standalone/Makefile +++ b/examples/standalone/Makefile @@ -85,7 +85,8 @@ endif # We don't want gcc reordering functions if possible. This ensures that an # application's entry point will be the first function in the application's # source file. -CFLAGS += $(call cc-option,-fno-toplevel-reorder) +CFLAGS_NTR := $(call cc-option,-fno-toplevel-reorder) +CFLAGS += $(CFLAGS_NTR) all: $(obj).depend $(OBJS) $(LIB) $(SREC) $(BIN) $(ELF) -- 1.7.6.4

10 13

Re: [U-Boot] SPL support and secondary image size
by jonsmirl＠gmail.com 04 Nov '11

04 Nov '11

On Thu, Nov 3, 2011 at 9:37 PM, Tom Rini <tom.rini(a)gmail.com> wrote: > On Thu, Nov 3, 2011 at 4:27 PM, jonsmirl(a)gmail.com <jonsmirl(a)gmail.com> wrote: >> Some more info on the out of tree NXP code... I didn't write it, I >> am just trying to get it working on a current uboot since the NXP >> u-boot code is too old for ARM device tree support. >> >> Most u-boot images are around 250KB. >> >> lpc3130 has 96K of SRAM. The ARM ROM on the chip can IPL from six >> sources: NAND, SPI, DFU USB, SD, NOR FLASH, UART. A header at the >> front of the IPL image tells the ROM how much to load. >> >> 96KB is large enough to build a single SPL image that can then >> continue loading from all six different sources. I have ported enough >> of the code to the new SPL system to build a SPL image derived off >> from the NXP code. For my application I want NAND and USB DFU. I am >> testing with UART. >> >> The secondary NXP loaders all want to know the length of what they are >> loading. NXP was able to get this length by building both the SPL and >> the main u-boot into a single image file. They then used dd to chop it >> up into the two files: u-boot-spl.bin and u-boot.bin > > OK, but this is new and you aren't restrained by that really, yes? > Are you able to tell at run time what the next source should be? What After the SPL program gets control it can reread the GPIO pins telling what the boot mode is. There is not restriction on how the boot can proceed, I can ignore the pins if I want to. I added a minor hack to the Makefile to get the file size passed into the SPL build. CFLAGS += -DUBOOT_FILESIZE=$(shell stat -c%s $(TOPDIR)/u-boot.bin) I can now load the SPL via UART, then load the real uboot via UART (straight binary) and then it doesn't work right so I have to debug it. > I mean is that on OMAP3/4/am335x if we load via UART, we load the SPL > binary via UART and it is told by the rom that UART was what it was > loaded by so SPL then expects to be given U-Boot by UART. But the rom > code isn't responsible, U-Boot SPL is and doesn't care (we added > ymodem support which needs pushing back to the community). Same deal > with SD or NAND. romcode loads one, tells us what loaded us, then > U-Boot SPL is loading the next part. > > -- > Tom > -- Jon Smirl jonsmirl(a)gmail.com

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[U-Boot] l am interested to buy your pup
by jerry tom 04 Nov '11

04 Nov '11

Hello Sales Hi my name is TOM i came i cross your pup adverstise and am hearing impaired so i will like know if the pup is still available for sale if so get back to me. REPLY ME ASAP YOURS TOM ----------------------------------------------------------------- Find the home of your dreams with eircom net property Sign up for email alerts now http://www.eircom.net/propertyalerts

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[U-Boot] sandbox crashes...
by Wolfgang Denk 04 Nov '11

04 Nov '11

Dear Simon, with current top of tree (v2011.09-690-gfec79ac) I see this (on a i686 host): -> ./MAKEALL sandbox Configuring for sandbox board... cmd_nvedit.c: In function ‘do_env_export’: cmd_nvedit.c:748:3: warning: format ‘%zX’ expects argument of type ‘size_t’, but argument 3 has type ‘long unsigned int’ [-Wformat] cmd_nvedit.c:774:2: warning: format ‘%zX’ expects argument of type ‘size_t’, but argument 3 has type ‘long unsigned int’ [-Wformat] cmd_nvedit.c: In function ‘do_env_import’: cmd_nvedit.c:865:3: warning: format ‘%zd’ expects argument of type ‘signed size_t’, but argument 2 has type ‘size_t’ [-Wformat] cmd_nvedit.c:865:3: warning: format ‘%zX’ expects argument of type ‘size_t’, but argument 3 has type ‘long unsigned int’ [-Wformat] hashtable.c: In function ‘hexport_r’: hashtable.c:494:2: warning: format ‘%d’ expects argument of type ‘int’, but argument 5 has type ‘size_t’ [-Wformat] hashtable.c:542:4: warning: format ‘%d’ expects argument of type ‘int’, but argument 2 has type ‘size_t’ [-Wformat] hashtable.c:542:4: warning: format ‘%d’ expects argument of type ‘int’, but argument 3 has type ‘long unsigned int’ [-Wformat] hashtable.c: In function ‘himport_r’: hashtable.c:643:3: warning: format ‘%d’ expects argument of type ‘int’, but argument 2 has type ‘size_t’ [-Wformat] text data bss dec hex filename 101737 3004 26128 130869 1ff35 ./u-boot --------------------- SUMMARY ---------------------------- Boards compiled: 1 Boards with warnings or errors: 1 ( sandbox ) ---------------------------------------------------------- -> git describe v2011.09-690-gfec79ac -> gdb u-boot GNU gdb (GDB) Fedora (7.3-43.fc15) Copyright (C) 2011 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "i686-redhat-linux-gnu". For bug reporting instructions, please see: <http://www.gnu.org/software/gdb/bugs/>... Reading symbols from /home/wd/git/u-boot/work/u-boot...done. (gdb) run Starting program: /home/wd/git/u-boot/work/u-boot Program received signal SIGSEGV, Segmentation fault. memset (s=0x0, c=0, count=72) at string.c:418 418 *sl++ = cl; Missing separate debuginfos, use: debuginfo-install glibc-2.14-5.i686 (gdb) bt #0 memset (s=0x0, c=0, count=72) at string.c:418 #1 0x08048de4 in board_init_f (bootflag=0) at board.c:153 #2 0x08048b58 in main (argc=1, argv=0xbfffeb44) at start.c:30 (gdb) memset(NULL, 0, 72) ? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de "I'm growing older, but not up." - Jimmy Buffett

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[U-Boot] [PATCH 1/2 v6] powerpc/mpc83xx: Add 512MB DDR support for mpc8360emds
by Chang-Ming.Huang＠freescale.com 04 Nov '11

04 Nov '11

From: Jerry Huang <Chang-Ming.Huang(a)freescale.com> The new MPC8360EMDS board supports 512MB DDR since 2008. For 512MB DDR: BAT0 is used for the first 256MB memory, BAT4 is used for the second 256MB memory and the address space of SDRAM follows the DDR, so if the size of DDR is 256MB, the BAT4 will be used for SDRAM and if the size of DDR is 512MB, the BAT4 will be used for the second 256MB memory and there is no BAT for SDRAM. Therefore, if the size of DDR is 512MB, this patch will use BAT6 for SDRAM and BAT5 will be used for PCI MEM to replace the BAT6 after the codes relocates to the DDR. Signed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> CC: Kim Phillips <kim.phillips(a)freescale.com> --- cahnges for v2: - fix multiline comment wrong changes for v3: - change the oscillator to 33330000, not 33300000 changes for v4: - add the mandatory history of changes changes for v5: - move the code to platform file from lib/board.c - add 2011 copyright changes for v6: - split into two patch - clean the code - add CC board/freescale/mpc8360emds/mpc8360emds.c | 27 ++++++++++++++++++++++++++- include/configs/MPC8360EMDS.h | 3 ++- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c index 0babd26..f150a09 100644 --- a/board/freescale/mpc8360emds/mpc8360emds.c +++ b/board/freescale/mpc8360emds/mpc8360emds.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006,2010 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc. * Dave Liu <daveliu(a)freescale.com> * * See file CREDITS for list of people who contributed to this @@ -23,6 +23,7 @@ #include <asm/mmu.h> #include <asm/io.h> #include <asm/fsl_enet.h> +#include <asm/mmu.h> #if defined(CONFIG_OF_LIBFDT) #include <libfdt.h> #endif @@ -138,9 +139,20 @@ int board_early_init_f(void) int board_early_init_r(void) { + gd_t *gd; #ifdef CONFIG_PQ_MDS_PIB pib_init(); #endif + /* + * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB + * So re-setup PCI MEM space used BAT5 after relocated to DDR + */ + gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); + if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { + write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L); + write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L); + } + return 0; } @@ -290,6 +302,19 @@ static int sdram_init(unsigned int base) if (rem) base = base - rem + sdram_size; + /* + * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB + * After relocated to DDR, reuse BAT5 for PCI MEM space + */ + if (base > CONFIG_MAX_MEM_MAPPED) { + unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE; + unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP; + + /* Setup the BAT6 for SDRAM */ + write_bat(DBAT6, batu, batl); + write_bat(IBAT6, batu, batl); + } + sdram_addr = (uint *)base; /* * Setup SDRAM Base and Option Registers diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index a959940..cfba894 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Freescale Semiconductor, Inc. + * Copyright (C) 2006,2011 Freescale Semiconductor, Inc. * * Dave Liu <daveliu(a)freescale.com> * @@ -506,6 +506,7 @@ */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ +#define CONFIG_BAT_RW /* DDR/LBC SDRAM: cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) -- 1.6.4

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[U-Boot] [PATCH] powerpc/mpc83xx: Cleanup usage of LBC and DDR constants
by Joe Hershberger 04 Nov '11

04 Nov '11

Attempt to make 83xx use constants consistently. In the course of switching from numerics to field constants, a number of reserved fields being assigned were found. Those places that seemed broken I marked with [RFC]... please provide guidance if you are familiar with that target. Signed-off-by: Joe Hershberger <joe.hershberger(a)ni.com> Cc: Joe Hershberger <joe.hershberger(a)gmail.com> Cc: Kim Phillips <kim.phillips(a)freescale.com> --- arch/powerpc/cpu/mpc83xx/spd_sdram.c | 9 ++ arch/powerpc/include/asm/fsl_lbc.h | 8 +- include/configs/MERGERBOX.h | 28 +++-- include/configs/MPC8308RDB.h | 50 +++++--- include/configs/MPC8313ERDB.h | 80 +++++++++---- include/configs/MPC8315ERDB.h | 49 ++++---- include/configs/MPC8323ERDB.h | 114 ++++++------------- include/configs/MPC832XEMDS.h | 213 +++++++++++++++++++--------------- include/configs/MPC8349EMDS.h | 107 ++++++++++------- include/configs/MPC8349ITX.h | 35 +++--- include/configs/MPC8360EMDS.h | 146 ++++++++++++++++-------- include/configs/MPC8360ERDK.h | 74 +++++++----- include/configs/MPC837XEMDS.h | 111 ++++++++++-------- include/configs/MPC837XERDB.h | 118 +++++++++++-------- include/configs/MVBLM7.h | 28 +++-- include/configs/SIMPC8313.h | 26 ++-- include/configs/TQM834x.h | 20 ++-- include/configs/km/km83xx-common.h | 28 +++-- include/configs/kmeter1.h | 20 ++-- include/configs/kmsupx5.h | 8 +- include/configs/mpc8308_p1m.h | 47 ++++---- include/configs/sbc8349.h | 65 +++++++---- include/configs/suvd3.h | 10 +- include/configs/tuda1.h | 21 ++-- include/configs/tuxa1.h | 23 ++-- include/configs/ve8313.h | 80 +++++++------ include/configs/vme8349.h | 75 ++++++++---- include/mpc83xx.h | 32 +++++- 28 files changed, 942 insertions(+), 683 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index 9b01f0d..3855bfd 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -46,10 +46,19 @@ void board_add_ram_info(int use_default) printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) + if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) + puts(", 16-bit"); + else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) + puts(", 32-bit"); + else + puts(", unknown width"); +#else if (ddr->sdram_cfg & SDRAM_CFG_32_BE) puts(", 32-bit"); else puts(", 64-bit"); +#endif if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) puts(", ECC on"); diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 8695a62..bf572b7 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -50,8 +50,10 @@ void lbc_sdram_init(void); #define BR_MSEL 0x000000E0 #define BR_MSEL_SHIFT 5 #define BR_MS_GPCM 0x00000000 /* GPCM */ +#if !defined(CONFIG_MPC834x) && !defined(CONFIG_MPC8360) #define BR_MS_FCM 0x00000020 /* FCM */ -#ifdef CONFIG_MPC83xx +#endif +#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8360) #define BR_MS_SDRAM 0x00000060 /* SDRAM */ #elif defined(CONFIG_MPC85xx) #define BR_MS_SDRAM 0x00000000 /* SDRAM */ @@ -138,8 +140,10 @@ void lbc_sdram_init(void); #define OR_GPCM_EHTR_SHIFT 1 #define OR_GPCM_EHTR_CLEAR 0x00000000 #define OR_GPCM_EHTR_SET 0x00000002 +#if !defined(CONFIG_MPC8308) #define OR_GPCM_EAD 0x00000001 #define OR_GPCM_EAD_SHIFT 0 +#endif /* helpers to convert values into an OR address mask (GPCM mode) */ #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ @@ -196,8 +200,10 @@ void lbc_sdram_init(void); #define OR_SDRAM_XAM_SHIFT 13 #define OR_SDRAM_COLS 0x00001C00 #define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_MIN_COLS 7 #define OR_SDRAM_ROWS 0x000001C0 #define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_MIN_ROWS 9 #define OR_SDRAM_PMSEL 0x00000020 #define OR_SDRAM_PMSEL_SHIFT 5 #define OR_SDRAM_EAD 0x00000001 diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h index f9681cd..8a1c4f0 100644 --- a/include/configs/MERGERBOX.h +++ b/include/configs/MERGERBOX.h @@ -159,11 +159,13 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\ + BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\ - OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\ - OR_GPCM_EHTR | OR_GPCM_EAD) + OR_GPCM_XACS | OR_GPCM_SCY_15 |\ + OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\ + OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -180,14 +182,14 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2<<BR_DECC_SHIFT) |\ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | BR_DECC_CHK_GEN |\ BR_PS_8 | BR_MS_FCM | BR_V) -#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | OR_FCM_BCTLD | OR_FCM_CST |\ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_FCM_BCTLD | OR_FCM_CST |\ OR_FCM_CHT | OR_FCM_SCY_1 | OR_FCM_RST |\ OR_FCM_TRLX | OR_FCM_EHTR) #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) /* * Serial Port @@ -409,7 +411,7 @@ /* DDR: cache cacheable */ #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ BATU_VP) @@ -423,7 +425,7 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ BATU_VP) @@ -437,23 +439,23 @@ #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ BATU_VS | BATU_VP) @@ -461,7 +463,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ BATU_VS | BATU_VP) diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 3ff175c..1e50194 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -149,7 +149,8 @@ #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) /* 0x80010102 */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 @@ -184,7 +185,7 @@ /* 0x03600100 */ #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE) + | SDRAM_CFG_DBW_32) /* 0x43080000 */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ @@ -240,17 +241,18 @@ #define CONFIG_SYS_BR0_PRELIM (\ CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ - (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ + BR_PS_16 /* 16 bit port size */ |\ + BR_MS_GPCM /* MSEL = GPCM */ |\ BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD) + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + /* [RFC]EAD is reserved on MPC8308: | OR_GPCM_EAD */) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ /* 127 64KB sectors and 8 8KB top sectors per device */ @@ -263,12 +265,13 @@ * NAND Flash on the Local Bus */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */ #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_OR1_PRELIM ( P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -282,9 +285,22 @@ #ifdef CONFIG_VSC7385_ENET #define CONFIG_TSEC2 -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ -#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 /* VSC7385 Base address */ +#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE /* VSC7385 Base address on CS2 */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + /* 0xF0000801 */ +#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_SETA \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + /* [RFC]EAD is reserved on MPC8308: | OR_GPCM_EAD */) + /* 0xFFFE09FF */ /* Access window base at VSC7385 base */ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access window size 128K */ @@ -464,7 +480,7 @@ */ /* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ BATU_VS | BATU_VP) @@ -472,7 +488,7 @@ #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ BATU_VP) @@ -480,17 +496,17 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 92c54d0..046fe0a 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -131,7 +131,8 @@ */ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ - | 0x00010000 /* TODO */ \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) /* 0x80010102 */ @@ -168,12 +169,13 @@ #if defined(CONFIG_DDR_2T_TIMING) #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_2T_EN \ - | SDRAM_CFG_DBW_32 ) + | SDRAM_CFG_DBW_32 \ + | SDRAM_CFG_2T_EN ) + /* 0x43088000 */ #else #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE ) + | SDRAM_CFG_DBW_32 ) /* 0x43080000 */ #endif #define CONFIG_SYS_SDRAM_CFG2 0x00401000 @@ -202,16 +204,17 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM ( 0xFF800000 /* 8 MByte */ \ +#define CONFIG_SYS_NOR_OR_PRELIM ( MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) /* 8 MByte */ \ | OR_GPCM_XACS \ | OR_GPCM_SCY_9 \ | OR_GPCM_EHTR \ | OR_GPCM_EAD ) /* 0xFF006FF7 TODO SLOW 16 MB flash size */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) /* 16 MB window size */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 135 /* sectors per device */ @@ -264,14 +267,15 @@ #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM ( P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -293,27 +297,53 @@ #endif #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM -/* local bus read write buffer mapping */ -#define CONFIG_SYS_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ -#define CONFIG_SYS_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xFA000000 -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ +/* local bus write LED / read status buffer (BCSR) mapping */ +#define CONFIG_SYS_BCSR_ADDR 0xFA000000 +#define CONFIG_SYS_BCSR_SIZE (32 * 1024) /* 0x00008000 */ +#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_BCSR_ADDR /* map at 0xFA000000 on LCS3 */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ + /* 0xFA000801 */ +#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCSR_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFF8FF7 */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_BCSR_ADDR +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) /* Vitesse 7385 */ -#define CONFIG_SYS_VSC7385_BASE 0xF0000000 - #ifdef CONFIG_VSC7385_ENET -#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ -#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ +#define CONFIG_SYS_VSC7385_BASE 0xF0000000 /* VSC7385 Base address */ +#define CONFIG_SYS_VSC7385_SIZE (128 * 1024) /* 0x00020000 */ + +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE/* VSC7385 Base address on LCS2 */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VSC7385_SIZE) \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_SETA \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFE09FF */ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE/* Access window base at VSC7385 base */ -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) #endif @@ -547,13 +577,13 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI2 not supported on 8313 */ @@ -563,11 +593,11 @@ #define CONFIG_SYS_IBAT4U (0) /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT7L (0) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index a0cfd00..c2a38d0 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -141,7 +141,8 @@ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ - | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) /* 0x80010102 */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 @@ -176,7 +177,7 @@ /* 0x03600100 */ #define CONFIG_SYS_DDR_SDRAM_CFG ( SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE ) + | SDRAM_CFG_DBW_32 ) /* 0x43080000 */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ @@ -225,19 +226,20 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \ - | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD ) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ @@ -268,20 +270,21 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 -#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_BLOCK_SIZE 16384 +#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) -#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) -#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 -#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 -#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 -#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10) +#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000 +#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384 +#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000 #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ @@ -303,7 +306,7 @@ #endif #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM @@ -569,40 +572,40 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 4d4c758..c77ed61 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -62,7 +62,7 @@ /* * IMMR new address */ -#define CONFIG_SYS_IMMR 0xE0000000 +#define CONFIG_SYS_IMMR 0xE0000000 /* * System performance @@ -77,7 +77,13 @@ #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */ +/* [RFC]This is not defined on the MPC8323: +#define CONFIG_SYS_DDRCDR ( DDRCDR_EN \ + | DDRCDR_PZ_NOMZ \ + | DDRCDR_NZ_NOMZ \ + | DDRCDR_M_ODR ) +*/ + /* 0x73000002 */ /* DDR II voltage is 1.8V */ #undef CONFIG_SPD_EEPROM #if defined(CONFIG_SPD_EEPROM) @@ -89,7 +95,7 @@ */ #define CONFIG_SYS_DDR_SIZE 64 /* MB */ #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ - | CSCONFIG_ODT_WR_ACS \ + /* [RFC]Reserved on MPC832x: | 0x00010000 */ \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9 ) /* 0x80010101 */ #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ @@ -177,18 +183,28 @@ * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ -#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ +#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFE006FF7 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -196,68 +212,6 @@ #undef CONFIG_SYS_FLASH_CHECKSUM /* - * SDRAM on the Local Bus - */ -#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ - -#ifdef CONFIG_SYS_LB_SDRAM -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ - -/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ - -#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 - -#endif - -/* - * Windows to access PIB via local bus - */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ - -/* * Serial Port */ #define CONFIG_CONS_INDEX 1 @@ -447,22 +401,22 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U @@ -472,19 +426,19 @@ #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f136a8e..785d51e 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -111,17 +111,53 @@ /* Manually set up DDR parameters */ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80840102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x3935d322 -#define CONFIG_SYS_DDR_TIMING_2 0x0f9048ca -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 -#define CONFIG_SYS_DDR_MODE 0x44400232 +#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ + | CSCONFIG_AP \ + | CSCONFIG_ODT_WR_CFG \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80840102 */ +#define CONFIG_SYS_DDR_TIMING_0 ( (0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT) ) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ( (3 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (3 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (13 << TIMING_CFG1_REFREC_SHIFT) \ + | (3 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x3935D322 */ +#define CONFIG_SYS_DDR_TIMING_2 ( (0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (31 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (10 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x0F9048CA */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 + /* 0x02000000 */ +#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* 0x44400232 */ #define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03200064 -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 +#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03200064 */ +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE) + /* 0x43080000 */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #endif @@ -172,12 +208,22 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM 0xfe006ff7 /* 16MB Flash size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) + +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xfe006ff7 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ @@ -185,88 +231,69 @@ #undef CONFIG_SYS_FLASH_CHECKSUM /* - * BCSR on the Local Bus + * Status buffer (BCSR) on the Local Bus */ -#define CONFIG_SYS_BCSR 0xF8000000 +#define CONFIG_SYS_BCSR 0xF8000000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ - -/* - * SDRAM on the Local Bus - */ -#undef CONFIG_SYS_LB_SDRAM /* The board has not SRDAM on local bus */ - -#ifdef CONFIG_SYS_LB_SDRAM -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64MB */ - -/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ -/* - * Base Register 2 and Option Register 2 configure SDRAM. - * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. - * - * For BR2, need: - * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 - * port size = 32-bits = BR2[19:20] = 11 - * no parity checking = BR2[21:22] = 00 - * SDRAM for MSEL = BR2[24:26] = 011 - * Valid = BR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861 - * - * CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * the top 17 bits of BR2. - */ - -#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /*Port size=32bit, MSEL=SDRAM */ - -/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. - * - * For OR2, need: - * 64MB mask for AM, OR2[0:7] = 1111 1100 - * XAM, OR2[17:18] = 11 - * 9 columns OR2[19-21] = 010 - * 13 rows OR2[23-25] = 100 - * EAD set for extra time OR[31] = 1 - * - * 0 4 8 12 16 20 24 28 - * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 - */ - -#define CONFIG_SYS_OR2_PRELIM 0xfc006901 - -#define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ -#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ - -#define CONFIG_SYS_LBC_LSDMR_COMMON 0x0063b723 - -#endif +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFFE9F7 */ /* - * Windows to access PIB via local bus + * Windows to access Platform I/O Boards (PIB) via local bus */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8008000 /* windows base 0xf8008000 */ -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000f /* windows size 64KB */ +#define CONFIG_SYS_PIB_BASE 0xF8008000 /* PIB window base 0xF8008000 */ +#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) /* * CS2 on Local Bus, to PIB */ -#define CONFIG_SYS_BR2_PRELIM 0xf8008801 /* CS2 base address at 0xf8008000 */ -#define CONFIG_SYS_OR2_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF8008801 */ +#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffffe9f7 */ /* * CS3 on Local Bus, to PIB */ -#define CONFIG_SYS_BR3_PRELIM 0xf8010801 /* CS3 base address at 0xf8010000 */ -#define CONFIG_SYS_OR3_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ +#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE) \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF8010801 */ +#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffffe9f7 */ /* * Serial Port @@ -465,29 +492,29 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U @@ -497,19 +524,19 @@ #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 45b6b5f..7dcb55a 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -113,24 +113,24 @@ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #if defined(CONFIG_DDR_II) #define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 #define CONFIG_SYS_DDR_MODE 0x47d00432 #define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) -#define CONFIG_SYS_DDR_TIMING_1 0x36332321 -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ +#define CONFIG_SYS_DDR_TIMING_1 0x36332321 +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ +#define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ #if defined(CONFIG_DDR_32BIT) /* set burst length to 8 for 32-bit data path */ @@ -143,12 +143,6 @@ #endif /* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - -/* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ @@ -158,14 +152,21 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* flash base address */\ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -185,11 +186,21 @@ /* * BCSR register on local bus 32KB, 8-bit wide for MDS config reg */ -#define CONFIG_SYS_BCSR 0xE2400000 +#define CONFIG_SYS_BCSR 0xE2400000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port-size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE8F0 /* length 32K */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)/* Access window size 32K */ +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0x00000801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_CLEAR \ + | OR_GPCM_EHTR_CLEAR) + /* 0xFFFFE8F0 */ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ @@ -209,7 +220,7 @@ */ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 -#define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_SYS_LBC_LBCR 0x00000000 /* * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. @@ -217,6 +228,12 @@ */ #undef CONFIG_SYS_LB_SDRAM +/* + * SDRAM on the Local Bus + */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ + #ifdef CONFIG_SYS_LB_SDRAM /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ /* @@ -232,14 +249,15 @@ * * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. */ -#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ + | BR_PS_32 /* Port-size = 32bit */ \ + | BR_MS_SDRAM /* MSEL = SDRAM */ \ + | BR_V) /* Valid */ + /* 0xF0001861 */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -255,7 +273,12 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 */ -#define CONFIG_SYS_OR2_PRELIM 0xFC006901 +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ + | OR_SDRAM_XAM \ + | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ + | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ + | OR_SDRAM_EAD) + /* 0xFC006901 */ #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ @@ -611,14 +634,14 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI @ 0x80000000 */ #ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT1L (0) @@ -628,9 +651,9 @@ #endif #ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT3L (0) @@ -640,11 +663,11 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index de233ff..e32ab1c 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -227,7 +227,6 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ -#define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ /* Vitesse 7385 */ @@ -248,12 +247,12 @@ boards, we say we have two, but don't display a message if we find only one. */ /* Flash */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | OR_UPM_XAM | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_16MB) /* Vitesse 7385 */ @@ -261,10 +260,10 @@ boards, we say we have two, but don't display a message if we find only one. */ #ifdef CONFIG_VSC7385_ENET -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ - OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ - OR_GPCM_EHTR | OR_GPCM_EAD) + OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) @@ -274,10 +273,10 @@ boards, we say we have two, but don't display a message if we find only one. */ /* LED */ #define CONFIG_SYS_LED_BASE 0xF9000000 -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ - OR_GPCM_EHTR | OR_GPCM_EAD) + OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_SET | OR_GPCM_EAD) /* Compact Flash */ @@ -606,14 +605,14 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI */ #ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT1L 0 @@ -623,9 +622,9 @@ boards, we say we have two, but don't display a message if we find only one. */ #endif #ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT3L 0 @@ -635,11 +634,11 @@ boards, we say we have two, but don't display a message if we find only one. */ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 49d64a5..b275486 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -106,7 +106,7 @@ #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */ #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) + DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) #define CONFIG_SYS_83XX_DDR_USES_CS0 @@ -131,25 +131,25 @@ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ #if defined(CONFIG_DDR_II) #define CONFIG_SYS_DDRCDR 0x80080001 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG 0x80330102 -#define CONFIG_SYS_DDR_TIMING_0 0x00220802 -#define CONFIG_SYS_DDR_TIMING_1 0x38357322 -#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00220802 +#define CONFIG_SYS_DDR_TIMING_1 0x38357322 +#define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 #define CONFIG_SYS_DDR_MODE 0x47d00432 #define CONFIG_SYS_DDR_MODE2 0x8000c000 -#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 +#define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 #else -#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) -#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ -#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9) +#define CONFIG_SYS_DDR_TIMING_1 0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */ +#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* may need tuning */ #define CONFIG_SYS_DDR_CONTROL 0x42008000 /* Self refresh,2T timing */ #define CONFIG_SYS_DDR_MODE 0x20000162 /* DLL,normal,seq,4/2.5 */ -#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ +#define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* page mode */ #endif #endif @@ -195,21 +195,22 @@ * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ -#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | OR_GPCM_XAM | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) + OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -219,24 +220,38 @@ /* * BCSR on the Local Bus */ -#define CONFIG_SYS_BCSR 0xF8000000 +#define CONFIG_SYS_BCSR 0xF8000000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000F /* Access window size 64K */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) + +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFFFFE9F7 */ /* * SDRAM on the Local Bus */ +/* [RFC]Given this base address, there is no BAT covering LBC_SDRAM */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* SDRAM base address */ #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ #define CONFIG_SYS_LB_SDRAM /* if board has SRDAM on local bus */ #ifdef CONFIG_SYS_LB_SDRAM -#define CONFIG_SYS_LBLAWBAR2 0 -#define CONFIG_SYS_LBLAWAR2 0x80000019 /* 64MB */ +/* [RFC]This used to be CONFIG_SYS_LBLAWBAR2 */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE /* [RFC]This was 0 before, overlapping DDR */ +/* [RFC]This used to be CONFIG_SYS_LBLAWAR2 */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */ /* @@ -253,7 +268,12 @@ * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861 */ -#define CONFIG_SYS_BR2 0x00001861 /*Port size=32bit, MSEL=SDRAM */ +/* [RFC]This used to be CONFIG_SYS_BR2 */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE /* [RFC]This was 0 before, overlapping DDR */ \ + | BR_PS_32 \ + | BR_MS_SDRAM \ + | BR_V) + /* 0xF0001861 */ /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -269,7 +289,13 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901 */ -#define CONFIG_SYS_OR2 0xfc006901 +/* [RFC]This used to be CONFIG_SYS_OR2 */ +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ + | OR_SDRAM_XAM \ + | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ + | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ + | OR_SDRAM_EAD) + /* 0xFC006901 */ #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ @@ -288,22 +314,50 @@ #endif /* - * Windows to access PIB via local bus + * Windows to access Platform I/O Boards (PIB) via local bus */ -#define CONFIG_SYS_LBLAWBAR3_PRELIM 0xf8010000 /* windows base 0xf8010000 */ -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000e /* windows size 32KB */ +#define CONFIG_SYS_PIB_BASE 0xF8008000 +#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024) + +/* [RFC]Previously, this LBLAW only covered the 2nd window (CS5) */ +#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE /* windows base */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) /* * CS4 on Local Bus, to PIB */ -#define CONFIG_SYS_BR4_PRELIM 0xf8008801 /* CS4 base address at 0xf8008000 */ -#define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ +#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_PIB_BASE \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF8008801 */ /* CS4 base address at 0xf8008000 */ +#define CONFIG_SYS_OR4_PRELIM (OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffffe9f7 */ /* * CS5 on Local Bus, to PIB */ -#define CONFIG_SYS_BR5_PRELIM 0xf8010801 /* CS5 base address at 0xf8010000 */ -#define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 /* size 32KB, port size 8bit, GPCM */ +#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_PIB_BASE + CONFIG_SYS_PIB_WINDOW_SIZE) \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF8010801 */ /* CS5 base address at 0xf8010000 */ +#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PIB_BASE \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffffe9f7 */ /* * Serial Port @@ -508,52 +562,52 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR/LBC SDRAM: cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* DDR/LBC SDRAM next 256M: cacheable */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM_BASE2 | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 851872a..9eea9c0 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -96,7 +96,10 @@ /* * DDRCDR - DDR Control Driver Register */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x80080001 */ #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ @@ -105,14 +108,15 @@ */ #define CONFIG_DDR_II #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | \ - CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS) + CSCONFIG_COL_BIT_10 | \ + CSCONFIG_ODT_WR_ONLY_CURRENT) #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 | SDRAM_CFG_ECC_EN) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 -#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) -#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ - (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) +#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) +#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \ + (1115 << SDRAM_INTERVAL_REFINT_SHIFT)) #define CONFIG_SYS_DDR_MODE 0x47800432 #define CONFIG_SYS_DDR_MODE2 0x8000c000 @@ -190,15 +194,16 @@ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ - OR_GPCM_XACS | OR_GPCM_SCY_15 | \ - OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ + OR_GPCM_XACS | OR_GPCM_SCY_15 | \ + OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -215,11 +220,17 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ +/* [RFC]Comment said 4KB window; code said 256MB window; OR1 says 64MB... what's correct? */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) /* Port size 8 bit, UPMA */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | 0x00000881) -#define CONFIG_SYS_OR1_PRELIM 0xfc000001 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ + | BR_PS_8 \ + | BR_MS_UPMA \ + | BR_V) + /* 0x60000881 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD) + /* 0xFC000001 */ /* * Fujitsu MB86277 (MINT) graphics controller @@ -227,11 +238,16 @@ #define CONFIG_SYS_VIDEO_BASE 0x70000000 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* Port size 32 bit, UPMB */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1) /* PS=11, UPMB */ -#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \ + | BR_PS_32 \ + | BR_MS_UPMB \ + | BR_V) + /* 0x000018a1 */ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD) + /* 0xFC000001 */ /* * Serial Port @@ -423,39 +439,39 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE | BATL_PP_RW | BATL_CACHEINHIBIT |\ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE | BATU_BL_64M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE | BATU_BL_64M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L @@ -463,12 +479,12 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index abccfd6..9529ccd 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -128,7 +128,8 @@ #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_83XX_DDR_USES_CS0 -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) + /* 0x80080001 */ /* ODT 150ohm on SoC */ #undef CONFIG_DDR_ECC /* support DDR ECC function */ #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ @@ -147,7 +148,8 @@ #define CONFIG_SYS_DDR_SIZE 512 /* MB */ #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f #define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ - | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \ + | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \ | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) /* 0x80010202 */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 @@ -223,34 +225,35 @@ */ #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 -#define CONFIG_SYS_LBC_LBCR 0x00000000 +#define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_FSL_ELBC 1 /* * FLASH on the Local Bus */ #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ - | (2 << BR_PS_SHIFT) /* 16 bit port size */ \ - | BR_V ) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ - | OR_UPM_XAM \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV2 \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD ) - /* 0xFE000FF7 */ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V ) /* valid */ +#define CONFIG_SYS_OR0_PRELIM ( MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD ) + /* 0xFE000FF7 */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -262,39 +265,51 @@ /* * BCSR on the Local Bus */ -#define CONFIG_SYS_BCSR 0xF8000000 +#define CONFIG_SYS_BCSR 0xF8000000 #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ - -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ -#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_BCSR \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V ) + /* 0xF8000801 */ +#define CONFIG_SYS_OR1_PRELIM ( OR_AM_32KB \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD ) + /* 0xFFFFE9F7 */ /* * NAND Flash on the Local Bus */ -#define CONFIG_CMD_NAND 1 +#define CONFIG_CMD_NAND 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ - | BR_PS_8 /* Port Size = 8 bit */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V ) /* valid */ -#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ - | OR_FCM_BCTLD \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_RST \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR ) - /* 0xFFFF919E */ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V ) /* valid */ +#define CONFIG_SYS_OR3_PRELIM ( OR_AM_32KB \ + | OR_FCM_BCTLD \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_RST \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR ) + /* 0xFFFF919E */ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) /* * Serial Port @@ -560,51 +575,51 @@ extern int board_pci_host_broken(void); #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* BCSR: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ea3056b..3da60e7 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -165,9 +165,9 @@ * Manually set up DDR parameters */ #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ @@ -178,7 +178,6 @@ | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) - /* 0x00220802 */ /* 0x00260802 */ /* DDR400 */ #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \ @@ -188,28 +187,35 @@ | (3 << TIMING_CFG1_WRREC_SHIFT) \ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | (2 << TIMING_CFG1_WRTORD_SHIFT)) - /* 0x3935d322 */ /* 0x3937d322 */ -#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 +#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (5 << TIMING_CFG2_CPO_SHIFT) \ + | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (8 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x02984cc8 */ #define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ #if defined(CONFIG_DDR_2T_TIMING) -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \ - | SDRAM_CFG_2T_EN \ - | SDRAM_CFG_DBW_32) +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE \ + | SDRAM_CFG_2T_EN) + /* 0x43088000 */ #else -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT) - /* 0x43000000 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2) + /* 0x43000000 */ #endif #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ - | (0x0442 << SDRAM_MODE_SD_SHIFT)) - /* 0x04400442 */ /* DDR400 */ + | (0x0442 << SDRAM_MODE_SD_SHIFT)) + /* 0x04400442 */ /* DDR400 */ #define CONFIG_SYS_DDR_MODE2 0x00000000 /* @@ -264,15 +270,17 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD) - /* 0xFF806FF7 TODO SLOW 8 MB flash size */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ + | BR_PS_16 /* 16 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_9 \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFF800191 */ +/* [RFC]Old comment: 0xFF806FF7 TODO SLOW 8 MB flash size */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -285,20 +293,20 @@ * NAND Flash on the Local Bus */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \ - (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ - BR_PS_8 | /* Port Size = 8 bit */ \ - BR_MS_FCM | /* MSEL = FCM */ \ - BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \ - OR_FCM_CSCT | \ - OR_FCM_CST | \ - OR_FCM_CHT | \ - OR_FCM_SCY_1 | \ - OR_FCM_TRLX | \ - OR_FCM_EHTR) +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ + | BR_PS_8 /* Port Size = 8 bit */ \ + | BR_MS_FCM /* MSEL = FCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ + | OR_FCM_CSCT \ + | OR_FCM_CST \ + | OR_FCM_CHT \ + | OR_FCM_SCY_1 \ + | OR_FCM_TRLX \ + | OR_FCM_EHTR) #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) /* Vitesse 7385 */ @@ -306,10 +314,22 @@ #ifdef CONFIG_VSC7385_ENET -#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */ -#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ + | BR_PS_8 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF0000801 */ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ + | OR_GPCM_CSNT \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_SETA \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xfffe09ff */ /* 128K bytes*/ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */ -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) #endif @@ -569,51 +589,51 @@ #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* L2 Switch: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index c201310..6c1d6e3 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -72,7 +72,10 @@ #define CONFIG_SYS_MEMTEST_END (70<<20) #define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDRCDR 0x22000001 +#define CONFIG_SYS_DDRCDR (DDRCDR_PZ_HIZ \ + | DDRCDR_NZ_HIZ \ + | DDRCDR_Q_DRN) + /* 0x22000001 */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 #define CONFIG_SYS_DDR_SIZE 512 @@ -100,20 +103,19 @@ #define CONFIG_SYS_FLASH_BASE 0xFF800000 #define CONFIG_SYS_FLASH_SIZE 8 -#define CONFIG_SYS_FLASH_SIZE_SHIFT 3 #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 256 -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ - OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\ - OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \ - OR_GPCM_EAD) +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | OR_UPM_XAM | \ + OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \ + OR_GPCM_SCY_15 | OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET | \ + OR_GPCM_EAD) #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) /* * U-Boot memory configuration @@ -334,13 +336,13 @@ #define CONFIG_HIGH_BATS 1 /* DDR */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT |\ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) @@ -351,12 +353,12 @@ #define CONFIG_SYS_IBAT4U 0 /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT7L 0 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 339e02b..e731574 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -148,25 +148,25 @@ #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ - | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ + | BR_DECC_CHK_GEN /* Use HW ECC */ \ | BR_PS_8 /* Port Size = 8 bit */ \ | BR_MS_FCM /* MSEL = FCM */ \ | BR_V ) /* valid */ #ifdef CONFIG_NAND_SP -#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM ( OR_AM_32KB \ | OR_FCM_CSCT \ | OR_FCM_CST \ | OR_FCM_CHT \ | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR ) -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000000E /* 32KB */ -#define CONFIG_SYS_NAND_PAGE_SIZE (512) /* NAND chip page size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) +#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ #define NAND_CACHE_PAGES 32 #elif defined(CONFIG_NAND_LP) -#define CONFIG_SYS_NAND_OR_PRELIM ( 0xFFFC0000 /* length 256K */ \ +#define CONFIG_SYS_NAND_OR_PRELIM ( OR_AM_256KB \ | OR_FCM_PGS \ | OR_FCM_CSCT \ | OR_FCM_CST \ @@ -174,8 +174,8 @@ | OR_FCM_SCY_1 \ | OR_FCM_TRLX \ | OR_FCM_EHTR ) -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000011 /* 256KB */ -#define CONFIG_SYS_NAND_PAGE_SIZE (2048) /* NAND chip page size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */ #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */ #define NAND_CACHE_PAGES 64 #else @@ -439,15 +439,15 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_10) +#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATL_PP_RW) #define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI2 not supported on 8313 */ @@ -455,11 +455,11 @@ #define CONFIG_SYS_IBAT4U (0) /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT7L (0) diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 5cd517d..dd2b50e 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -114,11 +114,11 @@ #define CONFIG_SYS_OR_TIMING_FLASH (OR_GPCM_CSNT | OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_5 | OR_GPCM_TRLX) -#define CONFIG_SYS_PRELIM_OR_AM 0xc0000000 /* OR addr mask: 1 GiB */ +#define CONFIG_SYS_PRELIM_OR_AM OR_AM_1GB /* OR addr mask: 1 GiB */ #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001D /* 1 GiB window size (2^(size + 1)) */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_1GB ) #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ @@ -408,22 +408,22 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR 0 - 512M */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATU_BL_256M | BATU_VS | BATU_VP) /* stack in DCACHE @ 512M (no backing mem) */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) /* PCI */ #ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | BATL_MEMCOHERENCE | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_IO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_IO_BASE | BATU_BL_16M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT3L (0) @@ -435,11 +435,11 @@ #endif /* IMMRBAR */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_IMMR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_IMMR | BATU_BL_1M | BATU_VS | BATU_VP) /* FLASH */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h index 2b1a84a..0a4e4a4 100644 --- a/include/configs/km/km83xx-common.h +++ b/include/configs/km/km83xx-common.h @@ -103,16 +103,17 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001b /* 256MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_5 | \ - OR_GPCM_TRLX | OR_GPCM_EAD) + OR_GPCM_TRLX_SET | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ @@ -123,15 +124,16 @@ */ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_KMBEC_FPGA_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001A /* 128MB window size */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_KMBEC_FPGA_BASE | \ - (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) #define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | OR_GPCM_EAD) + OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * Serial Port @@ -242,7 +244,7 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) @@ -250,7 +252,7 @@ #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR & PCI IO: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \ | BATU_VP) @@ -258,25 +260,25 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* PRIO1, PIGGY: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index 8639ddd..c44258e 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -72,9 +72,10 @@ #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \ CSCONFIG_ROW_BIT_13 | \ CSCONFIG_COL_BIT_10 | \ - CSCONFIG_ODT_WR_ACS) + CSCONFIG_ODT_WR_ONLY_CURRENT) -#define CONFIG_SYS_DDRCDR 0x40000001 +#define CONFIG_SYS_DDRCDR (DDRCDR_EN | DDRCDR_Q_DRN) + /* 0x40000001 */ #define CONFIG_SYS_DDR_MODE 0x47860452 #define CONFIG_SYS_DDR_MODE2 0x8080c000 @@ -136,37 +137,38 @@ * PAXE on the local bus CS3 */ #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE -#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */ +#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_512MB) #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PAXE_BASE | \ - (1 << BR_PS_SHIFT) | /* 8 bit port size */ \ + BR_PS_8 | /* 8 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ BR_V) #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ OR_GPCM_SCY_2 | \ - OR_GPCM_TRLX | OR_GPCM_EAD) + OR_GPCM_TRLX_SET | OR_GPCM_EAD) /* * MMU Setup */ /* PAXE: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ -#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CFG_IBAT6L (CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE) #define CFG_IBAT6U (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_DBAT6L CFG_IBAT6L #define CFG_DBAT6U CFG_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \ +#define CFG_IBAT7L (CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CFG_IBAT7U (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) #define CFG_DBAT7L CFG_IBAT7L diff --git a/include/configs/kmsupx5.h b/include/configs/kmsupx5.h index f8cd8e0..b0dd88c 100644 --- a/include/configs/kmsupx5.h +++ b/include/configs/kmsupx5.h @@ -69,16 +69,16 @@ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ - (OR_GPCM_TRLX & \ - (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) /* LPXF: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h index d7a3a96..c3d49fa 100644 --- a/include/configs/mpc8308_p1m.h +++ b/include/configs/mpc8308_p1m.h @@ -155,11 +155,13 @@ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ - | 0x00010000 /* ODT_WR to CSn */ \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) - /* 0x80010102 */ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ONLY_CURRENT \ + | CSCONFIG_ROW_BIT_13 \ + | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ | (0 << TIMING_CFG0_WRT_SHIFT) \ @@ -192,7 +194,7 @@ /* 0x03600100 */ #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE) + | SDRAM_CFG_DBW_32) /* 0x43080000 */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ @@ -248,17 +250,18 @@ #define CONFIG_SYS_BR0_PRELIM (\ CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ - (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ + BR_PS_16 /* 16 bit port size */ |\ + BR_MS_GPCM /* MSEL = GPCM */ |\ BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_4 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ - | OR_GPCM_EAD) + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + /* [RFC]Reserved on mpc8308: | OR_GPCM_EAD */) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -273,11 +276,12 @@ */ #define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 #define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_SJA1000_BASE \ - | (1 << BR_PS_SHIFT) /* 8 bit port size */ \ + | BR_PS_8 /* 8 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_OR1_PRELIM ( OR_AM_32KB \ | OR_GPCM_SCY_5 \ - | OR_GPCM_EHTR) + | OR_GPCM_EHTR_SET) /* 0xFFFF8052 */ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE @@ -288,11 +292,12 @@ */ #define CONFIG_SYS_CPLD_BASE 0xFBFF8000 #define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \ - | (1 << BR_PS_SHIFT) /* 8 bit port size */ \ + | BR_PS_8 /* 8 bit port size */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ | BR_V ) /* valid */ -#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K */ \ +#define CONFIG_SYS_OR2_PRELIM ( OR_AM_32KB \ | OR_GPCM_SCY_4 \ - | OR_GPCM_EHTR) + | OR_GPCM_EHTR_SET) /* 0xFFFF8042 */ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE @@ -456,7 +461,7 @@ */ /* DDR: cache cacheable */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ BATU_VS | BATU_VP) @@ -464,7 +469,7 @@ #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ BATU_VP) @@ -472,17 +477,17 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index b418cf2..db9340f 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -132,8 +132,9 @@ /* * SDRAM on the Local Bus */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0x10000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */ +/* [RFC]Changed to match code */ +#define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ /* * FLASH on the Local Bus @@ -144,13 +145,23 @@ #define CONFIG_SYS_FLASH_SIZE 8 /* flash size in MB */ /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* flash Base address */ \ - (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM 0xFF806FF7 /* 8 MB flash size */ +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ + BR_PS_16 | /* 16 bit port size */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) /* valid */ + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xFF806FF7 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* window base at flash base */ -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */ @@ -204,14 +215,15 @@ * * 0 4 8 12 16 20 24 28 * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 - * - * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into - * FIXME: the top 17 bits of BR2. */ -#define CONFIG_SYS_BR2_PRELIM 0xF0001861 /* Port-size=32bit, MSEL=SDRAM */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM 0xF0000000 -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* 64M */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ + | BR_PS_32 \ + | BR_MS_SDRAM \ + | BR_V) + /* 0xF0001861 */ +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. @@ -227,7 +239,12 @@ * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 */ -#define CONFIG_SYS_OR2_PRELIM 0xFC006901 +#define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_LBC_SDRAM_SIZE) \ + | OR_SDRAM_XAM \ + | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ + | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ + | OR_SDRAM_EAD) + /* 0xFC006901 */ #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ @@ -541,14 +558,14 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) /* PCI @ 0x80000000 */ #ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT1L (0) @@ -558,9 +575,9 @@ #endif #ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #else #define CONFIG_SYS_IBAT3L (0) @@ -570,13 +587,13 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) -/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ +/* LBC SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_LBC_SDRAM_BASE | BATL_PP_RW | BATL_MEMCOHERENCE | \ BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) +#define CONFIG_SYS_IBAT6U (CONFIG_SYS_LBC_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT7L (0) #define CONFIG_SYS_IBAT7U (0) diff --git a/include/configs/suvd3.h b/include/configs/suvd3.h index 0b59d51..ae19701 100644 --- a/include/configs/suvd3.h +++ b/include/configs/suvd3.h @@ -70,7 +70,7 @@ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_3 | \ - OR_GPCM_TRLX) + OR_GPCM_TRLX_SET) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ @@ -85,19 +85,19 @@ /* APP1: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U diff --git a/include/configs/tuda1.h b/include/configs/tuda1.h index 853c00a..577bbd0 100644 --- a/include/configs/tuda1.h +++ b/include/configs/tuda1.h @@ -73,8 +73,8 @@ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ - (OR_GPCM_TRLX & \ - (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) /* * PINC3 on the local bus CS3 @@ -91,11 +91,10 @@ #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ OR_GPCM_CSNT | \ - (OR_GPCM_ACS_DIV2 & /* ACS = 11 */\ - (~OR_GPCM_XACS)) | /* XACS = 0 */\ - (OR_GPCM_SCY_2 & \ - (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ - OR_GPCM_TRLX) + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ @@ -106,7 +105,7 @@ */ /* PAXG: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_MEMCOHERENCE) /* 512M should also include APP2... */ #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | \ @@ -114,21 +113,21 @@ BATU_VS | \ BATU_VP) #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* PINC3: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | \ BATU_BL_256M | \ BATU_VS | \ BATU_VP) #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | \ - BATL_PP_10 | \ + BATL_PP_RW | \ BATL_CACHEINHIBIT | \ BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U diff --git a/include/configs/tuxa1.h b/include/configs/tuxa1.h index ceeb5a3..36eaf4e 100644 --- a/include/configs/tuxa1.h +++ b/include/configs/tuxa1.h @@ -58,7 +58,7 @@ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LPXF_BASE #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LPXF_BASE | \ BR_PS_8 | \ BR_MS_GPCM | \ BR_V) @@ -67,8 +67,8 @@ OR_GPCM_CSNT | \ OR_GPCM_ACS_DIV4 | \ OR_GPCM_SCY_2 | \ - (OR_GPCM_TRLX & \ - (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR | \ OR_GPCM_EAD) /* * PINC2 on the local bus CS3 @@ -85,11 +85,10 @@ #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_PINC2_SIZE) | \ OR_GPCM_CSNT | \ - (OR_GPCM_ACS_DIV2 & /* ACS = 11 */ \ - (~OR_GPCM_XACS)) | /* XACS = 0 */ \ - (OR_GPCM_SCY_2 & \ - (~OR_GPCM_EHTR)) | /* EHTR = 0 */ \ - OR_GPCM_TRLX) + OR_GPCM_ACS_DIV2 | \ + OR_GPCM_SCY_2 | \ + OR_GPCM_TRLX_SET | \ + OR_GPCM_EHTR_CLEAR) #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ 0x0000c000 | \ @@ -99,20 +98,20 @@ * MMU Setup */ /* LPXF: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_LPXF_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT5L (CONFIG_SYS_LPXF_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* PINC2: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PINC2_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT6L (CONFIG_SYS_PINC2_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index abb57fe..23e811a 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -80,10 +80,11 @@ */ #define CONFIG_SYS_DDR_SIZE 128 /* MB */ #define CONFIG_SYS_DDR_CONFIG ( CSCONFIG_EN \ - | CSCONFIG_AP \ - | 0x00040000 /* TODO */ \ - | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) - /* 0x80840102 */ + | CSCONFIG_AP \ + | CSCONFIG_ODT_RD_NEVER \ + | CSCONFIG_ODT_WR_ALL \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) + /* 0x80840102 */ #define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ @@ -117,7 +118,7 @@ /* 0x03202000 */ #define CONFIG_SYS_SDRAM_CFG ( SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE ) + | SDRAM_CFG_DBW_32 ) /* 0x43080000 */ #define CONFIG_SYS_SDRAM_CFG2 0x00401000 #define CONFIG_SYS_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ @@ -144,18 +145,19 @@ #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ #define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 16 bit */ \ - BR_V) /* valid */ + BR_PS_16 | /* 16 bit */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) /* valid */ #define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_CSNT \ - | OR_GPCM_ACS_DIV4 \ - | OR_GPCM_SCY_5 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EAD) - /* 0xfe000c55 */ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV4 \ + | OR_GPCM_SCY_5 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EAD) + /* 0xfe000c55 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per dev */ @@ -202,18 +204,18 @@ #define CONFIG_SYS_NAND_BLOCK_SIZE 16384 #define CONFIG_SYS_NAND_BR_PRELIM ( CONFIG_SYS_NAND_BASE \ - | BR_PS_8 \ - | BR_DECC_CHK_GEN \ - | BR_MS_FCM \ - | BR_V ) /* valid */ - /* 0x61000c21 */ -#define CONFIG_SYS_NAND_OR_PRELIM (0xffff8000 \ - | OR_FCM_BCTLD \ - | OR_FCM_CHT \ - | OR_FCM_SCY_2 \ - | OR_FCM_RST \ - | OR_FCM_TRLX) - /* 0xffff90ac */ + | BR_PS_8 \ + | BR_DECC_CHK_GEN \ + | BR_MS_FCM \ + | BR_V ) /* valid */ + /* 0x61000c21 */ +#define CONFIG_SYS_NAND_OR_PRELIM ( OR_AM_32KB \ + | OR_FCM_BCTLD \ + | OR_FCM_CHT \ + | OR_FCM_SCY_2 \ + | OR_FCM_RST \ + | OR_FCM_TRLX) + /* 0xffff90ac */ #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM @@ -221,7 +223,7 @@ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM #define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM @@ -231,12 +233,12 @@ | BR_PS_8 \ | BR_V) /* 0x60000801 */ -#define CONFIG_SYS_OR2_PRELIM (0xfffe0000 \ +#define CONFIG_SYS_OR2_PRELIM ( OR_AM_128KB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_3 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xfffe0937 */ /* local bus read write buffer mapping SRAM@0x64000000 */ @@ -245,12 +247,12 @@ | BR_V) /* 0x62001001 */ -#define CONFIG_SYS_OR3_PRELIM (0xfe000000 \ +#define CONFIG_SYS_OR3_PRELIM ( OR_AM_32MB \ | OR_GPCM_CSNT \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) /* 0xfe0009f7 */ @@ -421,16 +423,16 @@ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) #if defined(CONFIG_PCI) /* PCI @ 0x80000000 */ -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10) +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) @@ -448,17 +450,17 @@ #define CONFIG_SYS_IBAT4U (0) /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | \ BATU_VP) /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) /* FPGA, SRAM, NAND @ 0x60000000 */ -#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT7L (0x60000000 | BATL_PP_RW | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (0x60000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index d153762..f6a47f3 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -109,7 +109,8 @@ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) #define CONFIG_DDR_2T_TIMING -#define CONFIG_SYS_DDRCDR 0x80080001 +#define CONFIG_SYS_DDRCDR (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) + /* 0x80080001 */ /* * FLASH on the Local Bus @@ -120,29 +121,57 @@ #define CONFIG_SYS_FLASH_BASE 0xffc00000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 4 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 16bit */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM 0xffc06ff7 /* 4 MB flash size */ + BR_PS_16 | /* 16bit */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) /* valid */ + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xffc06ff7 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000015 /* 4 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_4MB) #else #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */ #define CONFIG_SYS_FLASH_SIZE 128 /* flash size in MB */ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \ - (2 << BR_PS_SHIFT) | /* 16bit */ \ - BR_V) /* valid */ - -#define CONFIG_SYS_OR0_PRELIM 0xf8006ff7 /* 128 MB flash size */ + BR_PS_16 | /* 16bit */ \ + BR_MS_GPCM | /* MSEL = GPCM */ \ + BR_V) /* valid */ + +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ + | OR_GPCM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_15 \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ + | OR_GPCM_EAD) + /* 0xf8006ff7 */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x8000001a /* 128 MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_128MB) #endif /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ -#define CONFIG_SYS_BR1_PRELIM (0xf0000000 | 0x00001801) -#define CONFIG_SYS_OR1_PRELIM (0xfffc0008 | 0x00000200) -#define CONFIG_SYS_LBLAWBAR1_PRELIM 0xf0000000 -#define CONFIG_SYS_LBLAWAR1_PRELIM (0x80000000 | 0x00000011) +#define CONFIG_SYS_WINDOW1_BASE 0xf0000000 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_WINDOW1_BASE \ + | BR_PS_32 \ + | BR_MS_GPCM \ + | BR_V) + /* 0xF0001801 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_256KB \ + | 0x00000200 /* [RFC]Reserved ACS value on MPC8349 */ \ + | OR_GPCM_SETA) + /* 0xfffc0208 */ +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_WINDOW1_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256KB) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device*/ @@ -465,18 +494,18 @@ #define CONFIG_HIGH_BATS /* High BATs supported */ /* DDR @ 0x00000000 */ -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) /* PCI @ 0x80000000 */ #ifdef CONFIG_PCI -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) @@ -488,11 +517,11 @@ #endif #ifdef CONFIG_MPC83XX_PCI2 -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_RW | \ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | \ BATU_VS | BATU_VP) @@ -504,17 +533,17 @@ #endif /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | \ BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #if (CONFIG_SYS_DDR_SIZE == 512) #define CONFIG_SYS_IBAT7L (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ - BATL_PP_10 | BATL_MEMCOHERENCE) + BATL_PP_RW | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_SDRAM_BASE+0x10000000 | \ BATU_BL_256M | BATU_VS | BATU_VP) #else diff --git a/include/mpc83xx.h b/include/mpc83xx.h index 8292018..15ef487 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -905,9 +905,29 @@ */ #define CSCONFIG_EN 0x80000000 #define CSCONFIG_AP 0x00800000 -#define CSCONFIG_ODT_WR_ACS 0x00010000 -#if defined(CONFIG_MPC832x) +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#define CSCONFIG_ODT_RD_NEVER 0x00000000 +#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 +#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 +#define CSCONFIG_ODT_RD_ALL 0x00400000 +#define CSCONFIG_ODT_WR_NEVER 0x00000000 +#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 +#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 +#define CSCONFIG_ODT_WR_ALL 0x00040000 +#elif defined(CONFIG_MPC832x) +#define CSCONFIG_ODT_RD_CFG 0x00400000 #define CSCONFIG_ODT_WR_CFG 0x00040000 +#elif defined(CONFIG_MPC8360) || defined(CONFIG_MPC837x) +#define CSCONFIG_ODT_RD_NEVER 0x00000000 +#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000 +#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000 +#define CSCONFIG_ODT_RD_ONLY_OTHER_DIMM 0x00300000 +#define CSCONFIG_ODT_RD_ALL 0x00400000 +#define CSCONFIG_ODT_WR_NEVER 0x00000000 +#define CSCONFIG_ODT_WR_ONLY_CURRENT 0x00010000 +#define CSCONFIG_ODT_WR_ONLY_OTHER_CS 0x00020000 +#define CSCONFIG_ODT_WR_ONLY_OTHER_DIMM 0x00030000 +#define CSCONFIG_ODT_WR_ALL 0x00040000 #endif #define CSCONFIG_BANK_BIT_3 0x00004000 #define CSCONFIG_ROW_BIT 0x00000700 @@ -996,8 +1016,16 @@ #define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000 #define SDRAM_CFG_SDRAM_TYPE_SHIFT 24 #define SDRAM_CFG_DYN_PWR 0x00200000 +#if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) +#define SDRAM_CFG_DBW_MASK 0x00180000 +#define SDRAM_CFG_DBW_16 0x00100000 +#define SDRAM_CFG_DBW_32 0x00080000 +#else #define SDRAM_CFG_32_BE 0x00080000 +#endif +#if !defined(CONFIG_MPC8308) #define SDRAM_CFG_8_BE 0x00040000 +#endif #define SDRAM_CFG_NCAP 0x00020000 #define SDRAM_CFG_2T_EN 0x00008000 #define SDRAM_CFG_HSE 0x00000008 -- 1.6.0.2

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Re: [U-Boot] SPL support and secondary image size
by jonsmirl＠gmail.com 04 Nov '11

04 Nov '11

On Thu, Nov 3, 2011 at 7:08 PM, jonsmirl(a)gmail.com <jonsmirl(a)gmail.com> wrote: > On Thu, Nov 3, 2011 at 7:00 PM, Scott Wood <scottwood(a)freescale.com> wrote: >> On 11/03/2011 05:20 PM, jonsmirl(a)gmail.com wrote: >>> My primary SPL image needs the size of the secondary image built into >>> it. How do I access that size while building the primary SPL image? >> >> Does it need to be exact? Usually we just hardcode something that >> should be big enough. > > NXP has written custom out of tree support for SPL on the lpc3130/31. > I am reworking it to use the in-tree SPL code. lpc3130 supports six > boot modes but I have 64K of SRAM to work with. One of those modes is > to read the next image over the serial line, the existing NXP code > wants to know the length to read. > > http://git.lpclinux.com/?p=uboot-2009.11-lpc313x.git;a=summary > > The way they implemented SPL was to build it and main uboot into a > single image file. Then they used dd to cut it into two pieces. > Building it as a single image allows the initial loader to get at > things like the length of the second image. > > I will have to go through all of their code to see if the length > require is exact. > > >> >> -Scott >> >> > > > > -- > Jon Smirl > jonsmirl(a)gmail.com > -- Jon Smirl jonsmirl(a)gmail.com

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Re: [U-Boot] [PATCH v3 1/3] ids8313: add support for IDS8313 boards
by Kim Phillips 03 Nov '11

03 Nov '11

On Tue, 27 Sep 2011 13:56:32 +0200 <Sergej.Stepanov(a)ids.de> wrote: > The patch adds support for IDS8313 boards based on MPC8313 > It contains the following components: > - both of TSEC's, NOR- and NAND flash, I2C, SPI > > Signed-off-by: Sergej Stepanov <ste(a)ids.de> > Signed-off-by: Rolf Riehle <rl(a)ids.de> > Signed-off-by: Heiko Schocher <hs(a)denx.de> > Cc: Kim Phillips <kim.phillips(a)freescale.com> > --- > Changes to v2: > format issues are fixed > split into the patchset > Changes to v3: > add missing MAINTAINERS entry 3 out of 3 patches squashed and applied. Thanks, Kim

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