November 2011 - U-Boot

[U-Boot] [PATCH] ARM: dig297: Define MACH_TYPE_OMAP3_CPS for DIG297 board
by Luca Ceresoli 04 Nov '11

04 Nov '11

This was dropped in the latest mach-types sync (47af6f61bcd9) because it is not mainlined in Linux. Signed-off-by: Luca Ceresoli <luca.ceresoli(a)comelit.it> Cc: Sandeep Paulraj <s-paulraj(a)ti.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> Cc: Wolfgang Denk <wd(a)denx.de> --- include/configs/dig297.h | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/include/configs/dig297.h b/include/configs/dig297.h index 3a05c82..e1e308c 100644 --- a/include/configs/dig297.h +++ b/include/configs/dig297.h @@ -32,6 +32,13 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include <asm/mach-types.h> +#ifdef MACH_TYPE_OMAP3_CPS +#error "MACH_TYPE_OMAP3_CPS has been defined properly, please remove this." +#else +#define MACH_TYPE_OMAP3_CPS 2751 +#endif + /* * High Level Configuration Options */ -- 1.7.5.4

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[U-Boot] [PATCH] [X86] Add a target for running as a coreboot payload
by Gabe Black 04 Nov '11

04 Nov '11

Add a target for running u-boot as a coreboot payload in boards.cfg. Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- boards.cfg | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/boards.cfg b/boards.cfg index 604becf..cc7dd2b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -266,6 +266,7 @@ tcm-bf518 blackfin blackfin tcm-bf537 blackfin blackfin eNET x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x38040000 eNET_SRAM x86 x86 eNET - sc520 eNET:SYS_TEXT_BASE=0x19000000 +coreboot-x86 x86 x86 coreboot chromebook-x86 coreboot coreboot:SYS_TEXT_BASE=0xFC0000 sandbox sandbox sandbox sandbox sandbox - cobra5272 m68k mcf52x2 cobra5272 - idmr m68k mcf52x2 -- 1.7.3.1

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[U-Boot] HELLO
by Trish Baby 04 Nov '11

04 Nov '11

How are you today, I hope all is well with you.i get your mail in I am sorry for your concern with my Proposal for a relationship with you, but I know that it will grant my request in good faith and understanding, my name is Trish relationship with you, I would like to know more, you can send an email to my email address...SO I can send you more details about myself picture.I Including me believe we can move from here.But bear in mind that Love has no colors barrier, no educational back ground barrier, no socio-economic Barrier, religious, linguistic, the nationality or distance barrier, the only important thing is love.I waiting for your mail to my email address. With new friend Trish

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[U-Boot] Attention Honorable Beneficiary
by Dr. Sambo Namadi 04 Nov '11

04 Nov '11

>From Dr. Sambo Namadi Vice President Of Nigeria Federal Republic Of Nigeria Attention Honorable Beneficiary This is to officially notify you that we have verified your contract/Inheritances file and found out that why you have not received your payment is because you have not fulfilled the obligations that was given to you in respect of your contract/inheritance payment. Secondly, we have been informed that you are still dealing with the none officials in the bank, all your attempt to secure the release of the fund to you. We wish to advice you that such an illegal act like this have to stop if you wish to receive your payment since we have decided to bring a solution to your problem. Right now we have arranged your payment through our swift card payment center Asia pacific that is the latest instruction FROM MR. PRESIDENT,GOODLUCK EBELE JONATHAN (GCFR) PRESIDENT FEDERAL REPUBLIC OF NIGERIA AND FEDERAL MINISTRY OF FINANCE. This card center will send you an ATM card which you will use to withdraw your money in any ATM machine in any part of the world without any delay, but the maximum withdrawer is Ten thousand five hundred dollars per day, so if you like to receive your fund this way please let us know by contacting the card payment center and also send the following information to her in order to proceed immediately: 1. Full name 2. Phone and fax number 3. Address were you want them to send The ATM card to (P.O box not acceptable) 4. Your age and current occupation 5. A copy of your identification However, kindly find below the contact person: Mr. Philip Ebere Director, ATM payment department Email: philip_ebere1(a)yahoo.com.hk The ATM card payment center has been mandated to issue out (US$10, 500,000.00) Ten million five hundred thousand dollars as part payment for this fiscal year 2011. Also for your Information, you have to stop any further communication with any other person(s)or office(s) to avoid any hitches in receiving your at payment. For oral discussion, i can be reached on or email me back as soon as you receive this important message for further direction and also update me on any development from the above mentioned office. Note that because of impostors, we hereby issued you our code of Conduct, which is (ATM-9304) so you have to indicate this code when contacting the card center by using it as your subject. Best Regards, Dr. Sambo Namadi Vice President Of Nigeria Federal Republic Of Nigeria

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[U-Boot] [PATCH] AT91: pio: Add PIO3 features
by Hong Xu 04 Nov '11

04 Nov '11

This patch adds the support for new PIO controller introduced by some AT91 SoCs. New features include * More peripheral multiplexing * Pull-down, Schmitt trigger, Debouncer * More irq trigger mode (may be not interesting in U-Boot) Signed-off-by: Hong Xu <hong.xu(a)atmel.com> --- arch/arm/include/asm/arch-at91/at91_pio.h | 50 ++++++++++- drivers/gpio/at91_gpio.c | 130 +++++++++++++++++++++++++++- 2 files changed, 172 insertions(+), 8 deletions(-) diff --git a/arch/arm/include/asm/arch-at91/at91_pio.h b/arch/arm/include/asm/arch-at91/at91_pio.h index 416cabf..26e9766 100644 --- a/arch/arm/include/asm/arch-at91/at91_pio.h +++ b/arch/arm/include/asm/arch-at91/at91_pio.h @@ -4,6 +4,7 @@ * Copyright (C) 2005 Ivan Kokshaysky * Copyright (C) SAN People * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) * * Parallel I/O Controller (PIO) - System peripherals registers. * Based on AT91RM9200 datasheet revision E. @@ -17,7 +18,6 @@ #ifndef AT91_PIO_H #define AT91_PIO_H - #define AT91_ASM_PIO_RANGE 0x200 #define AT91_ASM_PIOC_ASR \ (ATMEL_BASE_PIO + AT91_PIO_PORTC * AT91_ASM_PIO_RANGE + 0x70) @@ -66,14 +66,51 @@ typedef struct at91_port { u32 puer; /* 0x64 Pull-up Enable Register */ u32 pusr; /* 0x68 Pad Pull-up Status Register */ u32 reserved4; +#if defined(ATMEL_CPU_HAS_PIO3) + u32 abcdsr1; /* 0x70 Peripheral ABCD Select Register 1 */ + u32 abcdsr2; /* 0x74 Peripheral ABCD Select Register 2 */ + u32 reserved5[2]; + u32 ifscdr; /* 0x80 Input Filter SCLK Disable Register */ + u32 ifscer; /* 0x84 Input Filter SCLK Enable Register */ + u32 ifscsr; /* 0x88 Input Filter SCLK Status Register */ + u32 scdr; /* 0x8C SCLK Divider Debouncing Register */ +#define PIO_SCDR_DIV_MASK (0x3fff << 0) /* Slow Clock Divider Mask */ + u32 ppddr; /* 0x90 Pad Pull-down Disable Register */ + u32 ppder; /* 0x94 Pad Pull-down Enable Register */ + u32 ppdsr; /* 0x98 Pad Pull-down Status Register */ + u32 reserved6; +#else u32 asr; /* 0x70 Select A Register */ u32 bsr; /* 0x74 Select B Register */ u32 absr; /* 0x78 AB Select Status Register */ u32 reserved5[9]; /* */ +#endif u32 ower; /* 0xA0 Output Write Enable Register */ u32 owdr; /* 0xA4 Output Write Disable Register */ - u32 owsr; /* OxA8 utput Write Status Register */ - u32 reserved6[85]; + u32 owsr; /* OxA8 Output Write Status Register */ +#if defined(ATMEL_CPU_HAS_PIO3) + u32 reserved7; /* */ + u32 aimer; /* Additional Interrupt Modes Enable Register*/ + u32 aimdr; /* Additional Interrupt Modes Disable Register*/ + u32 aimmr; /* Additional Intterupt Modes Mask Register */ + u32 reserved8; /* */ + u32 esr; /* 0xC0 Edge Select Register */ + u32 lsr; /* 0xC4 Level Select Register */ + u32 elsr; /* 0xC8 Edge/Level Status Register */ + u32 reserved9; /* 0xCC */ + u32 fellsr; /* 0xD0 Falling Edge/Low Level Select Register*/ + u32 rehlsr; /* 0xD4 Rising Edge/High Level Select Register*/ + u32 frlhsr; /* 0xD8 Fall/Rise - Low/High Status Register */ + u32 reserved10; /* */ + u32 locksr /* 0xE0 Lock Status */ + u32 wpmr /* 0xE4 Write Protect Mode Register */ + u32 wpsr /* 0xE4 Write Protect Status Register */ + u32 reserved11[5]; /* */ + u32 schmitt; /* 0x100 Schmitt Trigger Register */ + u32 reserved12[7]; +#else + u32 reserved6[21]; +#endif } at91_port_t; typedef union at91_pio { @@ -94,6 +131,13 @@ typedef union at91_pio { #ifdef CONFIG_AT91_GPIO int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup); int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup); +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div); +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on); +int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin); +#endif int at91_set_pio_input(unsigned port, unsigned pin, int use_pullup); int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on); int at91_set_pio_output(unsigned port, unsigned pin, int value); diff --git a/drivers/gpio/at91_gpio.c b/drivers/gpio/at91_gpio.c index be2a026..3676ba1 100644 --- a/drivers/gpio/at91_gpio.c +++ b/drivers/gpio/at91_gpio.c @@ -1,6 +1,8 @@ /* * Memory Setup stuff - taken from blob memsetup.S * + * Copyright (C) 2011 Hong Xu (hong.xu(a)atmel.com) + * * Copyright (C) 2009 Jens Scharsig (js_at_ng(a)scharsoft.de) * * Copyright (C) 2005 HP Labs @@ -58,7 +60,7 @@ int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "GPIO" peripheral role. + * mux the pin to the "GPIO" peripheral function. */ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) { @@ -75,7 +77,7 @@ int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup) } /* - * mux the pin to the "A" internal peripheral role. + * mux the pin to the "A" internal peripheral function. */ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) { @@ -86,14 +88,21 @@ int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].asr); +#endif writel(mask, &pio->port[port].pdr); } return 0; } /* - * mux the pin to the "B" internal peripheral role. + * mux the pin to the "B" internal peripheral function. */ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) { @@ -104,13 +113,120 @@ int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup) mask = 1 << pin; writel(mask, &pio->port[port].idr); at91_set_pio_pullup(port, pin, use_pullup); +#if defined(ATMEL_CPU_HAS_PIO3) + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) & ~mask, + &pio->port[port].abcdsr2); +#else writel(mask, &pio->port[port].bsr); +#endif + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +#if defined(ATMEL_CPU_HAS_PIO3) +/* + * mux the pin to the "C" internal peripheral function. + */ +int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) & ~mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); writel(mask, &pio->port[port].pdr); } return 0; } /* + * mux the pin to the "D" internal peripheral function. + */ +int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 mask; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + mask = 1 << pin; + writel(mask, &pio->port[port].idr); + at91_set_pio_pullup(port, pin, use_pullup); + writel(readl(&pio->port[port].abcdsr1) | mask, + &pio->port[port].abcdsr1); + writel(readl(&pio->port[port].abcdsr2) | mask, + &pio->port[port].abcdsr2); + writel(mask, &pio->port[port].pdr); + } + return 0; +} + +/* + * enable/disable the debounce filter. + */ +int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + if (is_on) { + writel(1 << pin, &pio->port[port].ifscer); + writel(div & PIO_SCDR_DIV_MASK, &pio->port[port].scdr); + writel(1 << pin, &pio->port[port].ifer); + } else { + writel(1 << pin, &pio->port[port].ifdr); + } + } + return 0; +} + +/* + * enable/disable the pull-down. + * If pull-up already enabled while calling the function, we disable it. + */ +int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_pulldown) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + writel(1 << pin, &pio->port[port].pudr); + if (is_pulldown) + writel(1 << pin, &pio->port[port].ppder); + else + writel(1 << pin, &pio->port[port].ppddr); + } + return 0; +} + +/* + * Set Schmitt trigger mode + */ +int at91_set_pio_schmitt_trig(unsigned port, unsigned pin, int is_enabled) +{ + at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIO; + u32 data; + + if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { + data = readl(&pio->port[port].schmitt); + if (is_enabled) + data &= ~(1 << pin); + else + data |= (1 << pin); + writel(data, &pio->port[port].schmitt); + } + return 0; +} +#endif + +/* * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and * configure it for an input. */ @@ -162,10 +278,14 @@ int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on) if ((port < ATMEL_PIO_PORTS) && (pin < 32)) { mask = 1 << pin; - if (is_on) + if (is_on) { +#if defined(ATMEL_CPU_HAS_PIO3) + writel(mask, &pio->port[port].ifscdr); +#endif writel(mask, &pio->port[port].ifer); - else + } else { writel(mask, &pio->port[port].ifdr); + } } return 0; } -- 1.7.3.3

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[U-Boot] [PATCH] mx31pdk: Enable D and I caches
by Fabio Estevam 04 Nov '11

04 Nov '11

Enable D and I caches on mx31pdk. Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Stefano, You explained that enabling cache may cause some drivers like FEC and MMC not to work properly. As mx31pdk does not have FEC or MMC driver I thought this should be OK. Tested by booting Linux kernel via TFTP and mounting a NFS rootfs. board/freescale/mx31pdk/mx31pdk.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 9f8bc53..1d7b4f6 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -71,11 +71,19 @@ int board_early_init_f(void) return 0; } +void enable_caches(void) +{ + icache_enable(); + dcache_enable(); +} + int board_init(void) { /* adress of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + enable_caches(); + return 0; } -- 1.6.0.4

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[U-Boot] Pull request for u-boot-marvell.git
by Prafulla Wadaskar 04 Nov '11

04 Nov '11

Hi Albert Please pull The following changes since commit d0a755e860362ca35c6d6e4fa8a7a0d5fc7e3ea6: Michael Walle (1): kirkwood: define CONFIG_SYS_CACHELINE_SIZE are available in the git repository at: u-boot-marvell.git master branch. Holger Brunck (4): arm/km: add boardid and hwkey to kernel command line arm/km: trigger reconfiguration for the Xilinx FPGA arm/km: enable jffs2 cmds arm/km: adapt bootcounter evaluation Lei Wen (2): pantheon: define CONFIG_SYS_CACHELINE_SIZE armada100: define CONFIG_SYS_CACHELINE_SIZE Simon Guinot (2): netspace_v2: fix SDRAM configuration netspace_v2: enable I2C EEPROM support Thomas Herzmann (1): arm/km: portl2 environment address update to P1B Valentin Longchamp (1): ARM: Reintroduce MACH_TYPE_KM_KIRKWOOD for keymile ARM boards arch/arm/include/asm/arch-armada100/config.h | 2 + arch/arm/include/asm/arch-pantheon/config.h | 2 + board/LaCie/netspace_v2/kwbimage-is2.cfg | 162 ++++++++++++++++++++++++++ board/LaCie/netspace_v2/kwbimage.cfg | 4 +- board/keymile/km_arm/km_arm.c | 44 +++++-- boards.cfg | 2 +- include/configs/km/km_arm.h | 9 +- include/configs/km_kirkwood.h | 3 + include/configs/netspace_v2.h | 18 +++- include/configs/portl2.h | 6 +- 10 files changed, 234 insertions(+), 18 deletions(-) create mode 100644 board/LaCie/netspace_v2/kwbimage-is2.cfg Regards.. Prafulla . . .

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[U-Boot] job offer for you
by jennifergates48＠yahoo.com 04 Nov '11

04 Nov '11

Hello, new job offer for you http://www.universfreeads.com/job.php?job=41264 ..

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[U-Boot] [PATCH 1/2] Powerpc/i2c: Use the same initialize codes
by Chang-Ming.Huang＠freescale.com 04 Nov '11

04 Nov '11

From: Jerry Huang <Chang-Ming.Huang(a)freescale.com> Make the I2C2 and I2C1 use the same initialize codes. Signed-off-by: Jerry Huang <Chang-Ming.Huang(a)freescale.com> --- drivers/i2c/fsl_i2c.c | 47 +++++++++++++++++++++++++---------------------- 1 files changed, 25 insertions(+), 22 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index cb13dee..258be0a 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -214,11 +214,20 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, return speed; } +unsigned int get_i2c_clock(int bus) +{ + if (bus) + return gd->i2c2_clk; /* I2C2 clock */ + else + return gd->i2c1_clk; /* I2C1 clock */ +} + void i2c_init(int speed, int slaveadd) { struct fsl_i2c *dev; unsigned int temp; + int bus_num, i; #ifdef CONFIG_SYS_I2C_INIT_BOARD /* Call board specific i2c bus reset routine before accessing the @@ -227,29 +236,23 @@ i2c_init(int speed, int slaveadd) */ i2c_init_board(); #endif - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C_OFFSET); - - writeb(0, &dev->cr); /* stop I2C controller */ - udelay(5); /* let it shutdown in peace */ - temp = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); - if (gd->flags & GD_FLG_RELOC) - i2c_bus_speed[0] = temp; - writeb(slaveadd << 1, &dev->adr); /* write slave address */ - writeb(0x0, &dev->sr); /* clear status register */ - writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ - -#ifdef CONFIG_SYS_I2C2_OFFSET - dev = (struct fsl_i2c *) (CONFIG_SYS_IMMR + CONFIG_SYS_I2C2_OFFSET); - - writeb(0, &dev->cr); /* stop I2C controller */ - udelay(5); /* let it shutdown in peace */ - temp = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); - if (gd->flags & GD_FLG_RELOC) - i2c_bus_speed[1] = temp; - writeb(slaveadd << 1, &dev->adr); /* write slave address */ - writeb(0x0, &dev->sr); /* clear status register */ - writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ +#ifdef CONFIG_SYS_I2C2_OFFSET + bus_num = 2; +#else + bus_num = 1; #endif + for (i = 0; i < bus_num; i++) { + dev = i2c_dev[i]; + + writeb(0, &dev->cr); /* stop I2C controller */ + udelay(5); /* let it shutdown in peace */ + temp = set_i2c_bus_speed(dev, get_i2c_clock(i), speed); + if (gd->flags & GD_FLG_RELOC) + i2c_bus_speed[i] = temp; + writeb(slaveadd << 1, &dev->adr);/* write slave address */ + writeb(0x0, &dev->sr); /* clear status register */ + writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ + } #ifdef CONFIG_SYS_I2C_BOARD_LATE_INIT /* Call board specific i2c bus reset routine AFTER the bus has been -- 1.7.4.1

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[U-Boot] [PATCH] The type expected by %zd is ssize_t, but it was being passed a size_t.
by Gabe Black 04 Nov '11

04 Nov '11

Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- common/cmd_nvedit.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 396a171..d9dc3f2 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -862,7 +862,7 @@ static int do_env_import(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv " - truncated\n", MAX_ENV_SIZE); } ++size; - printf("## Info: input data size = %zd = 0x%zX\n", size, size); + printf("## Info: input data size = %zu = 0x%zX\n", size, size); } if (chk) { -- 1.7.3.1

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