November 2011 - U-Boot

[U-Boot] [PATCH] VIDEO: mx3fb: GCC4.6 fix build warnings
by Stefano Babic 10 Nov '11

10 Nov '11

Fix: mx3fb.c: In function 'video_hw_init': mx3fb.c:827:30: warning: variable 'vesa_idx' set but not used Signed-off-by: Stefano Babic <sbabic(a)denx.de> CC: Anatolij Gustschin <agust(a)denx.de> --- drivers/video/mx3fb.c | 3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c index f30deb3..eb75c6a 100644 --- a/drivers/video/mx3fb.c +++ b/drivers/video/mx3fb.c @@ -824,7 +824,7 @@ void *video_hw_init(void) char *penv; u32 memsize; unsigned long t1, hsynch, vsynch; - int bits_per_pixel, i, tmp, vesa_idx = 0, videomode; + int bits_per_pixel, i, tmp, videomode; tmp = 0; @@ -857,7 +857,6 @@ void *video_hw_init(void) mode = (struct ctfb_res_modes *) &res_mode_init[vesa_modes[i].resindex]; bits_per_pixel = vesa_modes[i].bits_per_pixel; - vesa_idx = vesa_modes[i].resindex; } else { mode = (struct ctfb_res_modes *) &var_mode; bits_per_pixel = video_get_params(mode, penv); -- 1.7.6.4

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Re: [U-Boot] Is CCSRBAR relocation broken on P2020?
by Felix Radensky 10 Nov '11

10 Nov '11

Hi Ira, On 11/10/2011 10:00 PM, Felix Radensky wrote: > Hello Timur, Kumar, U-Boot List, > > I'm working on porting U-Boot to the Freescale P2020 COM-Express board. > See the ML post from 2011-09-27 titled "[PATCH 0/2] mpc85xx: support > for > Freescale COM Express P2020". > > When it was posted, the port was working on the top of tree U-Boot. > This > included relocation of the CCSRBAR from the power on location of > 0xff700000 to 0xffe00000. > > Today I updated U-Boot to top of tree to address the comments in the > initial mailing list posting. Upon attempting to boot the board, I get > no console output. I have traced this to commit 6ca88b0958 > ("powerpc/85xx: relocate CCSR before creating the initial RAM area"). > > Indeed, making sure that the code does not run by adding the following > to my board config file causes U-Boot to start correctly. Though the > CCSRBAR is not relocated, as expected. > > #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE > > As an alternative, reverting the commit causes my board to work again. > The CCSRBAR is relocated correctly. > > The P2020DS board is very similar to the board I am using. It performs > the same relocation of the CCSRBAR that I want to use as well. Does > anyone have a P2020DS that they can test with the current top of tree > U-Boot? Does it boot? Can you send the output of "md ffe00000 1"? > > Thanks, > Ira > I have P2020DS and can test it. Which configuration exactly, P2020DS or P2020DS_SDCARD ? Felix.

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[U-Boot] U-boot bootcmd
by Boris Borisov 10 Nov '11

10 Nov '11

Hello everybody ! I got recently one of Xburst based mini laptops ( Skytex SX E700) running version of Linux that I don't like. No support anymore so no info about how to start upgrade process or to boot from SD/USB. Info for similar laptops does not work. U-boot shell shows that I have 3 boot variables bootcmd, bootcmd_sd and bootcmd_sd_nerase. How I can find out what key combination is assigned to branch the normal boot process in other way. How you assign key combination or other event for this purpose in U-boot. Thank you P.S. I spend about an hour today reading the U-boot manual but no success ....

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[U-Boot] Is CCSRBAR relocation broken on P2020?
by Ira W. Snyder 10 Nov '11

10 Nov '11

Hello Timur, Kumar, U-Boot List, I'm working on porting U-Boot to the Freescale P2020 COM-Express board. See the ML post from 2011-09-27 titled "[PATCH 0/2] mpc85xx: support for Freescale COM Express P2020". When it was posted, the port was working on the top of tree U-Boot. This included relocation of the CCSRBAR from the power on location of 0xff700000 to 0xffe00000. Today I updated U-Boot to top of tree to address the comments in the initial mailing list posting. Upon attempting to boot the board, I get no console output. I have traced this to commit 6ca88b0958 ("powerpc/85xx: relocate CCSR before creating the initial RAM area"). Indeed, making sure that the code does not run by adding the following to my board config file causes U-Boot to start correctly. Though the CCSRBAR is not relocated, as expected. #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE As an alternative, reverting the commit causes my board to work again. The CCSRBAR is relocated correctly. The P2020DS board is very similar to the board I am using. It performs the same relocation of the CCSRBAR that I want to use as well. Does anyone have a P2020DS that they can test with the current top of tree U-Boot? Does it boot? Can you send the output of "md ffe00000 1"? Thanks, Ira

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[U-Boot] [PATCH v2 0/2] mpc85xx: support for Freescale COM Express P2020
by Ira W. Snyder 10 Nov '11

10 Nov '11

This is a cleaned up version of the U-Boot port provided with the BSP for the Freescale COM Express P2020 evaluation kit. Changes v1 -> v2: - fix checkpatch warnings - remove references to NAND (this board lacks NAND) - disable CCSR relocation Ira W. Snyder (2): mpc85xx: support board-specific reset function mpc85xx: support for Freescale COM Express P2020 MAINTAINERS | 4 + arch/powerpc/cpu/mpc85xx/cpu.c | 17 +- arch/powerpc/include/asm/immap_85xx.h | 1 + board/freescale/p2020come/Makefile | 46 +++ board/freescale/p2020come/ddr.c | 245 ++++++++++++++ board/freescale/p2020come/law.c | 36 ++ board/freescale/p2020come/p2020come.c | 401 +++++++++++++++++++++++ board/freescale/p2020come/tlb.c | 100 ++++++ boards.cfg | 2 + include/configs/P2020COME.h | 566 +++++++++++++++++++++++++++++++++ 10 files changed, 1417 insertions(+), 1 deletions(-) create mode 100644 board/freescale/p2020come/Makefile create mode 100644 board/freescale/p2020come/ddr.c create mode 100644 board/freescale/p2020come/law.c create mode 100644 board/freescale/p2020come/p2020come.c create mode 100644 board/freescale/p2020come/tlb.c create mode 100644 include/configs/P2020COME.h -- 1.7.3.4

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Re: [U-Boot] ppc -Os and _restgpr_##_x errors
by Felix Radensky 10 Nov '11

10 Nov '11

Hi Wolfgang, On 11/10/2011 05:45 PM, Felix Radensky wrote: > No, we should not. You should switch to a compiler version where this > problem has been fixed. See second entry at > http://www.denx.de/wiki/U-Boot/GccBugsAndIssues > It is not clear from the link above which GCC version solves the problem. Is it 4.5.3 ? Thanks. Felix.

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[U-Boot] Final Notice!!
by Irish Promo 10 Nov '11

10 Nov '11

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[U-Boot] [PATCH v2 0/4] Tegra2: mmc DMA related fixes
by Anton Staaf 10 Nov '11

10 Nov '11

I have removed the bounce buffer implmenetation from this patch set as it feels like a separate task now. This patch set is just magic number cleanup , a bit of refactoring, and bug fixes in the existing Tegra2 MMC driver. Changes in v2: - Added initial patch to define Tegra MMC register field values - Remove patches for bounce buffer implementation Anton Staaf (4): Tegra2: mmc: define register field values in tegra2_mmc.h Tegra2: mmc: Support DMA restarts at buffer boundaries Tegra2: mmc: Add data transfer completion timeout Tegra2: mmc: Factor out mmc_wait_inhibit functionality drivers/mmc/tegra2_mmc.c | 188 ++++++++++++++++++++++------------------------ drivers/mmc/tegra2_mmc.h | 80 ++++++++++++++++++++ 2 files changed, 169 insertions(+), 99 deletions(-) Cc: Andy Fleming <afleming(a)gmail.com> Cc: Tom Warren <twarren(a)nvidia.com> Cc: Stephen Warren <swarren(a)nvidia.com> Cc: Albert Aribaud <albert.u.boot(a)aribaud.net> -- 1.7.3.1

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[U-Boot] [PATCH v4 0/9] tegra2: Tidy up boot path
by Simon Glass 10 Nov '11

10 Nov '11

On Tegra2 the AVP runs the normal U-Boot code to a point, then halts and the A9 takes over. The current Tegra2 boot path is fairly complex, since it has a separate path and code for the Cortex-A9 and the AVP. In fact, they can largely execute the same code path. This series cleans up this logic and removes some parallel and un-needed code. Note this series is rebased against master, with the following patches added, which should be picked up first: http://patchwork.ozlabs.org/patch/122888/ http://patchwork.ozlabs.org/patch/122887/ http://patchwork.ozlabs.org/patch/122889/ http://patchwork.ozlabs.org/patch/118184/ Changes in v2: - Move Makefile armv4t flags from arch/arm/lib to Tegra's config.mk - Keep Tegra's config.mk file around so we can set the armv4t flags Changes in v4: - Revert series to version 1 - Rebase against master - Use cp_init_cp15() name consistently Simon Glass (9): tegra2: Add arch_cpu_init() to fire up Cortex-A9 tegra2: Simplify tegra_start() boot path arm: Move CP15 init out of cpu_init_crit() tegra2: Enable instruction cache tegra2: Remove unneeded boot code tegra2: Remove unneeded config option tegra2: Remove unused low-level Tegra2 UART code tegra2: Remove unneeded 'dynamic ram size' message tegra2: Don't use board pointer before it is set up arch/arm/cpu/armv7/start.S | 36 +++++----- arch/arm/cpu/armv7/tegra2/Makefile | 5 + arch/arm/cpu/armv7/tegra2/ap20.c | 54 +++++++------ arch/arm/cpu/armv7/tegra2/ap20.h | 10 +-- arch/arm/cpu/armv7/tegra2/board.c | 35 ++++----- arch/arm/cpu/armv7/tegra2/config.mk | 7 +- arch/arm/cpu/armv7/tegra2/lowlevel_init.S | 118 ----------------------------- arch/arm/include/asm/u-boot-arm.h | 3 + board/nvidia/common/board.c | 6 +- board/nvidia/common/board.h | 1 - drivers/serial/Makefile | 1 - drivers/serial/serial_tegra2.c | 77 ------------------- drivers/serial/serial_tegra2.h | 29 ------- include/configs/tegra2-common.h | 3 +- 14 files changed, 84 insertions(+), 301 deletions(-) delete mode 100644 drivers/serial/serial_tegra2.c delete mode 100644 drivers/serial/serial_tegra2.h -- 1.7.3.1

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[U-Boot] [PATCH v2] m28evk: Fix comment about the number of RAM banks
by Fabio Estevam 10 Nov '11

10 Nov '11

m28evk has one bank of RAM. Fix the comment. Cc: Marek Vasut <marek.vasut(a)gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam(a)freescale.com> --- Changes since v1: - Fix board name include/configs/m28evk.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h index 52dcd4a..d4bd207 100644 --- a/include/configs/m28evk.h +++ b/include/configs/m28evk.h @@ -80,7 +80,7 @@ /* * Memory configurations */ -#define CONFIG_NR_DRAM_BANKS 1 /* 2 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ #define PHYS_SDRAM_1 0x40000000 /* Base address */ #define PHYS_SDRAM_1_SIZE 0x40000000 /* Max 1 GB RAM */ #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ -- 1.6.0.4

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