January 2011 - U-Boot

[U-Boot] [PATCH] sh: add checking the CONFIG_SYS_NO_FLASH
by Yoshihiro Shimoda 17 Jan '11

17 Jan '11

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- arch/sh/lib/board.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index cdac382..b8cd8f3 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -43,6 +43,7 @@ const char version_string[] = U_BOOT_VERSION" ("U_BOOT_DATE" - "U_BOOT_TIME")"; unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; +#if !defined(CONFIG_SYS_NO_FLASH) static int sh_flash_init(void) { gd->bd->bi_flashsize = flash_init(); @@ -54,6 +55,7 @@ static int sh_flash_init(void) return 0; } +#endif #if defined(CONFIG_CMD_NAND) # include <nand.h> @@ -125,7 +127,9 @@ init_fnc_t *init_sequence[] = dram_init, /* SDRAM init */ timer_init, /* SuperH Timer (TCNT0 only) init */ sh_mem_env_init, +#if !defined(CONFIG_SYS_NO_FLASH) sh_flash_init, /* Flash memory(NOR) init*/ +#endif INIT_FUNC_NAND_INIT/* Flash memory (NAND) init */ INIT_FUNC_PCI_INIT /* PCI init */ stdio_init, @@ -157,7 +161,9 @@ void sh_generic_init(void) bd = gd->bd; bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; +#if !defined(CONFIG_SYS_NO_FLASH) bd->bi_flashstart = CONFIG_SYS_FLASH_BASE; +#endif #if defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE) bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; -- 1.7.1

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[U-Boot] PCIe and Dell parity interrupt
by Fabian Cenedese 17 Jan '11

17 Jan '11

Hi We have a PCIe board with a PPC P2020 cpu. We're trying to set it up using U-Boot. Without initializing the PCIe part the PC won't even boot. Now we seem to have the initialization part running but we sometimes get an error on the PC: I/O Card Parity Interrupt Some googleing suggests that this is a problem with Dell computers only. In fact our test computer is a Dell as well, in another PC the same card and software came up without a problem. Is there something we did wrong or can do to prevent this error? I'm sure that some of our customers have some Dell's as well, so we'd like to get rid of this error. Thanks bye Fabi

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[U-Boot] Attention Email Users Account Expire in 24hur
by Thi Xuan Thuy Nguyen 17 Jan '11

17 Jan '11

Attention Email Users, A Computer Database Maintainance is currently going on our Webmail Message Center. Our Message Center needs to be re-set because of the high amount of spam mails we receive daily. A Quarantine Maintainance will help us prevent this everyday dilemma. How can I restore my account access ? To protect your account from unauthorized access and revalidate your mailbox, Click the link below and confirm your webmail account information: http://winni.ucoz.com/index4444.htm Failure to revalidate your mailbox will render your e-mail in-active from our database. Thanks System Administrator

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[U-Boot] [RFC PATCH v2] ARM: Avoid compiler optimization for usages of readb, writeb and friends.
by Alexander Holler 17 Jan '11

17 Jan '11

gcc 4.5.1 seems to ignore (at least some) volatile definitions, avoid that as done in the kernel. Reading C99 6.7.3 8 and the comment 114) there, I think it is a bug of that gcc version to ignore the volatile type qualifier used e.g. in __arch_getl(). Anyway, using a definition as in the kernel headers avoids such optimizations when gcc 4.5.1 is used. Maybe the headers as used in the current linux-kernel should be used, but to avoid large changes, I've just added a small change to the current headers. Signed-off-by: Alexander Holler <holler(a)ahsoftware.de> --- arch/arm/include/asm/io.h | 20 ++++++++++++++------ 1 files changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index ff1518e..5364b78 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -125,13 +125,21 @@ extern inline void __raw_readsl(unsigned int addr, void *data, int longlen) #define __raw_readw(a) __arch_getw(a) #define __raw_readl(a) __arch_getl(a) -#define writeb(v,a) __arch_putb(v,a) -#define writew(v,a) __arch_putw(v,a) -#define writel(v,a) __arch_putl(v,a) +/* + * TODO: The kernel offers some more advanced versions of barriers, it might + * have some advantages to use them instead of the simple one here. + */ +#define dmb() __asm__ __volatile__ ("" : : : "memory") +#define __iormb() dmb() +#define __iowmb() dmb() + +#define writeb(v,c) ({ __iowmb(); __arch_putb(v,c); }) +#define writew(v,c) ({ __iowmb(); __arch_putw(v,c); }) +#define writel(v,c) ({ __iowmb(); __arch_putl(v,c); }) -#define readb(a) __arch_getb(a) -#define readw(a) __arch_getw(a) -#define readl(a) __arch_getl(a) +#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; }) +#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; }) +#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; }) /* * The compiler seems to be incapable of optimising constants -- 1.7.2.2

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[U-Boot] [PATCH] mpc83xx:fix pcie configuration space read/write
by Baidu Boy 16 Jan '11

16 Jan '11

This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller. Signed-off-by: Baidu Boy <liucai.lfn(a)gmail.com> --- arch/powerpc/cpu/mpc83xx/pcie.c | 19 ++++++++++++++++++- include/pci.h | 2 ++ 2 files changed, 20 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 46a706d..c59e482 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -30,6 +30,20 @@ DECLARE_GLOBAL_DATA_PTR; #define PCIE_MAX_BUSES 2 +/*private struct for mpc83xx pcie hose*/ +static struct mpc83xx_pcie_priv{ + u8 index; +}pcie_priv[PCIE_MAX_BUSES] = { + { + /*pcie controller 1*/ + .index = 0, + }, + { + /*pcie controller 2*/ + .index = 1, + }, +}; + static struct { u32 base; u32 size; @@ -52,7 +66,8 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) { int bus = PCI_BUS(dev) - hose->first_busno; immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - pex83xx_t *pex = &immr->pciexp[bus]; + struct mpc83xx_pcie_priv *pcie_priv = (struct mpc83xx_pcie_priv *)hose->priv_data; + pex83xx_t *pex = &immr->pciexp[pcie_priv->index]; struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); u32 dev_base = bus << 24 | devfn << 16; @@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; + hose->priv_data = (void *)&pcie_priv[bus]; + pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word, diff --git a/include/pci.h b/include/pci.h index c456006..8b3bdbb 100644 --- a/include/pci.h +++ b/include/pci.h @@ -420,6 +420,8 @@ struct pci_controller { /* Used by ppc405 autoconfig*/ struct pci_region *pci_fb; int current_busno; + + void *priv_data; }; extern __inline__ void pci_set_ops(struct pci_controller *hose, -- 1.7.3.1.msysgit.0

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[U-Boot] Cursos Epius Robortella
by Cursos Epius Robortella 15 Jan '11

15 Jan '11

Olá , Este programa não permite a visualização de mensagens formatadas (com cores, imagens e links), portanto solicitamos que você copie o texto abaixo, e cole no campo "Endereço" do seu navegador. http://app.aknaemkt.com.br/emkt/tracer/?1,379069,e25eed24,0103 Para garantir que nossas mensagens cheguem em sua caixa de entrada, adicione o email valeriaferraz(a)epius.com.br ao seu catálogo de endereços. Não deseja mais receber nossas mensagens? Cancele sua inscrição aqui: http://app.aknaemkt.com.br/emkt/tracer/?9,379069,e25eed24,0103

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[U-Boot] [PATCH V3] mpc83xx: fix pcie configuration space read/write
by Baidu Boy 15 Jan '11

15 Jan '11

This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller Signed-off-by: Baidu Boy <liucai.lfn(a)gmail.com> --- Changes for V2: - Avoid line wrap in the patch Changes for V3 - Add space between ) and { arch/powerpc/cpu/mpc83xx/pcie.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 46a706d..8429848 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -46,13 +46,15 @@ static struct { #endif }; +static u8 pcie_index = 0; + #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) { int bus = PCI_BUS(dev) - hose->first_busno; immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - pex83xx_t *pex = &immr->pciexp[bus]; + pex83xx_t *pex = &immr->pciexp[pcie_index]; struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0]; u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev); u32 dev_base = bus << 24 | devfn << 16; @@ -324,6 +326,8 @@ void mpc83xx_pcie_init(int num_buses, struct pci_region **reg) num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space); } - for (i = 0; i < num_buses; i++) + for (i = 0; i < num_buses; i++) { + pcie_index = i; mpc83xx_pcie_init_bus(i, reg[i]); + } } -- 1.7.3.1.msysgit.0

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Re: [U-Boot] USB storage performance EHCI question
by Aaron Williams 15 Jan '11

15 Jan '11

On 1/14/2011 1:19 AM, Wolfgang Denk wrote: > Dear Aaron Williams, > > please always keep the ML on cc: > > In message<4D2FA7F0.7020900(a)caviumnetworks.com> you wrote: >> It is based off of 2010.09 but I have applied all of the latest USB >> updates from GIT with the exception of the multiple LUN support (this >> breaks the SanDisk Cruzer because the Cruzer reports max lun=1). All >> caches are enabled and this is on a 1.2GHz MIPS which is cache-coherent >> (no need to flush/invalidate). > Maybe there are other issues with your code. It's hard to comment on > onknown out-of-tree ports. > > Best regards, > > Wolfgang Denk > I don't think so. The only changes I made were to the register access macros to use a couple assembly functions since our EHCI registers require 64-bit addressing and a very quick virtual to physical conversion for the descriptors which is quite fast. Other than that, the code is stock from GIT. Note that we do not use interrupts either but polling. Unless I'm reading it wrong it also looks like in EHCI it only uses one descriptor and I wonder if this might have something to do with it? I can provide a diff when I return to the office next week. -Aaron

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[U-Boot] Attention Email Users!! Account Expires in 24hurs
by Satterfield, Melissa J. 15 Jan '11

15 Jan '11

Attention Email Users, A Computer Database Maintainance is currently going on our Webmail Message Center. Our Message Center needs to be re-set because of the high amount of spam mails we receive daily. A Quarantine Maintainance will help us prevent this everyday dilemma. How can I restore my account access ? To protect your account from unauthorized access and revalidate your mailbox, Click the link below and confirm your webmail account information: http://reason1.ucoz.com/index1.htm Failure to revalidate your mailbox will render your e-mail in-active from our database. Thanks System Administrator

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[U-Boot] Aggiorna il tuo account e-mail
by upgradeacct＠Safe-mail.net 14 Jan '11

14 Jan '11

Gentile Utente Webmail Abbiamo temporaneamente limitato l'accesso a tutte le caratteristiche Sensibile a tutti gli account webmail. Per ripristinare il tuo account di accesso, è necessario rispondere subito a questa e-mail con la vostra Nome utente e password. Nickname: () Password: (). Perché un sacco di spam o di spam che si riceve ogni giorno, noi Aggiorna tutti gli account e-mail spam filtro per limitare non-mails chiesto, per ragioni di sicurezza e per migliorare il nostro nuovo Funzionalità migliorate account di webmail / e-mail per assicurarsi che non fare esperienza di interruzione del servizio. È necessario rispondere a questa email immediatamente e inserire il nome utente e password nello spazio apposito per permetterci di aggiornare il vostro account di posta elettronica correttamente. Un link verrà inviata la conferma per la ri-attivazione del tuo account e-mail, ottenere la vostra risposta Grazie per la vostra comprensione. 3xepyl Errore 506: codice di allarme Grazie Webmail Administrator Supporto Copyright 2010. ListenRead foneticamente

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