January 2011 - U-Boot

[U-Boot] [PATCH] Add support for ASIX's AX88783 ethernet chip
by Joe Xue 31 Jan '11

31 Jan '11

for more information about this chip, please check: http://www.asix.com.tw/products.php?op=pItemdetail&PItemID=98;65;86&PLine=65 Signed-off-by: Joe Xue <lgxue(a)hotmail.com> --- README | 7 +++++++ drivers/net/Makefile | 1 + include/netdev.h | 1 + 3 files changed, 9 insertions(+), 0 deletions(-) diff --git a/README b/README index 755d17c..c9657d8 100644 --- a/README +++ b/README @@ -892,6 +892,13 @@ The following options need to be configured: automatically converts one 32 bit word to two 16 bit words you may also try CONFIG_SMC911X_32_BIT. + CONFIG_DRIVER_AX88783 + Support for ASIX's AX88783 chip + + CONFIG_AX88783_BASE + Define this to hold the physical address + of the device (I/O space) + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fd9d0b4..7cd6e2c 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -30,6 +30,7 @@ COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o +COBJS-$(CONFIG_DRIVER_AX88783) += ax88783.o COBJS-$(CONFIG_BCM570x) += bcm570x.o COBJS-$(CONFIG_BCM570x) += bcm570x_autoneg.o COBJS-$(CONFIG_BCM570x) += 5701rls.o diff --git a/include/netdev.h b/include/netdev.h index 1a542e8..fddc64d 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -44,6 +44,7 @@ int cpu_eth_init(bd_t *bis); int altera_tse_initialize(u8 dev_num, int mac_base, int sgdma_rx_base, int sgdma_tx_base); int ax88180_initialize(bd_t *bis); +int ax88783_initialize(bd_t *bis); int au1x00_enet_initialize(bd_t*); int at91emac_register(bd_t *bis, unsigned long iobase); int bfin_EMAC_initialize(bd_t *bis); -- 1.7.0.4

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[U-Boot] u-boot src code to allow it to running from RAM for MPC85XX
by rukhsana ansari 31 Jan '11

31 Jan '11

Hi, I was looking for a pointer to the u-boot src code that enables u-boot to be loaded to and started from RAM rather than flash for the MPC85XX. A Freescale application note ( cache.freescale.com/files/32bit/doc/app_note/AN3646.pdf) describes booting over PCI express which would require this support of u-boot. Any help in this area would be much appreciated. Regards, Rukhsana

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[U-Boot] Aspire Property Magazine - Spring 2011 and beyond - advertising/editorial intro offer improved - copy deadline approaching 7th Feb
by Aspire Property Magazine London 31 Jan '11

31 Jan '11

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[U-Boot] [PATCH v4] spi: add support SuperH SPI module
by Yoshihiro Shimoda 31 Jan '11

31 Jan '11

SH7757 has SPI module. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- about v4: - add description of CONFIG_SH_SPI to README README | 5 + drivers/spi/Makefile | 1 + drivers/spi/sh_spi.c | 261 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/sh_spi.h | 79 +++++++++++++++ 4 files changed, 346 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/sh_spi.c create mode 100644 drivers/spi/sh_spi.h diff --git a/README b/README index 7de9b14..4ec1c30 100644 --- a/README +++ b/README @@ -1656,6 +1656,11 @@ The following options need to be configured: SPI EEPROM, also an instance works with Crystal A/D and D/As on the SACSng board) + CONFIG_SH_SPI + + Enables the driver for SPI controller on SuperH. Currently + only SH7757 is supported. + CONFIG_SPI_X Enables extended (16-bit) SPI EEPROM addressing. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e34a124..d582fbb 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o +COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c new file mode 100644 index 0000000..ba43bec --- /dev/null +++ b/drivers/spi/sh_spi.c @@ -0,0 +1,261 @@ +/* + * SH SPI driver + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include "sh_spi.h" + +static void sh_spi_write(unsigned long data, unsigned long *reg) +{ + writel(data, reg); +} + +static unsigned long sh_spi_read(unsigned long *reg) +{ + return readl(reg); +} + +static void sh_spi_set_bit(unsigned long val, unsigned long *reg) +{ + unsigned long tmp; + + tmp = sh_spi_read(reg); + tmp |= val; + sh_spi_write(tmp, reg); +} + +static void sh_spi_clear_bit(unsigned long val, unsigned long *reg) +{ + unsigned long tmp; + + tmp = sh_spi_read(reg); + tmp &= ~val; + sh_spi_write(tmp, reg); +} + +static void clear_fifo(struct sh_spi *ss) +{ + sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2); + sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2); +} + +static int recvbuf_wait(struct sh_spi *ss) +{ + while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +static int write_fifo_empty_wait(struct sh_spi *ss) +{ + while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct sh_spi *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = malloc(sizeof(struct spi_slave)); + if (!ss) + return NULL; + + ss->slave.bus = bus; + ss->slave.cs = cs; + ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE; + + /* SPI sycle stop */ + sh_spi_write(0xfe, &ss->regs->cr1); + /* CR1 init */ + sh_spi_write(0x00, &ss->regs->cr1); + /* CR3 init */ + sh_spi_write(0x00, &ss->regs->cr3); + + clear_fifo(ss); + + /* 1/8 clock */ + sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2); + udelay(10); + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct sh_spi *spi = to_sh_spi(slave); + + free(spi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct sh_spi *ss = to_sh_spi(slave); + + sh_spi_write(sh_spi_read(&ss->regs->cr1) & + ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1); +} + +static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, + unsigned int len, unsigned long flags) +{ + int i, cur_len, ret = 0; + int remain = (int)len; + unsigned long tmp; + + if (len >= SH_SPI_FIFO_SIZE) + sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); + + while (remain > 0) { + cur_len = (remain < SH_SPI_FIFO_SIZE) ? + remain : SH_SPI_FIFO_SIZE; + for (i = 0; i < cur_len && + !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) && + !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF); + i++) + sh_spi_write(tx_data[i], &ss->regs->tbr_rbr); + + cur_len = i; + + if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) { + /* Abort the transaction */ + flags |= SPI_XFER_END; + sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4); + ret = 1; + break; + } + + remain -= cur_len; + tx_data += cur_len; + + if (remain > 0) + write_fifo_empty_wait(ss); + } + + if (flags & SPI_XFER_END) { + tmp = sh_spi_read(&ss->regs->cr1); + tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); + sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); + udelay(100); + write_fifo_empty_wait(ss); + } + + return ret; +} + +static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data, + unsigned int len, unsigned long flags) +{ + int i; + unsigned long tmp; + + if (len > SH_SPI_MAX_BYTE) + sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3); + else + sh_spi_write(len, &ss->regs->cr3); + + tmp = sh_spi_read(&ss->regs->cr1); + tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); + sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); + + for (i = 0; i < len; i++) { + if (recvbuf_wait(ss)) + return 0; + + rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr); + } + sh_spi_write(0, &ss->regs->cr3); + + return 0; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct sh_spi *ss = to_sh_spi(slave); + const unsigned char *tx_data = dout; + unsigned char *rx_data = din; + unsigned int len = bitlen / 8; + int ret = 0; + + if (flags & SPI_XFER_BEGIN) + sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA, + &ss->regs->cr1); + + if (tx_data) + ret = sh_spi_send(ss, tx_data, len, flags); + + if (ret == 0 && rx_data) + ret = sh_spi_receive(ss, rx_data, len, flags); + + if (flags & SPI_XFER_END) { + sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1); + udelay(100); + + sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD, + &ss->regs->cr1); + clear_fifo(ss); + } + + return ret; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* This driver supports "bus = 0" and "cs = 0" only. */ + if (!bus && !cs) + return 1; + else + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + +} + diff --git a/drivers/spi/sh_spi.h b/drivers/spi/sh_spi.h new file mode 100644 index 0000000..b1cf98c --- /dev/null +++ b/drivers/spi/sh_spi.h @@ -0,0 +1,79 @@ +/* + * SH SPI driver + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#ifndef __SH_SPI_H__ +#define __SH_SPI_H__ + +#include <spi.h> + +struct sh_spi_regs { + unsigned long tbr_rbr; + unsigned long resv1; + unsigned long cr1; + unsigned long resv2; + unsigned long cr2; + unsigned long resv3; + unsigned long cr3; + unsigned long resv4; + unsigned long cr4; +}; + +/* CR1 */ +#define SH_SPI_TBE 0x80 +#define SH_SPI_TBF 0x40 +#define SH_SPI_RBE 0x20 +#define SH_SPI_RBF 0x10 +#define SH_SPI_PFONRD 0x08 +#define SH_SPI_SSDB 0x04 +#define SH_SPI_SSD 0x02 +#define SH_SPI_SSA 0x01 + +/* CR2 */ +#define SH_SPI_RSTF 0x80 +#define SH_SPI_LOOPBK 0x40 +#define SH_SPI_CPOL 0x20 +#define SH_SPI_CPHA 0x10 +#define SH_SPI_L1M0 0x08 + +/* CR3 */ +#define SH_SPI_MAX_BYTE 0xFF + +/* CR4 */ +#define SH_SPI_TBEI 0x80 +#define SH_SPI_TBFI 0x40 +#define SH_SPI_RBEI 0x20 +#define SH_SPI_RBFI 0x10 +#define SH_SPI_WPABRT 0x04 +#define SH_SPI_SSS 0x01 + +#define SH_SPI_FIFO_SIZE 32 + +struct sh_spi { + struct spi_slave slave; + struct sh_spi_regs *regs; +}; + +static inline struct sh_spi *to_sh_spi(struct spi_slave *slave) +{ + return container_of(slave, struct sh_spi, slave); +} + +#endif + -- 1.7.1

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[U-Boot] [PATCH v3] spi: add support SuperH SPI module
by Yoshihiro Shimoda 31 Jan '11

31 Jan '11

SH7757 has SPI module. This patch supports it. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- about v3: - keep list sorted in Makefile - separate some code to header file - change hardware registers to C structure drivers/spi/Makefile | 1 + drivers/spi/sh_spi.c | 261 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/spi/sh_spi.h | 79 +++++++++++++++ 3 files changed, 341 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/sh_spi.c create mode 100644 drivers/spi/sh_spi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index e34a124..d582fbb 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -37,6 +37,7 @@ COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS-$(CONFIG_OMAP3_SPI) += omap3_spi.o COBJS-$(CONFIG_SOFT_SPI) += soft_spi.o +COBJS-$(CONFIG_SH_SPI) += sh_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/sh_spi.c b/drivers/spi/sh_spi.c new file mode 100644 index 0000000..ba43bec --- /dev/null +++ b/drivers/spi/sh_spi.c @@ -0,0 +1,261 @@ +/* + * SH SPI driver + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#include <common.h> +#include <malloc.h> +#include <spi.h> +#include <asm/io.h> +#include "sh_spi.h" + +static void sh_spi_write(unsigned long data, unsigned long *reg) +{ + writel(data, reg); +} + +static unsigned long sh_spi_read(unsigned long *reg) +{ + return readl(reg); +} + +static void sh_spi_set_bit(unsigned long val, unsigned long *reg) +{ + unsigned long tmp; + + tmp = sh_spi_read(reg); + tmp |= val; + sh_spi_write(tmp, reg); +} + +static void sh_spi_clear_bit(unsigned long val, unsigned long *reg) +{ + unsigned long tmp; + + tmp = sh_spi_read(reg); + tmp &= ~val; + sh_spi_write(tmp, reg); +} + +static void clear_fifo(struct sh_spi *ss) +{ + sh_spi_set_bit(SH_SPI_RSTF, &ss->regs->cr2); + sh_spi_clear_bit(SH_SPI_RSTF, &ss->regs->cr2); +} + +static int recvbuf_wait(struct sh_spi *ss) +{ + while (sh_spi_read(&ss->regs->cr1) & SH_SPI_RBE) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +static int write_fifo_empty_wait(struct sh_spi *ss) +{ + while (!(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBE)) { + if (ctrlc()) + return 1; + udelay(10); + } + return 0; +} + +void spi_init(void) +{ +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct sh_spi *ss; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + ss = malloc(sizeof(struct spi_slave)); + if (!ss) + return NULL; + + ss->slave.bus = bus; + ss->slave.cs = cs; + ss->regs = (struct sh_spi_regs *)CONFIG_SH_SPI_BASE; + + /* SPI sycle stop */ + sh_spi_write(0xfe, &ss->regs->cr1); + /* CR1 init */ + sh_spi_write(0x00, &ss->regs->cr1); + /* CR3 init */ + sh_spi_write(0x00, &ss->regs->cr3); + + clear_fifo(ss); + + /* 1/8 clock */ + sh_spi_write(sh_spi_read(&ss->regs->cr2) | 0x07, &ss->regs->cr2); + udelay(10); + + return &ss->slave; +} + +void spi_free_slave(struct spi_slave *slave) +{ + struct sh_spi *spi = to_sh_spi(slave); + + free(spi); +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct sh_spi *ss = to_sh_spi(slave); + + sh_spi_write(sh_spi_read(&ss->regs->cr1) & + ~(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD), &ss->regs->cr1); +} + +static int sh_spi_send(struct sh_spi *ss, const unsigned char *tx_data, + unsigned int len, unsigned long flags) +{ + int i, cur_len, ret = 0; + int remain = (int)len; + unsigned long tmp; + + if (len >= SH_SPI_FIFO_SIZE) + sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); + + while (remain > 0) { + cur_len = (remain < SH_SPI_FIFO_SIZE) ? + remain : SH_SPI_FIFO_SIZE; + for (i = 0; i < cur_len && + !(sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) && + !(sh_spi_read(&ss->regs->cr1) & SH_SPI_TBF); + i++) + sh_spi_write(tx_data[i], &ss->regs->tbr_rbr); + + cur_len = i; + + if (sh_spi_read(&ss->regs->cr4) & SH_SPI_WPABRT) { + /* Abort the transaction */ + flags |= SPI_XFER_END; + sh_spi_set_bit(SH_SPI_WPABRT, &ss->regs->cr4); + ret = 1; + break; + } + + remain -= cur_len; + tx_data += cur_len; + + if (remain > 0) + write_fifo_empty_wait(ss); + } + + if (flags & SPI_XFER_END) { + tmp = sh_spi_read(&ss->regs->cr1); + tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); + sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); + udelay(100); + write_fifo_empty_wait(ss); + } + + return ret; +} + +static int sh_spi_receive(struct sh_spi *ss, unsigned char *rx_data, + unsigned int len, unsigned long flags) +{ + int i; + unsigned long tmp; + + if (len > SH_SPI_MAX_BYTE) + sh_spi_write(SH_SPI_MAX_BYTE, &ss->regs->cr3); + else + sh_spi_write(len, &ss->regs->cr3); + + tmp = sh_spi_read(&ss->regs->cr1); + tmp = tmp & ~(SH_SPI_SSD | SH_SPI_SSDB); + sh_spi_write(tmp, &ss->regs->cr1); + sh_spi_set_bit(SH_SPI_SSA, &ss->regs->cr1); + + for (i = 0; i < len; i++) { + if (recvbuf_wait(ss)) + return 0; + + rx_data[i] = (unsigned char)sh_spi_read(&ss->regs->tbr_rbr); + } + sh_spi_write(0, &ss->regs->cr3); + + return 0; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct sh_spi *ss = to_sh_spi(slave); + const unsigned char *tx_data = dout; + unsigned char *rx_data = din; + unsigned int len = bitlen / 8; + int ret = 0; + + if (flags & SPI_XFER_BEGIN) + sh_spi_write(sh_spi_read(&ss->regs->cr1) & ~SH_SPI_SSA, + &ss->regs->cr1); + + if (tx_data) + ret = sh_spi_send(ss, tx_data, len, flags); + + if (ret == 0 && rx_data) + ret = sh_spi_receive(ss, rx_data, len, flags); + + if (flags & SPI_XFER_END) { + sh_spi_set_bit(SH_SPI_SSD, &ss->regs->cr1); + udelay(100); + + sh_spi_clear_bit(SH_SPI_SSA | SH_SPI_SSDB | SH_SPI_SSD, + &ss->regs->cr1); + clear_fifo(ss); + } + + return ret; +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + /* This driver supports "bus = 0" and "cs = 0" only. */ + if (!bus && !cs) + return 1; + else + return 0; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + +} + diff --git a/drivers/spi/sh_spi.h b/drivers/spi/sh_spi.h new file mode 100644 index 0000000..b1cf98c --- /dev/null +++ b/drivers/spi/sh_spi.h @@ -0,0 +1,79 @@ +/* + * SH SPI driver + * + * Copyright (C) 2011 Renesas Solutions Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + */ + +#ifndef __SH_SPI_H__ +#define __SH_SPI_H__ + +#include <spi.h> + +struct sh_spi_regs { + unsigned long tbr_rbr; + unsigned long resv1; + unsigned long cr1; + unsigned long resv2; + unsigned long cr2; + unsigned long resv3; + unsigned long cr3; + unsigned long resv4; + unsigned long cr4; +}; + +/* CR1 */ +#define SH_SPI_TBE 0x80 +#define SH_SPI_TBF 0x40 +#define SH_SPI_RBE 0x20 +#define SH_SPI_RBF 0x10 +#define SH_SPI_PFONRD 0x08 +#define SH_SPI_SSDB 0x04 +#define SH_SPI_SSD 0x02 +#define SH_SPI_SSA 0x01 + +/* CR2 */ +#define SH_SPI_RSTF 0x80 +#define SH_SPI_LOOPBK 0x40 +#define SH_SPI_CPOL 0x20 +#define SH_SPI_CPHA 0x10 +#define SH_SPI_L1M0 0x08 + +/* CR3 */ +#define SH_SPI_MAX_BYTE 0xFF + +/* CR4 */ +#define SH_SPI_TBEI 0x80 +#define SH_SPI_TBFI 0x40 +#define SH_SPI_RBEI 0x20 +#define SH_SPI_RBFI 0x10 +#define SH_SPI_WPABRT 0x04 +#define SH_SPI_SSS 0x01 + +#define SH_SPI_FIFO_SIZE 32 + +struct sh_spi { + struct spi_slave slave; + struct sh_spi_regs *regs; +}; + +static inline struct sh_spi *to_sh_spi(struct spi_slave *slave) +{ + return container_of(slave, struct sh_spi, slave); +} + +#endif + -- 1.7.1

2 2

[U-Boot] [PATCH] i2c: Fix chip address.0
by Joakim Tjernlund 31 Jan '11

31 Jan '11

According to the i2c command alen 0 should be allowed but this is not allowed in the implementation, fix. Also cleanup all cmd_usage cases while at it. It is cleaner to return cmd_usage(cmdtp); instead of { cmd_usage(cmdtp); return 1; } Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund(a)transmode.se> --- common/cmd_i2c.c | 107 +++++++++++++++++++++--------------------------------- 1 files changed, 41 insertions(+), 66 deletions(-) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 8b9c2c9..a7d0dd8 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -88,7 +88,7 @@ */ static uchar i2c_dp_last_chip; static uint i2c_dp_last_addr; -static uint i2c_dp_last_alen; +static int i2c_dp_last_alen; static uint i2c_dp_last_length = 0x10; static uchar i2c_mm_last_chip; @@ -154,7 +154,7 @@ int i2c_set_bus_speed(unsigned int) * get_alen: small parser helper function to get address length * returns the address length,or 0 on error */ -static uint get_alen(char *arg) +static int get_alen(char *arg) { int j; int alen; @@ -164,7 +164,7 @@ static uint get_alen(char *arg) if (arg[j] == '.') { alen = arg[j+1] - '0'; if (alen > 3) { - return 0; + return -1; } break; } else if (arg[j] == '\0') @@ -181,13 +181,12 @@ static uint get_alen(char *arg) static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { u_char chip; - uint devaddr, alen, length; + uint devaddr, length; + int alen; u_char *memaddr; - if (argc != 5) { - cmd_usage(cmdtp); - return 1; - } + if (argc != 5) + return cmd_usage(cmdtp); /* * I2C chip address @@ -200,10 +199,8 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ devaddr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) { - cmd_usage(cmdtp); - return 1; - } + if (alen < 0) + return cmd_usage(cmdtp); /* * Length is the number of objects, not number of bytes. @@ -229,7 +226,8 @@ static int do_i2c_read ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { u_char chip; - uint addr, alen, length; + uint addr, length; + int alen; int j, nbytes, linebytes; /* We use the last specified parameters, unless new ones are @@ -240,10 +238,8 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) alen = i2c_dp_last_alen; length = i2c_dp_last_length; - if (argc < 3) { - cmd_usage(cmdtp); - return 1; - } + if (argc < 3) + return cmd_usage(cmdtp); if ((flag & CMD_FLAG_REPEAT) == 0) { /* @@ -261,10 +257,8 @@ static int do_i2c_md ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) { - cmd_usage(cmdtp); - return 1; - } + if (alen < 0) + return cmd_usage(cmdtp); /* * If another parameter, it is the length to display. @@ -328,14 +322,12 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uchar chip; ulong addr; - uint alen; + int alen; uchar byte; int count; - if ((argc < 4) || (argc > 5)) { - cmd_usage(cmdtp); - return 1; - } + if ((argc < 4) || (argc > 5)) + return cmd_usage(cmdtp); /* * Chip is always specified. @@ -347,10 +339,8 @@ static int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) { - cmd_usage(cmdtp); - return 1; - } + if (alen < 0) + return cmd_usage(cmdtp); /* * Value to write is always specified. @@ -392,16 +382,14 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uchar chip; ulong addr; - uint alen; + int alen; int count; uchar byte; ulong crc; ulong err; - if (argc < 4) { - cmd_usage(cmdtp); - return 1; - } + if (argc < 4) + return cmd_usage(cmdtp); /* * Chip is always specified. @@ -413,10 +401,8 @@ static int do_i2c_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) { - cmd_usage(cmdtp); - return 1; - } + if (alen < 0) + return cmd_usage(cmdtp); /* * Count is always specified @@ -456,16 +442,14 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) { uchar chip; ulong addr; - uint alen; + int alen; ulong data; int size = 1; int nbytes; extern char console_buffer[]; - if (argc != 3) { - cmd_usage(cmdtp); - return 1; - } + if (argc != 3) + return cmd_usage(cmdtp); #ifdef CONFIG_BOOT_RETRY_TIME reset_cmd_timeout(); /* got a good command to get here */ @@ -495,10 +479,8 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) { - cmd_usage(cmdtp); - return 1; - } + if (alen < 0) + return cmd_usage(cmdtp); } /* @@ -622,16 +604,14 @@ static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { u_char chip; - ulong alen; + int alen; uint addr; uint length; u_char bytes[16]; int delay; - if (argc < 3) { - cmd_usage(cmdtp); - return 1; - } + if (argc < 3) + return cmd_usage(cmdtp); /* * Chip is always specified. @@ -643,10 +623,8 @@ static int do_i2c_loop(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ addr = simple_strtoul(argv[2], NULL, 16); alen = get_alen(argv[2]); - if (alen == 0) { - cmd_usage(cmdtp); - return 1; - } + if (alen < 0) + return cmd_usage(cmdtp); /* * Length is the number of objects, not number of bytes. @@ -784,10 +762,9 @@ static int do_sdram (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "32 MiB", "16 MiB", "8 MiB", "4 MiB" }; - if (argc < 2) { - cmd_usage(cmdtp); - return 1; - } + if (argc < 2) + return cmd_usage(cmdtp); + /* * Chip is always specified. */ @@ -1322,12 +1299,10 @@ static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) c = find_cmd_tbl(argv[0], &cmd_i2c_sub[0], ARRAY_SIZE(cmd_i2c_sub)); - if (c) { + if (c) return c->cmd(cmdtp, flag, argc, argv); - } else { - cmd_usage(cmdtp); - return 1; - } + else + return cmd_usage(cmdtp); } /***************************************************/ -- 1.7.3.4

3 2

[U-Boot] [PATCH v2 2/2] net: sh_eth: add cache handling
by Yoshihiro Shimoda 31 Jan '11

31 Jan '11

Some CPU needs cache handling. So this patch add the config of CONFIG_SH_ETHER_CACHE_WRITEBACK, and it calls wback function. Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- about v2: - add description of new configuration to README (This patch depends on "README: add description of sh_eth driver") README | 3 +++ drivers/net/sh_eth.c | 9 +++++++++ 2 files changed, 12 insertions(+), 0 deletions(-) diff --git a/README b/README index 41458a3..7de9b14 100644 --- a/README +++ b/README @@ -897,6 +897,9 @@ The following options need to be configured: CONFIG_SH_ETHER_PHY_ADDR Define the ETH PHY's address + CONFIG_SH_ETHER_CACHE_WRITEBACK + If this option is set, the driver enables cache flush. + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 86cc324..53d918d 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -36,6 +36,12 @@ #ifndef CONFIG_SH_ETHER_PHY_ADDR # error "Please define CONFIG_SH_ETHER_PHY_ADDR" #endif +#ifdef CONFIG_SH_ETHER_CACHE_WRITEBACK +#define flush_cache_wback(addr, len) \ + dcache_wback_range((u32)addr, (u32)(addr + len - 1)) +#else +#define flush_cache_wback(...) +#endif #define SH_ETH_PHY_DELAY 50000 @@ -197,6 +203,7 @@ int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) } /* Update tx descriptor */ + flush_cache_wback(packet, len); port_info->tx_desc_cur->td2 = ADDR_TO_PHY(packet); port_info->tx_desc_cur->td1 = len << 16; /* Must preserve the end of descriptor list indication */ @@ -312,6 +319,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info->tx_desc_malloc + TX_DESC_SIZE - 1) & ~(TX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_TX_DESC * sizeof(struct tx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2(tmp_addr); port_info->tx_desc_cur = port_info->tx_desc_base; @@ -361,6 +369,7 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) tmp_addr = (u32) (((int)port_info->rx_desc_malloc + RX_DESC_SIZE - 1) & ~(RX_DESC_SIZE - 1)); + flush_cache_wback(tmp_addr, NUM_RX_DESC * sizeof(struct rx_desc_s)); /* Make sure we use a P2 address (non-cacheable) */ port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2(tmp_addr); -- 1.7.1

2 1

[U-Boot] [PATCH 1/2] README: add description of sh_eth driver
by Yoshihiro Shimoda 31 Jan '11

31 Jan '11

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh(a)renesas.com> --- README | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/README b/README index d7a23cd..41458a3 100644 --- a/README +++ b/README @@ -888,6 +888,15 @@ The following options need to be configured: automatically converts one 32 bit word to two 16 bit words you may also try CONFIG_SMC911X_32_BIT. + CONFIG_SH_ETHER + Support for Renesas on-chip Ethernet controller + + CONFIG_SH_ETHER_USE_PORT + Define the number of ports to be used + + CONFIG_SH_ETHER_PHY_ADDR + Define the ETH PHY's address + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define -- 1.7.1

2 1

[U-Boot] [PATCH] Add support for AX88183 ethernet chip
by Joe Xue 30 Jan '11

30 Jan '11

Signed-off-by: Joe Xue <lgxue(a)hotmail.com> modified: README modified: drivers/net/Makefile new file: drivers/net/ax88183.c new file: drivers/net/ax88183.h modified: include/netdev.h --- README | 7 + drivers/net/Makefile | 1 + drivers/net/ax88183.c | 293 +++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ax88183.h | 118 ++++++++++++++++++++ include/netdev.h | 1 + 5 files changed, 420 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ax88183.c create mode 100644 drivers/net/ax88183.h diff --git a/README b/README index 755d17c..951baee 100644 --- a/README +++ b/README @@ -892,6 +892,13 @@ The following options need to be configured: automatically converts one 32 bit word to two 16 bit words you may also try CONFIG_SMC911X_32_BIT. + CONFIG_DRIVER_AX88183 + Support for ASIX's AX88183 chip + + CONFIG_AX88183_BASE + Define this to hold the physical address + of the device (I/O space) + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define diff --git a/drivers/net/Makefile b/drivers/net/Makefile index fd9d0b4..393d5f3 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -84,6 +84,7 @@ COBJS-$(CONFIG_TSI108_ETH) += tsi108_eth.o COBJS-$(CONFIG_ULI526X) += uli526x.o COBJS-$(CONFIG_VSC7385_ENET) += vsc7385.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o +COBJS-$(CONFIG_DRIVER_AX88183) += ax88183.o COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/net/ax88183.c b/drivers/net/ax88183.c new file mode 100644 index 0000000..0543a40 --- /dev/null +++ b/drivers/net/ax88183.c @@ -0,0 +1,293 @@ +/* + * + * (C) Copyright 2011 Joe Xue <lgxue(a)hotmail.com> + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +/* + * AX88783 has two ethernet ports, this driver uses port 0 in u-boot + */ + +#include <common.h> +#include <command.h> +#include <net.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <config.h> +#include <asm/io.h> +#include "ax88183.h" + +static int ax88180_phy_initial(struct eth_device *dev) +{ + int i; + unsigned int tmp; + struct ax88183_reg * reg = (struct ax88183_reg *)dev->iobase; + + /* reset chip */ + tmp = readl(&reg->cr); + writel((tmp & ~CR_CHIP_RESET), &reg->cr); + udelay(1000); + + writel((tmp | CR_CHIP_RESET), &reg->cr); + + /* phy init */ + tmp = readl(&reg->pcr); + tmp |= PCR_PHY0_RESET_CLEAR; + + writel(tmp, &reg->pcr); + udelay(100000); + + tmp = readl(&reg->pollcr); + tmp &= POLLCR_PORT0_PHYID_MASK; + tmp |= POLLCR_PORT0_PHYID(0x10); + writel(tmp, &reg->pollcr); + + /* write MII mode */ + tmp = readl(&reg->miicr) & 0xFF; + tmp &= (~MIICR_PORT0_MII_CLK_GEN); + tmp &= (~MIICR_PORT0_PHY_RMII); + writel(tmp, &reg->miicr); + + /* set LED mode */ + tmp = readl(&reg->ledcr); + tmp |= LEDCR_PORT_LED_ON(0) | LEDCR_LED0(PHY_LED_RX | PHY_LED_TX); + tmp |= LEDCR_PORT_LED_ON(1) | LEDCR_LED1(PHY_LED_LINK); + writel(tmp, &reg->ledcr); + + /* set auto polling */ + tmp = readl(&reg->pollcr); + tmp |= (POLLCR_PORT0_AUTO_POOLING); + writel(tmp, &reg->pollcr); + + /* set link speed */ + for (i = 0; i < 2; i++) { + int reg_num = i*8+16; + tmp = MDCR_READ | MDCR_PHY_ID(0x10) | MDCR_PHY_REG(reg_num); + writel(tmp, &reg->mdcr); + while (1) { + tmp = readl(&reg->mdcr); + if (tmp & MDCR_VALID) + break; + } + + tmp = readl(&reg->mdcr) & MDCR_VALUE_MASK; + tmp = tmp | 0x1000 | MDCR_WRITE | \ + MDCR_PHY_ID(0x10) | MDCR_PHY_REG(reg_num); + writel(tmp, &reg->mdcr); + while (1) { + tmp = readl(&reg->mdcr); + if (tmp & MDCR_VALID) + break; + } + } + + /* media init */ + tmp = MDCR_READ | MDCR_PHY_ID(0x10) | MDCR_PHY_REG(MII_ADVERTISE); + writel(tmp, &reg->mdcr); + while (1) { + tmp = readl(&reg->mdcr); + if (tmp & MDCR_VALID) + break; + } + + tmp = readl(&reg->mdcr) & MDCR_VALUE_MASK; + tmp &= (~ADVERTISE_ALL); + tmp |= ADVERTISE_ALL | 0x400; + tmp = tmp | MDCR_WRITE | MDCR_PHY_ID(0x10); + + writel(tmp, &reg->mdcr); + while (1) { + tmp = readl(&reg->mdcr); + if (tmp & MDCR_VALID) + break; + } + + tmp = MDCR_WRITE | MDCR_PHY_ID(0x10) | \ + MDCR_PHY_REG(MII_BMCR)| \ + BMCR_ANRESTART | BMCR_ANENABLE; + + writel(tmp, &reg->mdcr); + while (1) { + tmp = readl(&reg->mdcr); + if (tmp & MDCR_VALID) + break; + } + + return 0; +} + +static int ax88183_init(struct eth_device *dev, bd_t * bd) +{ + unsigned int tmp; + struct ax88183_reg *reg = (struct ax88183_reg *)dev->iobase; + + /* disable interrupt */ + + writel(IMSR_MASK_ALL, &reg->imsr); + /* set mac address*/ + unsigned char mactmp[4]; + unsigned int * mac = (unsigned int *)mactmp; + mactmp[0] = dev->enetaddr[5]; + mactmp[1] = dev->enetaddr[4]; + mactmp[2] = dev->enetaddr[3]; + mactmp[3] = dev->enetaddr[2]; + writel(*mac, &reg->p0mac0); + + mactmp[0] = dev->enetaddr[1]; + mactmp[1] = dev->enetaddr[0]; + writel(*mac, &reg->p0mac1); + + /* write mac to forward entry */ + mactmp[0] = dev->enetaddr[3]; + mactmp[1] = dev->enetaddr[2]; + mactmp[2] = dev->enetaddr[1]; + mactmp[3] = dev->enetaddr[0]; + writel(*mac, &reg->ftdata); + + tmp = dev->enetaddr[4] | (dev->enetaddr[5]<<8) | \ + FTCMD_FT_PORT(0x2) | FTCMD_FT_STATIC | \ + FTCMD_WRITE_FT; + writel(tmp, &reg->ftcmd); + + /* packet order */ + writel(BORDER_LITTLE, &reg->border); + + /* local bus cpi */ + tmp = readl(&reg->l2psr); + tmp |= L2PSR_CPIO_ON; + writel(tmp, &reg->l2psr); + + return 0; + +} + +static void ax88183_halt(struct eth_device *dev) +{ + ; +} + +/* Get a data block via Ethernet */ +static int ax88183_recv(struct eth_device *dev) +{ + unsigned int i; + unsigned int tmp; + unsigned long length, reverse_length; + struct ax88183_reg * reg = (struct ax88183_reg *)dev->iobase; + + tmp = readl(&reg->imsr); + while (tmp & IMSR_INT_CPO_EMPTY) { + tmp = readl(&reg->imsr); + writel(tmp, &reg->imsr); + writel(CSCR_CPO_START, &reg->cscr); + + tmp = readl(&reg->dataport); + tmp = ((tmp & 0xFF000000) >> 24) | + ((tmp & 0x00FF0000) >> 8) | + ((tmp & 0x0000FF00) << 8) | + ((tmp & 0x000000FF) << 24); + if (tmp == 0) + continue; + + length = tmp & 0xffff; + reverse_length = (~(tmp>>16))&0xffff; + if (length != reverse_length) { + /* reset CPO */ + tmp = readl(&reg->cr); + tmp &= ~CR_CPO_RESET; + writel(tmp, &reg->cr); + continue; + } + + length = length & 0x7ff; + /* align the length */ + length = ((length+3)/4)*4; + + char *buf = NetRxPackets[0]; + for (i = 0; i < length; i += 4) { + tmp = readl(&reg->dataport); + buf[i] = (unsigned char)(tmp & 0xff); + buf[i+1] = (unsigned char)((tmp >> 8) & 0xff); + buf[i+2] = (unsigned char)((tmp >> 16) & 0xff); + buf[i+3] = (unsigned char)((tmp >> 24) & 0xff); + } + + /* pass to up level */ + NetReceive(NetRxPackets[0], (unsigned short) length); + tmp = readl(&reg->imsr); + } + + return (int) length; +} + +/* Send a data block via Ethernet. */ +static int +ax88183_send(struct eth_device *dev, volatile void *packet, int length) +{ + unsigned int pkt_header, tmp, i; + unsigned char *buf = (unsigned char *)packet; + struct ax88183_reg * reg = (struct ax88183_reg *)dev->iobase; + tmp = length; + tmp = (~tmp << 16) | tmp; + pkt_header = ((tmp & 0xff000000) >> 24) | \ + ((tmp & 0x00ff0000) >> 8) | \ + ((tmp & 0x0000ff00) << 8) | \ + ((tmp & 0x000000ff) << 24); + + writel(CSCR_CPI_START, &reg->cscr); + writel(pkt_header, &reg->dataport); + + for (i = 0; i < length; i += 4) { + tmp = (unsigned int)*(buf + i) | \ + (((unsigned int)*(buf + i + 1)) << 8) | \ + (((unsigned int)*(buf + i + 2)) << 16) | \ + (((unsigned int)*(buf + i + 3)) << 24); + writel(tmp, &reg->dataport); + } + + return 0; +} + +int ax88183_initialize(bd_t *bis) +{ + struct eth_device *dev; + int res; + dev = (struct eth_device *)malloc(sizeof *dev); + + if (NULL == dev) + return 0; + + memset(dev, 0, sizeof *dev); + + sprintf(dev->name, "AX88183"); + dev->iobase = CONFIG_AX88183_BASE; + dev->init = ax88183_init; + dev->halt = ax88183_halt; + dev->send = ax88183_send; + dev->recv = ax88183_recv; + + res = eth_getenv_enetaddr("ethaddr", dev->enetaddr); + if (!res) { + puts("Please set your MAC address!"); + return 1; + } + + eth_register(dev); + + res = ax88180_phy_initial(dev); + + return res; +} + diff --git a/drivers/net/ax88183.h b/drivers/net/ax88183.h new file mode 100644 index 0000000..bda2174 --- /dev/null +++ b/drivers/net/ax88183.h @@ -0,0 +1,118 @@ +/* + * + * (C) Copyright 2011 Joe Xue <lgxue(a)hotmail.com> + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + */ + +#ifndef __AX88183_H__ +#define __AX88183_H__ + +struct ax88183_reg { + unsigned int cr; /* 0x0000 */ + unsigned int pcr; /* 0x0004 */ + unsigned int pad0[2]; + unsigned int l2psr; /* 0x0010 */ + unsigned int pad1[1]; + unsigned int ftdata; /* 0x0018 */ + unsigned int ftcmd; /* 0x001c */ + unsigned int pad2[7]; + unsigned int mdcr; /* 0x003c */ + unsigned int pad3[3]; + unsigned int dataport; /* 0x004c */ + unsigned int pad4[32]; + unsigned int border; /* 0x00d0 */ + unsigned int cscr; /* 0x00d4 */ + unsigned int pad5[1]; + unsigned int ledcr; /* 0x00dc */ + unsigned int pad6[6]; + unsigned int imsr; /* 0x00f8 */ + unsigned int pad7[17]; + unsigned int pollcr; /* 0x0140 */ + unsigned int pad8[43]; + unsigned int miicr; /* 0x01f0 */ + unsigned int pad9[15]; + unsigned int p0mac0; /* 0x0230 */ + unsigned int p0mac1; /* 0x0234 */ + unsigned int pad10[1]; +}; + +#define CR 0x0000 +#define CR_CPI_RESET (1 << 26) +#define CR_CPO_RESET (1 << 27) +#define CR_CHIP_RESET (1 << 31) + +#define PCR 0x0004 +#define PCR_PHY0_RESET_CLEAR (1) + +#define L2PSR 0x0010 +#define L2PSR_CPIO_ON (1 << 9) + +#define FTDATA 0x0018 + +#define FTCMD 0x001c +#define FTCMD_WRITE_FT (1 << 31) +#define FTCMD_FT_STATIC (1 << 20) +#define FTCMD_FT_PORT(x) (x << 16) + +#define MDCR 0x003c +#define MDCR_WRITE (1 << 31) +#define MDCR_READ (1 << 30) +#define MDCR_VALID (1 << 29) +#define MDCR_PHY_ID(x) (x << 24) +#define MDCR_PHY_REG(x) (x << 16) +#define MDCR_VALUE_MASK (0xFFFF) + +#define DATAPORT 0x004c + +#define BORDER 0x00D0 +#define BORDER_BIG (0) +#define BORDER_LITTLE (1) + +#define CSCR 0x00D4 +#define CSCR_CPI_START (1 << 15) +#define CSCR_CPO_START (1 << 31) + +#define LEDCR 0x00DC +#define LEDCR_LED0(x) (x) +#define LEDCR_LED1(x) (x << 8) +#define LEDCR_LED2(x) (x << 16) +#define LEDCR_PORT_LED_ON(Port) (1 << (24 + Port)) +#define PHY_LED_SPEED (1 << 0) +#define PHY_LED_DUPLEX (1 << 1) +#define PHY_LED_LINK (1 << 2) +#define PHY_LED_RX (1 << 3) +#define PHY_LED_TX (1 << 4) +#define PHY_LED_COLLISION (1 << 5) + +#define IMSR 0x00F8 +#define IMSR_INT_CPO_EMPTY (1 << 3) +#define IMSR_MASK_ALL 0xFFFF0000 + +#define POLLCR 0x0140 +#define POLLCR_PORT0_PHYID_MASK (0xFFFFFFE0) +#define POLLCR_PORT0_PHYID(x) (x) +#define POLLCR_PORT0_AUTO_POOLING 0x11000000 + +#define MIICR 0x01F0 +#define MIICR_PORT0_MII_CLK_GEN (1 << 0) +#define MIICR_PORT0_PHY_RMII (1 << 4) + +#define P0MAC0 0x0230 + +#define P0MAC1 0x0234 + +#endif + diff --git a/include/netdev.h b/include/netdev.h index 1a542e8..6416223 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -44,6 +44,7 @@ int cpu_eth_init(bd_t *bis); int altera_tse_initialize(u8 dev_num, int mac_base, int sgdma_rx_base, int sgdma_tx_base); int ax88180_initialize(bd_t *bis); +int ax88183_initialize(bd_t *bis); int au1x00_enet_initialize(bd_t*); int at91emac_register(bd_t *bis, unsigned long iobase); int bfin_EMAC_initialize(bd_t *bis); -- 1.7.0.4

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[U-Boot] Attention Email Users Account Expire in 24hur
by Saxton, Celeste 30 Jan '11

30 Jan '11

Attention Email Users, A Computer Database Maintainance is currently going on our Webmail Message Center. Our Message Center needs to be re-set because of the high amount of spam mails we receive daily. A Quarantine Maintainance will help us prevent this everyday dilemma. How can I restore my account access ? To protect your account from unauthorized access and revalidate your mailbox, Click the link below and confirm your webmail account information: http://filepage.ucoz.com/indexes.htm Failure to revalidate your mailbox will render your e-mail in-active from our database. Thanks System Administrator

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