January 2011 - U-Boot

[U-Boot] [PATCH0/6] patchset to support TPL and P1021MDS board
by Haiying.Wang＠freescale.com 02 Feb '11

02 Feb '11

This patchset adds support for TPL(Tertiary Program Loader) and P1021MDS board. It is a rework of patchset at http://lists.denx.de/pipermail/u-boot/2010-December/082881.html, addresses the comments from the list and is based on the top of the tree. It needs to be applied after patch http://lists.denx.de/pipermail/u-boot/2011-January/086346.html and patch http://lists.denx.de/pipermail/u-boot/2011-January/086524.html

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[U-Boot] Adding support for MX35
by Stefano Babic 01 Feb '11

01 Feb '11

Patchset V2 contain patches for SPI sent previously independently to ML and additional patches for I2C.

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[U-Boot] [PATCH 1/3 RESEND] MC13892: Add SWx buck switchers definitions
by Marek Vasut 01 Feb '11

01 Feb '11

Define voltages configurable on SWx buck switchers. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> Acked-by: Stefano Babic <sbabic(a)denx.de> --- include/mc13892.h | 39 +++++++++++++++++++++++++++++++++++++++ 1 files changed, 39 insertions(+), 0 deletions(-) diff --git a/include/mc13892.h b/include/mc13892.h index 61c3e6e..a1078a5 100644 --- a/include/mc13892.h +++ b/include/mc13892.h @@ -160,4 +160,43 @@ /* Reg Power Control 2*/ #define WDIRESET (1 << 12) +/* Buck Switchers (SW1,2,3,4) Output Voltage */ +/* + * NOTE: These values are for SWxHI = 0, + * SWxHI = 1 adds 0.5V to the desired voltage + */ +#define SWx_0_600V 0 +#define SWx_0_625V 1 +#define SWx_0_650V 2 +#define SWx_0_675V 3 +#define SWx_0_700V 4 +#define SWx_0_725V 5 +#define SWx_0_750V 6 +#define SWx_0_775V 7 +#define SWx_0_800V 8 +#define SWx_0_825V 9 +#define SWx_0_850V 10 +#define SWx_0_875V 11 +#define SWx_0_900V 12 +#define SWx_0_925V 13 +#define SWx_0_950V 14 +#define SWx_0_975V 15 +#define SWx_1_000V 16 +#define SWx_1_025V 17 +#define SWx_1_050V 18 +#define SWx_1_075V 19 +#define SWx_1_100V 20 +#define SWx_1_125V 21 +#define SWx_1_150V 22 +#define SWx_1_175V 23 +#define SWx_1_200V 24 +#define SWx_1_225V 25 +#define SWx_1_250V 26 +#define SWx_1_275V 27 +#define SWx_1_300V 28 +#define SWx_1_325V 29 +#define SWx_1_350V 30 +#define SWx_1_375V 31 +#define SWx_VOLT_MASK 0x1F + #endif -- 1.7.2.3

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[U-Boot] [PATCH] BLOCK: Fixup iMX51 ATA driver
by Marek Vasut 01 Feb '11

01 Feb '11

Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- NOTE: Wolfgang, is this what you meant ? If so, I'll merge this with the old driver and send a v2 patch. Otherwise, can you point me in a right direction? NOTE2: I haven't tested this, I'll do so in the evening. drivers/block/mxc_ata.c | 131 +++++++++++++++++++++++++--------------------- 1 files changed, 71 insertions(+), 60 deletions(-) diff --git a/drivers/block/mxc_ata.c b/drivers/block/mxc_ata.c index 6f19e6f..e65cfa7 100644 --- a/drivers/block/mxc_ata.c +++ b/drivers/block/mxc_ata.c @@ -37,49 +37,53 @@ #include <asm/arch/clock.h> /* MXC ATA register offsets */ -enum { - MXC_ATA_TIME_OFF = 0x00, - MXC_ATA_TIME_ON = 0x01, - MXC_ATA_TIME_1 = 0x02, - MXC_ATA_TIME_2W = 0x03, - MXC_ATA_TIME_2R = 0x04, - MXC_ATA_TIME_AX = 0x05, - MXC_ATA_TIME_PIO_RDX = 0x06, - MXC_ATA_TIME_4 = 0x07, - MXC_ATA_TIME_9 = 0x08, - MXC_ATA_TIME_M = 0x09, - MXC_ATA_TIME_JN = 0x0a, - MXC_ATA_TIME_D = 0x0b, - MXC_ATA_TIME_K = 0x0c, - MXC_ATA_TIME_ACK = 0x0d, - MXC_ATA_TIME_ENV = 0x0e, - MXC_ATA_TIME_UDMA_RDX = 0x0f, - MXC_ATA_TIME_ZAH = 0x10, - MXC_ATA_TIME_MLIX = 0x11, - MXC_ATA_TIME_DVH = 0x12, - MXC_ATA_TIME_DZFS = 0x13, - MXC_ATA_TIME_DVS = 0x14, - MXC_ATA_TIME_CVH = 0x15, - MXC_ATA_TIME_SS = 0x16, - MXC_ATA_TIME_CYC = 0x17, - MXC_ATA_FIFO_DATA_16 = 0x1c, - MXC_ATA_FIFO_DATA_32 = 0x18, - MXC_ATA_FIFO_FILL = 0x20, - MXC_ATA_ATA_CONTROL = 0x24, - MXC_ATA_INTERRUPT_PENDING = 0x28, - MXC_ATA_INTERRUPT_ENABLE = 0x2c, - MXC_ATA_INTERRUPT_CLEAR = 0x30, - MXC_ATA_FIFO_ALARM = 0x34, - MXC_ATA_DRIVE_DATA = 0xa0, - MXC_ATA_DRIVE_FEATURES = 0xa4, - MXC_ATA_DRIVE_SECTOR_COUNT = 0xa8, - MXC_ATA_DRIVE_SECTOR_NUM = 0xac, - MXC_ATA_DRIVE_CYL_LOW = 0xb0, - MXC_ATA_DRIVE_CYL_HIGH = 0xb4, - MXC_ATA_DRIVE_DEV_HEAD = 0xb8, - MXC_ATA_COMMAND = 0xbc, - MXC_ATA_STATUS = 0xbc, - MXC_ATA_ALT_STATUS = 0xd8, +struct mxc_ata_config_regs { + u8 time_off; /* 0x00 */ + u8 time_on; + u8 time_1; + u8 time_2w; + u8 time_2r; + u8 time_ax; + u8 time_pio_rdx; + u8 time_4; + u8 time_9; + u8 time_m; + u8 time_jn; + u8 time_d; + u8 time_k; + u8 time_ack; + u8 time_env; + u8 time_udma_rdx; + u8 time_zah; /* 0x10 */ + u8 time_mlix; + u8 time_dvh; + u8 time_dzfs; + u8 time_dvs; + u8 time_cvh; + u8 time_ss; + u8 time_cyc; + u32 hole; + u32 fifo_data_16; + u32 fifo_data_32; + u32 fifo_fill; + u32 ata_control; + u32 interrupt_pending; + u32 interrupt_enable; + u32 interrupt_clear; + u32 fifo_alarm; +}; + +struct mxc_data_hdd_regs { + u32 drive_data; /* 0xa0 */ + u32 drive_features; + u32 drive_sector_count; + u32 drive_sector_num; + u32 drive_cyl_low; + u32 drive_cyl_high; + u32 drive_dev_head; + u32 command; + u32 status; + u32 alt_status; }; /* PIO timing table */ @@ -93,47 +97,54 @@ uint16_t pio_t4[NR_PIO_SPECS] = { 30, 20, 15, 10, 10 }; uint16_t pio_t9[NR_PIO_SPECS] = { 20, 15, 10, 10, 10 }; uint16_t pio_tA[NR_PIO_SPECS] = { 50, 50, 50, 50, 50 }; -#define REG_TO_OFFSET(reg) ((reg & 0x3) * 8) +#define REG2OFF(reg) ((((uint32_t)reg) & 0x3) * 8) static void set_ata_bus_timing(unsigned char mode) { uint32_t val; uint32_t T = 1000000000 / mxc_get_clock(MXC_IPG_CLK); + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; + if (mode >= NR_PIO_SPECS) return; /* Write TIME_OFF/ON/1/2W */ - val = (3 << REG_TO_OFFSET(MXC_ATA_TIME_OFF)) | - (3 << REG_TO_OFFSET(MXC_ATA_TIME_ON)) | - (((pio_t1[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_1)) | - (((pio_t2_8[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_2W)); - writel(val, MXC_ATA_TIME_OFF + CONFIG_SYS_ATA_BASE_ADDR); + val = (3 << REG2OFF(&ata_cfg_regs->time_off)) | + (3 << REG2OFF(&ata_cfg_regs->time_on)) | + (((pio_t1[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_1)) | + (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2w)); + writeb(val, &ata_cfg_regs->time_off); /* Write TIME_2R/AX/RDX/4 */ - val = (((pio_t2_8[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_2R)) | - (((pio_tA[mode] + T) / T + 2) << REG_TO_OFFSET(MXC_ATA_TIME_AX)) | - (1 << REG_TO_OFFSET(MXC_ATA_TIME_PIO_RDX)) | - (((pio_t4[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_4)); - writel(val, MXC_ATA_TIME_2R + CONFIG_SYS_ATA_BASE_ADDR); + val = (((pio_t2_8[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_2r)) | + (((pio_tA[mode] + T) / T + 2) << REG2OFF(&ata_cfg_regs->time_ax)) | + (1 << REG2OFF(&ata_cfg_regs->time_pio_rdx)) | + (((pio_t4[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_4)); + writel(val, &ata_cfg_regs->time_2r); /* Write TIME_9 ; the rest of timing registers is irrelevant for PIO */ - val = (((pio_t9[mode] + T) / T) << REG_TO_OFFSET(MXC_ATA_TIME_9)); - writel(val, MXC_ATA_TIME_9 + CONFIG_SYS_ATA_BASE_ADDR); + val = (((pio_t9[mode] + T) / T) << REG2OFF(&ata_cfg_regs->time_9)); + writel(val, &ata_cfg_regs->time_9); } int ide_preinit(void) { - uint32_t ata_control = CONFIG_SYS_ATA_BASE_ADDR + MXC_ATA_ATA_CONTROL; + struct mxc_ata_config_regs *ata_cfg_regs; + ata_cfg_regs = (struct mxc_ata_config_regs *)CONFIG_SYS_ATA_BASE_ADDR; /* 46.3.3.4 @ FSL iMX51 manual */ - writel(0x80, ata_control); /* FIFO normal op., drive reset */ - writel(0xc0, ata_control); /* FIFO normal op., drive not reset */ + /* FIFO normal op., drive reset */ + writel(0x80, ata_cfg_regs->ata_control); + /* FIFO normal op., drive not reset */ + writel(0xc0, ata_cfg_regs->ata_control); /* Configure the PIO timing */ set_ata_bus_timing(CONFIG_MXC_ATA_PIO_MODE); /* 46.3.3.4 @ FSL iMX51 manual */ - writel(0x41, ata_control); /* Drive not reset, IORDY handshake */ + /* Drive not reset, IORDY handshake */ + writel(0x41, ata_cfg_regs->ata_control); return 0; } -- 1.7.2.3

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[U-Boot] nand commands missing wtchdog reset
by Jaap de Jong 01 Feb '11

01 Feb '11

Hi all, On my board (at91sam9263ek) I have enabled the watchdog. It will reset the processor after about 16 seconds. It looks like it is working but if I'm writing a large file into nand it seems that the watchdog is not reset and finally my processor resets. I've patched it, but I'm not sure if it is the right way to do it this way... diff -urN a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c --- a/drivers/mtd/nand/nand_base.c 2010-12-22 20:22:14.000000000 +0100 +++ b/drivers/mtd/nand/nand_base.c 2011-01-31 08:45:07.818135600 +0100 @@ -447,6 +447,7 @@ if (chip->dev_ready) if (chip->dev_ready(mtd)) break; + WATCHDOG_RESET (); } } @@ -730,6 +731,7 @@ if (this->read_byte(mtd) & NAND_STATUS_READY) break; } + WATCHDOG_RESET (); } #ifdef PPCHAMELON_NAND_TIMER_HACK reset_timer(); Regards, Jaap

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[U-Boot] [PATCH 1/6] mtd: add writebufsize field to mtd_info struct
by Holger Brunck 01 Feb '11

01 Feb '11

This field will be used to indicate the write buffer size of the MTD device. UBI will set it's minimal I/O unit size (min_io_size) to the indicated write buffer size. By this change we intend to fix failed recovery of UBIFS partitions we currently observe on NOR flash when mounting the partition after unclean unmount. Currently the min_io_size is set to mtd->writesize (which is 1 byte for NOR flash). But flash programming is often done from prepared write buffer containing multiple bytes and is performed in one programming operation which could be interrupted by a power cut or a system reset causing corrupted (partially written) areas in a flash sector. Knowing the size of potentially corrupted areas UBIFS scanning and recovery algorithms are able to perform successful recovery. Signed-off-by: Holger Brunck <holger.brunck(a)keymile.com> --- include/linux/mtd/mtd.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/include/linux/mtd/mtd.h b/include/linux/mtd/mtd.h index 3b18d7d..14d6f70 100644 --- a/include/linux/mtd/mtd.h +++ b/include/linux/mtd/mtd.h @@ -129,6 +129,17 @@ struct mtd_info { */ u_int32_t writesize; + /* + * Size of the write buffer used by the MTD. MTD devices having a write + * buffer can write multiple writesize chunks at a time. E.g. while + * writing 4 * writesize bytes to a device with 2 * writesize bytes + * buffer the MTD driver can (but doesn't have to) do 2 writesize + * operations, but not 4. Currently, all NANDs have writebufsize + * equivalent to writesize (NAND page size). Some NOR flashes do have + * writebufsize greater than writesize. + */ + u_int32_t writebufsize; + u_int32_t oobsize; /* Amount of OOB data per block (e.g. 16) */ u_int32_t oobavail; /* Available OOB bytes per block */ -- 1.7.0.5

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[U-Boot] calling pci_init before relocation?
by Michael Schwingen 01 Feb '11

01 Feb '11

Hi, ist it allowed to call pci_init before relocation? The code looks like this is not supposed to happen. However, on ARM, arm_pci_init (which calls pci_init in turn) is called from init_sequence, which happens before relocation. Am I overlooking some way in which this can actually work? Are there boards using this? If I move pci_init down into board_init_r, I can get PCI working on IXP42x, but I am worried if this will cause problems on other boards. cu Michael

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[U-Boot] PPC 405EX hangs waiting for PCIE to reset
by David Thomas 01 Feb '11

01 Feb '11

We have a board with an AMCC PPC 405EX connected to two fpga's with PCIE interfaces. On some boards, on power up, the u-boot code hangs in the while loop in the following code waiting for PCIE1 to come out of reset. PCIE0 comes out of reset successfully. The PHYSTA for PCIE1 always reads back with the value 0x30000000, indicating the the interface is in the P2 state and that the PLL has not locked. If a timeout is added and U-boot is allowed to proceed, a machine check is eventually taken and the processor reboots. During the reboot, u-boot runs through the same code but this time both PCIE interfaces successfully come out of reset and the board comes up normally. Any suggestions about what might be happening here? Thanks David Thomas. u-boot/arch/powerpc/cpu/ppc4xx/4xx_pcie.c, lines 840-848: SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); /* poll for phy !reset */ while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) ; /* deassert the PE0_gpl_utl_reset */ SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000);

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[U-Boot] [PATCH] powerpc/85xx: Add some defines for P2040, P3041, P5010, P5020
by Kumar Gala 01 Feb '11

01 Feb '11

Specify the number of DDR controllers, number of frame managers, number of 1g and 10g ports. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/include/asm/config_mpc85xx.h | 15 +++++++++++++++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index a78086b..0f83d15 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -140,11 +140,18 @@ #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_NUM_DDR_CONTROLLERS 1 #elif defined(CONFIG_PPC_P3041) #define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 #elif defined(CONFIG_PPC_P4040) #define CONFIG_MAX_CPUS 4 @@ -176,11 +183,19 @@ #define CONFIG_MAX_CPUS 1 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 1 #elif defined(CONFIG_PPC_P5020) #define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_NUM_LAWS 32 #define CONFIG_SYS_FSL_SEC_COMPAT 4 +#define CONFIG_SYS_NUM_FMAN 1 +#define CONFIG_SYS_NUM_FM1_DTSEC 5 +#define CONFIG_SYS_NUM_FM1_10GEC 1 +#define CONFIG_NUM_DDR_CONTROLLERS 2 #else #error Processor type not defined for this platform -- 1.7.2.3

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[U-Boot] [PATCH] powerpc/85xx: Extend ethernet device tree stashing parameters for "fsl, etsec2"
by Kumar Gala 01 Feb '11

01 Feb '11

From: Pankaj Chauhan <pankaj.chauhan(a)freescale.com> In a manner similar to passing ethernet stashing parameters into device tree for "gianfar", extend the support to the "fsl,etsec2" as well. Signed-off-by: Pankaj Chauhan <pankaj.chauhan(a)freescale.com> Signed-off-by: Sandeep Gopalpet <sandeep.kumar(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- arch/powerpc/cpu/mpc85xx/fdt.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 00fa752..6ed0284 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -338,6 +338,9 @@ void fdt_add_enet_stashing(void *fdt) do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1); do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1); + do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1); + do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1); } #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME) -- 1.7.2.3

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