September 2010 - U-Boot

[U-Boot] [PATCH 1/4] tools: enable img2srec for "all" target
by Mike Frysinger 15 Nov '10

15 Nov '10

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- tools/Makefile | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index 749d994..ea271bf 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -41,6 +41,7 @@ include $(TOPDIR)/config.mk # Enable all the config-independent tools ifneq ($(HOST_TOOLS_ALL),) CONFIG_LCD_LOGO = y +CONFIG_CMD_LOADS = y CONFIG_CMD_NET = y CONFIG_INCA_IP = y CONFIG_NETCONSOLE = y -- 1.7.2

5 20

[U-Boot] [PATCH 1/5] e1000: Clean up handling of dual-port NICs and support 82571
by Kyle Moffett 15 Nov '10

15 Nov '10

Consolidate the test for a dual-port NIC to one location for easy modification, then fix support for the dual-port 82571. Signed-off-by: Kyle Moffett <Kyle.D.Moffett(a)boeing.com> --- drivers/net/e1000.c | 66 +++++++++++++++++++++++++------------------------- drivers/net/e1000.h | 6 ---- 2 files changed, 33 insertions(+), 39 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 2825342..28cedf7 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1096,6 +1096,20 @@ e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask) return E1000_SUCCESS; } +static boolean_t e1000_is_second_port(struct e1000_hw *hw) +{ + switch (hw->mac_type) { + case e1000_80003es2lan: + case e1000_82546: + case e1000_82571: + if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) + return TRUE; + /* Fallthrough */ + default: + return FALSE; + } +} + /****************************************************************************** * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the * second function of dual function devices @@ -1122,11 +1136,11 @@ e1000_read_mac_addr(struct eth_device *nic) nic->enetaddr[i] = eeprom_data & 0xff; nic->enetaddr[i + 1] = (eeprom_data >> 8) & 0xff; } - if ((hw->mac_type == e1000_82546) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { - /* Invert the last bit if this is the second device */ - nic->enetaddr[5] += 1; - } + + /* Invert the last bit if this is the second device */ + if (e1000_is_second_port(hw)) + nic->enetaddr[5] ^= 1; + #ifdef CONFIG_E1000_FALLBACK_MAC if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) { unsigned char fb_mac[NODE_ADDRESS_SIZE] = CONFIG_E1000_FALLBACK_MAC; @@ -2528,16 +2542,13 @@ e1000_check_mng_mode(struct e1000_hw *hw) static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) { + uint16_t swfw = E1000_SWFW_PHY0_SM; uint32_t reg_val; - uint16_t swfw; DEBUGFUNC(); - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + if (e1000_is_second_port(hw)) swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } + if (e1000_swfw_sync_acquire(hw, swfw)) return -E1000_ERR_SWFW_SYNC; @@ -2552,16 +2563,13 @@ e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data) static int32_t e1000_read_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *data) { + uint16_t swfw = E1000_SWFW_PHY0_SM; uint32_t reg_val; - uint16_t swfw; DEBUGFUNC(); - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + if (e1000_is_second_port(hw)) swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } + if (e1000_swfw_sync_acquire(hw, swfw)) return -E1000_ERR_SWFW_SYNC; @@ -4259,11 +4267,13 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) default: mdelay(10); break; + case e1000_80003es2lan: /* Separate *_CFG_DONE_* bit for each port */ - if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1) + if (e1000_is_second_port(hw)) cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1; - /* Fall Through */ + /* Fall Through */ + case e1000_82571: case e1000_82572: while (timeout) { @@ -4292,10 +4302,10 @@ e1000_get_phy_cfg_done(struct e1000_hw *hw) int32_t e1000_phy_hw_reset(struct e1000_hw *hw) { + uint16_t swfw = E1000_SWFW_PHY0_SM; uint32_t ctrl, ctrl_ext; uint32_t led_ctrl; int32_t ret_val; - uint16_t swfw; DEBUGFUNC(); @@ -4308,16 +4318,14 @@ e1000_phy_hw_reset(struct e1000_hw *hw) DEBUGOUT("Resetting Phy...\n"); if (hw->mac_type > e1000_82543) { - if ((hw->mac_type == e1000_80003es2lan) && - (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) { + if (e1000_is_second_port(hw)) swfw = E1000_SWFW_PHY1_SM; - } else { - swfw = E1000_SWFW_PHY0_SM; - } + if (e1000_swfw_sync_acquire(hw, swfw)) { DEBUGOUT("Unable to acquire swfw sync\n"); return -E1000_ERR_SWFW_SYNC; } + /* Read the device control register and assert the E1000_CTRL_PHY_RST * bit. Then, take it out of reset. */ @@ -4771,14 +4779,6 @@ e1000_sw_init(struct eth_device *nic, int cardnum) break; } - /* lan a vs. lan b settings */ - if (hw->mac_type == e1000_82546) - /*this also works w/ multiple 82546 cards */ - /*but not if they're intermingled /w other e1000s */ - hw->lan_loc = (cardnum % 2) ? e1000_lan_b : e1000_lan_a; - else - hw->lan_loc = e1000_lan_a; - /* flow control settings */ hw->fc_high_water = E1000_FC_HIGH_THRESH; hw->fc_low_water = E1000_FC_LOW_THRESH; diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index eb0804b..8597e23 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -111,11 +111,6 @@ typedef enum { e1000_100_full = 3 } e1000_speed_duplex_type; -typedef enum { - e1000_lan_a = 0, - e1000_lan_b = 1 -} e1000_lan_loc; - /* Flow Control Settings */ typedef enum { e1000_fc_none = 0, @@ -1055,7 +1050,6 @@ struct e1000_hw { uint32_t phy_init_script; uint32_t txd_cmd; e1000_media_type media_type; - e1000_lan_loc lan_loc; e1000_fc_type fc; e1000_bus_type bus_type; #if 0 -- 1.7.1

2 5

[U-Boot] [PATCH NET 1/2] Net: Remove redundant CONFIG_NET_MULTI directives
by Ben Warren 15 Nov '10

15 Nov '10

All are within an #ifdef CONFIG_NET_MULTI block already Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- net/eth.c | 16 ++++------------ 1 files changed, 4 insertions(+), 12 deletions(-) diff --git a/net/eth.c b/net/eth.c index 993306f..5c70d4f 100644 --- a/net/eth.c +++ b/net/eth.c @@ -263,7 +263,6 @@ int eth_initialize(bd_t *bis) dev = dev->next; } while(dev != eth_devices); -#ifdef CONFIG_NET_MULTI /* update current ethernet name */ if (eth_current) { char *act = getenv("ethact"); @@ -271,7 +270,6 @@ int eth_initialize(bd_t *bis) setenv("ethact", eth_current->name); } else setenv("ethact", NULL); -#endif putc ('\n'); } @@ -441,7 +439,7 @@ int eth_receive(volatile void *packet, int length) void eth_try_another(int first_restart) { static struct eth_device *first_failed = NULL; - char *ethrotate; + char *ethrotate, *act; /* * Do not rotate between network interfaces when @@ -460,21 +458,16 @@ void eth_try_another(int first_restart) eth_current = eth_current->next; -#ifdef CONFIG_NET_MULTI /* update current ethernet name */ - { - char *act = getenv("ethact"); - if (act == NULL || strcmp(act, eth_current->name) != 0) - setenv("ethact", eth_current->name); - } -#endif + act = getenv("ethact"); + if (act == NULL || strcmp(act, eth_current->name) != 0) + setenv("ethact", eth_current->name); if (first_failed == eth_current) { NetRestartWrap = 1; } } -#ifdef CONFIG_NET_MULTI void eth_set_current(void) { static char *act = NULL; @@ -501,7 +494,6 @@ void eth_set_current(void) setenv("ethact", eth_current->name); } -#endif char *eth_get_name (void) { -- 1.6.0.4

3 5

[U-Boot] [PATCH 1/3] mpc8641hpcn: Update PCI code
by Peter Tyser 14 Nov '10

14 Nov '10

Update to use the recent, common FSL PCI initialization code. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- I was making the same changes to X-ES code, so applied them to other users of the old PCI init code. I only compile tested them on these boards. board/freescale/mpc8641hpcn/mpc8641hpcn.c | 97 +++++++---------------------- 1 files changed, 22 insertions(+), 75 deletions(-) diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index fee310a..092ead6 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -142,56 +142,26 @@ int first_free_busno = 0; void pci_init_board(void) { + struct fsl_pci_info pci_info[2]; + int pcie_ep; + int num = 0; + #ifdef CONFIG_PCIE1 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; - struct pci_controller *hose = &pcie1_hose; - struct pci_region *r = hose->regions; volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; - uint devdisr = gur->devdisr; + uint devdisr = in_be32(&gur->devdisr); uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); -#ifdef DEBUG - uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) - >> MPC8641_PORBMSR_HA_SHIFT; - uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); -#endif if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { - debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); - debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); - if (pci->pme_msg_det) { - pci->pme_msg_det = 0xffffffff; - debug(" with errors. Clearing. Now 0x%08x", - pci->pme_msg_det); - } - debug("\n"); - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BUS, - CONFIG_SYS_PCIE1_MEM_PHYS, - CONFIG_SYS_PCIE1_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BUS, - CONFIG_SYS_PCIE1_IO_PHYS, - CONFIG_SYS_PCIE1_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 1 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); + SET_STD_PCIE_INFO(pci_info[num], 1); + pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); + printf(" PCIE1 connected to ULI as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie1_hose, first_free_busno); /* * Activate ULI1575 legacy chip by performing a fake @@ -201,45 +171,22 @@ void pci_init_board(void) + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000))); } else { - puts("PCI-EXPRESS 1: Disabled\n"); + puts(" PCIE1: disabled\n"); } -} #else - puts("PCI-EXPRESS1: Disabled\n"); + puts(" PCIE1: disabled\n"); #endif /* CONFIG_PCIE1 */ #ifdef CONFIG_PCIE2 -{ - volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; - struct pci_controller *hose = &pcie2_hose; - struct pci_region *r = hose->regions; - - /* outbound memory */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_MEM_BUS, - CONFIG_SYS_PCIE2_MEM_PHYS, - CONFIG_SYS_PCIE2_MEM_SIZE, - PCI_REGION_MEM); - - /* outbound io */ - pci_set_region(r++, - CONFIG_SYS_PCIE2_IO_BUS, - CONFIG_SYS_PCIE2_IO_PHYS, - CONFIG_SYS_PCIE2_IO_SIZE, - PCI_REGION_IO); - - hose->region_count = r - hose->regions; - - hose->first_busno=first_free_busno; - - fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); - - first_free_busno=hose->last_busno+1; - printf (" PCI-EXPRESS 2 on bus %02x - %02x\n", - hose->first_busno,hose->last_busno); -} + SET_STD_PCIE_INFO(pci_info[num], 2); + pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); + printf(" PCIE2 connected as %s (base addr %lx)\n", + pcie_ep ? "Endpoint" : "Root Complex", + pci_info[num].regs); + first_free_busno = fsl_pci_init_port(&pci_info[num++], + &pcie2_hose, first_free_busno); #else - puts("PCI-EXPRESS 2: Disabled\n"); + puts(" PCIE2: disabled\n"); #endif /* CONFIG_PCIE2 */ } -- 1.7.0.4

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[U-Boot] Pull request u-boot-marvell.git
by Prafulla Wadaskar 29 Oct '10

29 Oct '10

Hi Tom Pls pull The following changes since commit 376e7fadbad3285231e390c6534feb5af86d594b: Minkyu Kang (1): SAMSUNG: goni: add the GPL licence are available in the git repository at: u-boot-marvrell.git .. Master branch.. Albert Aribaud (3): Initial support for Marvell Orion5x SoC Add Orion5x support to 16550 device driver Add support for the LaCie ED Mini V2 board MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + arch/arm/cpu/arm926ejs/orion5x/Makefile | 55 +++++ arch/arm/cpu/arm926ejs/orion5x/cpu.c | 270 ++++++++++++++++++++++ arch/arm/cpu/arm926ejs/orion5x/dram.c | 64 +++++ arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S | 293 ++++++++++++++++++++++++ arch/arm/cpu/arm926ejs/orion5x/timer.c | 181 +++++++++++++++ arch/arm/include/asm/arch-orion5x/cpu.h | 203 ++++++++++++++++ arch/arm/include/asm/arch-orion5x/mv88f5182.h | 40 ++++ arch/arm/include/asm/arch-orion5x/orion5x.h | 69 ++++++ board/LaCie/edminiv2/Makefile | 53 +++++ board/LaCie/edminiv2/config.mk | 27 +++ board/LaCie/edminiv2/edminiv2.c | 92 ++++++++ drivers/serial/serial.c | 3 + include/configs/edminiv2.h | 172 ++++++++++++++ 16 files changed, 1530 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/orion5x/Makefile create mode 100644 arch/arm/cpu/arm926ejs/orion5x/cpu.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/dram.c create mode 100644 arch/arm/cpu/arm926ejs/orion5x/lowlevel_init.S create mode 100644 arch/arm/cpu/arm926ejs/orion5x/timer.c create mode 100644 arch/arm/include/asm/arch-orion5x/cpu.h create mode 100644 arch/arm/include/asm/arch-orion5x/mv88f5182.h create mode 100644 arch/arm/include/asm/arch-orion5x/orion5x.h create mode 100644 board/LaCie/edminiv2/Makefile create mode 100644 board/LaCie/edminiv2/config.mk create mode 100644 board/LaCie/edminiv2/edminiv2.c create mode 100644 include/configs/edminiv2.h Regards.. Prafulla . .

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[U-Boot] Is the Numonyx's M29W128 fully supported in U-Boot?
by txema lopez 28 Oct '10

28 Oct '10

Hi all, We have a MPC5200B custom board and we are evaluating the Numonyx M29W128 Flash as a second source for the Spansion's S29GL128. I've checked the top of the tree version of the U-Boot (u-boot.git) CFI driver and the Numonyx Flash is not detected. This is the U-Boot debug output: FLASH: flash detect cfi fwc addr fe000000 cmd f0 f0 8bit x 8 bit fwc addr fe000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fe000010 is= 0 51 fwc addr fe000000 cmd f0 f0f0 16bit x 8 bit fwc addr fe0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fe000020 is= 5100 5151 fwc addr fe000000 cmd f0 00f0 16bit x 16 bit fwc addr fe0000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr fe000020 is= 6d69 0051 fwc addr fe000000 cmd f0 f0f0f0f0 32bit x 8 bit fwc addr fe000154 cmd 98 98989898 32bit x 8 bit is= cmd 51(Q) addr fe000040 is= 4e6f7620 51515151 fwc addr fe000000 cmd f0 00f000f0 32bit x 16 bit fwc addr fe000154 cmd 98 00980098 32bit x 16 bit is= cmd 51(Q) addr fe000040 is= 4e6f7620 00510051 fwc addr fe000000 cmd f0 000000f0 32bit x 32 bit fwc addr fe000154 cmd 98 00000098 32bit x 32 bit is= cmd 51(Q) addr fe000040 is= 4e6f7620 00000051 fwrite addr fe000000 cmd f0 f0f0f0f0f0f0f0f0 64 bit x 8 bit fwrite addr fe0002a8 cmd 98 9898989898989898 64 bit x 8 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 5151515151515151 fwrite addr fe000000 cmd f0 00f000f000f000f0 64 bit x 16 bit fwrite addr fe0002a8 cmd 98 0098009800980098 64 bit x 16 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 0051005100510051 fwrite addr fe000000 cmd f0 000000f0000000f0 64 bit x 32 bit fwrite addr fe0002a8 cmd 98 0000009800000098 64 bit x 32 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 0000005100000051 fwrite addr fe000000 cmd f0 00000000000000f0 64 bit x 64 bit fwrite addr fe0002a8 cmd 98 0000000000000098 64 bit x 64 bit is= cmd 51(Q) addr fe000080 is= 0000000000000000 0000000000000051 not found ## Unknown FLASH on Bank 0 - Size = 0x00000000 = 0 MB This is the debug output for the Spansion Flash that works fine. FLASH: flash detect cfi fwc addr fe000000 cmd f0 f0 8bit x 8 bit fwc addr fe000055 cmd 98 98 8bit x 8 bit is= cmd 51(Q) addr fe000010 is= 0 51 fwc addr fe000000 cmd f0 f0f0 16bit x 8 bit fwc addr fe0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fe000020 is= 5151 5151 is= cmd 52(R) addr fe000022 is= 5252 5252 is= cmd 59(Y) addr fe000024 is= 5959 5959 ushort addr is at fe000050 info->portwidth = 2 addr[0] = 0x2 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 device interface is 2 found port 2 chip 1 port 16 bits chip 8 bits ushort addr is at fe000026 info->portwidth = 2 addr[0] = 0x2 addr[1] = 0x2 addr[2] = 0x0 addr[3] = 0x0 retval = 0x2 fe000020 : 51 51 52 52 59 59 02 02 00 00 40 40 00 00 00 00 QQRRYY....@@.... fe000030 : 00 00 00 00 00 00 27 27 36 36 00 00 00 00 06 06 ......''66...... fe000040 : 06 06 09 09 13 13 03 03 05 05 03 03 02 02 18 18 ................ fe000050 : 02 02 00 00 06 06 00 00 01 01 7f 7f 00 00 00 00 ................ fe000060 : 02 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ fe000070 : 00 00 00 00 00 00 00 00 00 00 ff ff ff ff ff ff ................ fe000080 : 50 50 52 52 49 49 31 31 33 33 14 14 02 02 01 01 PPRRII1133...... fe000090 : 00 00 08 08 00 00 00 00 02 02 b5 b5 c5 c5 04 04 ................ manufacturer is 2 size_ratio 1 port 16 bits chip 8 bits found 1 erase regions long addr is at fe00005a info->portwidth = 2 addr[0] = 0x7f addr[1] = 0x7f addr[2] = 0x0 addr[3] = 0x0 addr[4] = 0x0 addr[5] = 0x0 addr[6] = 0x2 addr[7] = 0x2 erase_region_count = 128 erase_region_size = 131072 ushort addr is at fe000054 info->portwidth = 2 addr[0] = 0x6 addr[1] = 0x6 addr[2] = 0x0 addr[3] = 0x0 retval = 0x6 So the problem seems to be that the Numonyx Flash do not put the CFI query information in the odd bytes as you can see here: fwc addr fe000000 cmd f0 f0f0 16bit x 8 bit fwc addr fe0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr fe000020 is= 5100 5151 I've checked the U-Boot mainling list and I've found only something about a M29W128 bug but in a coldfire architecture. So I think the Numonyx Flash has been tested in some boards but I don't knwon if there is full support in U-Boot for it. If not, is there a patch available or in process? Any clue will be welcomed. TIA,

3 5

[U-Boot] [PATCH] Add generic support for samsung s3c2440
by C Nauman 28 Oct '10

28 Oct '10

This patch adds generic support for the Samsung s3c2440 processor. Started from patch posted 2009-06-19 by Kevin Morfitt. Then modified for changes in the code that have occurred since. Signed-off-by: Craig Nauman <cnauman <at> diagraph.com> --- diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h index 15f53dd..d4abd24 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0.h @@ -82,6 +82,10 @@ struct s3c24x0_interrupt { u32 SUBSRCPND; u32 INTSUBMSK; #endif +#ifdef CONFIG_S3C2440 + u32 SUBSRCPND; + u32 INTSUBMSK; +#endif }; @@ -91,10 +95,16 @@ struct s3c24x0_dma { #ifdef CONFIG_S3C2410 u32 DISRCC; #endif +#ifdef CONFIG_S3C2440 + u32 DISRCC; +#endif u32 DIDST; #ifdef CONFIG_S3C2410 u32 DIDSTC; #endif +#ifdef CONFIG_S3C2440 + u32 DIDSTC; +#endif u32 DCON; u32 DSTAT; u32 DCSRC; @@ -106,6 +116,9 @@ struct s3c24x0_dma { #ifdef CONFIG_S3C2410 u32 res[7]; #endif +#ifdef CONFIG_S3C2440 + u32 res[7]; +#endif }; struct s3c24x0_dmas { @@ -122,6 +135,9 @@ struct s3c24x0_clock_power { u32 CLKCON; u32 CLKSLOW; u32 CLKDIVN; +#if defined(CONFIG_S3C2440) + u32 CAMDIVN; +#endif }; @@ -147,9 +163,16 @@ struct s3c24x0_lcd { u32 LCDINTMSK; u32 LPCSEL; #endif +#ifdef CONFIG_S3C2440 + u32 LCDINTPND; + u32 LCDSRCPND; + u32 LCDINTMSK; + u32 LPCSEL; +#endif }; +#ifdef CONFIG_S3C2410 /* NAND FLASH (see S3C2410 manual chapter 6) */ struct s3c2410_nand { u32 NFCONF; @@ -159,6 +182,23 @@ struct s3c2410_nand { u32 NFSTAT; u32 NFECC; }; +#endif +#ifdef CONFIG_S3C2440 +/* NAND FLASH (see S3C2440 manual chapter 6) */ +struct s3c2440_nand { + u32 NFCONF; + u32 NFCONT; + u32 NFCMD; + u32 NFADDR; + u32 NFDATA; + u32 NFECCD0; + u32 NFECCD1; + u32 NFECCD; + u32 NFSTAT; + u32 NFSTAT0; + u32 NFSTAT1; +}; +#endif /* UART (see manual chapter 11) */ @@ -447,6 +487,65 @@ struct s3c24x0_gpio { u32 GSTATUS3; u32 GSTATUS4; #endif +#if defined(CONFIG_S3C2440) + u32 GPACON; + u32 GPADAT; + u32 res1[2]; + u32 GPBCON; + u32 GPBDAT; + u32 GPBUP; + u32 res2; + u32 GPCCON; + u32 GPCDAT; + u32 GPCUP; + u32 res3; + u32 GPDCON; + u32 GPDDAT; + u32 GPDUP; + u32 res4; + u32 GPECON; + u32 GPEDAT; + u32 GPEUP; + u32 res5; + u32 GPFCON; + u32 GPFDAT; + u32 GPFUP; + u32 res6; + u32 GPGCON; + u32 GPGDAT; + u32 GPGUP; + u32 res7; + u32 GPHCON; + u32 GPHDAT; + u32 GPHUP; + u32 res8; + + u32 MISCCR; + u32 DCLKCON; + u32 EXTINT0; + u32 EXTINT1; + u32 EXTINT2; + u32 EINTFLT0; + u32 EINTFLT1; + u32 EINTFLT2; + u32 EINTFLT3; + u32 EINTMASK; + u32 EINTPEND; + u32 GSTATUS0; + u32 GSTATUS1; + u32 GSTATUS2; + u32 GSTATUS3; + u32 GSTATUS4; + + u32 res9; + u32 DSC0; + u32 DSC1; + u32 MSLCON; + u32 GPJCON; + u32 GPJDAT; + u32 GPJUP; + u32 res10; +#endif }; diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h index c37d4a1..54184c4 100644 --- a/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h +++ b/arch/arm/include/asm/arch-s3c24x0/s3c24x0_cpu.h @@ -22,6 +22,8 @@ #include <asm/arch/s3c2400.h> #elif defined CONFIG_S3C2410 #include <asm/arch/s3c2410.h> +#elif defined CONFIG_S3C2440 + #include <asm/arch/s3c2440.h> #else #error Please define the s3c24x0 cpu type #endif diff --git a/arch/arm/include/asm/arch-s3c24x0/s3c2440.h b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h new file mode 100644 index 0000000..7e4518e --- /dev/null +++ b/arch/arm/include/asm/arch-s3c24x0/s3c2440.h @@ -0,0 +1,163 @@ +/* + * (C) Copyright 2003 + * David Müller ELSOFT AG Switzerland. d.mueller(a)elsoft.ch + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************ + * NAME : s3c2440.h + * Version : 31.3.2003 + * + * Based on S3C2440 User's manual Rev x.x + ************************************************/ + +#ifndef __S3C2440_H__ +#define __S3C2440_H__ + +#define S3C24X0_UART_CHANNELS 3 +#define S3C24X0_SPI_CHANNELS 2 + +/* S3C2440 only supports 512 Byte HW ECC */ +#define S3C2440_ECCSIZE 512 +#define S3C2440_ECCBYTES 3 + +enum s3c24x0_uarts_nr { + S3C24X0_UART0, + S3C24X0_UART1, + S3C24X0_UART2 +}; + +/* S3C2440 device base addresses */ +#define S3C24X0_MEMCTL_BASE 0x48000000 +#define S3C24X0_USB_HOST_BASE 0x49000000 +#define S3C24X0_INTERRUPT_BASE 0x4A000000 +#define S3C24X0_DMA_BASE 0x4B000000 +#define S3C24X0_CLOCK_POWER_BASE 0x4C000000 +#define S3C24X0_LCD_BASE 0x4D000000 +#define S3C2440_NAND_BASE 0x4E000000 +#define S3C24X0_UART_BASE 0x50000000 +#define S3C24X0_TIMER_BASE 0x51000000 +#define S3C24X0_USB_DEVICE_BASE 0x52000140 +#define S3C24X0_WATCHDOG_BASE 0x53000000 +#define S3C24X0_I2C_BASE 0x54000000 +#define S3C24X0_I2S_BASE 0x55000000 +#define S3C24X0_GPIO_BASE 0x56000000 +#define S3C24X0_RTC_BASE 0x57000000 +#define S3C2440_ADC_BASE 0x58000000 +#define S3C24X0_SPI_BASE 0x59000000 +#define S3C2440_SDI_BASE 0x5A000000 + + +/* include common stuff */ +#include <asm/arch/s3c24x0.h> + + +static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void) +{ + return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE; +} + +static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void) +{ + return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE; +} + +static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void) +{ + return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE; +} + +static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void) +{ + return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE; +} + +static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void) +{ + return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE; +} + +static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void) +{ + return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE; +} + +static inline struct s3c2440_nand *s3c2440_get_base_nand(void) +{ + return (struct s3c2440_nand *)S3C2440_NAND_BASE; +} + +static inline struct s3c24x0_uart + *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n) +{ + return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000)); +} + +static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void) +{ + return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE; +} + +static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void) +{ + return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE; +} + +static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void) +{ + return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE; +} + +static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void) +{ + return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE; +} + +static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void) +{ + return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE; +} + +static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void) +{ + return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE; +} + +static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void) +{ + return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE; +} + +static inline struct s3c2440_adc *s3c2440_get_base_adc(void) +{ + return (struct s3c2440_adc *)S3C2440_ADC_BASE; +} + +static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void) +{ + return (struct s3c24x0_spi *)S3C24X0_SPI_BASE; +} + +static inline struct s3c2440_sdi *s3c2440_get_base_sdi(void) +{ + return (struct s3c2440_sdi *)S3C2440_SDI_BASE; +} + +#endif /*__S3C2440_H__*/ diff --git a/arch/arm/cpu/arm920t/s3c24x0/speed.c b/arch/arm/cpu/arm920t/s3c24x0/speed.c index b13283a..0d7136c 100644 --- a/arch/arm/cpu/arm920t/s3c24x0/speed.c +++ b/arch/arm/cpu/arm920t/s3c24x0/speed.c @@ -64,7 +64,18 @@ static ulong get_PLLCLK(int pllreg) p = ((r & 0x003F0) >> 4) + 2; s = r & 0x3; +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) return (CONFIG_SYS_CLK_FREQ * m) / (p << s); +#elif defined(CONFIG_S3C2440) + /* To avoid integer overflow, changed the calc order */ + if (pllreg == MPLL) + return ( 2 * m * (CONFIG_SYS_CLK_FREQ / (p << s )) ); + else + return ( m * (CONFIG_SYS_CLK_FREQ / (p << s )) ); +#else +#error "get_PLLCLK not implemented for CPU type" +#endif + } /* return FCLK frequency */ @@ -77,8 +88,23 @@ ulong get_FCLK(void) ulong get_HCLK(void) { struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power(); - +#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK(); +#elif defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442) + switch (readl(&clk_power->CLKDIVN) & 0x6) { + case 0x0: + return get_FCLK(); + case 0x2: + return get_FCLK()/2; + case 0x4: + return (readl(&clk_power->CAMDIVN) & 0x200) ? get_FCLK()/8 : get_FCLK()/4; + case 0x6: + return (readl(&clk_power->CAMDIVN) & 0x100) ? get_FCLK()/6 : get_FCLK()/3; + } + return 0; +#else +#error "get_HCLK not implemented for CPU type" +#endif } /* return PCLK frequency */ -- Craig Nauman Diagraph an ITW Company cnauman at diagraph dot com

3 12

[U-Boot] [PATCH] mmc: seperate block number into small parts for multi-write cmd
by Lei Wen 27 Oct '10

27 Oct '10

As mmc host limitation, the max number of block in one go should be limited to 65535, and the max buffer size should not excceed 512k bytes. Signed-off-by: Lei Wen <leiwen(a)marvell.com> --- drivers/mmc/mmc.c | 56 +++++++++++++++++++++++++++++++++------------------- 1 files changed, 35 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 94d1ac2..ea398a5 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -77,29 +77,16 @@ struct mmc *find_mmc_device(int dev_num) return NULL; } -static ulong -mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) +int mmc_write_block(struct mmc *mmc, ulong *src, ulong start, uint blocknum) { struct mmc_cmd cmd; struct mmc_data data; - int err; - int stoperr = 0; - struct mmc *mmc = find_mmc_device(dev_num); - int blklen; - - if (!mmc) - return -1; - + int blklen, err; blklen = mmc->write_bl_len; - err = mmc_set_blocklen(mmc, mmc->write_bl_len); - - if (err) { - printf("set write bl len failed\n\r"); - return err; - } - - if (blkcnt > 1) + BUG_ON(blklen * blocknum > 524288); + BUG_ON(blocknum > 65535); + if (blocknum > 1) cmd.cmdidx = MMC_CMD_WRITE_MULTIPLE_BLOCK; else cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK; @@ -113,7 +100,7 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) cmd.flags = 0; data.src = src; - data.blocks = blkcnt; + data.blocks = blocknum; data.blocksize = blklen; data.flags = MMC_DATA_WRITE; @@ -124,14 +111,41 @@ mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) return err; } - if (blkcnt > 1) { + if (blocknum > 1) { cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION; cmd.cmdarg = 0; cmd.resp_type = MMC_RSP_R1b; cmd.flags = 0; - stoperr = mmc_send_cmd(mmc, &cmd, NULL); + mmc_send_cmd(mmc, &cmd, NULL); } + return blocknum; +} + +static ulong +mmc_bwrite(int dev_num, ulong start, lbaint_t blkcnt, const void*src) +{ + int err; + struct mmc *mmc = find_mmc_device(dev_num); + unsigned int max; + lbaint_t tmp = blkcnt, cur; + + if (!mmc) + return -1; + + err = mmc_set_blocklen(mmc, mmc->write_bl_len); + if (err) { + printf("set write bl len failed\n\r"); + return err; + } + + max = 524288 / mmc->write_bl_len; + do { + cur = (tmp > max) ? max : tmp; + tmp -= cur; + if(mmc_write_block(mmc, src, start, cur) != cur) + return -1; + } while (tmp > 0); return blkcnt; } -- 1.7.0.4

5 29

[U-Boot] [PATCH 3/3] mpc83xx: turn on icache in core initialization to improve u-boot boot time
by Kim Phillips 27 Oct '10

27 Oct '10

before, MPC8349ITX boots u-boot in 4.3sec: column1 is elapsed time since first message column2 is elapsed time since previous message column3 is the message 0.000 0.000: U-Boot 2010.03-00126-gfd4e49c (Apr 11 2010 - 17:25:29) MPC83XX 0.000 0.000: 0.000 0.000: Reset Status: 0.000 0.000: 0.032 0.032: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.032 0.000: Board: Freescale MPC8349E-mITX 0.032 0.000: UPMA: Configured for compact flash 0.032 0.000: I2C: ready 0.061 0.028: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 1.516 1.456: FLASH: 16 MB 2.641 1.125: PCI: Bus Dev VenId DevId Class Int 2.652 0.011: 00 10 1095 3114 0180 00 2.652 0.000: PCI: Bus Dev VenId DevId Class Int 2.652 0.000: In: serial 2.652 0.000: Out: serial 2.652 0.000: Err: serial 2.682 0.030: Board revision: 1.0 (PCF8475A) 3.080 0.398: Net: TSEC1: No support for PHY id ffffffff; assuming generic 3.080 0.000: TSEC0, TSEC1 4.300 1.219: IDE: Bus 0: .** Timeout ** after, MPC8349ITX boots u-boot in 3.0sec: 0.010 0.010: U-Boot 2010.03-00127-g4b468cc-dirty (Apr 11 2010 - 17:47:29) MPC83XX 0.010 0.000: 0.010 0.000: Reset Status: 0.010 0.000: 0.017 0.007: CPU: e300c1, MPC8349E, Rev: 1.1 at 533.333 MHz, CSB: 266.667 MHz 0.017 0.000: Board: Freescale MPC8349E-mITX 0.038 0.020: UPMA: Configured for compact flash 0.038 0.000: I2C: ready 0.038 0.000: DRAM: 256 MB (DDR1, 64-bit, ECC off, 266.667 MHz) 0.260 0.222: FLASH: 16 MB 1.390 1.130: PCI: Bus Dev VenId DevId Class Int 1.390 0.000: 00 10 1095 3114 0180 00 1.390 0.000: PCI: Bus Dev VenId DevId Class Int 1.400 0.010: In: serial 1.400 0.000: Out: serial 1.400 0.000: Err: serial 1.400 0.000: Board revision: 1.0 (PCF8475A) 1.832 0.432: Net: TSEC1: No support for PHY id ffffffff; assuming generic 1.832 0.000: TSEC0, TSEC1 3.038 1.205: IDE: Bus 0: .** Timeout ** also tested on these boards (albeit with a less accurate boottime measurement method): seconds: before after 8349MDS ~2.6 ~2.2 8360MDS ~2.8 ~2.6 8313RDB ~2.5 ~2.3 #nand boot 837xRDB ~3.1 ~2.3 also tested on an 8323ERDB. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- please test! include/configs/MPC8313ERDB.h | 3 ++- include/configs/MPC8315ERDB.h | 5 +++-- include/configs/MPC8323ERDB.h | 5 +++-- include/configs/MPC832XEMDS.h | 5 +++-- include/configs/MPC8349EMDS.h | 3 ++- include/configs/MPC8360EMDS.h | 5 +++-- include/configs/MPC8360ERDK.h | 5 +++-- include/configs/MPC837XEMDS.h | 5 +++-- include/configs/MPC837XERDB.h | 5 +++-- include/configs/MVBLM7.h | 3 ++- include/configs/SIMPC8313.h | 5 +++-- include/configs/TQM834x.h | 3 ++- include/configs/km83xx-common.h | 3 ++- include/configs/sbc8349.h | 3 ++- include/configs/vme8349.h | 3 ++- 15 files changed, 38 insertions(+), 23 deletions(-) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index a2e4cd4..94695fc 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -517,7 +517,8 @@ #define CONFIG_SYS_HID0_INIT 0x000000000 #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ - HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index b106aa9..6972fe8 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -536,8 +536,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) #define CONFIG_SYS_HID2 HID2_HBE diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 50aea79..7c84393 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -438,8 +438,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index f7632e0..7bd2793 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -455,8 +455,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 5c410c9..73dbea4 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -598,7 +598,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) /* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 620e32c..87a137b 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -495,8 +495,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a43e465..e78cf60 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -412,8 +412,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 1565ff9..b30d0e3 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -544,8 +544,9 @@ extern int board_pci_host_broken(void); /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 97a05a2..1654f46 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -552,8 +552,9 @@ /* * Core HID Setup */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index 6cc8d58..26897c6 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -321,7 +321,8 @@ #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_HIGH_BATS 1 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 40e89d9..84af8df 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -411,8 +411,9 @@ | SICRL_ETSEC2_A ) #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT ) #define CONFIG_SYS_HID2 HID2_HBE diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index f08c0a9..c1e0e64 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -405,7 +405,8 @@ extern int tqm834x_num_flash_banks; /* i-cache and d-cache disabled */ #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL CONFIG_SYS_HID0_INIT +#define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE #define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/km83xx-common.h b/include/configs/km83xx-common.h index 71dfd25..a551b4d 100644 --- a/include/configs/km83xx-common.h +++ b/include/configs/km83xx-common.h @@ -255,7 +255,8 @@ * Core HID Setup */ #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE /* diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 80f83ac..deaddde 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -542,7 +542,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) /* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index cb987a1..f493e75 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -449,7 +449,8 @@ #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) #define CONFIG_SYS_HID2 HID2_HBE -- 1.7.0.5

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[U-Boot] [RFC PATCH 0/3] Add device tree support for ARM to U-Boot
by John Rigby 27 Oct '10

27 Oct '10

These patches add device tree support to the bootm command in u-boot for the ARM. I'm sending the patches to this list first for comments before sending it to the wider audience on the u-boot list. The only testing so far has shown that this patch does not break non-dt booting. I don't have a dt enabled beagle kernel so I have not tried that yet. John Rigby (3): FDT: Add fixup support of multiple banks of memory ARM: WIP: add flat device tree support ARM: add config for beagle with fdt enabled MAKEALL | 1 + arch/arm/include/asm/config.h | 1 + arch/arm/lib/bootm.c | 128 ++++++++++++++- boards.cfg | 1 + common/cmd_bootm.c | 5 +- common/fdt_support.c | 86 +++++----- common/image.c | 7 +- include/configs/omap3_beagle_dt.h | 344 +++++++++++++++++++++++++++++++++++++ include/fdt_support.h | 1 + include/image.h | 2 +- 10 files changed, 531 insertions(+), 45 deletions(-) create mode 100644 include/configs/omap3_beagle_dt.h

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