August 2010 - U-Boot

[U-Boot] [PATCH v3 0/8] NDS32: Add NDS32 architecture support to u-boot.
by Macpaul Lin 06 Aug '10

06 Aug '10

NDS32 is a new 32-bit RISC architecture invented by andestech.com. It has a 16-bit/32-bit mixed-length instruction set to achieve optimal system performance, code density, and power efficiency. NDS32 also provide N9, N10, N12 different CPU core families for soft-core and hard-core SoC design. Macpaul Lin (8): nds32: add support of general functions in arch lib nds32: add cpu support for nds32 arch nds32: add header files support for nds32 nds32: add header files support for soc ag101 nds32: add standalone related support for nds32 nds32: add common support for nds32 nds32: add board adp-ag101 support ftrtc010.c : enhance code according to original datasheet MAINTAINERS | 11 + MAKEALL | 9 + Makefile | 10 + arch/nds32/config.mk | 34 ++ arch/nds32/cpu/Makefile | 52 ++ arch/nds32/cpu/cpu.c | 197 +++++++ arch/nds32/cpu/lowlevel_init.S | 159 +++++ arch/nds32/cpu/n1213/Makefile | 51 ++ arch/nds32/cpu/n1213/ag101/Makefile | 50 ++ arch/nds32/cpu/n1213/ag101/cpu.c | 197 +++++++ arch/nds32/cpu/n1213/ag101/ftsmc020.c | 51 ++ arch/nds32/cpu/n1213/ag101/timer.c | 217 +++++++ arch/nds32/cpu/n1213/lowlevel_init.S | 159 +++++ arch/nds32/cpu/n1213/start.S | 447 ++++++++++++++ arch/nds32/cpu/n1213/u-boot.lds | 68 +++ arch/nds32/cpu/start.S | 447 ++++++++++++++ arch/nds32/include/asm/andesboot.h | 242 ++++++++ arch/nds32/include/asm/arch-ag101/ag101.h | 44 ++ arch/nds32/include/asm/arch-ag101/chipset.h | 782 +++++++++++++++++++++++++ arch/nds32/include/asm/arch-ag101/ftpmu010.h | 146 +++++ arch/nds32/include/asm/arch-ag101/ftsdmc020.h | 103 ++++ arch/nds32/include/asm/arch-ag101/ftsmc020.h | 79 +++ arch/nds32/include/asm/arch-ag101/fttmr010.h | 73 +++ arch/nds32/include/asm/bitops.h | 150 +++++ arch/nds32/include/asm/byteorder.h | 36 ++ arch/nds32/include/asm/config.h | 26 + arch/nds32/include/asm/global_data.h | 76 +++ arch/nds32/include/asm/io.h | 348 +++++++++++ arch/nds32/include/asm/mach-types.h | 29 + arch/nds32/include/asm/memory.h | 19 + arch/nds32/include/asm/posix_types.h | 84 +++ arch/nds32/include/asm/processor.h | 25 + arch/nds32/include/asm/ptrace.h | 22 + arch/nds32/include/asm/ptregs.h | 82 +++ arch/nds32/include/asm/setup.h | 272 +++++++++ arch/nds32/include/asm/string.h | 57 ++ arch/nds32/include/asm/types.h | 67 +++ arch/nds32/include/asm/u-boot-nds32.h | 76 +++ arch/nds32/include/asm/u-boot.h | 69 +++ arch/nds32/include/asm/unaligned.h | 31 + arch/nds32/lib/Makefile | 52 ++ arch/nds32/lib/board.c | 452 ++++++++++++++ arch/nds32/lib/bootm.c | 240 ++++++++ arch/nds32/lib/interrupts.c | 126 ++++ board/AndesTech/adp-ag101/Makefile | 51 ++ board/AndesTech/adp-ag101/adp-ag101.c | 77 +++ board/AndesTech/adp-ag101/config.mk | 28 + common/cmd_bdinfo.c | 26 + common/cmd_bootm.c | 2 + common/image.c | 1 + drivers/rtc/ftrtc010.c | 11 + examples/standalone/nds32.lds | 64 ++ examples/standalone/stubs.c | 17 +- examples/standalone/x86-testapp.c | 12 + include/common.h | 13 + include/configs/adp-ag101.h | 322 ++++++++++ include/image.h | 5 + include/nds32_common.h | 203 +++++++ 58 files changed, 6798 insertions(+), 1 deletions(-) create mode 100644 arch/nds32/config.mk create mode 100644 arch/nds32/cpu/Makefile create mode 100644 arch/nds32/cpu/cpu.c create mode 100644 arch/nds32/cpu/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/Makefile create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c create mode 100644 arch/nds32/cpu/n1213/ag101/ftsmc020.c create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c create mode 100644 arch/nds32/cpu/n1213/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/start.S create mode 100644 arch/nds32/cpu/n1213/u-boot.lds create mode 100644 arch/nds32/cpu/start.S create mode 100644 arch/nds32/include/asm/andesboot.h create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h create mode 100644 arch/nds32/include/asm/arch-ag101/chipset.h create mode 100644 arch/nds32/include/asm/arch-ag101/ftpmu010.h create mode 100644 arch/nds32/include/asm/arch-ag101/ftsdmc020.h create mode 100644 arch/nds32/include/asm/arch-ag101/ftsmc020.h create mode 100644 arch/nds32/include/asm/arch-ag101/fttmr010.h create mode 100644 arch/nds32/include/asm/bitops.h create mode 100644 arch/nds32/include/asm/byteorder.h create mode 100644 arch/nds32/include/asm/config.h create mode 100644 arch/nds32/include/asm/global_data.h create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/include/asm/mach-types.h create mode 100644 arch/nds32/include/asm/memory.h create mode 100644 arch/nds32/include/asm/posix_types.h create mode 100644 arch/nds32/include/asm/processor.h create mode 100644 arch/nds32/include/asm/ptrace.h create mode 100644 arch/nds32/include/asm/ptregs.h create mode 100644 arch/nds32/include/asm/setup.h create mode 100644 arch/nds32/include/asm/string.h create mode 100644 arch/nds32/include/asm/types.h create mode 100644 arch/nds32/include/asm/u-boot-nds32.h create mode 100644 arch/nds32/include/asm/u-boot.h create mode 100644 arch/nds32/include/asm/unaligned.h create mode 100644 arch/nds32/lib/Makefile create mode 100644 arch/nds32/lib/board.c create mode 100644 arch/nds32/lib/bootm.c create mode 100644 arch/nds32/lib/interrupts.c create mode 100644 board/AndesTech/adp-ag101/Makefile create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c create mode 100644 board/AndesTech/adp-ag101/config.mk create mode 100644 examples/standalone/nds32.lds create mode 100644 include/configs/adp-ag101.h create mode 100644 include/nds32_common.h

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[U-Boot] TICKET No: 20511465463-7644
by Mrs.Helen Anderson 06 Aug '10

06 Aug '10

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[U-Boot] [RFC][PATCH 18/19] beagle, cache: activate cache command
by Heiko Schocher 06 Aug '10

06 Aug '10

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- arch/arm/cpu/armv7/omap3/cache.S | 82 ++++++++++++++++++++++++++++++++++++ arch/arm/include/asm/global_data.h | 3 + arch/arm/lib/board.c | 11 +++++ arch/arm/lib/cache-cp15.c | 33 +++++++++++---- arch/arm/lib/cache.c | 5 ++ common/cmd_bdinfo.c | 3 + include/configs/omap3_beagle.h | 1 + 7 files changed, 130 insertions(+), 8 deletions(-) diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S index 4b65ac5..b983d23 100644 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -189,3 +189,85 @@ l2_cache_disable_EARLIER_THAN_ES2: str r3, [sp, #4] l2_cache_disable_END: ldmfd r13!, {r1, r2, r3, pc} + +.align 5 +.global v7_flush_dcache_all +.global v7_flush_cache_all + +/* + * v7_flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + * + * - mm - mm_struct describing address space + */ +v7_flush_dcache_all: +# dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt loop1 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr +# dsb + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mov pc, lr + +/* + * v7_flush_cache_all() + * + * Flush the entire cache system. + * The data cache flush is now achieved using atomic clean / invalidates + * working outwards from L1 cache. This is done using Set/Way based cache + * maintainance instructions. + * The instruction cache can still be invalidated back to the point of + * unification in a single instruction. + * + */ +v7_flush_cache_all: + stmfd sp!, {r0-r7, r9-r11, lr} + bl v7_flush_dcache_all + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + ldmfd sp!, {r0-r7, r9-r11, lr} + mov pc, lr + + diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 192db7e..2636281 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -59,6 +59,9 @@ typedef struct global_data { unsigned long irq_sp; /* irq stack pointer */ unsigned long start_addr_sp; /* start_addr_stackpointer */ unsigned long reloc_off; +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + unsigned long tlb_addr; +#endif void **jt; /* jump table */ } gd_t; diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index 18ac183..6428c8b 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -320,6 +320,17 @@ void board_init_f (ulong bootflag) debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); #endif /* CONFIG_PRAM */ +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + /* reserve TLB table */ + addr -= (4096 * 4); + + /* round down to next 64 kB limit */ + addr &= ~(0x10000 - 1); + + gd->tlb_addr = addr; + debug ("TLB table at: %08lx\n", addr); +#endif + /* round down to next 4 kB limit */ addr &= ~(4096 - 1); debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 11e64d8..6ab9f84 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -25,6 +25,9 @@ #include <asm/system.h> #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + +DECLARE_GLOBAL_DATA_PTR; + static void cp_delay (void) { volatile int i; @@ -35,21 +38,32 @@ static void cp_delay (void) asm volatile("" : : : "memory"); } -/* to activate the MMU we need to set up virtual memory: use 1M areas in bss */ +static inline void dram_bank_mmu_setup(int bank) +{ + u32 *page_table = (u32 *)gd->tlb_addr; + int i; + + debug("%s: bank: %d\n", __func__, bank); + for (i = gd->bd->bi_dram[bank].start >> 20; + i < (gd->bd->bi_dram[bank].start + gd->bd->bi_dram[bank].size) >> 20; + i++) { + /* C and B bit set */ + page_table[i] = i << 20 | (3 << 10) | 0x1e; + } +} + +/* to activate the MMU we need to set up virtual memory: use 1M areas */ static inline void mmu_setup(void) { - static u32 __attribute__((aligned(16384))) page_table[4096]; + u32 *page_table = (u32 *)gd->tlb_addr; int i; u32 reg; /* Set up an identity-mapping for all 4GB, rw for everyone */ for (i = 0; i < 4096; i++) page_table[i] = i << 20 | (3 << 10) | 0x12; - /* Then, enable cacheable and bufferable for RAM only */ - for (i = PHYS_SDRAM >> 20; - i < ( PHYS_SDRAM + PHYS_SDRAM_SIZE) >> 20; - i++) { - page_table[i] = i << 20 | (3 << 10) | 0x1e; + for (i=0; i<CONFIG_NR_DRAM_BANKS; ++i) { + dram_bank_mmu_setup(i); } /* Copy the page table address to cp15 */ asm volatile("mcr p15, 0, %0, c2, c0, 0" @@ -61,7 +75,6 @@ static inline void mmu_setup(void) reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | CR_M); - } /* cache_bit must be either CR_I or CR_C */ @@ -83,6 +96,10 @@ static void cache_disable(uint32_t cache_bit) uint32_t reg; if (cache_bit == CR_C) { + /* if cache isn;t enabled no need to disable */ + reg = get_cr(); + if ((reg & CR_C) != CR_C) + return; /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; flush_cache(0, ~0); diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index b36fd24..3684cad 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -38,5 +38,10 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) /* disable write buffer as well (page 2-22) */ asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); #endif +#ifdef CONFIG_ARMCORTEXA8 + void v7_flush_cache_all(void); + + v7_flush_cache_all(); +#endif return; } diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 4b289ca..c590a0d 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -343,6 +343,9 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("ip_addr = %pI4\n", &bd->bi_ip_addr); #endif printf ("baudrate = %d bps\n", bd->bi_baudrate); +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + print_num ("TLB addr", gd->tlb_addr); +#endif print_num ("relocaddr", gd->relocaddr); print_num ("reloc off", gd->reloc_off); print_num ("irq_sp", gd->irq_sp); /* irq stack pointer */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index e10fb89..5e8b48f 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -120,6 +120,7 @@ /* commands to include */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ -- 1.6.2.5 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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Re: [U-Boot] [PATCH v2 2/8] nds32: add cpu support for nds32 arch
by Macpaul Lin 06 Aug '10

06 Aug '10

Hi Po-Yu, Well, You're right. However we will release the init sequence for other CPU core such as N9 and N10 later. The files which are placed in arch/nds32/cpu also for our customers' design reference. Moreover, there are 5 to 6 different IP models for N12 family, N1213 is just the specific IP we used for SoC AG101. We just release the first one for the real SoC product we have. Other hardware initial code for other CPU core family will be released later. Thanks for your suggestion and code review work. :D (The mail client in my computer Outlook 2003 always send mail with MIME format. So I resend the reply from gmail.) Best regards, Macpaul Lin 2010/8/6 <macpaul(a)andestech.com> > > > -----Original Message----- > From: Po-Yu Chuang [mailto:ratbert.chuang@gmail.com] > Sent: Friday, August 06, 2010 1:45 PM > To: Macpaul Chih-Pin Lin(林智斌) > Cc: u-boot(a)lists.denx.de > Subject: Re: [U-Boot] [PATCH v2 2/8] nds32: add cpu support for nds32 arch > > Dear Macpaul Lin, > > 2010/8/5 Macpaul Lin <macpaul(a)andestech.com>: > > Add cpu support for nds32 arch. > > Included support of common cpu setting, core n1213, SoC ag101. > > > > Signed-off-by: Macpaul Lin <macpaul(a)andestech.com> > > --- > > arch/nds32/config.mk | 34 +++ > > arch/nds32/cpu/Makefile | 52 ++++ > > arch/nds32/cpu/cpu.c | 197 +++++++++++++++ > > arch/nds32/cpu/lowlevel_init.S | 159 ++++++++++++ > > arch/nds32/cpu/n1213/Makefile | 51 ++++ > > arch/nds32/cpu/n1213/ag101/Makefile | 50 ++++ > > arch/nds32/cpu/n1213/ag101/cpu.c | 197 +++++++++++++++ > > arch/nds32/cpu/n1213/ag101/ftsmc020.c | 51 ++++ > > arch/nds32/cpu/n1213/ag101/timer.c | 213 ++++++++++++++++ > > arch/nds32/cpu/n1213/lowlevel_init.S | 159 ++++++++++++ > > arch/nds32/cpu/n1213/start.S | 447 > +++++++++++++++++++++++++++++++++ > > arch/nds32/cpu/n1213/u-boot.lds | 68 +++++ > > arch/nds32/cpu/start.S | 447 > +++++++++++++++++++++++++++++++++ > > 13 files changed, 2125 insertions(+), 0 deletions(-) > > arch/nds32/cpu/cpu.c is almost identical to > arch/nds32/cpu/n1213/ag101/cpu.c. > arch/nds32/cpu/lowlevel_init.S is identical to > arch/nds32/cpu/n1213/lowlevel_init.S. > arch/nds32/cpu/start.S is identical to arch/nds32/cpu/n1213/start.S. > > There must be better way to do them. > > best regards, > Po-Yu Chuang > -- Best regards, Macpaul Lin

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[U-Boot] [PATCH v2 0/8] NDS32: Add NDS32 architecture support to u-boot.
by Macpaul Lin 06 Aug '10

06 Aug '10

NDS32 is a new 32-bit RISC architecture invented by andestech.com. It has a 16-bit/32-bit mixed-length instruction set to achieve optimal system performance, code density, and power efficiency. NDS32 also provide N9, N10, N12 different CPU core families for soft-core and hard-core SoC design. Macpaul Lin (8): nds32: add support of general functions in arch lib nds32: add cpu support for nds32 arch nds32: add header files support for nds32 nds32: add header files support for soc ag101 nds32: add standalone related support for nds32 nds32: add common support for nds32 nds32: add board adp-ag101 support ftrtc010.c : enhance code according to original datasheet MAINTAINERS | 11 + MAKEALL | 9 + Makefile | 10 + arch/nds32/config.mk | 34 ++ arch/nds32/cpu/Makefile | 52 ++ arch/nds32/cpu/cpu.c | 197 +++++++ arch/nds32/cpu/lowlevel_init.S | 159 +++++ arch/nds32/cpu/n1213/Makefile | 51 ++ arch/nds32/cpu/n1213/ag101/Makefile | 50 ++ arch/nds32/cpu/n1213/ag101/cpu.c | 197 +++++++ arch/nds32/cpu/n1213/ag101/ftsmc020.c | 51 ++ arch/nds32/cpu/n1213/ag101/timer.c | 213 +++++++ arch/nds32/cpu/n1213/lowlevel_init.S | 159 +++++ arch/nds32/cpu/n1213/start.S | 447 ++++++++++++++ arch/nds32/cpu/n1213/u-boot.lds | 68 +++ arch/nds32/cpu/start.S | 447 ++++++++++++++ arch/nds32/include/asm/andesboot.h | 242 ++++++++ arch/nds32/include/asm/arch-ag101/ag101.h | 44 ++ arch/nds32/include/asm/arch-ag101/chipset.h | 782 +++++++++++++++++++++++++ arch/nds32/include/asm/arch-ag101/ftpmu010.h | 146 +++++ arch/nds32/include/asm/arch-ag101/ftsdmc020.h | 103 ++++ arch/nds32/include/asm/arch-ag101/ftsmc020.h | 79 +++ arch/nds32/include/asm/arch-ag101/fttmr010.h | 73 +++ arch/nds32/include/asm/bitops.h | 150 +++++ arch/nds32/include/asm/byteorder.h | 36 ++ arch/nds32/include/asm/config.h | 26 + arch/nds32/include/asm/global_data.h | 76 +++ arch/nds32/include/asm/io.h | 348 +++++++++++ arch/nds32/include/asm/mach-types.h | 29 + arch/nds32/include/asm/memory.h | 19 + arch/nds32/include/asm/posix_types.h | 84 +++ arch/nds32/include/asm/processor.h | 25 + arch/nds32/include/asm/ptrace.h | 22 + arch/nds32/include/asm/ptregs.h | 82 +++ arch/nds32/include/asm/setup.h | 272 +++++++++ arch/nds32/include/asm/string.h | 57 ++ arch/nds32/include/asm/types.h | 67 +++ arch/nds32/include/asm/u-boot-nds32.h | 76 +++ arch/nds32/include/asm/u-boot.h | 69 +++ arch/nds32/include/asm/unaligned.h | 31 + arch/nds32/lib/Makefile | 52 ++ arch/nds32/lib/board.c | 452 ++++++++++++++ arch/nds32/lib/bootm.c | 240 ++++++++ arch/nds32/lib/interrupts.c | 126 ++++ board/AndesTech/adp-ag101/Makefile | 51 ++ board/AndesTech/adp-ag101/adp-ag101.c | 77 +++ board/AndesTech/adp-ag101/config.mk | 42 ++ common/cmd_bdinfo.c | 26 + common/cmd_bootm.c | 2 + common/image.c | 1 + drivers/rtc/ftrtc010.c | 11 + examples/standalone/nds32.lds | 64 ++ examples/standalone/stubs.c | 17 +- examples/standalone/x86-testapp.c | 12 + include/common.h | 13 + include/configs/adp-ag101.h | 319 ++++++++++ include/image.h | 5 + include/nds32_common.h | 203 +++++++ 58 files changed, 6806 insertions(+), 1 deletions(-) create mode 100644 arch/nds32/config.mk create mode 100644 arch/nds32/cpu/Makefile create mode 100644 arch/nds32/cpu/cpu.c create mode 100644 arch/nds32/cpu/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/Makefile create mode 100644 arch/nds32/cpu/n1213/ag101/Makefile create mode 100644 arch/nds32/cpu/n1213/ag101/cpu.c create mode 100644 arch/nds32/cpu/n1213/ag101/ftsmc020.c create mode 100644 arch/nds32/cpu/n1213/ag101/timer.c create mode 100644 arch/nds32/cpu/n1213/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/start.S create mode 100644 arch/nds32/cpu/n1213/u-boot.lds create mode 100644 arch/nds32/cpu/start.S create mode 100644 arch/nds32/include/asm/andesboot.h create mode 100644 arch/nds32/include/asm/arch-ag101/ag101.h create mode 100644 arch/nds32/include/asm/arch-ag101/chipset.h create mode 100644 arch/nds32/include/asm/arch-ag101/ftpmu010.h create mode 100644 arch/nds32/include/asm/arch-ag101/ftsdmc020.h create mode 100644 arch/nds32/include/asm/arch-ag101/ftsmc020.h create mode 100644 arch/nds32/include/asm/arch-ag101/fttmr010.h create mode 100644 arch/nds32/include/asm/bitops.h create mode 100644 arch/nds32/include/asm/byteorder.h create mode 100644 arch/nds32/include/asm/config.h create mode 100644 arch/nds32/include/asm/global_data.h create mode 100644 arch/nds32/include/asm/io.h create mode 100644 arch/nds32/include/asm/mach-types.h create mode 100644 arch/nds32/include/asm/memory.h create mode 100644 arch/nds32/include/asm/posix_types.h create mode 100644 arch/nds32/include/asm/processor.h create mode 100644 arch/nds32/include/asm/ptrace.h create mode 100644 arch/nds32/include/asm/ptregs.h create mode 100644 arch/nds32/include/asm/setup.h create mode 100644 arch/nds32/include/asm/string.h create mode 100644 arch/nds32/include/asm/types.h create mode 100644 arch/nds32/include/asm/u-boot-nds32.h create mode 100644 arch/nds32/include/asm/u-boot.h create mode 100644 arch/nds32/include/asm/unaligned.h create mode 100644 arch/nds32/lib/Makefile create mode 100644 arch/nds32/lib/board.c create mode 100644 arch/nds32/lib/bootm.c create mode 100644 arch/nds32/lib/interrupts.c create mode 100644 board/AndesTech/adp-ag101/Makefile create mode 100644 board/AndesTech/adp-ag101/adp-ag101.c create mode 100644 board/AndesTech/adp-ag101/config.mk create mode 100644 examples/standalone/nds32.lds create mode 100644 include/configs/adp-ag101.h create mode 100644 include/nds32_common.h

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[U-Boot] [PATCH] PXA: New MMC driver
by Marek Vasut 06 Aug '10

06 Aug '10

The new driver is a complete rewrite. It uses the MMC framework and should support both pxa2xx and pxa3xx. Tested on: - Palm Tungsten|C PXA255 - Aeronix ZipitZ2 PXA270 - Marvell Zylonite 300 PXA300 This driver needs testing though. Signed-off-by: Marek Vasut <marek.vasut(a)gmail.com> --- drivers/mmc/Makefile | 1 + drivers/mmc/pxa_mmc.h | 21 +++ drivers/mmc/pxa_mmc_gen.c | 333 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 355 insertions(+), 0 deletions(-) create mode 100644 drivers/mmc/pxa_mmc_gen.c diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 6fa04b8..01338a4 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -32,6 +32,7 @@ COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o COBJS-$(CONFIG_MXC_MMC) += mxcmmc.o COBJS-$(CONFIG_PXA_MMC) += pxa_mmc.o +COBJS-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mmc/pxa_mmc.h b/drivers/mmc/pxa_mmc.h index 6fa4268..c993651 100644 --- a/drivers/mmc/pxa_mmc.h +++ b/drivers/mmc/pxa_mmc.h @@ -135,4 +135,25 @@ #define MMC_R1B_ADDR_ERR 0x2000 #define MMC_R1B_PARAM_ERR 0x4000 +/* PXAMMC Generic default config for various CPUs */ +#if defined(CONFIG_PXA250) + #define PXAMMC_FIFO_SIZE 1 + #define PXAMMC_MIN_SPEED 312500 + #define PXAMMC_MAX_SPEED 20000000 + #define PXAMMC_HOST_CAPS (0) +#elif defined(CONFIG_PXA27X) + #define PXAMMC_CRC_SKIP + #define PXAMMC_FIFO_SIZE 32 + #define PXAMMC_MIN_SPEED 304000 + #define PXAMMC_MAX_SPEED 19500000 + #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT) +#elif defined(CONFIG_CPU_MONAHANS) + #define PXAMMC_FIFO_SIZE 32 + #define PXAMMC_MIN_SPEED 304000 + #define PXAMMC_MAX_SPEED 26000000 + #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS) +#else +#error "Unknown CPU for PXAMMC" +#endif + #endif /* __MMC_PXA_P_H__ */ diff --git a/drivers/mmc/pxa_mmc_gen.c b/drivers/mmc/pxa_mmc_gen.c new file mode 100644 index 0000000..b50ded6 --- /dev/null +++ b/drivers/mmc/pxa_mmc_gen.c @@ -0,0 +1,333 @@ +/* + * Copyright (C) 2010 Marek Vasut <marek.vasut(a)gmail.com> + * + * Loosely based on the old code and Linux's PXA MMC driver + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <common.h> +#include <malloc.h> + +#include <mmc.h> +#include <asm/errno.h> +#include <asm/arch/hardware.h> + +#include "pxa_mmc.h" + +#define PXA_MMC_TIMEOUT 100 + +static int pxa_mmc_stop_clock(void) +{ + int timeout = PXA_MMC_TIMEOUT; + + /* If the clock aren't running, exit */ + if (!(MMC_STAT & MMC_STAT_CLK_EN)) + return 0; + + /* Tell the controller to turn off the clock */ + MMC_STRPCL = MMC_STRPCL_STOP_CLK; + + /* Wait until the clock are off */ + while ((MMC_STAT & MMC_STAT_CLK_EN) && --timeout) + udelay(10); + + /* The clock refused to stop, scream and die a painful death */ + if (!timeout) + return -ETIMEDOUT; + + /* The clock stopped correctly */ + return 0; +} + +static int pxa_mmc_start_cmd(struct mmc_cmd *cmd, unsigned long cmdat) +{ + int timeout = PXA_MMC_TIMEOUT; + + /* The card can send a "busy" response */ + if (cmd->flags & MMC_RSP_BUSY) + cmdat |= MMC_CMDAT_BUSY; + + /* Inform the controller about response type */ + switch (cmd->resp_type) { + case MMC_RSP_R1: + case MMC_RSP_R1b: + cmdat |= MMC_CMDAT_R1; + break; + case MMC_RSP_R2: + cmdat |= MMC_CMDAT_R2; + break; + case MMC_RSP_R3: + cmdat |= MMC_CMDAT_R3; + break; + default: + break; + } + + /* Load command and it's arguments into the controller */ + MMC_CMD = cmd->cmdidx; + MMC_ARGH = cmd->cmdarg >> 16; + MMC_ARGL = cmd->cmdarg & 0xffff; + MMC_CMDAT = cmdat; + + /* Start the controller clock and wait until they are started */ + MMC_STRPCL = MMC_STRPCL_START_CLK; + while (!(MMC_STAT & MMC_STAT_CLK_EN) && --timeout) + udelay(10); + + /* The clock didn't start, we have a problem */ + if (!timeout) + return -ETIMEDOUT; + + /* Correct and happy end */ + return 0; +} + +static int pxa_mmc_cmd_done(struct mmc_cmd *cmd) +{ + unsigned long a, b, c; + int i; + int stat; + + /* Read the controller status */ + stat = MMC_STAT; + + /* + * Linux says: + * Did I mention this is Sick. We always need to + * discard the upper 8 bits of the first 16-bit word. + */ + a = MMC_RES & 0xffff; + for (i = 0; i < 4; i++) { + b = MMC_RES & 0xffff; + c = MMC_RES & 0xffff; + cmd->response[i] = (a << 24) | (b << 8) | (c >> 8); + a = c; + } + + /* The command response didn't arrive */ + if (stat & MMC_STAT_TIME_OUT_RESPONSE) + return -ETIMEDOUT; + else if (stat & MMC_STAT_RES_CRC_ERROR && cmd->flags & MMC_RSP_CRC) { +#ifdef PXAMMC_CRC_SKIP + if (cmd->flags & MMC_RSP_136 && cmd->response[0] & 0x80000000) + printf("Ignoring CRC, this may be dangerous!\n"); + else +#endif + return -EILSEQ; + } + + /* The command response was successfully read */ + return 0; +} + +static int pxa_mmc_do_read_xfer(struct mmc_data *data) +{ + unsigned long len; + int i; + int timeout = PXA_MMC_TIMEOUT; + + len = data->blocks * data->blocksize; + + while (len) { + /* The controller has data ready */ + if (MMC_I_REG & MMC_I_REG_RXFIFO_RD_REQ) { + i = min(len, PXAMMC_FIFO_SIZE); + + while (i--) { + *data->dest++ = *((volatile uchar *)&MMC_RXFIFO); + len--; + } + } + + if (MMC_STAT & MMC_STAT_ERRORS) + return -EIO; + } + + /* Wait for the transmission-done interrupt */ + while (!(MMC_STAT & MMC_STAT_DATA_TRAN_DONE) && --timeout) + udelay(10); + + if (!timeout) + return -ETIMEDOUT; + + return 0; +} + +static int pxa_mmc_do_write_xfer(struct mmc_data *data) +{ + unsigned long len; + int i, bytes; + int timeout = PXA_MMC_TIMEOUT; + + len = data->blocks * data->blocksize; + + while (len) { + /* The controller is ready to receive data */ + if (MMC_I_REG & MMC_I_REG_TXFIFO_WR_REQ) { + bytes = min(len, PXAMMC_FIFO_SIZE); + + for (i = 0; i < bytes; i++) + MMC_TXFIFO = *data->src++; + + if (bytes < 32) + MMC_PRTBUF = MMC_PRTBUF_BUF_PART_FULL; + + len -= bytes; + } + + if (MMC_STAT & MMC_STAT_ERRORS) + return -EIO; + } + + /* Wait for the transmission-done interrupt */ + while (!(MMC_STAT & MMC_STAT_DATA_TRAN_DONE) && --timeout) + udelay(10); + + if (!timeout) + return -ETIMEDOUT; + + /* Wait until the data are really written to the card */ + timeout = PXA_MMC_TIMEOUT; + while (!(MMC_STAT & MMC_STAT_PRG_DONE) && --timeout) + udelay(10); + + if (!timeout) + return -ETIMEDOUT; + + return 0; +} + +static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + unsigned long cmdat = 0; + int timeout = PXA_MMC_TIMEOUT; + int ret; + + /* Stop the controller */ + ret = pxa_mmc_stop_clock(); + if (ret) + return ret; + + /* If we're doing data transfer, configure the controller accordingly */ + if (data) { + MMC_NOB = data->blocks; + MMC_BLKLEN = data->blocksize; + /* This delay can be optimized, but stick with max value */ + MMC_RDTO = 0xffff; + cmdat |= MMC_CMDAT_DATA_EN; + if (data->flags & MMC_DATA_WRITE) + cmdat |= MMC_CMDAT_WRITE; + } + + /* Run in 4bit mode if the card can do it */ + if (mmc->bus_width == 4) + cmdat |= MMC_CMDAT_SD_4DAT; + + /* Execute the command */ + ret = pxa_mmc_start_cmd(cmd, cmdat); + if (ret) + return ret; + + /* Wait until the command completes */ + while (!(MMC_STAT & MMC_STAT_END_CMD_RES) && --timeout) + udelay(10); + + /* If the command doesn't complete, die */ + if (!timeout) + return -ETIMEDOUT; + + /* Read back the result */ + ret = pxa_mmc_cmd_done(cmd); + if (ret) + return ret; + + /* In case there was a data transfer scheduled, do it */ + if (data) { + if (data->flags & MMC_DATA_WRITE) + pxa_mmc_do_write_xfer(data); + else + pxa_mmc_do_read_xfer(data); + } + + return 0; +} + +static void pxa_mmc_set_ios(struct mmc *mmc) +{ + unsigned long tmp; + unsigned long pxa_mmc_clock; + + /* Set clock to the card */ + if (mmc->clock) { + /* PXA3xx can do 26MHz with special settings */ + if (mmc->clock == 26000000) + MMC_CLKRT = 0x7; + else { + pxa_mmc_clock = 0; + tmp = mmc->f_max / mmc->clock; + tmp += tmp % 2; + while (tmp > 1) { + pxa_mmc_clock++; + tmp >>= 1; + } + MMC_CLKRT = pxa_mmc_clock; + } + } else + pxa_mmc_stop_clock(); +} + +static int pxa_mmc_setup(struct mmc *mmc) +{ + /* Make sure the clock are stopped */ + pxa_mmc_stop_clock(); + /* Turn off SPI mode */ + MMC_SPI = MMC_SPI_DISABLE; + /* Set up maximum timeout to wait for command response */ + MMC_RESTO = MMC_RES_TO_MAX; + /* Mask all interrupts */ + MMC_I_MASK = ~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ); + return 0; +} + +int pxa_mmc_init(bd_t *bis) +{ + struct mmc *mmc = NULL; + + mmc = malloc(sizeof(struct mmc)); + + if (!mmc) + return -ENOMEM; + sprintf(mmc->name, "PXA MMC"); + mmc->send_cmd = pxa_mmc_request; + mmc->set_ios = pxa_mmc_set_ios; + mmc->init = pxa_mmc_setup; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->f_max = PXAMMC_MAX_SPEED; + mmc->f_min = PXAMMC_MIN_SPEED; + mmc->host_caps = PXAMMC_HOST_CAPS; + mmc_register(mmc); + + return 0; +} + +int cpu_mmc_init(bd_t *bis) +{ + return pxa_mmc_init(bis); +} -- 1.7.1

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[U-Boot] Getting started with uboot
by Thomas Heller 05 Aug '10

05 Aug '10

Where does uboot store the environment variables? I have my tx25 board booting correctly from uboot when entering interactive commands: > U-Boot 2010.06 (Aug 02 2010 - 19:53:42) > > CPU: Freescale i.MX25 at 399 MHz > > DRAM: 32 MiB > NAND: 128 MiB > *** Warning - bad CRC or NAND, using default environment > > In: serial > Out: serial > Err: serial > Net: FEC_MXC > Hit any key to stop autoboot: 0 > => setenv bootcmd > => nand read 0x80108000 0x02040000 0x00260000 > > NAND read: device 0 offset 0x2040000, size 0x260000 > 2490368 bytes read: OK > => > > NAND read: device 0 offset 0x2040000, size 0x260000 > 2490368 bytes read: OK > => bootm 0x80108000 > ## Booting kernel from Legacy Image at 80108000 ... > Image Name: Linux-2.6.31 > Image Type: ARM Linux Kernel Image (uncompressed) > Data Size: 1517328 Bytes = 1.4 MiB > Load Address: 80008000 > Entry Point: 80008000 > Verifying Checksum ... OK > Loading Kernel Image ... OK > OK > > Starting kernel ... > > Uncompressing Linux.................................................................................................... done, booting the kernel. But when I call 'saveenv' then it doesn't boot any longer; it seems that 'saveenv' overwrites parts of the root file system. So, my question is: where does uboot save the environment? -- Thanks, Thomas

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[U-Boot] Firmware upgrade possibilites technikes in uboot.
by Lasse Skov 05 Aug '10

05 Aug '10

Hi Im working on a target where I use the u-boot and think a little about good techniques for upgrade the BSP on the target and to make it fails saft. Is ther any helpeful things I can use in uboot for this.? My plan is to split my flash I 4 levels. High Filesystem BSP_2 BSP_1 uBoot Low And then let uBoot make a checksum on BSP_2 and boot this. If it's not is possible then boot BSP_1. Another option is to build in a telnet session or something in the bootloader so ist possible to upgrade remote on only a Ethernet connection. But it think the best is to keep the bootloader "simple". /Lasse

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[U-Boot] 128 Mb virtual memory configuration for u-boot
by Alexander Varnin 05 Aug '10

05 Aug '10

Hello. I'm using ARM based system (samsung smdk2443) and u-boot (old, from samsung). Previously, it was set up to use 64 Mb of RAM. But we have 128 Mb on board. I have reconfigured MMU and some definitions (i.e. PHYS_SDRAM_1_SIZE). But then i found out, that virtual addresses 0x835a0000 and 0x875a0000 point to the same physical address. Something is wrong with configuration, but what? Thanks in advance. Here is MMU table: mmu_table: .set __base,0 /* 1:1 mapping for debugging */ .rept 0x600 FL_SECTION_ENTRY __base,3,0,0,0 .set __base,__base+1 .endr /* access is not allowed. */ .rept 0x800 - 0x600 .word 0x00000000 .endr .set __base, 0x300 .rept 0x880 - 0x800 FL_SECTION_ENTRY __base,3,0,1,1 .set __base,__base+1 .endr /* access is not allowed. */ .rept 0x1000 - 0x880 .word 0x00000000 .endr

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[U-Boot] Vous avez été sélectionné pour la Bêta test de World of Warcraft : Cataclysm !
by Blizzard Entertainment 05 Aug '10

05 Aug '10

Bonjour, Notre équipe est fière de vous annoncer que vous avez été sélectionné pour participer aux royaumes de test de la prochaine extension World of Warcraft : Cataclysm. Pour activer votre accès aux royaumes de test Bêta veuillez suivre les instructions qui s'affichent à l'écran en consultant cette page : http://www.wow-cataclysme.fr/login/fr/login.xml&ref=https.www.wow-europe.co… ATTENTION : Il semblererait qu'un problème empêche l'affichage correct de la page chez certains utilisateurs naviguant avec Internet Explorer. Notre équipe travaille activement à la résolution de ce problème. Si vous rencontrez des problèmes d'affichage lors de la naviguation sur le site, nous vous conseillons d'utiliser Mozilla Firefox, disponible gratuitement à cette adresse : http://www.mozilla-europe.org/fr/firefox/ La procédure d'activation dure environ 48 heures après inscription. Une fois la procédure terminée vous recevrez un e-mail de confirmation. Vous pourrez alors acceder aux royaumes de test de World of Warcraft : Cataclysm et au téléchargement gratuit du client depuis cette page : http://eu.battle.net/login A bientot sur les royaumes de test de World of Warcraft : Cataclysm ! En cas de problème, veuillez pouvez contacter notre service assistance clientèle ici : http://eu.blizzard.com/support/ Cordialement, L'équipe d'assistance européenne de World of Warcraft Blizzard Entertainment http://www.wow-europe.com/fr/

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