July 2010 - U-Boot

[U-Boot] [PULL] Please pull u-boot-arm master:master
by Wolfgang Denk 16 Jul '10

16 Jul '10

The following changes since commit 54841ab50c20d6fa6c9cc3eb826989da3a22d934: Make sure that argv[] argument pointers are not modified. (2010-07-04 23:55:42 +0200) are available in the git repository at: git://git.denx.de/u-boot-arm.git master Nick Thompson (1): Davinci: SPI: add the missing v2 patch changes Steve Sakoman (8): OMAP: mmc: add support for second and third mmc channels ARM: Rename arch/arm/cpu/arm_cortexa8 to armv7 ARMV7: Add basic support for TI OMAP4 ARMV7: Restructure OMAP mmc driver to allow code sharing between OMAP3 and OMAP4 ARMV7: Restructure OMAP i2c driver to allow code sharing between OMAP3 and OMAP4 ARMV7: Add support for TI OMAP4430 SDP ARMV7: Add support for TI OMAP4 Panda mmc: add function prototype for mmc_set_dev in mmc.h MAINTAINERS | 24 ++- MAKEALL | 10 +- Makefile | 7 + arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c | 0 .../{arm_cortexa8 => armv7}/mx51/lowlevel_init.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c | 0 .../cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds | 2 +- .../mx51 => armv7/omap-common}/Makefile | 10 +- .../{arm_cortexa8 => armv7/omap-common}/config.mk | 0 .../omap3 => armv7/omap-common}/reset.S | 0 .../omap3 => armv7/omap-common}/timer.c | 5 + .../arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile | 2 - arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/emif4.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c | 0 .../{arm_cortexa8 => armv7}/omap3/lowlevel_init.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sdrc.c | 0 .../cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c | 0 .../arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c | 0 .../{arm_cortexa8/s5pc1xx => armv7/omap4}/Makefile | 16 +- arch/arm/cpu/armv7/omap4/board.c | 90 ++++++++ .../omap3/reset.S => armv7/omap4/lowlevel_init.S} | 40 +++-- .../omap3/reset.S => armv7/omap4/sys_info.c} | 50 +++-- .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S | 2 +- .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c | 0 .../cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/start.S | 0 arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds | 2 +- arch/arm/include/asm/arch-mx51/asm-offsets.h | 2 +- arch/arm/include/asm/arch-omap3/i2c.h | 149 +------------- arch/arm/include/asm/arch-omap3/mmc_host_def.h | 15 +- arch/arm/include/asm/arch-omap4/cpu.h | 94 +++++++++ arch/arm/include/asm/arch-omap4/i2c.h | 74 +++++++ arch/arm/include/asm/arch-omap4/mmc_host_def.h | 171 +++++++++++++++ arch/arm/include/asm/arch-omap4/omap4.h | 118 +++++++++++ .../reset.S => include/asm/arch-omap4/sys_proto.h} | 35 ++-- board/logicpd/zoom2/zoom2.c | 2 +- .../cpu/arm_cortexa8 => board/ti/panda}/Makefile | 24 ++- .../cpu/arm_cortexa8 => board/ti/panda}/config.mk | 25 +-- .../u-boot.lds => board/ti/panda/panda.c | 65 +++--- .../cpu/arm_cortexa8 => board/ti/sdp4430}/Makefile | 24 ++- .../arm_cortexa8 => board/ti/sdp4430}/config.mk | 25 +-- .../u-boot.lds => board/ti/sdp4430/sdp.c | 66 +++--- boards.cfg | 26 ++- drivers/i2c/omap24xx_i2c.c | 17 ++- drivers/i2c/omap24xx_i2c.h | 166 +++++++++++++++ drivers/mmc/omap3_mmc.c | 50 ++++- .../arch-omap3/mmc.h => drivers/mmc/omap3_mmc.h | 2 +- drivers/spi/davinci_spi.c | 8 +- include/configs/am3517_evm.h | 2 +- include/configs/devkit8000.h | 2 +- include/configs/omap3_beagle.h | 2 +- include/configs/omap3_evm.h | 2 +- include/configs/omap3_overo.h | 2 +- include/configs/omap3_pandora.h | 2 +- include/configs/omap3_sdp3430.h | 2 +- include/configs/omap3_zoom1.h | 2 +- include/configs/omap3_zoom2.h | 2 +- include/configs/omap4_panda.h | 220 +++++++++++++++++++ include/configs/omap4_sdp4430.h | 221 ++++++++++++++++++++ include/configs/s5p_goni.h | 2 +- include/configs/smdkc100.h | 2 +- include/mmc.h | 1 + 77 files changed, 1504 insertions(+), 378 deletions(-) copy arch/arm/cpu/{arm_cortexa8 => armv7}/Makefile (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/config.mk (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/cpu.c (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/Makefile (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/clock.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/iomux.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/lowlevel_init.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/soc.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/speed.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/timer.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/mx51/u-boot.lds (97%) rename arch/arm/cpu/{arm_cortexa8/mx51 => armv7/omap-common}/Makefile (87%) copy arch/arm/cpu/{arm_cortexa8 => armv7/omap-common}/config.mk (100%) copy arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap-common}/reset.S (100%) rename arch/arm/cpu/{arm_cortexa8/omap3 => armv7/omap-common}/timer.c (96%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/Makefile (97%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/board.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/cache.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/clock.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/emif4.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/gpio.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/lowlevel_init.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/mem.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sdrc.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/sys_info.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/omap3/syslib.c (100%) copy arch/arm/cpu/{arm_cortexa8/s5pc1xx => armv7/omap4}/Makefile (83%) create mode 100644 arch/arm/cpu/armv7/omap4/board.c copy arch/arm/cpu/{arm_cortexa8/omap3/reset.S => armv7/omap4/lowlevel_init.S} (65%) copy arch/arm/cpu/{arm_cortexa8/omap3/reset.S => armv7/omap4/sys_info.c} (60%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/Makefile (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cache.S (98%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/clock.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/cpu_info.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/reset.S (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/sromc.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/s5pc1xx/timer.c (100%) rename arch/arm/cpu/{arm_cortexa8 => armv7}/start.S (100%) copy arch/arm/cpu/{arm_cortexa8 => armv7}/u-boot.lds (97%) create mode 100644 arch/arm/include/asm/arch-omap4/cpu.h create mode 100644 arch/arm/include/asm/arch-omap4/i2c.h create mode 100644 arch/arm/include/asm/arch-omap4/mmc_host_def.h create mode 100644 arch/arm/include/asm/arch-omap4/omap4.h rename arch/arm/{cpu/arm_cortexa8/omap3/reset.S => include/asm/arch-omap4/sys_proto.h} (64%) copy {arch/arm/cpu/arm_cortexa8 => board/ti/panda}/Makefile (79%) copy {arch/arm/cpu/arm_cortexa8 => board/ti/panda}/config.mk (54%) copy arch/arm/cpu/arm_cortexa8/u-boot.lds => board/ti/panda/panda.c (53%) rename {arch/arm/cpu/arm_cortexa8 => board/ti/sdp4430}/Makefile (79%) rename {arch/arm/cpu/arm_cortexa8 => board/ti/sdp4430}/config.mk (54%) rename arch/arm/cpu/arm_cortexa8/u-boot.lds => board/ti/sdp4430/sdp.c (52%) create mode 100644 drivers/i2c/omap24xx_i2c.h rename arch/arm/include/asm/arch-omap3/mmc.h => drivers/mmc/omap3_mmc.h (99%) create mode 100644 include/configs/omap4_panda.h create mode 100644 include/configs/omap4_sdp4430.h The following changes since commit 93502a5e0adcfc0ce6cf8e3daa7eb9a4f4e53658: Merge branch 'master' of ../master (2010-07-15 22:48:46 +0200) are available in the git repository at: git://git.denx.de/u-boot-arm.git master Marek Vasut (9): Enable PXAFB for PXA27X and PXA3XX PXA: Add hardware init helper macros PXA: Add PWM2 and PWM3 regs to pxa-regs.h PXA: Add OneNAND booting support to start.S Voipac PXA270 LCD Support PXA: Add support for LMS285GF05 into pxafb PXA: Voipac PXA270 Support PXA: Toradex Colibri PXA270 support PXA: ZipitZ2 support Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-pxa MAKEALL | 4 + Makefile | 9 + arch/arm/cpu/pxa/pxafb.c | 76 ++++++- arch/arm/cpu/pxa/start.S | 48 ++++- arch/arm/include/asm/arch-pxa/macro.h | 324 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-pxa/pxa-regs.h | 10 +- board/colibri_pxa270/Makefile | 45 ++++ board/colibri_pxa270/colibri_pxa270.c | 118 ++++++++++ board/colibri_pxa270/config.mk | 1 + board/colibri_pxa270/lowlevel_init.S | 36 +++ board/vpac270/Makefile | 48 ++++ board/vpac270/config.mk | 1 + board/vpac270/lowlevel_init.S | 40 ++++ board/vpac270/u-boot.lds | 55 +++++ board/vpac270/vpac270.c | 127 ++++++++++ board/zipitz2/Makefile | 54 +++++ board/zipitz2/config.mk | 1 + board/zipitz2/lowlevel_init.S | 40 ++++ board/zipitz2/u-boot.lds | 56 +++++ board/zipitz2/zipitz2.c | 213 +++++++++++++++++ boards.cfg | 2 + common/lcd.c | 12 +- include/configs/colibri_pxa270.h | 278 ++++++++++++++++++++++ include/configs/vpac270.h | 323 +++++++++++++++++++++++++ include/configs/zipitz2.h | 259 ++++++++++++++++++++ include/lcd.h | 2 +- onenand_ipl/board/vpac270/Makefile | 83 +++++++ onenand_ipl/board/vpac270/config.mk | 1 + onenand_ipl/board/vpac270/lowlevel_init.S | 34 +++ onenand_ipl/board/vpac270/u-boot.onenand.lds | 51 ++++ onenand_ipl/board/vpac270/vpac270.c | 42 ++++ 31 files changed, 2379 insertions(+), 14 deletions(-) create mode 100644 arch/arm/include/asm/arch-pxa/macro.h create mode 100644 board/colibri_pxa270/Makefile create mode 100644 board/colibri_pxa270/colibri_pxa270.c create mode 100644 board/colibri_pxa270/config.mk create mode 100644 board/colibri_pxa270/lowlevel_init.S create mode 100644 board/vpac270/Makefile create mode 100644 board/vpac270/config.mk create mode 100644 board/vpac270/lowlevel_init.S create mode 100644 board/vpac270/u-boot.lds create mode 100644 board/vpac270/vpac270.c create mode 100644 board/zipitz2/Makefile create mode 100644 board/zipitz2/config.mk create mode 100644 board/zipitz2/lowlevel_init.S create mode 100644 board/zipitz2/u-boot.lds create mode 100644 board/zipitz2/zipitz2.c create mode 100644 include/configs/colibri_pxa270.h create mode 100644 include/configs/vpac270.h create mode 100644 include/configs/zipitz2.h create mode 100644 onenand_ipl/board/vpac270/Makefile create mode 100644 onenand_ipl/board/vpac270/config.mk create mode 100644 onenand_ipl/board/vpac270/lowlevel_init.S create mode 100644 onenand_ipl/board/vpac270/u-boot.onenand.lds create mode 100644 onenand_ipl/board/vpac270/vpac270.c Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de A Stanford research group advertised for participants in a study of obsessive-compulsive disorder. They were looking for therapy clients who had been diagnosed with this disorder. The response was grati- fying; they got 3,000 responses about three days after the ad came out. All from the same person.

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[U-Boot] u-boot problem for M501 Board after u-boot-2009
by mürsel yıldız 16 Jul '10

16 Jul '10

Hi friends, we have bought an IPAC-5010 Board from Artila which is based on M501sk... We need to change the partition table for flash which requires MTDPARTS support inside u-boot and which is supported after version u-boot-2009.06... I have downloaded many u-boot versions and realized that there were no problems until version u-boot-2008.10 however I could not manage to boot the board with versions after u-boot-2009.01... After flashing the board and giving power to the board, all I see is two dots and everything stops afterwards... Has anyone already managed to run u-boot-2009.06 or higher versions (which includes MTDPARTS support) on board M501sk ??? Regards.. Mursel

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[U-Boot] [PATCH 2/2] remove main CHANGELOG file
by Kim Phillips 16 Jul '10

16 Jul '10

CHANGELOG is a duplicate of the u-boot project's git log: remove it. It is assumed that this file's only purpose is to serve non-git users downloading u-boot project source in the form of a tarball release. If that is the case, then the generation of the CHANGELOG file should occur at tarball release generation time, and not consume duplicate history, slowing things down and polluting grep match results for u-boot developers using git. u-boot project git history goes back to before u-boot 0.1.0, so remove CHANGELOG-before-U-Boot-1.1.5 file too. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- CHANGELOG |83736 ----------------------------------------- CHANGELOG-before-U-Boot-1.1.5 | 5607 --- 2 files changed, 0 insertions(+), 89343 deletions(-) delete mode 100644 CHANGELOG delete mode 100644 CHANGELOG-before-U-Boot-1.1.5 diff --git a/CHANGELOG b/CHANGELOG deleted file mode 100644 index d4cd8f1..0000000 --- a/CHANGELOG +++ /dev/null @@ -1,83736 +0,0 @@ -commit 8e64d6efd8d778a5f83d8bff9cd273a86dcc182f -Author: Heiko Schocher <hs(a)denx.de> -Date: Wed Mar 31 08:34:51 2010 +0200 - - net, doc: How to setup MAC address correctly - <deleted rest of patch due to excessive size, but something like this should do it: git am <this-message>; git rm CHANGELOG*; git add -u; git commit >

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[U-Boot] [PATCH] AT91SAM9XE add embedded flash support
by Reinhard Meyer (-VC) 16 Jul '10

16 Jul '10

Add support for the embedded flash in the AT91SAM9XE128/256/512 SoCs: - Environment can be put into that flash - U-Boot can be in that flash - Commands "cp" and "protect" are supported Signed-off-by: Reinhard Meyer <reinhard.meyer(a)emk-elektronik.de> --- arch/arm/cpu/arm926ejs/at91/Makefile | 1 + arch/arm/cpu/arm926ejs/at91/eflash.c | 277 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-at91/at91_dbu.h | 41 ++++ arch/arm/include/asm/arch-at91/at91_eefc.h | 51 +++++ 4 files changed, 370 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/at91/eflash.c create mode 100644 arch/arm/include/asm/arch-at91/at91_dbu.h create mode 100644 arch/arm/include/asm/arch-at91/at91_eefc.h diff --git a/arch/arm/cpu/arm926ejs/at91/Makefile b/arch/arm/cpu/arm926ejs/at91/Makefile index 4f467be..def3980 100644 --- a/arch/arm/cpu/arm926ejs/at91/Makefile +++ b/arch/arm/cpu/arm926ejs/at91/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_AT91SAM9263) += at91sam9263_devices.o COBJS-$(CONFIG_AT91SAM9RL) += at91sam9rl_devices.o COBJS-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o COBJS-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o +COBJS-$(CONFIG_AT91_EFLASH) += eflash.o COBJS-$(CONFIG_AT91_LED) += led.o COBJS-y += clock.o COBJS-y += cpu.o diff --git a/arch/arm/cpu/arm926ejs/at91/eflash.c b/arch/arm/cpu/arm926ejs/at91/eflash.c new file mode 100644 index 0000000..83dce7d --- /dev/null +++ b/arch/arm/cpu/arm926ejs/at91/eflash.c @@ -0,0 +1,277 @@ +/* + * (C) Copyright 2010 + * Reinhard Meyer, EMK Elektronik, reinhard.meyer(a)emk-elektronik.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +/* + * this driver supports the enhanced embedded flash in the Atmel + * AT91SAM9XE devices with the following geometry: + * + * AT91SAM9XE128: 1 plane of 8 regions of 32 pages (total 256 pages) + * AT91SAM9XE256: 1 plane of 16 regions of 32 pages (total 512 pages) + * AT91SAM9XE512: 1 plane of 32 regions of 32 pages (total 1024 pages) + * (the exact geometry is read from the flash at runtime, so any + * future devices should already be covered) + * + * Regions can be write/erase protected. + * Whole (!) pages can be individually written with erase on the fly. + * Writing partial pages will corrupt the rest of the page. + * + * The flash is presented to u-boot with each region being a sector, + * having the following effects: + * Each sector can be hardware protected (protect on/off). + * Each page in a sector can be rewritten anytime. + * Since pages are erased when written, the "erase" does nothing. + * The first "CONFIG_EFLASH_PROTSECTORS" cannot be unprotected + * by u-Boot commands. + * + * Note: Redundant environment will not work in this flash since + * it does use partial page writes. Make sure the environent spans + * whole pages! + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/at91_eefc.h> +#include <asm/arch/at91_dbu.h> + +/* checks to detect configuration errors */ +#if CONFIG_SYS_MAX_FLASH_BANKS!=1 +#error eflash: this driver can only handle 1 bank +#endif + +/*#define DEBUG_FLASH*/ + +#ifdef DEBUG_FLASH +#define DEBUGF(fmt,args...) printf("eflash: "fmt ,##args) +#else +#define DEBUGF(fmt,args...) +#endif + +/* global structure */ +flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; +static u32 pagesize; + +unsigned long flash_init (void) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + at91_dbu_t *dbu = (at91_dbu_t *) 0xfffff200; + u32 id, size, nplanes, planesize, nlocks; + u32 addr, i, tmp=0; + +#ifdef DEBUG_FLASH + puts("eflash: init\n"); +#endif + + flash_info[0].flash_id = FLASH_UNKNOWN; + + /* check if its an AT91ARM9XE SoC */ + if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { +#ifdef DEBUG_FLASH + puts("eflash: not an AT91SAM9XE\n"); +#endif + return 0; + } + + /* now query the eflash for its structure */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + id = readl(&eefc->frr); /* word 0 */ + size = readl(&eefc->frr); /* word 1 */ + pagesize = readl(&eefc->frr); /* word 2 */ + nplanes = readl(&eefc->frr); /* word 3 */ + planesize = readl(&eefc->frr); /* word 4 */ + DEBUGF("id=%08x size=%u pagesize=%u planes=%u planesize=%u\n", + id, size, pagesize, nplanes, planesize); + for (i=1; i<nplanes; i++) { + tmp = readl(&eefc->frr); /* words 5..4+nplanes-1 */ + }; + nlocks = readl(&eefc->frr); /* word 4+nplanes */ + DEBUGF("nlocks=%u\n", nlocks); + /* since we are going to use the lock regions as sectors, check count */ + if (nlocks > CONFIG_SYS_MAX_FLASH_SECT) { + printf("eflash: number of lock regions(%u) "\ + "> CONFIG_SYS_MAX_FLASH_SECT. reducing...\n", + nlocks); + nlocks = CONFIG_SYS_MAX_FLASH_SECT; + } + flash_info[0].size = size; + flash_info[0].sector_count = nlocks; + flash_info[0].flash_id = id; + + addr = AT91SAM9XE_FLASH_BASE; + for (i=0; i<nlocks; i++) { + tmp = readl(&eefc->frr); /* words 4+nplanes+1.. */ + flash_info[0].start[i] = addr; + flash_info[0].protect[i] = 0; + addr += tmp; + }; + + /* now read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; i<flash_info[0].sector_count; i++) { + if (i%32 == 0) + tmp = readl(&eefc->frr); + flash_info[0].protect[i] = (tmp >> (i%32)) & 1; +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (i < CONFIG_EFLASH_PROTSECTORS) + flash_info[0].protect[i] = 1; +#endif + } + + return size; +} + +void flash_print_info (flash_info_t *info) +{ + int i; + + puts("AT91SAM9XE embedded flash\n"); + if (info->size >= (1 << 20)) { + i = 20; + } else { + i = 10; + } + printf(" Size: %ld %cB in %d Sectors\n", + info->size >> i, + (i == 20) ? 'M' : 'k', + info->sector_count); + + printf(" Sector Start Addresses:"); + for (i=0; i<info->sector_count; ++i) { + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s", + info->start[i], + info->protect[i] ? " (RO)" : " " + ); + } + printf ("\n"); + return; +} + +int flash_real_protect (flash_info_t *info, long sector, int prot) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + u32 pagenum = (info->start[sector]-AT91SAM9XE_FLASH_BASE)/pagesize; + u32 i, tmp=0; + + DEBUGF("protect sector=%ld prot=%d\n", sector, prot); + +#if defined(CONFIG_EFLASH_PROTSECTORS) + if (sector < CONFIG_EFLASH_PROTSECTORS) { + if (!prot) { + printf("eflash: sector %lu cannot be unprotected\n", + sector); + } + return 1; /* return anyway, caller does not care for result */ + } +#endif + if (prot) { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_SLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } else { + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_CLB | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + } + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* now read the protection information for all regions */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GLB, &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + for (i=0; i<info->sector_count; i++) { + if (i%32 == 0) + tmp = readl(&eefc->frr); + info->protect[i] = (tmp >> (i%32)) & 1; + } + return 0; +} + +static u32 erase_write_page (u32 pagenum) +{ + at91_eefc_t *eefc = (at91_eefc_t *) 0xfffffa00; + + DEBUGF("erase+write page=%u\n", pagenum); + + /* give erase and write page command */ + writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_EWP | + (pagenum << AT91_EEFC_FCR_FARG_SHIFT), &eefc->fcr); + while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) + ; + /* return status */ + return readl(&eefc->fsr) + & (AT91_EEFC_FSR_FCMDE | AT91_EEFC_FSR_FLOCKE); +} + +int flash_erase (flash_info_t *info, int s_first, int s_last) +{ + DEBUGF("erase first=%d last=%d\n", s_first, s_last); + return 0; +} + +/* + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + */ + +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) +{ + u32 pagenum; + u32 *src32, *dst32; + u32 i; + + DEBUGF("write src=%08lx addr=%08lx cnt=%lx\n", + (ulong)src, addr, cnt); + + /* REQUIRE addr to be on a page start, abort if not */ + if (addr % pagesize) { + printf ("eflash: start %08lx is not on page start\n"\ + " write aborted\n", addr); + return 1; + } + + /* now start copying data */ + pagenum = (addr-AT91SAM9XE_FLASH_BASE)/pagesize; + src32 = (u32 *) src; + dst32 = (u32 *) addr; + while (cnt > 0) { + i = pagesize / 4; + /* fill page buffer */ + while (i--) + *dst32++ = *src32++; + /* write page */ + if (erase_write_page(pagenum)) + return 1; + pagenum++; + if (cnt > pagesize) + cnt -= pagesize; + else + cnt = 0; + } + return 0; +} + diff --git a/arch/arm/include/asm/arch-at91/at91_dbu.h b/arch/arm/include/asm/arch-at91/at91_dbu.h new file mode 100644 index 0000000..669d933 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_dbu.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer(a)emk-elektronik.de + * + * Debug Unit + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_DBU_H +#define AT91_DBU_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_dbu { + u32 cr; /* Control Register WO */ + u32 mr; /* Mode Register RW */ + u32 ier; /* Interrupt Enable Register WO */ + u32 idr; /* Interrupt Disable Register WO */ + u32 imr; /* Interrupt Mask Register RO */ + u32 sr; /* Status Register RO */ + u32 rhr; /* Receive Holding Register RO */ + u32 thr; /* Transmit Holding Register WO */ + u32 brgr; /* Baud Rate Generator Register RW */ + u32 res1[7];/* 0x0024 - 0x003C Reserved */ + u32 cidr; /* Chip ID Register RO */ + u32 exid; /* Chip ID Extension Register RO */ + u32 fnr; /* Force NTRST Register RW */ +} at91_dbu_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_DBU_CID_ARCH_MASK 0x0ff00000 +#define AT91_DBU_CID_ARCH_9xx 0x01900000 +#define AT91_DBU_CID_ARCH_9XExx 0x02900000 + +#endif diff --git a/arch/arm/include/asm/arch-at91/at91_eefc.h b/arch/arm/include/asm/arch-at91/at91_eefc.h new file mode 100644 index 0000000..9bb3ea2 --- /dev/null +++ b/arch/arm/include/asm/arch-at91/at91_eefc.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2010 + * Reinhard Meyer, reinhard.meyer(a)emk-elektronik.de + * + * Enhanced Embedded Flash Controller + * Based on AT91SAM9XE datasheet + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_EEFC_H +#define AT91_EEFC_H + +#ifndef __ASSEMBLY__ + +typedef struct at91_eefc { + u32 fmr; /* Flash Mode Register RW */ + u32 fcr; /* Flash Command Register WO */ + u32 fsr; /* Flash Status Register RO */ + u32 frr; /* Flash Result Register RO */ +} at91_eefc_t; + +#endif /* __ASSEMBLY__ */ + +#define AT91_EEFC_FMR_FWS_MASK 0x00000f00 +#define AT91_EEFC_FMR_FRDY_BIT 0x00000001 + +#define AT91_EEFC_FCR_KEY 0x5a000000 +#define AT91_EEFC_FCR_FARG_MASK 0x00ffff00 +#define AT91_EEFC_FCR_FARG_SHIFT 8 +#define AT91_EEFC_FCR_FCMD_GETD 0x0 +#define AT91_EEFC_FCR_FCMD_WP 0x1 +#define AT91_EEFC_FCR_FCMD_WPL 0x2 +#define AT91_EEFC_FCR_FCMD_EWP 0x3 +#define AT91_EEFC_FCR_FCMD_EWPL 0x4 +#define AT91_EEFC_FCR_FCMD_EA 0x5 +#define AT91_EEFC_FCR_FCMD_SLB 0x8 +#define AT91_EEFC_FCR_FCMD_CLB 0x9 +#define AT91_EEFC_FCR_FCMD_GLB 0xA +#define AT91_EEFC_FCR_FCMD_SGPB 0xB +#define AT91_EEFC_FCR_FCMD_CGPB 0xC +#define AT91_EEFC_FCR_FCMD_GGPB 0xD + +#define AT91_EEFC_FSR_FRDY 1 +#define AT91_EEFC_FSR_FCMDE 2 +#define AT91_EEFC_FSR_FLOCKE 4 + +#endif -- 1.5.6.5

1 1

[U-Boot] [PATCH v4] [U-BOOT] Zoom3: Add support for OMAP3630 Zoom3 board.
by Aldo Cedillo 16 Jul '10

16 Jul '10

From: Aldo Brett Cedillo Martinez <aldo.cedillo(a)ti.com> This patch gives basic functionality to OMAP3630 Zoom3 board. This version has been rebased againts u-boot-ti Signed-off-by: Aldo Brett Cedillo Martinez <aldo.cedillo(a)ti.com> --- MAINTAINERS | 4 + MAKEALL | 1 + board/logicpd/zoom3/Makefile | 54 +++++++ board/logicpd/zoom3/config.mk | 33 +++++ board/logicpd/zoom3/debug_board.c | 66 +++++++++ board/logicpd/zoom3/led.c | 133 +++++++++++++++++ board/logicpd/zoom3/zoom3.c | 201 ++++++++++++++++++++++++++ board/logicpd/zoom3/zoom3.h | 164 +++++++++++++++++++++ board/logicpd/zoom3/zoom3_serial.c | 132 +++++++++++++++++ board/logicpd/zoom3/zoom3_serial.h | 76 ++++++++++ boards.cfg | 1 + common/serial.c | 2 + include/configs/omap3_zoom3.h | 274 ++++++++++++++++++++++++++++++++++++ include/serial.h | 7 + 14 files changed, 1148 insertions(+), 0 deletions(-) create mode 100644 board/logicpd/zoom3/Makefile create mode 100644 board/logicpd/zoom3/config.mk create mode 100644 board/logicpd/zoom3/debug_board.c create mode 100644 board/logicpd/zoom3/led.c create mode 100644 board/logicpd/zoom3/zoom3.c create mode 100644 board/logicpd/zoom3/zoom3.h create mode 100644 board/logicpd/zoom3/zoom3_serial.c create mode 100644 board/logicpd/zoom3/zoom3_serial.h create mode 100644 include/configs/omap3_zoom3.h diff --git a/MAINTAINERS b/MAINTAINERS index 1520312..260fda3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -813,6 +813,10 @@ Alex Z lart SA1100 dnp1110 SA1110 +Aldo Brett Cedillo Martinez <aldo.cedillo(a)ti.com> + + omap3_zoom3 ARM CORTEX-A8 (OMAP3xx SoC) + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index 2e98b6c..4254a5c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -657,6 +657,7 @@ LIST_ARMV7=" \ omap3_sdp3430 \ omap3_zoom1 \ omap3_zoom2 \ + omap3_zoom3 \ omap4_panda \ omap4_sdp4430 \ s5p_goni \ diff --git a/board/logicpd/zoom3/Makefile b/board/logicpd/zoom3/Makefile new file mode 100644 index 0000000..79c02ab --- /dev/null +++ b/board/logicpd/zoom3/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# Aldo Cedillo <aldo.cedillo(a)ti.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS-y := $(BOARD).o +COBJS-y += debug_board.o +COBJS-y += zoom3_serial.o +COBJS-$(CONFIG_STATUS_LED) += led.o + +COBJS := $(sort $(COBJS-y)) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +#defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/logicpd/zoom3/config.mk b/board/logicpd/zoom3/config.mk new file mode 100644 index 0000000..33f394b --- /dev/null +++ b/board/logicpd/zoom3/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2009 +# Texas Instruments, <www.ti.com> +# +# Zoom II uses OMAP3 (ARM-CortexA8) CPU +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 0x80000000 (bank0) +# 0xA0000000 (bank1) +# Linux-Kernel is expected to be at 0x80008000, entry 0x80008000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/board/logicpd/zoom3/debug_board.c b/board/logicpd/zoom3/debug_board.c new file mode 100644 index 0000000..0cb84ed --- /dev/null +++ b/board/logicpd/zoom3/debug_board.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2010 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/mux.h> +#include <asm/arch/gpio.h> + +#define DEBUG_BOARD_CONNECTED 1 +#define DEBUG_BOARD_NOT_CONNECTED 0 + +static int debug_board_connected = DEBUG_BOARD_CONNECTED; + +static void zoom3_debug_board_detect(void) +{ + int val = 0; + + /* + * TODO gpio 158 is UART1_RX, should we make a macro of this + * instead of the raw number? + */ + if (!omap_request_gpio(158)) { + /* + * GPIO to query for debug board + * 158 db board query + */ + omap_set_gpio_direction(158, 1); + val = omap_get_gpio_datain(158); + omap_free_gpio(158); + } + + if (!val) + debug_board_connected = DEBUG_BOARD_NOT_CONNECTED; +} + +int zoom3_debug_board_connected(void) +{ + static int first_time = 1; + + if (first_time) { + zoom3_debug_board_detect(); + first_time = 0; + } + + return debug_board_connected; +} diff --git a/board/logicpd/zoom3/led.c b/board/logicpd/zoom3/led.c new file mode 100644 index 0000000..1871d79 --- /dev/null +++ b/board/logicpd/zoom3/led.c @@ -0,0 +1,133 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <status_led.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/gpio.h> + +static unsigned int saved_state[2] = {STATUS_LED_OFF, STATUS_LED_OFF}; + +/* + * GPIO LEDs + * 173 red + * 154 blue + * 61 blue2 + */ +#define ZOOM3_LED_RED 173 +#define ZOOM3_LED_BLUE 154 +#define ZOOM3_LED_BLUE2 61 + +void red_LED_off(void) +{ + /* red */ + if (!omap_request_gpio(ZOOM3_LED_RED)) { + omap_set_gpio_direction(ZOOM3_LED_RED, 0); + omap_set_gpio_dataout(ZOOM3_LED_RED, 0); + } + + saved_state[STATUS_LED_RED] = STATUS_LED_OFF; +} + +void blue_LED_off(void) +{ + /* blue */ + if (!omap_request_gpio(ZOOM3_LED_BLUE)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE, 0); + } + + /* blue 2 */ + if (!omap_request_gpio(ZOOM3_LED_BLUE2)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE2, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE2, 0); + } + + saved_state[STATUS_LED_BLUE] = STATUS_LED_OFF; +} + +void red_LED_on(void) +{ + blue_LED_off(); + + /* red */ + if (!omap_request_gpio(ZOOM3_LED_RED)) { + omap_set_gpio_direction(ZOOM3_LED_RED, 0); + omap_set_gpio_dataout(ZOOM3_LED_RED, 1); + } + + saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; +} + +void blue_LED_on(void) +{ + red_LED_off(); + + /* blue */ + if (!omap_request_gpio(ZOOM3_LED_BLUE)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE, 1); + } + + /* blue 2 */ + if (!omap_request_gpio(ZOOM3_LED_BLUE2)) { + omap_set_gpio_direction(ZOOM3_LED_BLUE2, 0); + omap_set_gpio_dataout(ZOOM3_LED_BLUE2, 1); + } + + saved_state[STATUS_LED_BLUE] = STATUS_LED_ON; +} + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + if (STATUS_LED_BLUE == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_BLUE]) + blue_LED_off(); + else + blue_LED_on(); + } else if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == saved_state[STATUS_LED_RED]) + red_LED_off(); + else + red_LED_on(); + } +} + +void __led_set(led_id_t mask, int state) +{ + if (STATUS_LED_BLUE == mask) { + if (STATUS_LED_ON == state) + blue_LED_on(); + else + blue_LED_off(); + } else if (STATUS_LED_RED == mask) { + if (STATUS_LED_ON == state) + red_LED_on(); + else + red_LED_off(); + } +} diff --git a/board/logicpd/zoom3/zoom3.c b/board/logicpd/zoom3/zoom3.c new file mode 100644 index 0000000..f5a8201 --- /dev/null +++ b/board/logicpd/zoom3/zoom3.c @@ -0,0 +1,201 @@ +/* + * Copyright (c) 2010 Texas Instruments <www.ti.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * Derived from Zoom2 code by + * Tom Rix <Tom.Rix(a)windriver.com> + * + * Derived from Zoom1 code by + * Nishanth Menon <nm(a)ti.com> + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <khasim(a)ti.com> + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <netdev.h> +#ifdef CONFIG_STATUS_LED +#include <status_led.h> +#endif +#include <twl4030.h> +#include <asm/io.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mem.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include "zoom3.h" +#include "zoom3_serial.h" + + +/* + * This is the zoom3, board specific, gpmc configuration for the + * quad uart on the debug board. The more general gpmc configurations + * are setup at the cpu level in vim arch/arm/cpu/armv7/omap3/mem.c + * + * The details of the setting of the serial gpmc setup are not available. + * The values were provided by another party. + */ +static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { + 0x00011000, + 0x001f1f01, + 0x00080803, + 0x1d091d09, + 0x041f1f1f, + 0x1d0904c4, 0 +}; + +/* Used to track the revision of the board */ +static zoom3_revision revision = ZOOM3_REVISION_UNKNOWN; + +/* + * Routine: zoom3_get_version + * Description: Return the revision of the Zoom3 this code is running on. + */ +zoom3_revision zoom3_get_revision(void) +{ + return revision; +} + +/* + * Routine: zoom3_identify + * Description: Detect which version of Zoom3 we are running on. + */ +void zoom3_identify(void) +{ + /* + * To check for production board vs beta board, + * check if gpio 94 is clear. + * + * No way yet to check for alpha board identity. + * Alpha boards were produced in very limited quantities + * and they are not commonly used. The are mentioned here + * only for completeness. + */ + if (!omap_request_gpio(94)) { + unsigned int val; + + omap_set_gpio_direction(94, 1); + val = omap_get_gpio_datain(94); + omap_free_gpio(94); + + if (val) + revision = ZOOM3_REVISION_BETA; + else + revision = ZOOM3_REVISION_PRODUCTION; + } + + puts("Board revision "); + + switch (revision) { + case ZOOM3_REVISION_PRODUCTION: + puts("Production\n"); + break; + case ZOOM3_REVISION_BETA: + puts("Beta\n"); + break; + default: + puts("Unknown\n"); + break; + } +} + +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + u32 *gpmc_config; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + + /* Configure console support for zoom3 */ + gpmc_config = gpmc_serial_TL16CP754C; + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3], + SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M); + + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM3; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP36XX_SDRC_CS0 + 0x100); + +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif + return 0; +} + +/* + * Routine: misc_init_r + * Description: Configure zoom board specific configurations + */ +int misc_init_r(void) +{ + zoom3_identify(); + #if (CONFIG_TWL4030_POWER) + twl4030_power_init(); + twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); + #endif + dieid_num_r(); + + /* + * Board reset + * The board is reset by holding the large button + * on the top right side of the main board + * for eight seconds + * + * There are reported problems of some beta boards + * continously resetting. For those boards, disable resetting. + */ + #if (CONFIG_TWL4030_POWER) + if (ZOOM3_REVISION_PRODUCTION <= zoom3_get_revision()) + twl4030_power_reset_init(); + #endif + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuratino Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + /* platform specific muxes */ + MUX_ZOOM3(); +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_LAN91C96 + rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE); +#endif + return rc; +} +#endif diff --git a/board/logicpd/zoom3/zoom3.h b/board/logicpd/zoom3/zoom3.h new file mode 100644 index 0000000..b67208c --- /dev/null +++ b/board/logicpd/zoom3/zoom3.h @@ -0,0 +1,164 @@ +/* + * Copyright (c) 2010 Texas Instruments + * + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * Derived from: board/omap3/zoom2/zoom2.h + * Tom Rix <Tom.Rix(a)windriver.com> + * + * Derived from: board/omap3/zoom1/zoom1.h + * Nishanth Menon <nm(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _BOARD_ZOOM3_H_ +#define _BOARD_ZOOM3_H_ + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "OMAP3 Zoom3", + "NAND", +}; + +typedef enum { + ZOOM3_REVISION_UNKNOWN = 0, + ZOOM3_REVISION_ALPHA, + ZOOM3_REVISION_BETA, + ZOOM3_REVISION_PRODUCTION +} zoom3_revision; + +zoom3_revision zoom3_get_revision(void); + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_ZOOM3() do {\ + /* SDRC*/\ +MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ +MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ +MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ +MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ +MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ +MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ +MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ +MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ +MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* SDRC_D8 */\ +MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /* SDRC_D9 */\ +MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /* SDRC_D10 */\ +MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /* SDRC_D11 */\ +MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /* SDRC_D12 */\ +MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /* SDRC_D13 */\ +MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /* SDRC_D14 */\ +MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /* SDRC_D15 */\ +MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /* SDRC_D16 */\ +MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /* SDRC_D17 */\ +MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /* SDRC_D18 */\ +MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /* SDRC_D19 */\ +MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /* SDRC_D20 */\ +MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /* SDRC_D21 */\ +MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /* SDRC_D22 */\ +MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /* SDRC_D23 */\ +MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /* SDRC_D24 */\ +MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /* SDRC_D25 */\ +MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /* SDRC_D26 */\ +MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /* SDRC_D27 */\ +MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /* SDRC_D28 */\ +MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /* SDRC_D29 */\ +MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /* SDRC_D30 */\ +MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /* SDRC_D31 */\ +MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /* SDRC_CLK */\ +MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /* SDRC_DQS0 */\ +MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /* SDRC_DQS1 */\ +MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /* SDRC_DQS2 */\ +MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /* SDRC_DQS3 */\ +/* GPMC */\ +MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /* GPMC_A1 */\ +MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /* GPMC_A2 */\ +MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /* GPMC_A3 */\ +MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /* GPMC_A4 */\ +MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /* GPMC_A5 */\ +MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /* GPMC_A6 */\ +MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /* GPMC_A7 */\ +MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /* GPMC_A8 */\ +MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /* GPMC_A9 */\ +MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /* GPMC_A10 */\ +MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /* GPMC_D0 */\ +MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /* GPMC_D1 */\ +MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /* GPMC_D2 */\ +MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /* GPMC_D3 */\ +MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /* GPMC_D4 */\ +MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /* GPMC_D5 */\ +MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /* GPMC_D6 */\ +MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /* GPMC_D7 */\ +MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /* GPMC_D8 */\ +MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /* GPMC_D9 */\ +MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /* GPMC_D10 */\ +MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /* GPMC_D11 */\ +MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /* GPMC_D12 */\ +MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /* GPMC_D13 */\ +MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /* GPMC_D14 */\ +MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /* GPMC_D15 */\ +MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\ +MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M7)) /* GPMC_nCS1 */\ +MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M7)) /* GPMC_nCS2 */\ +MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M7)) /* GPMC_nCS3 */\ +MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M7)) /* GPMC_nCS4 */\ +MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M7)) /* GPMC_nCS5 */\ +MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M7)) /* GPMC_nCS6 */\ +MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M7)) /* GPMC_nCS7 */\ +MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /* GPMC_CLK */\ +MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /* GPMC_nADV_ALE */\ +MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /* GPMC_nOE */\ +MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /* GPMC_nWE */\ +MUX_VAL(CP(GPMC_NWP), (IDIS | PTU | DIS | M0)) /* GPMC_nWP */\ +MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /* GPMC_nBE0_CLE */\ +MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /* GPMC_nBE1 */\ +MUX_VAL(CP(GPMC_WAIT0), (IEN | PTD | EN | M0)) /* GPMC_WAIT0 */\ +MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /* GPMC_WAIT1 */\ +MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /* GPMC_WAIT2 */\ +MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /* GPMC_WAIT3 */\ +/* IDCC modem Power On */\ +MUX_VAL(CP(CAM_D11), (IEN | PTU | EN | M4)) /* GPIO_110 */\ +MUX_VAL(CP(CAM_D4), (IEN | PTU | EN | M4)) /* GPIO_103 */\ +/* GPMC CS7 has LAN9211 device */\ +MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\ +MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M4)) /* LAN9221 */\ +MUX_VAL(CP(MCSPI1_CS2), (IEN | PTD | EN | M0)) /* MCSPI1_CS2 */\ +/* GPMC CS3 has Serial TL16CP754C device */\ +MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPMC_nCS3 */\ +/* Toggle Reset pin of TL16CP754C device */\ +MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTU | EN | M4)) /* GPIO_152 */\ + udelay(10);\ +MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | EN | M4)) /* GPIO_152 */\ +MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /* SDRC_CKE1 */\ +/* LEDS */\ +MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | EN | M4)) /* GPIO_173 red */\ +MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | EN | M4)) /* GPIO_154 blue */\ +MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | EN | M4)) /* GPIO_61 blue2 */\ +} while (0) + +#endif /* _BOARD_ZOOM3_H_ */ diff --git a/board/logicpd/zoom3/zoom3_serial.c b/board/logicpd/zoom3/zoom3_serial.c new file mode 100644 index 0000000..e50c6dc --- /dev/null +++ b/board/logicpd/zoom3/zoom3_serial.c @@ -0,0 +1,132 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * This file was adapted from arch/powerpc/cpu/mpc5xxx/serial.c + * + */ + +#include <common.h> +#include <serial.h> +#include <ns16550.h> +#include <asm/arch/cpu.h> +#include "zoom3_serial.h" + +int quad_init_dev(unsigned long base) +{ + /* + * The Quad UART is on the debug board. + * Check if the debug board is attached before using the UART + */ + if (zoom3_debug_board_connected()) { + NS16550_t com_port = (NS16550_t) base; + int baud_divisor = CONFIG_SYS_NS16550_CLK / 16 / + CONFIG_BAUDRATE; + /* + * Zoom3 has a board specific initialization of its UART. + * This generic initialization has been copied from + * drivers/serial/ns16550.c. The macros have been expanded. + * + * Do the following instead of + * NS16550_init (com_port, clock_divisor); + */ + com_port->ier = 0x00; + + /* + * On Zoom3 board Set pre-scalar to 1 + * CLKSEL is GND => MCR[7] is 1 => preslr is 4 + * So change the prescl to 1 + */ + com_port->lcr = 0xbf; + com_port->fcr |= 0x10; + com_port->mcr &= 0x7f; + + /* This is generic ns16550.c setup */ + com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; + com_port->dll = 0; + com_port->dlm = 0; + com_port->lcr = UART_LCR_8N1; + com_port->mcr = UART_MCR_DTR | UART_MCR_RTS; + com_port->fcr = UART_FCR_FIFO_EN | UART_FCR_RXSR | + UART_FCR_TXSR; + com_port->lcr = UART_LCR_BKSE | UART_LCR_8N1; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = UART_LCR_8N1; + } + + /* + * We have to lie here, otherwise the board init code will hang + * on the check + */ + return 0; +} + +void quad_putc_dev(unsigned long base, const char c) +{ + if (zoom3_debug_board_connected()) { + if (c == '\n') + quad_putc_dev(base, '\r'); + + NS16550_putc((NS16550_t) base, c); + } else { + usbtty_putc(c); + } +} + +void quad_puts_dev(unsigned long base, const char *s) +{ + if (zoom3_debug_board_connected()) { + while ((s != NULL) && (*s != '\0')) + quad_putc_dev(base, *s++); + } else { + usbtty_puts(s); + } +} + +int quad_getc_dev(unsigned long base) +{ + if (zoom3_debug_board_connected()) + return NS16550_getc((NS16550_t) base); + + return usbtty_getc(); +} + +int quad_tstc_dev(unsigned long base) +{ + if (zoom3_debug_board_connected()) + return NS16550_tstc((NS16550_t) base); + + return usbtty_tstc(); +} + +void quad_setbrg_dev(unsigned long base) +{ + if (zoom3_debug_board_connected()) { + int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / + CONFIG_BAUDRATE; + + NS16550_reinit((NS16550_t) base, clock_divisor); + } +} + +QUAD_INIT(0) +QUAD_INIT(1) +QUAD_INIT(2) +QUAD_INIT(3) diff --git a/board/logicpd/zoom3/zoom3_serial.h b/board/logicpd/zoom3/zoom3_serial.h new file mode 100644 index 0000000..f581a7f --- /dev/null +++ b/board/logicpd/zoom3/zoom3_serial.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2009 Wind River Systems, Inc. + * Tom Rix <Tom.Rix(a)windriver.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#ifndef ZOOM3_SERIAL_H +#define ZOOM3_SERIAL_H + +extern int zoom3_debug_board_connected(void); + +#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom3 serial chip address */ + +#define QUAD_BASE_0 SERIAL_TL16CP754C_BASE +#define QUAD_BASE_1 (SERIAL_TL16CP754C_BASE + 0x100) +#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200) +#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300) + +#define S(a) #a +#define N(a) S(quad##a) +#define U(a) S(UART##a) + +#define QUAD_INIT(n) \ +int quad_init_##n(void) \ +{ \ + return quad_init_dev(QUAD_BASE_##n); \ +} \ +void quad_setbrg_##n(void) \ +{ \ + quad_setbrg_dev(QUAD_BASE_##n); \ +} \ +void quad_putc_##n(const char c) \ +{ \ + quad_putc_dev(QUAD_BASE_##n, c); \ +} \ +void quad_puts_##n(const char *s) \ +{ \ + quad_puts_dev(QUAD_BASE_##n, s); \ +} \ +int quad_getc_##n(void) \ +{ \ + return quad_getc_dev(QUAD_BASE_##n); \ +} \ +int quad_tstc_##n(void) \ +{ \ + return quad_tstc_dev(QUAD_BASE_##n); \ +} \ +struct serial_device zoom3_serial_device##n = \ +{ \ + N(n), \ + U(n), \ + quad_init_##n, \ + NULL, \ + quad_setbrg_##n, \ + quad_getc_##n, \ + quad_tstc_##n, \ + quad_putc_##n, \ + quad_puts_##n, \ +}; + +#endif /* ZOOM3_SERIAL_H */ diff --git a/boards.cfg b/boards.cfg index 59cc128..8f9fed9 100644 --- a/boards.cfg +++ b/boards.cfg @@ -259,6 +259,7 @@ omap3_overo arm armv7 overo - omap3 omap3_pandora arm armv7 pandora - omap3 omap3_zoom1 arm armv7 zoom1 logicpd omap3 omap3_zoom2 arm armv7 zoom2 logicpd omap3 +omap3_zoom3 arm armv7 zoom3 logicpd omap3 omap3_beagle arm armv7 beagle ti omap3 omap3_evm arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 diff --git a/common/serial.c b/common/serial.c index fceabfa..2a644ba 100644 --- a/common/serial.c +++ b/common/serial.c @@ -92,6 +92,8 @@ struct serial_device *__default_serial_console (void) #endif #elif defined(CONFIG_OMAP3_ZOOM2) return ZOOM2_DEFAULT_SERIAL_DEVICE; +#elif defined(CONFIG_OMAP3_ZOOM3) + return ZOOM3_DEFAULT_SERIAL_DEVICE; #else #error No default console #endif diff --git a/include/configs/omap3_zoom3.h b/include/configs/omap3_zoom3.h new file mode 100644 index 0000000..8c52fb7 --- /dev/null +++ b/include/configs/omap3_zoom3.h @@ -0,0 +1,274 @@ +/* + * (C) Copyright 2006-2010 Texas Instruments. + * + * Richard Woodruff <r-woodruff2(a)ti.com> + * Syed Mohammed Khasim <x0khasim(a)ti.com> + * Nishanth Menon <nm(a)ti.com> + * Tom Rix <Tom.Rix(a)windriver.com> + * Aldo Cedillo <aldo.cedillo(a)ti.com> + * + * Configuration settings for the TI OMAP3630 Zoom 3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP36XX 1 /* which is a 36XX */ +#define CONFIG_OMAP3_ZOOM3 1 /* working with a Zoom3 */ + +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +/* + * Display CPU and board information + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ +/* Sector */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/* + * Hardware drivers + */ + +/* + * NS16550 Configuration + * Zoom3 uses the TL16CP754C on the debug board + */ +#define CONFIG_SERIAL_MULTI 1 + +/* + * 0 - 1 : first USB with respect to the left edge of the debug board + * 2 - 3 : second USB with respect to the left edge of the debug board + */ +#define ZOOM3_DEFAULT_SERIAL_DEVICE (&zoom3_serial_device0) + +#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_REG_SIZE (-2) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {115200} + +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ + +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 + +/* DDR - Use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + +/* Status LED */ +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ +#define CONFIG_BOARD_SPECIFIC_LED 1 +#define STATUS_LED_BLUE 0 /* Check what color is used */ +#define STATUS_LED_RED 1 /* when using 3630 */ +/* Blue */ +#define STATUS_LED_BIT STATUS_LED_BLUE +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +/* Red */ +#define STATUS_LED_BIT1 STATUS_LED_RED +#define STATUS_LED_STATE1 STATUS_LED_OFF +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +/* Optional value */ +#define STATUS_LED_BOOT STATUS_LED_BIT + +/* GPIO banks */ +#ifdef CONFIG_STATUS_LED +#define CONFIG_OMAP3_GPIO_2 /* ZOOM2_LED_BLUE2 */ +#define CONFIG_OMAP3_GPIO_6 /* ZOOM2_LED_RED */ +#endif +#define CONFIG_OMAP3_GPIO_3 /* board revision */ +#define CONFIG_OMAP3_GPIO_5 /* debug board detection, ZOOM2_LED_BLUE */ + +/* USB */ +#define CONFIG_MUSB_UDC 1 +#define CONFIG_USB_OMAP3 1 + +/* USB device configuration */ +#define CONFIG_USB_DEVICE 1 +#define CONFIG_USB_TTY 1 +/* Change these to suit your needs */ +#define CONFIG_USBD_VENDORID 0x0451 +#define CONFIG_USBD_PRODUCTID 0x5678 +#define CONFIG_USBD_MANUFACTURER "Texas Instruments" +#define CONFIG_USBD_PRODUCT_NAME "Zoom3" + +/* Commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_FAT /* FAT support */ +#undef CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */ + +#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMI /* iminfo */ +#undef CONFIG_CMD_IMLS /* List all found images */ +#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ +#undef CONFIG_CMD_NFS /* NFS support */ + +#define CONFIG_SYS_NO_FLASH + +/* + * Board NAND info + */ +#define CONFIG_NAND_OMAP_GPMC +#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ + /* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ + /* to access nand at */ + /* CS0 */ +#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define CONFIG_SYS_MAX_NAND_DEVICE 1 + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "usbtty=cdc_acm\0" \ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_PROMPT "OMAP3 Zoom3 #" +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* Memset from start of memory to 31MB */ +#define OMAP36XX_SDRC_CS0 OMAP34XX_SDRC_CS0 /* It's the same as in 34XX */ +#define OMAP36XX_SDRC_CS1 OMAP34XX_SDRC_CS1 /* It's the same as in 34XX */ +#define CONFIG_SYS_MEMTEST_START (OMAP36XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP36XX_SDRC_CS0 + 0x01f00000) +/* The default load address is the start of memory */ +#define CONFIG_SYS_LOAD_ADDR (OMAP36XX_SDRC_CS0) +/* Everything, incl board info, in Hz */ +#undef CONFIG_SYS_CLKS_IN_HZ + +/* + * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define OMAP36XX_GPT2 OMAP34XX_GPT2 /* It's the same as in 34XX */ +#define CONFIG_SYS_TIMERBASE (OMAP36XX_GPT2) +#define CONFIG_SYS_PTV 7 /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((V_SCLK) / (2 << CONFIG_SYS_PTV)) + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using these settings + */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ +#endif + +/* + * Physical memory map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not */ + /* be populated */ +#define PHYS_SDRAM_1 OMAP36XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) +#define PHYS_SDRAM_2 OMAP36XX_SDRC_CS1 + +/* SDRAM bank allocation method */ +#define SDRC_R_B_C + +/* + * FLASH and environment organization + */ + +/* **** PISMO SUPPORT **** */ +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M +#define PISMO1_ONEN_SIZE GPMC_SIZE_128M + +#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ + /* one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_SYS_FLASH_BASE boot_flash_base + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE + +#define CONFIG_ENV_IS_IN_NAND 1 +#define SMNAND_ENV_OFFSET 0x0c0000 /* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec +#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/* + * CFI FLASH driver setup + */ +/* timout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +#ifndef __ASSEMBLY__ +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_blash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#endif /* __CONFIG_H */ + diff --git a/include/serial.h b/include/serial.h index 6513d8e..236e5d1 100644 --- a/include/serial.h +++ b/include/serial.h @@ -66,6 +66,13 @@ extern struct serial_device zoom2_serial_device2; extern struct serial_device zoom2_serial_device3; #endif +#if defined(CONFIG_OMAP3_ZOOM3) +extern struct serial_device zoom3_serial_device0; +extern struct serial_device zoom3_serial_device1; +extern struct serial_device zoom3_serial_device2; +extern struct serial_device zoom3_serial_device3; +#endif + extern struct serial_device serial_ffuart_device; extern struct serial_device serial_btuart_device; extern struct serial_device serial_stuart_device; -- 1.6.3.3

2 1

[U-Boot] [PULL] U-Boot-pxa
by Marek Vasut 16 Jul '10

16 Jul '10

Please merge into -master. The following changes since commit d6f324d03d7829a1da1dee8b60f91b173a3976f0: Merge branch 'next' of git://git.denx.de/u-boot-nios (2010-07-14 22:07:41 +0200) are available in the git repository at: git://git.denx.de/u-boot-pxa.git master Marek Vasut (9): Enable PXAFB for PXA27X and PXA3XX PXA: Add hardware init helper macros PXA: Add PWM2 and PWM3 regs to pxa-regs.h PXA: Add OneNAND booting support to start.S Voipac PXA270 LCD Support PXA: Add support for LMS285GF05 into pxafb PXA: Voipac PXA270 Support PXA: Toradex Colibri PXA270 support PXA: ZipitZ2 support MAKEALL | 4 + Makefile | 9 + arch/arm/cpu/pxa/pxafb.c | 76 ++++++- arch/arm/cpu/pxa/start.S | 48 ++++- arch/arm/include/asm/arch-pxa/macro.h | 324 ++++++++++++++++++++++++++ arch/arm/include/asm/arch-pxa/pxa-regs.h | 10 +- board/colibri_pxa270/Makefile | 45 ++++ board/colibri_pxa270/colibri_pxa270.c | 118 ++++++++++ board/colibri_pxa270/config.mk | 1 + board/colibri_pxa270/lowlevel_init.S | 36 +++ board/vpac270/Makefile | 48 ++++ board/vpac270/config.mk | 1 + board/vpac270/lowlevel_init.S | 40 ++++ board/vpac270/u-boot.lds | 55 +++++ board/vpac270/vpac270.c | 127 ++++++++++ board/zipitz2/Makefile | 54 +++++ board/zipitz2/config.mk | 1 + board/zipitz2/lowlevel_init.S | 40 ++++ board/zipitz2/u-boot.lds | 56 +++++ board/zipitz2/zipitz2.c | 213 +++++++++++++++++ boards.cfg | 2 + common/lcd.c | 12 +- include/configs/colibri_pxa270.h | 278 ++++++++++++++++++++++ include/configs/vpac270.h | 323 +++++++++++++++++++++++++ include/configs/zipitz2.h | 259 ++++++++++++++++++++ include/lcd.h | 2 +- onenand_ipl/board/vpac270/Makefile | 83 +++++++ onenand_ipl/board/vpac270/config.mk | 1 + onenand_ipl/board/vpac270/lowlevel_init.S | 34 +++ onenand_ipl/board/vpac270/u-boot.onenand.lds | 51 ++++ onenand_ipl/board/vpac270/vpac270.c | 42 ++++ 31 files changed, 2379 insertions(+), 14 deletions(-) create mode 100644 arch/arm/include/asm/arch-pxa/macro.h create mode 100644 board/colibri_pxa270/Makefile create mode 100644 board/colibri_pxa270/colibri_pxa270.c create mode 100644 board/colibri_pxa270/config.mk create mode 100644 board/colibri_pxa270/lowlevel_init.S create mode 100644 board/vpac270/Makefile create mode 100644 board/vpac270/config.mk create mode 100644 board/vpac270/lowlevel_init.S create mode 100644 board/vpac270/u-boot.lds create mode 100644 board/vpac270/vpac270.c create mode 100644 board/zipitz2/Makefile create mode 100644 board/zipitz2/config.mk create mode 100644 board/zipitz2/lowlevel_init.S create mode 100644 board/zipitz2/u-boot.lds create mode 100644 board/zipitz2/zipitz2.c create mode 100644 include/configs/colibri_pxa270.h create mode 100644 include/configs/vpac270.h create mode 100644 include/configs/zipitz2.h create mode 100644 onenand_ipl/board/vpac270/Makefile create mode 100644 onenand_ipl/board/vpac270/config.mk create mode 100644 onenand_ipl/board/vpac270/lowlevel_init.S create mode 100644 onenand_ipl/board/vpac270/u-boot.onenand.lds create mode 100644 onenand_ipl/board/vpac270/vpac270.c

3 3

[U-Boot] [PATCH 2/3] at91: Update meesc board to new SoC access
by Daniel Gorsulowski 15 Jul '10

15 Jul '10

* convert meesc board to use c stucture SoC access * change gpio access to at91_gpio syntax * moved CONFIG_SYS_HZ below board and cpu defines (purely cosmetic) Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski(a)esd.eu> --- board/esd/meesc/meesc.c | 118 ++++++++++++++++++++++++----------------------- include/configs/meesc.h | 9 ++-- 2 files changed, 65 insertions(+), 62 deletions(-) diff --git a/board/esd/meesc/meesc.c b/board/esd/meesc/meesc.c index a1b66cb..1477fab 100644 --- a/board/esd/meesc/meesc.c +++ b/board/esd/meesc/meesc.c @@ -1,12 +1,12 @@ /* + * (C) Copyright 2010 + * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> + * esd electronic system design gmbh <www.esd.eu> + * * (C) Copyright 2007-2008 * Stelian Pop <stelian.pop(a)leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009 - * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> - * esd electronic system design gmbh <www.esd.eu> - * * See file CREDITS for list of people who contributed to this * project. * @@ -28,13 +28,13 @@ #include <common.h> #include <asm/arch/at91sam9263.h> -#include <asm/arch/at91sam9_matrix.h> #include <asm/arch/at91sam9_smc.h> #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/at91_matrix.h> +#include <asm/arch/at91_pio.h> #include <asm/arch/clk.h> -#include <asm/arch/gpio.h> #include <asm/arch/hardware.h> #include <asm/arch/io.h> #include <netdev.h> @@ -52,10 +52,10 @@ int get_hw_rev(void) if (hw_rev >= 0) return hw_rev; - hw_rev = at91_get_gpio_value(AT91_PIN_PB19); - hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2; - hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3; + hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19); + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2; + hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3; if (hw_rev == 15) hw_rev = 0; @@ -67,44 +67,44 @@ int get_hw_rev(void) static void meesc_nand_hw_init(void) { unsigned long csa; + at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE; + at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE; /* Enable CS3 */ - csa = at91_sys_read(AT91_MATRIX_EBI0CSA); - at91_sys_write(AT91_MATRIX_EBI0CSA, - csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA); + csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A; + writel(csa, &matrix->csa[0]); /* Configure SMC CS3 for NAND/SmartMedia */ - at91_sys_write(AT91_SMC_SETUP(3), - AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC_PULSE(3), - AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) | - AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3)); - at91_sys_write(AT91_SMC_CYCLE(3), - AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5)); - at91_sys_write(AT91_SMC_MODE(3), - AT91_SMC_READMODE | AT91_SMC_WRITEMODE | - AT91_SMC_EXNWMODE_DISABLE | -#ifdef CONFIG_SYS_NAND_DBW_16 - AT91_SMC_DBW_16 | -#else /* CONFIG_SYS_NAND_DBW_8 */ - AT91_SMC_DBW_8 | -#endif - AT91_SMC_TDF_(2)); + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), + &smc->cs[3].setup); + + writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(2), + &smc->cs[3].mode); /* Configure RDY/BSY */ - at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); + at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1); /* Enable NandFlash */ - at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); + at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); } #endif /* CONFIG_CMD_NAND */ #ifdef CONFIG_MACB static void meesc_macb_hw_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* Enable clock */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC); + writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer); at91_macb_hw_init(); } #endif @@ -117,26 +117,27 @@ static void meesc_macb_hw_init(void) */ static void meesc_ethercat_hw_init(void) { + at91_smc_t *smc1 = (at91_smc_t *) AT91_SMC1_BASE; + /* Configure SMC EBI1_CS0 for EtherCAT */ - at91_sys_write(AT91_SMC1_SETUP(0), - AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | - AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); - at91_sys_write(AT91_SMC1_PULSE(0), - AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | - AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9)); - at91_sys_write(AT91_SMC1_CYCLE(0), - AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5)); + writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) | + AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0), + &smc1->cs[0].setup); + writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) | + AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9), + &smc1->cs[0].pulse); + writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6), + &smc1->cs[0].cycle); /* * Configure behavior at external wait signal, byte-select mode, 16 bit * data bus width, none data float wait states and TDF optimization */ - at91_sys_write(AT91_SMC1_MODE(0), - AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | - AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | - AT91_SMC_TDFMODE); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY | + AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) | + AT91_SMC_MODE_TDF, &smc1->cs[0].mode); /* Configure RDY/BSY */ - at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ + at91_set_b_periph(AT91_PIO_PORTE, 20, 0); /* EBI1_NWAIT */ } int dram_init(void) @@ -150,7 +151,7 @@ int board_eth_init(bd_t *bis) { int rc = 0; #ifdef CONFIG_MACB - rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00); + rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x00); #endif return rc; } @@ -175,7 +176,7 @@ int checkboard(void) gd->bd->bi_arch_number = MACH_TYPE_ETHERCAN2; puts("Board: EtherCAN/2 Gateway"); /* switch on LED1D */ - at91_set_gpio_output(AT91_PIN_PB12, 1); + at91_set_pio_output(AT91_PIO_PORTB, 12, 1); break; default: /* assume, no ET1100 present, arch number of EtherCAN/2-Board */ @@ -222,8 +223,9 @@ u32 get_board_rev(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { - char *str; - char buf[32]; + char *str; + char buf[32]; + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; /* * Normally the processor clock has a divisor of 2. @@ -231,10 +233,9 @@ int misc_init_r(void) * Check the user has set environment mdiv to 4 to change the divisor. */ if ((str = getenv("mdiv")) && (strcmp(str, "4") == 0)) { - at91_sys_write(AT91_PMC_MCKR, - (at91_sys_read(AT91_PMC_MCKR) & ~AT91_PMC_MDIV) | - AT91SAM9_PMC_MDIV_4); - at91_clock_init(0); + writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | + AT91SAM9_PMC_MDIV_4, &pmc->mckr); + at91_clock_init(CONFIG_SYS_AT91_MAIN_CLOCK); serial_setbrg(); /* Notify the user that the clock is not default */ printf("Setting master clock to %s MHz\n", @@ -247,10 +248,13 @@ int misc_init_r(void) int board_init(void) { + at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE; + /* Peripheral Clock Enable Register */ - at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA | - 1 << AT91SAM9263_ID_PIOB | - 1 << AT91SAM9263_ID_PIOCDE); + writel( 1 << AT91SAM9263_ID_PIOA | + 1 << AT91SAM9263_ID_PIOB | + 1 << AT91SAM9263_ID_PIOCDE, + &pmc->pcer); /* initialize ET1100 Controller */ meesc_ethercat_hw_init(); diff --git a/include/configs/meesc.h b/include/configs/meesc.h index d3cc582..89f99fa 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -31,14 +31,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_AT91_LEGACY - /* Common stuff */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_MEESC 1 /* Board is esd MEESC */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ @@ -58,6 +56,7 @@ /* * Hardware drivers */ +#define CONFIG_AT91_GPIO 1 /* Console output */ #define CONFIG_AT91_GPIO 1 @@ -122,8 +121,8 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTA, 22 #endif -- 1.5.3

2 1

[U-Boot] [PATCH 1/3] at91: Defined main clock frequency on esd at91 boards
by Daniel Gorsulowski 15 Jul '10

15 Jul '10

Autodetection is undesired now Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski(a)esd.eu> --- include/configs/meesc.h | 9 +++++---- include/configs/otc570.h | 1 + 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/include/configs/meesc.h b/include/configs/meesc.h index e085f4a..d3cc582 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -1,12 +1,12 @@ /* + * (C) Copyright 2010 + * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> + * esd electronic system design gmbh <www.esd.eu> + * * (C) Copyright 2007-2008 * Stelian Pop <stelian.pop(a)leadtechdesign.com> * Lead Tech Design <www.leadtechdesign.com> * - * (C) Copyright 2009 - * Daniel Gorsulowski <daniel.gorsulowski(a)esd.eu> - * esd electronic system design gmbh <www.esd.eu> - * * Configuation settings for the esd MEESC board. * * See file CREDITS for list of people who contributed to this @@ -38,6 +38,7 @@ #define CONFIG_MEESC 1 /* Board is esd MEESC */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ #define CONFIG_PREBOOT /* enable preboot variable */ diff --git a/include/configs/otc570.h b/include/configs/otc570.h index fb0f576..4a1cede 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -35,6 +35,7 @@ #define CONFIG_OTC570 1 /* Board is esd OTC570 */ #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ #define CONFIG_AT91SAM9263 1 /* It's an AT91SAM9263 SoC */ +#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */ #define CONFIG_SYS_HZ 1000 /* decrementer freq */ #define CONFIG_DISPLAY_BOARDINFO 1 #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info and speed */ -- 1.5.3

2 1

[U-Boot] [PATCH 2/2] 8xx, kup4: add FDT support
by Heiko Schocher 15 Jul '10

15 Jul '10

Signed-off-by: Heiko Schocher <hs(a)denx.de> --- board/kup/kup4k/kup4k.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++ include/configs/KUP4K.h | 4 +++ 2 files changed, 63 insertions(+), 0 deletions(-) diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 9feee68..a35e3e6 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -24,6 +24,7 @@ #include <common.h> #include <command.h> +#include <libfdt.h> #include <mpc8xx.h> #include <hwconfig.h> #include <i2c.h> @@ -295,4 +296,62 @@ static unsigned char swapbyte(unsigned char c) return result; } +/* + * Device Tree Support + */ +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +int fdt_set_node_and_value (void *blob, + char *nodename, + char *regname, + void *var, + int size) +{ + int ret = 0; + int nodeoffset = 0; + + nodeoffset = fdt_path_offset (blob, nodename); + if (nodeoffset >= 0) { + ret = fdt_setprop (blob, nodeoffset, regname, var, + size); + if (ret < 0) { + printf("ft_blob_update(): " + "cannot set %s/%s property; err: %s\n", + nodename, regname, fdt_strerror (ret)); + } + } else { + printf("ft_blob_update(): " + "cannot find %s node err:%s\n", + nodename, fdt_strerror (nodeoffset)); + } + return ret; +} +/* + * update "brg" property in the blob + */ +void ft_blob_update (void *blob, bd_t *bd) +{ + uchar enetaddr[6]; + ulong brg_data = 0; + + /* BRG */ + brg_data = cpu_to_be32(bd->bi_busfreq); + fdt_set_node_and_value(blob, + "/soc/cpm", "brg-frequency", + &brg_data, sizeof(brg_data)); + + /* MAC addr */ + if (eth_getenv_enetaddr("ethaddr", enetaddr)) { + fdt_set_node_and_value(blob, + "ethernet0", "local-mac-address", + enetaddr, sizeof(u8) * 6); + } + +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + ft_blob_update(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index 1b4c1a9..4b38210 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -520,5 +520,9 @@ #define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ #define CONFIG_VERSION_VARIABLE 1 +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ -- 1.6.2.5 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

2 1

[U-Boot] [PATCH 1/2] 8xx, kup4: minor configuration changes
by Heiko Schocher 15 Jul '10

15 Jul '10

- nfs-options removed - hda->sda changed - mtd parts added - loadaddress changed - cmd-line length increased - lcd stuff removed - code cleanup Signed-off-by: Klaus Heydeck <heydeck(a)kieback-peter.de> --- board/kup/common/kup.c | 52 ++++--- board/kup/common/kup.h | 45 +++-- board/kup/kup4k/kup4k.c | 408 ++++++++++++++++---------------------------- board/kup/kup4k/s1d13706.h | 174 ------------------- board/kup/kup4x/kup4x.c | 212 ++++++------------------ include/configs/KUP4K.h | 161 ++++++++++------- include/configs/KUP4X.h | 62 ++++---- 7 files changed, 386 insertions(+), 728 deletions(-) delete mode 100644 board/kup/kup4k/s1d13706.h diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c index 2418d59..96a2c2c 100644 --- a/board/kup/common/kup.c +++ b/board/kup/common/kup.c @@ -24,49 +24,61 @@ #include <common.h> #include <mpc8xx.h> #include "kup.h" +#include <asm/io.h> -int misc_init_f (void) + +int misc_init_f(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile sysconf8xx_t *siu = &immap->im_siu_conf; - while (siu->sc_sipend & 0x20000000) { - /* printf("waiting for 5V VCC\n"); */ - ; + while (in_be32 (&siu->sc_sipend) & 0x20000000) { + debug("waiting for 5V VCC\n"); } /* RS232 / RS485 default is RS232 */ - immap->im_ioport.iop_padat &= ~(PA_RS485); - immap->im_ioport.iop_papar &= ~(PA_RS485); - immap->im_ioport.iop_paodr &= ~(PA_RS485); - immap->im_ioport.iop_padir |= (PA_RS485); + clrbits_be16 (&immap->im_ioport.iop_padat, PA_RS485); + clrbits_be16 (&immap->im_ioport.iop_papar, PA_RS485); + clrbits_be16 (&immap->im_ioport.iop_paodr, PA_RS485); + setbits_be16 (&immap->im_ioport.iop_padir, PA_RS485); + + /* IO Reset min 1 msec */ + setbits_be16 (&immap->im_ioport.iop_padat, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + clrbits_be16 (&immap->im_ioport.iop_papar, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + clrbits_be16 (&immap->im_ioport.iop_paodr, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + setbits_be16 (&immap->im_ioport.iop_padir, + (PA_RESET_IO_01 | PA_RESET_IO_02)); + udelay(1000); + clrbits_be16 (&immap->im_ioport.iop_padat, + (PA_RESET_IO_01 | PA_RESET_IO_02)); return (0); } - #ifdef CONFIG_IDE_LED -void ide_led (uchar led, uchar status) +void ide_led(uchar led, uchar status) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; /* We have one led for both pcmcia slots */ - if (status) { /* led on */ - immap->im_ioport.iop_padat &= ~(PA_LED_YELLOW); - } else { - immap->im_ioport.iop_padat |= (PA_LED_YELLOW); - } + if (status) + clrbits_be16 (&immap->im_ioport.iop_padat, PA_LED_YELLOW); + else + setbits_be16 (&immap->im_ioport.iop_padat, PA_LED_YELLOW); } #endif -void poweron_key (void) +void poweron_key(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1); - immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1); - - if (immap->im_ioport.iop_pcdat & (PC_SWITCH1)) + clrbits_be16 (&immap->im_ioport.iop_pcpar, PC_SWITCH1); + clrbits_be16 (&immap->im_ioport.iop_pcdir, PC_SWITCH1); + if (in_be16 (&immap->im_ioport.iop_pcdat) & (PC_SWITCH1)) setenv ("key1", "off"); else setenv ("key1", "on"); } + diff --git a/board/kup/common/kup.h b/board/kup/common/kup.h index b736283..55c0e82 100644 --- a/board/kup/common/kup.h +++ b/board/kup/common/kup.h @@ -24,23 +24,34 @@ #ifndef __KUP_H #define __KUP_H -#define PA_8 0x0080 -#define PA_11 0x0010 -#define PA_12 0x0008 - -#define PB_14 0x00020000 -#define PB_17 0x00004000 - -#define PC_9 0x0040 - -#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ -#define PA_LED_YELLOW PA_8 -#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off*/ -#define PB_LCD_PWM PB_17 /* PB 17 */ -#define PC_SWITCH1 PC_9 /* Reboot switch */ - -extern void poweron_key (void); - +#define PA_8 0x0080 +#define PA_9 0x0040 +#define PA_10 0x0020 +#define PA_11 0x0010 +#define PA_12 0x0008 + +#define PB_14 0x00020000 +#define PB_15 0x00010000 +#define PB_16 0x00008000 +#define PB_17 0x00004000 + +#define PC_4 0x0800 +#define PC_5 0x0400 +#define PC_9 0x0040 + +#define PA_RS485 PA_11 /* SCC1: 0=RS232 1=RS485 */ +#define PA_LED_YELLOW PA_8 +#define PA_RESET_IO_01 PA_9 /* Reset left IO */ +#define PA_RESET_IO_02 PA_10 /* Reset right IO */ +#define PB_PROG_IO_01 PB_15 /* Program left IO */ +#define PB_PROG_IO_02 PB_16 /* Program right IO */ +#define BP_USB_VCC PB_14 /* VCC for USB devices 0=vcc on, 1=vcc off */ +#define PB_LCD_PWM PB_17 /* PB 17 */ +#define PC_SWITCH1 PC_9 /* Reboot switch */ + + +extern void poweron_key(void); extern void load_sernum_ethaddr(void); #endif /* __KUP_H */ + diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c index 98f5f5a..9feee68 100644 --- a/board/kup/kup4k/kup4k.c +++ b/board/kup/kup4k/kup4k.c @@ -23,35 +23,19 @@ */ #include <common.h> +#include <command.h> #include <mpc8xx.h> +#include <hwconfig.h> +#include <i2c.h> #include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO - #include "s1d13706.h" -#endif - -DECLARE_GLOBAL_DATA_PTR; - -#undef DEBUG -#ifdef DEBUG -# define debugk(fmt,args...) printf(fmt ,##args) -#else -# define debugk(fmt,args...) -#endif - -typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; - - -/* ------------------------------------------------------------------------- */ +#include <asm/io.h> -#ifdef CONFIG_KUP4K_LOGO -void lcd_logo(bd_t *bd); -#endif +static unsigned char swapbyte(unsigned char c); +static int read_diag(void); +DECLARE_GLOBAL_DATA_PTR; -/* ------------------------------------------------------------------------- */ +/* ----------------------------------------------------------------------- */ #define _NOT_USED_ 0xFFFFFFFF @@ -60,7 +44,7 @@ const uint sdram_table[] = { * Single Read. (Offset 0 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00, - 0x1FF77C47, /* last */ + 0x1FF77C47, /* last */ /* * SDRAM Initialization (offset 5 in UPMA RAM) @@ -70,28 +54,28 @@ const uint sdram_table[] = { * sequence, which is executed by a RUN command. * */ - 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ + 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */ /* * Burst Read. (Offset 8 in UPMA RAM) */ 0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00, - 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ + 0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Single Write. (Offset 18 in UPMA RAM) */ - 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ + 0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */ _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Burst Write. (Offset 20 in UPMA RAM) */ 0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00, - 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ - _NOT_USED_, + 0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, @@ -99,156 +83,169 @@ const uint sdram_table[] = { * Refresh (Offset 30 in UPMA RAM) */ 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, - 0xFFFFFC84, 0xFFFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, + 0xFFFFFC84, 0xFFFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, /* * Exception. (Offset 3c in UPMA RAM) */ - 0x7FFFFC07, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, + 0x7FFFFC07, /* last */ + _NOT_USED_, _NOT_USED_, _NOT_USED_, }; -/* ------------------------------------------------------------------------- */ - +/* ----------------------------------------------------------------------- */ /* * Check Board Identity: */ -int checkboard (void) +int checkboard(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - uchar *latch,rev,mod; + uchar rev,mod,tmp,pcf,ak_rev,ak_mod; /* * Init ChipSelect #4 (CAN + HW-Latch) */ - immap->im_memctl.memc_or4 = 0xFFFF8926; - immap->im_memctl.memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch=(uchar *)0x90000200; - rev = (*latch & 0xF8) >> 3; - mod=(*latch & 0x03); - printf ("Board: KUP4K Rev %d.%d\n",rev,mod); + out_be32 (&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); + out_be32 (&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); + + /* + * Init ChipSelect #5 (S1D13768) + */ + out_be32 (&immap->im_memctl.memc_or5, CONFIG_SYS_OR5); + out_be32 (&immap->im_memctl.memc_br5, CONFIG_SYS_BR5); + + tmp = swapbyte (in_8 ( (unsigned char*) LATCH_ADDR)); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); + + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + if (read_diag()) + gd->flags &= ~GD_FLG_SILENT; + printf ("Board: KUP4K Rev %d.%d AK:",rev,mod); + /* + * TI Application report: Before using the IO as an input, + * a high must be written to the IO first + */ + pcf = 0xFF; + i2c_write (0x21, 0, 0 , &pcf, 1); + if (i2c_read (0x21, 0, 0, &pcf, 1)) { + puts ("n/a\n"); + } + else { + ak_rev = (pcf & 0xF8) >> 3; + ak_mod = (pcf & 0x07); + printf ("%d.%d\n",ak_rev,ak_mod); + } return (0); } -/* ------------------------------------------------------------------------- */ +/* ----------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) + +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); + long int size = 0; + uchar *latch,rev,mod,tmp; /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. + * Init ChipSelect #4 (CAN + HW-Latch) to determine Hardware Revision + * Rev 1..6 -> 48 MB RAM; Rev >= 7 -> 96 MB */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000088; + out_be32 (&immap->im_memctl.memc_or4, CONFIG_SYS_OR4); + out_be32 (&immap->im_memctl.memc_br4, CONFIG_SYS_BR4); - /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ -/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ -/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ + latch = (uchar *)0x90000200; + tmp = swapbyte (*latch); + rev = (tmp & 0xF8) >> 3; + mod = (tmp & 0x07); -/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ -/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ + upmconfig (UPMA, (uint *) sdram_table, + sizeof (sdram_table) / sizeof (uint)); + out_be16 (&memctl->memc_mptpr, CONFIG_SYS_MPTPR); - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + out_be32 (&memctl->memc_mar, 0x00000088); + /* no refresh yet */ + if(rev >= 7) + out_be32 (&memctl->memc_mamr, + CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE))); + else + out_be32 (&memctl->memc_mamr, + CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE))); udelay (200); /* perform SDRAM initializsation sequence */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + /* SDRAM bank 0 */ + out_be32 (&memctl->memc_mcr, 0x80002105); udelay (1); - memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ + out_be32 (&memctl->memc_mcr, 0x80002830); /* execute twice */ udelay (1); - memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ + out_be32 (&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ udelay (1); - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ + /* SDRAM bank 1 */ + out_be32 (&memctl->memc_mcr, 0x80004105); udelay (1); - memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ + out_be32 (&memctl->memc_mcr, 0x80004830); /* execute twice */ udelay (1); - memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ + out_be32 (&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ udelay (1); - memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ + /* SDRAM bank 2 */ + out_be32 (&memctl->memc_mcr, 0x80006105); udelay (1); - memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ + out_be32 (&memctl->memc_mcr, 0x80006830); /* execute twice */ udelay (1); - memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + out_be32 (&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ udelay (1); - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ + setbits_be32 (&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ udelay (1000); -#if 0 /* 3 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; -#else /* 3 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; + out_be16 (&memctl->memc_mptpr, CONFIG_SYS_MPTPR); udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFC000A00; - memctl->memc_br3 = 0x02000081; -#endif - - udelay (10000); - - return (size_b0 + size_b1 + size_b2); + if(rev >= 7){ + size = 32 * 3 * 1024 * 1024; + out_be32 (&memctl->memc_or1, CONFIG_SYS_OR1_9COL); + out_be32 (&memctl->memc_br1, CONFIG_SYS_BR1_9COL); + out_be32 (&memctl->memc_or2, CONFIG_SYS_OR2_9COL); + out_be32 (&memctl->memc_br2, CONFIG_SYS_BR2_9COL); + out_be32 (&memctl->memc_or3, CONFIG_SYS_OR3_9COL); + out_be32 (&memctl->memc_br3, CONFIG_SYS_BR3_9COL); + } + else{ + size = 16 * 3 * 1024 * 1024; + out_be32 (&memctl->memc_or1, CONFIG_SYS_OR1_8COL); + out_be32 (&memctl->memc_br1, CONFIG_SYS_BR1_8COL); + out_be32 (&memctl->memc_or2, CONFIG_SYS_OR2_8COL); + out_be32 (&memctl->memc_br2, CONFIG_SYS_BR2_8COL); + out_be32 (&memctl->memc_or3, CONFIG_SYS_OR3_8COL); + out_be32 (&memctl->memc_br3, CONFIG_SYS_BR3_8COL); + } + return (size); } -/* ------------------------------------------------------------------------- */ +/* ----------------------------------------------------------------------- */ + -int misc_init_r (void) +int misc_init_r(void) { -#ifdef CONFIG_STATUS_LED volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; -#endif -#ifdef CONFIG_KUP4K_LOGO - bd_t *bd = gd->bd; - lcd_logo (bd); -#endif /* CONFIG_KUP4K_LOGO */ #ifdef CONFIG_IDE_LED /* Configure PA8 as output port */ - immap->im_ioport.iop_padir |= 0x80; - immap->im_ioport.iop_paodr |= 0x80; - immap->im_ioport.iop_papar &= ~0x80; - immap->im_ioport.iop_padat |= 0x80; /* turn it off */ + setbits_be16 (&immap->im_ioport.iop_padir, 0x80); + setbits_be16 (&immap->im_ioport.iop_paodr, 0x80); + clrbits_be16 (&immap->im_ioport.iop_papar, 0x80); + setbits_be16 (&immap->im_ioport.iop_padat, 0x80); /* turn it off */ #endif load_sernum_ethaddr(); setenv("hw","4k"); @@ -256,149 +253,46 @@ int misc_init_r (void) return (0); } -#ifdef CONFIG_KUP4K_LOGO - -void lcd_logo (bd_t * bd) +static int read_diag(void) { - FB_INFO_S1D13xxx fb_info; - S1D_INDEX s1dReg; - S1D_VALUE s1dValue; - volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl; - ushort i; - uchar *fb; - int rs, gs, bs; - int r = 8, g = 8, b = 4; - int r1, g1, b1; - int n; - char tmp[64]; /* long enough for environment variables */ - int tft = 0; - - immr->im_cpm.cp_pbpar &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbodr &= ~(PB_LCD_PWM); - immr->im_cpm.cp_pbdat &= ~(PB_LCD_PWM); /* set to 0 = enabled */ - immr->im_cpm.cp_pbdir |= (PB_LCD_PWM); - -/*----------------------------------------------------------------------------- */ -/* Initialize the chip and the frame buffer driver. */ -/*----------------------------------------------------------------------------- */ - memctl = &immr->im_memctl; - - - /* - * Init ChipSelect #5 (S1D13768) - */ - memctl->memc_or5 = 0xFFC007F0; /* 4 MB 17 WS or externel TA */ - memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */ - __asm__ ("eieio"); - - fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR); - fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR); - - if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28) - || (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) { - printf ("Warning:LCD Controller S1D13706 not found\n"); - setenv ("lcd", "none"); - return; - } - - - for (i = 0; i < sizeof(aS1DRegs_prelimn) / sizeof(aS1DRegs_prelimn[0]); i++) { - s1dReg = aS1DRegs_prelimn[i].Index; - s1dValue = aS1DRegs_prelimn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_prelimn[i].Index, aS1DRegs_prelimn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; + int diag; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + + clrbits_be16 (&immr->im_ioport.iop_pcdir, PC_4); /* input */ + clrbits_be16 (&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ + setbits_be16 (&immr->im_ioport.iop_pcdir, PC_5); /* output */ + clrbits_be16 (&immr->im_ioport.iop_pcpar, PC_4); /* gpio */ + setbits_be16 (&immr->im_ioport.iop_pcdat, PC_5); /* 1 */ + udelay(500); + if (in_be16 (&immr->im_ioport.iop_pcdat) & PC_4){ + clrbits_be16 (&immr->im_ioport.iop_pcdat, PC_5);/* 0 */ + udelay(500); + if(in_be16 (&immr->im_ioport.iop_pcdat) & PC_4){ + diag=0; + } + else{ + diag=1; + } } - - - n = getenv_r ("lcd", tmp, sizeof (tmp)); - if (n > 0) { - if (!strcmp ("tft", tmp)) - tft = 1; - else - tft = 0; + else{ + diag=0; } -#if 0 - if (((S1D_VALUE *) fb_info.RegAddr)[0xAC] & 0x04) - tft = 0; - else - tft = 1; -#endif + clrbits_be16 (&immr->im_ioport.iop_pcdir, PC_5); /* input */ + return (diag); +} - debugk ("Port=0x%02x -> TFT=%d\n", tft, - ((S1D_VALUE *) fb_info.RegAddr)[0xAC]); - - /* init controller */ - if (!tft) { - for (i = 0; i < sizeof(aS1DRegs_stn) / sizeof(aS1DRegs_stn[0]); i++) { - s1dReg = aS1DRegs_stn[i].Index; - s1dValue = aS1DRegs_stn[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_stn[i].Index, - aS1DRegs_stn[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof(S1D_VALUE)] = - s1dValue; - } - n = getenv_r ("contrast", tmp, sizeof (tmp)); - ((S1D_VALUE *) fb_info.RegAddr)[0xB3] = - (n > 0) ? (uchar) simple_strtoul (tmp, NULL, 10) * 255 / 100 : 0xA0; - switch (bd->bi_busfreq) { - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41; - break; - case 48000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34; - break; - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 64000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66; - break; - } - /* setenv("lcd","stn"); */ - } else { - for (i = 0; i < sizeof(aS1DRegs_tft) / sizeof(aS1DRegs_tft[0]); i++) { - s1dReg = aS1DRegs_tft[i].Index; - s1dValue = aS1DRegs_tft[i].Value; - debugk ("s13768 reg: %02x value: %02x\n", - aS1DRegs_tft[i].Index, - aS1DRegs_tft[i].Value); - ((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] = - s1dValue; - } +static unsigned char swapbyte(unsigned char c) +{ + unsigned char result=0; + int i=0; - switch (bd->bi_busfreq) { - default: - printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n", bd->bi_busfreq); - case 40000000: - ((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x42; - ((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x30; - break; - } - /* setenv("lcd","tft"); */ + for(i=0;i<8;++i){ + result=result<<1; + result|=(c&1); + c=c>>1; } + return result; +} - /* create and set colormap */ - rs = 256 / (r - 1); - gs = 256 / (g - 1); - bs = 256 / (b - 1); - for (i = 0; i < 256; i++) { - r1 = (rs * ((i / (g * b)) % r)) * 255; - g1 = (gs * ((i / b) % g)) * 255; - b1 = (bs * ((i) % b)) * 255; - debugk ("%d %04x %04x %04x\n", i, r1 >> 4, g1 >> 4, b1 >> 4); - S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4), - (b1 >> 4)); - } - /* copy bitmap */ - fb = (uchar *) (fb_info.VmemAddr); - memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240); -} -#endif /* CONFIG_KUP4K_LOGO */ diff --git a/board/kup/kup4k/s1d13706.h b/board/kup/kup4k/s1d13706.h deleted file mode 100644 index cd5eccc..0000000 --- a/board/kup/kup4k/s1d13706.h +++ /dev/null @@ -1,174 +0,0 @@ -/*---------------------------------------------------------------------------- */ -/* */ -/* File generated by S1D13706CFG.EXE */ -/* */ -/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */ -/* All rights reserved. */ -/* */ -/*---------------------------------------------------------------------------- */ - -/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */ - -#define S1D_DISPLAY_WIDTH 320 -#define S1D_DISPLAY_HEIGHT 240 -#define S1D_DISPLAY_BPP 8 -#define S1D_DISPLAY_SCANLINE_BYTES 320 -#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L -#define S1D_PHYSICAL_VMEM_SIZE 0x14000L -#define S1D_PHYSICAL_REG_ADDR 0x80080000L -#define S1D_PHYSICAL_REG_SIZE 0x100 -#define S1D_DISPLAY_PCLK 6250 -#define S1D_PALETTE_SIZE 256 -#define S1D_REGDELAYOFF 0xFFFE -#define S1D_REGDELAYON 0xFFFF - -#define S1D_WRITE_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \ - ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \ - ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \ - ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ -} - -#define S1D_READ_PALETTE(p,i,r,g,b) \ -{ \ - ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \ - r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \ - g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \ - b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \ -} - -typedef unsigned short S1D_INDEX; -typedef unsigned char S1D_VALUE; - - -typedef struct -{ - S1D_INDEX Index; - S1D_VALUE Value; -} S1D_REGS; - - -static S1D_REGS aS1DRegs_prelimn[] = -{ - {0x10,0x00}, /* PANEL Type Register */ - {0xA8,0x00}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - -}; - -static S1D_REGS aS1DRegs_stn[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x10,0xD0}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xF0}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x87}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x80}, /* Vertical Sync Pulse Width Register */ - {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x83}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; - -static S1D_REGS aS1DRegs_tft[] = -{ - {0x04,0x10}, /* BUSCLK MEMCLK Config Register */ - {0x05,0x42}, /* PCLK Config Register */ - {0x10,0x61}, /* PANEL Type Register */ - {0x11,0x00}, /* MOD Rate Register */ - {0x12,0x30}, /* Horizontal Total Register */ - {0x14,0x27}, /* Horizontal Display Period Register */ - {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */ - {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */ - {0x18,0xFA}, /* Vertical Total Register 0 */ - {0x19,0x00}, /* Vertical Total Register 1 */ - {0x1C,0xEF}, /* Vertical Display Period Register 0 */ - {0x1D,0x00}, /* Vertical Display Period Register 1 */ - {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */ - {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */ - {0x20,0x07}, /* Horizontal Sync Pulse Width Register */ - {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */ - {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */ - {0x24,0x00}, /* Vertical Sync Pulse Width Register */ - {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */ - {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */ - {0x70,0x03}, /* Display Mode Register */ - {0x71,0x00}, /* Special Effects Register */ - {0x74,0x00}, /* Main Window Display Start Address Register 0 */ - {0x75,0x00}, /* Main Window Display Start Address Register 1 */ - {0x76,0x00}, /* Main Window Display Start Address Register 2 */ - {0x78,0x50}, /* Main Window Address Offset Register 0 */ - {0x79,0x00}, /* Main Window Address Offset Register 1 */ - {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */ - {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */ - {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */ - {0x80,0x50}, /* Sub Window Address Offset Register 0 */ - {0x81,0x00}, /* Sub Window Address Offset Register 1 */ - {0x84,0x00}, /* Sub Window X Start Pos Register 0 */ - {0x85,0x00}, /* Sub Window X Start Pos Register 1 */ - {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */ - {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */ - {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */ - {0x8D,0x00}, /* Sub Window X End Pos Register 1 */ - {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */ - {0x91,0x00}, /* Sub Window Y End Pos Register 1 */ - {0xA0,0x00}, /* Power Save Config Register */ - {0xA1,0x00}, /* CPU Access Control Register */ - {0xA2,0x00}, /* Software Reset Register */ - {0xA3,0x00}, /* BIG Endian Support Register */ - {0xA4,0x00}, /* Scratch Pad Register 0 */ - {0xA5,0x00}, /* Scratch Pad Register 1 */ - {0xA8,0x01}, /* GPIO Config Register 0 */ - {0xA9,0x80}, /* GPIO Config Register 1 */ - {0xAC,0x01}, /* GPIO Status Control Register 0 */ - {0xAD,0x00}, /* GPIO Status Control Register 1 */ - {0xB0,0x10}, /* PWM CV Clock Control Register */ - {0xB1,0x80}, /* PWM CV Clock Config Register */ - {0xB2,0x00}, /* CV Clock Burst Length Register */ - {0xAD,0x80}, /* reset seq */ - {0x70,0x03}, -}; diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c index 65a222b..e82e011 100644 --- a/board/kup/kup4x/kup4x.c +++ b/board/kup/kup4x/kup4x.c @@ -26,28 +26,8 @@ #include <mpc8xx.h> #include <post.h> #include "../common/kup.h" -#ifdef CONFIG_KUP4K_LOGO -/* #include "s1d13706.h" */ -#endif - -#define KUP4X_USB - - -typedef struct { - volatile unsigned char *VmemAddr; - volatile unsigned char *RegAddr; -} FB_INFO_S1D13xxx; +#include <asm/io.h> -/* ------------------------------------------------------------------------- */ - -int usb_init_kup4x (void); - - -#ifdef CONFIG_KUP4K_LOGO -void lcd_logo (bd_t * bd); -#endif - -/* ------------------------------------------------------------------------- */ #define _NOT_USED_ 0xFFFFFFFF @@ -106,207 +86,115 @@ const uint sdram_table[] = { _NOT_USED_, _NOT_USED_, _NOT_USED_, }; -/* ------------------------------------------------------------------------- */ /* * Check Board Identity: */ -int checkboard (void) +int checkboard(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile uchar *latch; - uchar rev, mod; + uchar latch, rev, mod; /* * Init ChipSelect #4 (CAN + HW-Latch) */ - memctl->memc_or4 = 0xFFFF8926; - memctl->memc_br4 = 0x90000401; - __asm__ ("eieio"); - latch = (volatile uchar *) 0x90000200; - rev = (*latch & 0xF8) >> 3; - mod = (*latch & 0x03); + out_be32 (&memctl->memc_or4, 0xFFFF8926); + out_be32 (&memctl->memc_br4, 0x90000401); + + latch = in_8 ( (unsigned char *) LATCH_ADDR); + rev = (latch & 0xF8) >> 3; + mod = (latch & 0x03); printf ("Board: KUP4X Rev %d.%d\n",rev,mod); return (0); } -/* ------------------------------------------------------------------------- */ -phys_size_t initdram (int board_type) +phys_size_t initdram(int board_type) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size_b0 = 0; - long int size_b1 = 0; - long int size_b2 = 0; - long int size_b3 = 0; upmconfig (UPMA, (uint *) sdram_table, sizeof (sdram_table) / sizeof (uint)); - /* - * Preliminary prescaler for refresh (depends on number of - * banks): This value is selected for four cycles every 62.4 us - * with two SDRAM banks or four cycles every 31.2 us with one - * bank. It will be adjusted after memory sizing. - */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - memctl->memc_mar = 0x00000088; - - /* - * Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at - * preliminary addresses - these have to be modified after the - * SDRAM size has been determined. - */ -/* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; */ -/* memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */ + out_be16 (&memctl->memc_mptpr, CONFIG_SYS_MPTPR); -/* memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM; */ -/* memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM; */ + out_be32 (&memctl->memc_mar, 0x00000088); - memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE)); /* no refresh yet */ + out_be32 (&memctl->memc_mamr, + CONFIG_SYS_MAMR & (~(MAMR_PTAE))); /* no refresh yet */ udelay (200); /* perform SDRAM initializsation sequence */ - memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */ + /* SDRAM bank 0 */ + out_be32 (&memctl->memc_mcr, 0x80002105); udelay (1); - memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */ + out_be32 (&memctl->memc_mcr, 0x80002830); /* execute twice */ udelay (1); - memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */ + out_be32 (&memctl->memc_mcr, 0x80002106); /* RUN MRS Pattern from loc 6 */ udelay (1); - memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */ + /* SDRAM bank 1 */ + out_be32 (&memctl->memc_mcr, 0x80004105); udelay (1); - memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */ + out_be32 (&memctl->memc_mcr, 0x80004830); /* execute twice */ udelay (1); - memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */ + out_be32 (&memctl->memc_mcr, 0x80004106); /* RUN MRS Pattern from loc 6 */ udelay (1); - memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */ + /* SDRAM bank 2 */ + out_be32 (&memctl->memc_mcr, 0x80006105); udelay (1); - memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */ + out_be32 (&memctl->memc_mcr, 0x80006830); /* execute twice */ udelay (1); - memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + out_be32 (&memctl->memc_mcr, 0x80006106); /* RUN MRS Pattern from loc 6 */ udelay (1); - memctl->memc_mcr = 0x8000C105; /* SDRAM bank 2 */ + /* SDRAM bank 3 */ + out_be32 (&memctl->memc_mcr, 0x8000C105); udelay (1); - memctl->memc_mcr = 0x8000C830; /* SDRAM bank 2 - execute twice */ + out_be32 (&memctl->memc_mcr, 0x8000C830); /* execute twice */ udelay (1); - memctl->memc_mcr = 0x8000C106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */ + out_be32 (&memctl->memc_mcr, 0x8000C106); /* RUN MRS Pattern from loc 6 */ udelay (1); - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - udelay (1000); -#if 0 /* 4 x 8MB */ - size_b0 = 0x00800000; - size_b1 = 0x00800000; - size_b2 = 0x00800000; - size_b3 = 0x00800000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; + setbits_be32 (&memctl->memc_mamr, MAMR_PTAE); /* enable refresh */ + udelay (1000); - memctl->memc_or1 = 0xFF800A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFF000A00; - memctl->memc_br2 = 0x00800081; - memctl->memc_or3 = 0xFE000A00; - memctl->memc_br3 = 0x01000081; - memctl->memc_or6 = 0xFE000A00; - memctl->memc_br6 = 0x01800081; -#else /* 4 x 16 MB */ - size_b0 = 0x01000000; - size_b1 = 0x01000000; - size_b2 = 0x01000000; - size_b3 = 0x01000000; - memctl->memc_mptpr = CONFIG_SYS_MPTPR; + /* 4 x 16 MB */ + out_be16 (&memctl->memc_mptpr, CONFIG_SYS_MPTPR); udelay (1000); - memctl->memc_or1 = 0xFF000A00; - memctl->memc_br1 = 0x00000081; - memctl->memc_or2 = 0xFE000A00; - memctl->memc_br2 = 0x01000081; - memctl->memc_or3 = 0xFD000A00; - memctl->memc_br3 = 0x02000081; - memctl->memc_or6 = 0xFC000A00; - memctl->memc_br6 = 0x03000081; -#endif + out_be32 (&memctl->memc_or1, 0xFF000A00); + out_be32 (&memctl->memc_br1, 0x00000081); + out_be32 (&memctl->memc_or2, 0xFE000A00); + out_be32 (&memctl->memc_br2, 0x01000081); + out_be32 (&memctl->memc_or3, 0xFD000A00); + out_be32 (&memctl->memc_br3, 0x02000081); + out_be32 (&memctl->memc_or6, 0xFC000A00); + out_be32 (&memctl->memc_br6, 0x03000081); udelay (10000); - - return (size_b0 + size_b1 + size_b2 + size_b3); + return (4 * 16 * 1024 * 1024); } -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ -#if 0 -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) +int misc_init_r(void) { volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - volatile long int *addr; - ulong cnt, val; - ulong save[32]; /* to make test non-destructive */ - unsigned char i = 0; - - memctl->memc_mamr = mamr_value; - - for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) { - addr = base + cnt; /* pointer arith! */ - - save[i++] = *addr; - *addr = ~cnt; - } - - /* write 0 to base address */ - addr = base; - save[i] = *addr; - *addr = 0; - - /* check at base address */ - if ((val = *addr) != 0) { - *addr = save[i]; - return (0); - } - - for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) { - addr = base + cnt; /* pointer arith! */ - - val = *addr; - *addr = save[--i]; - - if (val != (~cnt)) { - return (cnt * sizeof (long)); - } - } - return (maxsize); -} -#endif -int misc_init_r (void) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; #ifdef CONFIG_IDE_LED /* Configure PA8 as output port */ - immap->im_ioport.iop_padir |= 0x80; - immap->im_ioport.iop_paodr |= 0x80; - immap->im_ioport.iop_papar &= ~0x80; - immap->im_ioport.iop_padat |= 0x80; /* turn it off */ -#endif -#ifdef KUP4X_USB - usb_init_kup4x (); + setbits_be16 (&immap->im_ioport.iop_padir, 0x80); + setbits_be16 (&immap->im_ioport.iop_paodr, 0x80); + clrbits_be16 (&immap->im_ioport.iop_papar, 0x80); + setbits_be16 (&immap->im_ioport.iop_padat, 0x80); /* turn it off */ #endif load_sernum_ethaddr(); setenv ("hw", "4x"); poweron_key (); return (0); } + + diff --git a/include/configs/KUP4K.h b/include/configs/KUP4K.h index a829984..1b4c1a9 100644 --- a/include/configs/KUP4K.h +++ b/include/configs/KUP4K.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck(a)kieback-peter.de * @@ -42,11 +42,7 @@ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE #define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else #define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif #define CONFIG_BOARD_TYPES 1 /* support board types */ @@ -55,33 +51,39 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ -"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 0:1; bootm 200000\0" \ -"slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;" \ - "run addhw; diskboot 200000 2:1; bootm 200000\0" \ -"nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0" \ +"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \ + "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \ +"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \ + "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \ +"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \ +"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \ + bootm 400000 \0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ -"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ +"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ -"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \ +"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \ ":${netmask}:${hostname}:${netdev}:off\0" \ -"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \ +"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \ + hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \ +"console=ttyCPM0,115200\0" \ "netdev=eth0\0" \ -"contrast=55\0" \ +"contrast=20\0" \ "silent=1\0" \ +"mtdparts=" MTDPARTS_DEFAULT "\0" \ "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \ -"update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};" \ +"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \ "cp.b 200000 40050000 14000\0" #define CONFIG_BOOTCOMMAND \ - "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot" + "run fat_boot; run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot" +#define CONFIG_PREBOOT "setenv preboot; saveenv" #define CONFIG_MISC_INIT_R 1 #define CONFIG_MISC_INIT_F 1 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #define CONFIG_WATCHDOG 1 /* watchdog enabled */ @@ -106,11 +108,11 @@ /* * enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE +#define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CONFIG_SYS_I2C_SLAVE 0xFE #ifdef CONFIG_SOFT_I2C /* @@ -135,8 +137,8 @@ * I2C Configuration */ -#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ +#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ /* List of I2C addresses to be verified by POST */ @@ -151,21 +153,8 @@ #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_MII -#if 0 -#define CONFIG_ETHADDR 00:0B:64:00:00:00 /* our OUI from IEEE */ -#endif -#define CONFIG_KUP4K_LOGO 0x40050000 /* Address of logo bitmap */ - /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#if 1 -/* POST support */ - -#define CONFIG_POST (CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_RTC | \ - CONFIG_SYS_POST_I2C) -#endif - /* * Command line configuration. @@ -176,7 +165,9 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_I2C #define CONFIG_CMD_IDE +#define CONFIG_CMD_MII #define CONFIG_CMD_NFS +#define CONFIG_CMD_FAT #define CONFIG_CMD_SNTP #ifdef CONFIG_POST @@ -191,18 +182,21 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x002C00000 /* 4 ... 44 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x000400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x005C00000 /* 4 ... 92 MB in DRAM */ +#define CONFIG_SYS_ALT_MEMTEST 1 +#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200 /* using latch as scratch register */ -#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 } @@ -259,19 +253,23 @@ #define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ #define CONFIG_ENV_SECT_SIZE 0x10000 -/* Address and size of Redundant Environment Sector */ -#if 0 -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif + +/*----------------------------------------------------------------------- + * Dynamic MTD partition support + */ +#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \ + "64k(env)," \ + "128k(splash)," \ + "512k(etc)," \ + "64k(hw-info)" + /*----------------------------------------------------------------------- * Hardware Information Block */ -#if 1 #define CONFIG_SYS_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */ #define CONFIG_SYS_HWINFO_SIZE 0x00000100 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ -#endif +#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */ + /*----------------------------------------------------------------------- * Cache Configuration */ @@ -286,12 +284,7 @@ *----------------------------------------------------------------------- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze */ -#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */ -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif /*----------------------------------------------------------------------- * SIUMCR - SIU Module Configuration 11-6 @@ -416,12 +409,15 @@ /* * FLASH timing: */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_2_CLK | OR_EHTR | OR_BI) +#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \ + OR_SCY_5_CLK | OR_EHTR | OR_BI) -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CONFIG_SYS_OR0_REMAP \ + (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM \ + (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_BR0_PRELIM \ + ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ @@ -475,7 +471,39 @@ /* * MAMR settings for SDRAM */ -#define CONFIG_SYS_MAMR 0x80802114 + +/* 8 column SDRAM */ +#define CONFIG_SYS_MAMR_8COL 0x68802114 +/* 9 column SDRAM */ +#define CONFIG_SYS_MAMR_9COL 0x68904114 + +/* + * Chip Selects + */ +#define CONFIG_SYS_OR0 +#define CONFIG_SYS_BR0 + +#define CONFIG_SYS_OR1_8COL 0xFF000A00 +#define CONFIG_SYS_BR1_8COL 0x00000081 +#define CONFIG_SYS_OR2_8COL 0xFE000A00 +#define CONFIG_SYS_BR2_8COL 0x01000081 +#define CONFIG_SYS_OR3_8COL 0xFC000A00 +#define CONFIG_SYS_BR3_8COL 0x02000081 + +#define CONFIG_SYS_OR1_9COL 0xFE000A00 +#define CONFIG_SYS_BR1_9COL 0x00000081 +#define CONFIG_SYS_OR2_9COL 0xFE000A00 +#define CONFIG_SYS_BR2_9COL 0x02000081 +#define CONFIG_SYS_OR3_9COL 0xFE000A00 +#define CONFIG_SYS_BR3_9COL 0x04000081 + +#define CONFIG_SYS_OR4 0xFFFF8926 +#define CONFIG_SYS_BR4 0x90000401 + +#define CONFIG_SYS_OR5 0xFFC007F0 /* EPSON: 4 MB 17 WS or externel TA */ +#define CONFIG_SYS_BR5 0x80080801 /* Start at 0x80080000 */ + +#define LATCH_ADDR 0x90000200 /* * Internal Definitions @@ -487,11 +515,10 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay -#endif -#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ -#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_AUTOBOOT_STOP_STR "." +#define CONFIG_SILENT_CONSOLE 1 +#define CONFIG_SYS_DEVICE_NULLDEV 1 /* enble null device */ +#define CONFIG_VERSION_VARIABLE 1 #endif /* __CONFIG_H */ + diff --git a/include/configs/KUP4X.h b/include/configs/KUP4X.h index be6dfda..2e2ce0f 100644 --- a/include/configs/KUP4X.h +++ b/include/configs/KUP4X.h @@ -35,23 +35,20 @@ * (easy to change) */ -#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ -#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ +#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */ +#define CONFIG_KUP4X 1 /* ...on a KUP4X module */ -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ #undef CONFIG_8xx_CONS_SMC2 #undef CONFIG_8xx_CONS_NONE -#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#if 0 -#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ -#else -#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#endif +#define CONFIG_BAUDRATE 115200 /* console baudrate */ -#define CONFIG_BOARD_TYPES 1 /* support board types */ +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ -#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */ -#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */ +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_SYS_8XX_FACT 8 /* Multiply by 8 */ +#define CONFIG_SYS_8XX_XIN 16000000 /* 16 MHz in */ #define MPC8XX_HZ ((CONFIG_SYS_8XX_XIN) * (CONFIG_SYS_8XX_FACT)) @@ -67,9 +64,9 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \ "run addhw;diskboot 200000 0:1;bootm 200000\0" \ -"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\ - run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\ - usb stop; bootm 200000\0" \ +"usb_boot=setenv bootargs root=/dev/sda2 ip=off; \ + run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1; \ + usb stop; bootm 200000\0" \ "nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \ "panic_boot=echo No Bootdevice !!! reset\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \ @@ -91,7 +88,7 @@ #define CONFIG_MISC_INIT_F 1 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ #define CONFIG_WATCHDOG 1 /* watchdog enabled */ @@ -144,8 +141,8 @@ * I2C Configuration */ -#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ +#define CONFIG_SYS_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */ /* List of I2C addresses to be verified by POST */ @@ -160,22 +157,16 @@ #define CONFIG_SYS_DISCOVER_PHY #define CONFIG_MII -#if 0 -#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */ -#endif #undef CONFIG_KUP4K_LOGO /* Define to allow the user to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#if 1 /* POST support */ - #define CONFIG_POST (CONFIG_SYS_POST_CPU | \ CONFIG_SYS_POST_RTC | \ CONFIG_SYS_POST_I2C) -#endif /* @@ -426,9 +417,12 @@ #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ OR_SCY_2_CLK | OR_EHTR | OR_BI) -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) +#define CONFIG_SYS_OR0_REMAP \ + (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_OR0_PRELIM \ + (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) +#define CONFIG_SYS_BR0_PRELIM \ + ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ @@ -444,6 +438,15 @@ /* + * Chip Selects + */ + +#define CONFIG_SYS_OR4 0xFFFF8926 +#define CONFIG_SYS_BR4 0x90000401 + +#define LATCH_ADDR 0x90000200 + +/* * Internal Definitions * * Boot Flags @@ -453,10 +456,7 @@ #define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ -#if 0 -#define CONFIG_AUTOBOOT_PROMPT \ - "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay -#endif + #define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */ #define CONFIG_SILENT_CONSOLE 1 -- 1.6.2.5 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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