May 2010 - U-Boot

[U-Boot] [PATCH] cmd_usb.c: show cmd usage if no args given
by Serge Ziryukin 06 May '10

06 May '10

Signed-off-by: Serge Ziryukin <ftrvxmtrx(a)gmail.com> --- common/cmd_usb.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/common/cmd_usb.c b/common/cmd_usb.c index ee3755c..fcb5f76 100644 --- a/common/cmd_usb.c +++ b/common/cmd_usb.c @@ -516,6 +516,11 @@ int do_usb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) block_dev_desc_t *stor_dev; #endif + if (argc < 2) { + cmd_usage(cmdtp); + return 1; + } + if ((strncmp(argv[1], "reset", 5) == 0) || (strncmp(argv[1], "start", 5) == 0)) { usb_stop(); -- 1.7.1

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[U-Boot] [PATCH v2] powerpc: Consolidate bootcount_{store|load} for PowerPC
by Stefan Roese 06 May '10

06 May '10

This patch consolidates bootcount_{store|load} for PowerPC by implementing a common version in arch/powerpc/lib/bootcount.c. This code is now used by all PowerPC variants that currently have these functions implemented. The functions now use the proper IO-accessor functions to read/write the values. This code also supports two different bootcount versions: a) Use 2 seperate words (2 * 32bit) to store the bootcounter b) Use only 1 word (2 * 16bit) to store the bootcounter Version b) was already used by MPC5xxx. Signed-off-by: Stefan Roese <sr(a)denx.de> Acked-by: Detlev Zundel <dzu(a)denx.de> Cc: Michael Zaidman <michael.zaidman(a)gmail.com> Cc: Wolfgang Denk <wd(a)denx.de> Cc: Kim Phillips <kim.phillips(a)freescale.com> Cc: Anatolij Gustschin <agust(a)denx.de> --- v2: - Replace CONFIG_SYS_BOOTCOUNT_USE_32BIT with CONFIG_SYS_BOOTCOUNT_SINGLEWORD as suggested by Detlev - Use CONFIG_8xx for MPC8xx define section - Replace CONFIG_BOOTCOUNT_ADDR with CONFIG_SYS_BOOTCOUNT_ADDR arch/powerpc/cpu/mpc5xxx/cpu.c | 20 -------- arch/powerpc/cpu/mpc8260/commproc.c | 24 --------- arch/powerpc/cpu/mpc83xx/cpu.c | 30 ------------ arch/powerpc/cpu/mpc8xx/commproc.c | 26 ---------- arch/powerpc/cpu/ppc4xx/commproc.c | 24 --------- arch/powerpc/lib/Makefile | 1 + arch/powerpc/lib/bootcount.c | 90 +++++++++++++++++++++++++++++++++++ 7 files changed, 91 insertions(+), 124 deletions(-) create mode 100644 arch/powerpc/lib/bootcount.c diff --git a/arch/powerpc/cpu/mpc5xxx/cpu.c b/arch/powerpc/cpu/mpc5xxx/cpu.c index b20234d..44b8a7a 100644 --- a/arch/powerpc/cpu/mpc5xxx/cpu.c +++ b/arch/powerpc/cpu/mpc5xxx/cpu.c @@ -154,26 +154,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) } #endif -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); - - *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = (volatile ulong *) (MPC5XXX_CDM_BRDCRMB); - - if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) - return 0; - else - return (*save_addr & 0x0000ffff); -} -#endif /* CONFIG_BOOTCOUNT_LIMIT */ - #ifdef CONFIG_MPC5xxx_FEC /* Default initializations for FEC controllers. To override, * create a board-specific function called: diff --git a/arch/powerpc/cpu/mpc8260/commproc.c b/arch/powerpc/cpu/mpc8260/commproc.c index 111a67c..c522bc5 100644 --- a/arch/powerpc/cpu/mpc8260/commproc.c +++ b/arch/powerpc/cpu/mpc8260/commproc.c @@ -195,27 +195,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c index 51180d6..fb32f01 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu.c +++ b/arch/powerpc/cpu/mpc83xx/cpu.c @@ -302,33 +302,3 @@ int cpu_mmc_init(bd_t *bis) return 0; #endif } - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -#if !defined(CONFIG_MPC8360) -#error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented" -#endif - -#if !defined(CONFIG_BOOTCOUNT_ADDR) -#define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long)) -#endif - -#include <asm/io.h> - -void bootcount_store (ulong a) -{ - void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); - out_be32 (reg, a); - out_be32 (reg + 4, BOOTCOUNT_MAGIC); -} - -ulong bootcount_load (void) -{ - void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR); - - if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC) - return 0; - else - return in_be32 (reg); -} -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/cpu/mpc8xx/commproc.c b/arch/powerpc/cpu/mpc8xx/commproc.c index a87a0dc..2c85377 100644 --- a/arch/powerpc/cpu/mpc8xx/commproc.c +++ b/arch/powerpc/cpu/mpc8xx/commproc.c @@ -103,29 +103,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + - CPM_BOOTCOUNT_ADDR ); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)( ((immap_t *) CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + - CPM_BOOTCOUNT_ADDR ); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/cpu/ppc4xx/commproc.c b/arch/powerpc/cpu/ppc4xx/commproc.c index a1696d3..6bf95e6 100644 --- a/arch/powerpc/cpu/ppc4xx/commproc.c +++ b/arch/powerpc/cpu/ppc4xx/commproc.c @@ -51,27 +51,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST || CONFIG_LOGBUFFER*/ - -#ifdef CONFIG_BOOTCOUNT_LIMIT - -void bootcount_store (ulong a) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR); - - save_addr[0] = a; - save_addr[1] = BOOTCOUNT_MAGIC; -} - -ulong bootcount_load (void) -{ - volatile ulong *save_addr = - (volatile ulong *)(CONFIG_SYS_OCM_DATA_ADDR + CONFIG_SYS_BOOTCOUNT_ADDR); - - if (save_addr[1] != BOOTCOUNT_MAGIC) - return 0; - else - return save_addr[0]; -} - -#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile index 334e457..5f85502 100644 --- a/arch/powerpc/lib/Makefile +++ b/arch/powerpc/lib/Makefile @@ -33,6 +33,7 @@ SOBJS-y += reloc.o COBJS-y += bat_rw.o COBJS-y += board.o COBJS-y += bootm.o +COBJS-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount.o COBJS-y += cache.o COBJS-y += extable.o COBJS-y += interrupts.o diff --git a/arch/powerpc/lib/bootcount.c b/arch/powerpc/lib/bootcount.c new file mode 100644 index 0000000..6346527 --- /dev/null +++ b/arch/powerpc/lib/bootcount.c @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> + +/* + * Only override CONFIG_SYS_BOOTCOUNT_ADDR if not already defined. This + * way, some boards can define it directly in their config header. + */ +#if !defined(CONFIG_SYS_BOOTCOUNT_ADDR) + +#if defined(CONFIG_MPC5xxx) +#define CONFIG_SYS_BOOTCOUNT_ADDR (MPC5XXX_CDM_BRDCRMB) +#define CONFIG_SYS_BOOTCOUNT_SINGLEWORD +#endif /* defined(CONFIG_MPC5xxx) */ + +#if defined(CONFIG_8xx) +#define CONFIG_SYS_BOOTCOUNT_ADDR (((immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_dpmem + \ + CPM_BOOTCOUNT_ADDR) +#endif /* defined(CONFIG_8xx) */ + +#if defined(CONFIG_MPC8260) +#include <asm/cpm_8260.h> + +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + CPM_BOOTCOUNT_ADDR) +#endif /* defined(CONFIG_MPC8260) */ + +#if defined(CONFIG_MPC8360) +#include <asm/immap_qe.h> + +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_IMMR + 0x110000 + \ + QE_MURAM_SIZE - 2 * sizeof(u32)) +#endif /* defined(CONFIG_MPC8360) */ + +#if defined(CONFIG_4xx) +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_OCM_DATA_ADDR + \ + CONFIG_SYS_BOOTCOUNT_ADDR) +#endif /* defined(CONFIG_4xx) */ + +#endif /* !defined(CONFIG_SYS_BOOTCOUNT_ADDR) */ + +void bootcount_store(ulong a) +{ + void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR; + +#if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) + out_be32(reg, (BOOTCOUNT_MAGIC & 0xffff0000) | a); +#else + out_be32(reg, a); + out_be32(reg + 4, BOOTCOUNT_MAGIC); +#endif +} + +ulong bootcount_load(void) +{ + void *reg = (void *)CONFIG_SYS_BOOTCOUNT_ADDR; + +#if defined(CONFIG_SYS_BOOTCOUNT_SINGLEWORD) + if (in_be16(reg + 2) != (BOOTCOUNT_MAGIC & 0xffff)) + return 0; + else + return in_be16(reg); +#else + if (in_be32(reg + 4) != BOOTCOUNT_MAGIC) + return 0; + else + return in_be32(reg); +#endif +} -- 1.7.1

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[U-Boot] [GIT PULL] Pull request: u-boot-imx
by Stefano Babic 06 May '10

06 May '10

Hi Tom, please pull from u-boot-imx. The following changes since commit b88c5988db176a0f9de5598d5167ee2498637d40: Kim Phillips (1): configs: remove unused CONFIG_COMMAND_HISTORY are available in the git repository at: git://git.denx.de/u-boot-imx master Anatolij Gustschin (1): tx25: fix crash while booting Linux Fabio Estevam (1): MX51: Fix MX51 CPU detect message Magnus Lilja (1): i.MX31: Activate NAND support for i.MX31 Litekit board. Stefano Babic (7): MX51evk: Removed warnings MX: Added Freescale Power Management Driver MX: RTC13783 uses general function to access PMIC MX31: Add support for PMIC to the QONG module SPI: added support for MX51 to mxc_spi MX: Added definition file for MC13892 Add SPI support to mx51evk board arch/arm/cpu/arm_cortexa8/mx51/soc.c | 2 +- board/davedenx/qong/qong.c | 20 +++ board/freescale/mx51evk/mx51evk.c | 143 +++++++++++++++++++++- board/karo/tx25/tx25.c | 3 + drivers/misc/Makefile | 1 + drivers/misc/fsl_pmic.c | 200 +++++++++++++++++++++++++++++ drivers/rtc/mc13783-rtc.c | 72 +++--------- drivers/spi/mxc_spi.c | 231 +++++++++++++++++++++++++++++++--- include/configs/imx31_litekit.h | 19 +++- include/configs/mx31ads.h | 8 +- include/configs/mx31pdk.h | 9 +- include/configs/mx51evk.h | 15 +++ include/configs/qong.h | 14 ++ include/fsl_pmic.h | 128 +++++++++++++++++++ include/mc13892.h | 160 +++++++++++++++++++++++ 15 files changed, 935 insertions(+), 90 deletions(-) create mode 100644 drivers/misc/fsl_pmic.c create mode 100644 include/fsl_pmic.h create mode 100644 include/mc13892.h -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot] NAND flash parameters.
by Ayewin Oung 06 May '10

06 May '10

Hi List How do I modify SLC NAND flash parameters for u-boot ? When I say "nand parameters", I meant things like " how many pages in a block, how many blocks and how big is each page," not timing. Is it per NAND controller implementation specific or is it more generic across u-boot? As always thanks in advance. Ayewin

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[U-Boot] PRIVATE HOME LENDER
by PRIVATE HOME LENDER 06 May '10

06 May '10

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[U-Boot] U-Boot "public API" example desired
by jimc＠sdateam.com 06 May '10

06 May '10

Is there an example available of the use of the U-Boot "public API" or of a "stand-alone application", that can be, or is, sanctioned by someone who would definitely know (for example, Wolfgang Denk) as being not a derived work? I've seen several discussions in various mailing lists about these interfaces but I have not seen a definite example that qualifies. It is not clear that the examples in the U-Boot source trees completely qualify. The most recent tree I've seen is 2010.03, which I got from ftp://ftp.denx.de/pub/u-boot/u-boot-2010.03.tar.bz2. Web searches I've done have revealed only theoretical discussion or discussion of future needs and possible improvements. I've probably missed it, can someone provide a pointer? Thank you very much. Jim

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[U-Boot] [PATCH-V3 2/2] omap3: Consolidate SDRC related operations
by hvaibhav＠ti.com 06 May '10

06 May '10

From: Vaibhav Hiremath <hvaibhav(a)ti.com> Consolidated SDRC related functions into one file - sdrc.c And also replaced sdrc_init with generic memory init function (mem_init), this generalization of omap memory setup is necessary to support the new emif4 interface introduced in AM3517. Changes from V2: - Removed all instances of #ifdef CONFIG_SDRC Changes from V1: - Refreshed against latest denx/master Signed-off-by: Vaibhav Hiremath <hvaibhav(a)ti.com> Signed-off-by: Sanjeev Premi <premi(a)ti.com> --- arch/arm/cpu/arm_cortexa8/omap3/Makefile | 4 +- arch/arm/cpu/arm_cortexa8/omap3/board.c | 35 +----- arch/arm/cpu/arm_cortexa8/omap3/mem.c | 90 ------------ arch/arm/cpu/arm_cortexa8/omap3/sdrc.c | 202 +++++++++++++++++++++++++++ arch/arm/cpu/arm_cortexa8/omap3/sys_info.c | 41 ------ arch/arm/include/asm/arch-omap3/cpu.h | 1 + arch/arm/include/asm/arch-omap3/mem.h | 13 ++ arch/arm/include/asm/arch-omap3/sys_proto.h | 2 - include/configs/devkit8000.h | 2 + include/configs/omap3_beagle.h | 2 + include/configs/omap3_evm.h | 2 + include/configs/omap3_overo.h | 2 + include/configs/omap3_pandora.h | 2 + include/configs/omap3_sdp3430.h | 2 + include/configs/omap3_zoom1.h | 2 + include/configs/omap3_zoom2.h | 2 + 16 files changed, 236 insertions(+), 168 deletions(-) create mode 100644 arch/arm/cpu/arm_cortexa8/omap3/sdrc.c diff --git a/arch/arm/cpu/arm_cortexa8/omap3/Makefile b/arch/arm/cpu/arm_cortexa8/omap3/Makefile index 136b163..1e80eb3 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/Makefile +++ b/arch/arm/cpu/arm_cortexa8/omap3/Makefile @@ -37,8 +37,10 @@ COBJS += syslib.o COBJS += sys_info.o COBJS += timer.o +COBJS-$(CONFIG_SDRC) += sdrc.o + SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) all: $(obj).depend $(LIB) diff --git a/arch/arm/cpu/arm_cortexa8/omap3/board.c b/arch/arm/cpu/arm_cortexa8/omap3/board.c index 69a08fd..d2500ca 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/board.c +++ b/arch/arm/cpu/arm_cortexa8/omap3/board.c @@ -40,8 +40,6 @@ extern omap3_sysinfo sysinfo; -extern u32 is_mem_sdr(void); - /****************************************************************************** * Routine: delay * Description: spinning delay to use before udelay works @@ -233,7 +231,7 @@ void s_init(void) per_clocks_enable(); if (!in_sdram) - sdrc_init(); + mem_init(); } /****************************************************************************** @@ -274,37 +272,6 @@ void watchdog_init(void) } /****************************************************************************** - * Routine: dram_init - * Description: sets uboots idea of sdram size - *****************************************************************************/ -int dram_init(void) -{ - DECLARE_GLOBAL_DATA_PTR; - unsigned int size0 = 0, size1 = 0; - - size0 = get_sdr_cs_size(CS0); - - /* - * If a second bank of DDR is attached to CS1 this is - * where it can be started. Early init code will init - * memory on CS0. - */ - if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { - do_sdrc_init(CS1, NOT_EARLY); - make_cs1_contiguous(); - - size1 = get_sdr_cs_size(CS1); - } - - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = size0; - gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); - gd->bd->bi_dram[1].size = size1; - - return 0; -} - -/****************************************************************************** * Dummy function to handle errors for EABI incompatibility *****************************************************************************/ void abort(void) diff --git a/arch/arm/cpu/arm_cortexa8/omap3/mem.c b/arch/arm/cpu/arm_cortexa8/omap3/mem.c index dfb7e4c..bd914b0 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/mem.c +++ b/arch/arm/cpu/arm_cortexa8/omap3/mem.c @@ -79,26 +79,6 @@ static const u32 gpmc_onenand[GPMC_MAX_REG] = { #endif -static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; - -/************************************************************************** - * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow - * command line mem=xyz use all memory with out discontinuous support - * compiled in. Could do it at the ATAG, but there really is two banks... - * Called as part of 2nd phase DDR init. - **************************************************************************/ -void make_cs1_contiguous(void) -{ - u32 size, a_add_low, a_add_high; - - size = get_sdr_cs_size(CS0); - size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ - a_add_high = (size & 3) << 8; /* set up low field */ - a_add_low = (size & 0x3C) >> 2; /* set up high field */ - writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); - -} - /******************************************************** * mem_ok() - test used to see if timings are correct * for a part. Helps in guessing which part @@ -123,76 +103,6 @@ u32 mem_ok(u32 cs) return 1; } -/******************************************************** - * sdrc_init() - init the sdrc chip selects CS0 and CS1 - * - early init routines, called from flash or - * SRAM. - *******************************************************/ -void sdrc_init(void) -{ - /* only init up first bank here */ - do_sdrc_init(CS0, EARLY_INIT); -} - -/************************************************************************* - * do_sdrc_init(): initialize the SDRAM for use. - * -code sets up SDRAM basic SDRC timings for CS0 - * -optimal settings can be placed here, or redone after i2c - * inspection of board info - * - * - code called once in C-Stack only context for CS0 and a possible 2nd - * time depending on memory configuration from stack+global context - **************************************************************************/ - -void do_sdrc_init(u32 cs, u32 early) -{ - struct sdrc_actim *sdrc_actim_base; - - if(cs) - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - else - sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - - if (early) { - /* reset sdrc controller */ - writel(SOFTRESET, &sdrc_base->sysconfig); - wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, - 12000000); - writel(0, &sdrc_base->sysconfig); - - /* setup sdrc to ball mux */ - writel(SDRC_SHARING, &sdrc_base->sharing); - - /* Disable Power Down of CKE cuz of 1 CKE on combo part */ - writel(WAKEUPPROC | PWDNEN | SRFRONRESET | PAGEPOLICY_HIGH, - &sdrc_base->power); - - writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); - sdelay(0x20000); - } - - writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | - RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | - DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); - writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); - writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); - writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); - - writel(CMD_NOP, &sdrc_base ->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - - /* - * CAS latency 3, Write Burst = Read Burst, Serial Mode, - * Burst length = 4 - */ - writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr); - - if (!mem_ok(cs)) - writel(0, &sdrc_base->cs[cs].mcfg); -} - void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) { diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c new file mode 100644 index 0000000..96fd990 --- /dev/null +++ b/arch/arm/cpu/arm_cortexa8/omap3/sdrc.c @@ -0,0 +1,202 @@ +/* + * Functions related to OMAP3 SDRC. + * + * This file has been created after exctracting and consolidating + * the SDRC related content from mem.c and board.c, also created + * generic init function (mem_init). + * + * Copyright (C) 2004-2010 + * Texas Instruments Incorporated - http://www.ti.com/ + * + * Author : + * Vaibhav Hiremath <hvaibhav(a)ti.com> + * + * Original implementation by (mem.c, board.c) : + * Sunil Kumar <sunilsaini05(a)gmail.com> + * Shashi Ranjan <shashiranjanmca05(a)gmail.com> + * Manikandan Pillai <mani.pillai(a)ti.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> + +extern omap3_sysinfo sysinfo; + +static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; + +/* + * is_mem_sdr - + * - Return 1 if mem type in use is SDR + */ +u32 is_mem_sdr(void) +{ + if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) + return 1; + return 0; +} + +/* + * make_cs1_contiguous - + * - For es2 and above remap cs1 behind cs0 to allow command line + * mem=xyz use all memory with out discontinuous support compiled in. + * Could do it at the ATAG, but there really is two banks... + * - Called as part of 2nd phase DDR init. + */ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(CS0); + size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); + +} + + +/* + * get_sdr_cs_size - + * - Get size of chip select 0/1 + */ +u32 get_sdr_cs_size(u32 cs) +{ + u32 size; + + /* get ram size field */ + size = readl(&sdrc_base->cs[cs].mcfg) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size <<= 21; /* multiply by 2 MiB to find size in MB */ + return size; +} + +/* + * get_sdr_cs_offset - + * - Get offset of cs from cs0 start + */ +u32 get_sdr_cs_offset(u32 cs) +{ + u32 offset; + + if (!cs) + return 0; + + offset = readl(&sdrc_base->cs_cfg); + offset = (offset & 15) << 27 | (offset & 0x30) >> 17; + + return offset; +} + +/* + * do_sdrc_init - + * - Initialize the SDRAM for use. + * - Sets up SDRC timings for CS0 + * - code called once in C-Stack only context for CS0 and a possible 2nd + * time depending on memory configuration from stack+global context + */ +void do_sdrc_init(u32 cs, u32 early) +{ + struct sdrc_actim *sdrc_actim_base; + + if (cs) + sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; + else + sdrc_actim_base = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + + if (early) { + /* reset sdrc controller */ + writel(SOFTRESET, &sdrc_base->sysconfig); + wait_on_value(RESETDONE, RESETDONE, &sdrc_base->status, + 12000000); + writel(0, &sdrc_base->sysconfig); + + /* setup sdrc to ball mux */ + writel(SDRC_SHARING, &sdrc_base->sharing); + + /* Disable Power Down of CKE cuz of 1 CKE on combo part */ + writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, + &sdrc_base->power); + + writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); + sdelay(0x20000); + } + + writel(RASWIDTH_13BITS | CASWIDTH_10BITS | ADDRMUXLEGACY | + RAMSIZE_128 | BANKALLOCATION | B32NOT16 | B32NOT16 | + DEEPPD | DDR_SDRAM, &sdrc_base->cs[cs].mcfg); + writel(ARCV | ARE_ARCV_1, &sdrc_base->cs[cs].rfr_ctrl); + writel(V_ACTIMA_165, &sdrc_actim_base->ctrla); + writel(V_ACTIMB_165, &sdrc_actim_base->ctrlb); + + writel(CMD_NOP, &sdrc_base->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + + /* + * CAS latency 3, Write Burst = Read Burst, Serial Mode, + * Burst length = 4 + */ + writel(CASL3 | BURSTLENGTH4, &sdrc_base->cs[cs].mr); + + if (!mem_ok(cs)) + writel(0, &sdrc_base->cs[cs].mcfg); +} + +/* + * dram_init - + * - Sets uboots idea of sdram size + */ +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { + do_sdrc_init(CS1, NOT_EARLY); + make_cs1_contiguous(); + + size1 = get_sdr_cs_size(CS1); + } + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; + + return 0; +} + +/* + * mem_init - + * - Init the sdrc chip, + * - Selects CS0 and CS1, + */ +void mem_init(void) +{ + /* only init up first bank here */ + do_sdrc_init(CS0, EARLY_INIT); +} diff --git a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c index 08fb32e..1df4401 100644 --- a/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c +++ b/arch/arm/cpu/arm_cortexa8/omap3/sys_info.c @@ -32,7 +32,6 @@ #include <i2c.h> extern omap3_sysinfo sysinfo; -static struct sdrc *sdrc_base = (struct sdrc *)OMAP34XX_SDRC_BASE; static struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE; static char *rev_s[CPU_3XX_MAX_REV] = { "1.0", @@ -104,46 +103,6 @@ u32 get_cpu_rev(void) } } -/**************************************************** - * is_mem_sdr() - return 1 if mem type in use is SDR - ****************************************************/ -u32 is_mem_sdr(void) -{ - if (readl(&sdrc_base->cs[CS0].mr) == SDRC_MR_0_SDR) - return 1; - return 0; -} - -/*********************************************************************** - * get_cs0_size() - get size of chip select 0/1 - ************************************************************************/ -u32 get_sdr_cs_size(u32 cs) -{ - u32 size; - - /* get ram size field */ - size = readl(&sdrc_base->cs[cs].mcfg) >> 8; - size &= 0x3FF; /* remove unwanted bits */ - size <<= 21; /* multiply by 2 MiB to find size in MB */ - return size; -} - -/*********************************************************************** - * get_sdr_cs_offset() - get offset of cs from cs0 start - ************************************************************************/ -u32 get_sdr_cs_offset(u32 cs) -{ - u32 offset; - - if (!cs) - return 0; - - offset = readl(&sdrc_base->cs_cfg); - offset = (offset & 15) << 27 | (offset & 0x30) >> 17; - - return offset; -} - /*************************************************************************** * get_gpmc0_base() - Return current address hardware will be * fetching from. The below effectively gives what is correct, its a bit diff --git a/arch/arm/include/asm/arch-omap3/cpu.h b/arch/arm/include/asm/arch-omap3/cpu.h index aa8de32..ce16da7 100644 --- a/arch/arm/include/asm/arch-omap3/cpu.h +++ b/arch/arm/include/asm/arch-omap3/cpu.h @@ -215,6 +215,7 @@ struct sdrc { u8 res4[0xC]; struct sdrc_cs cs[2]; /* 0x80 || 0xB0 */ }; + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 9439758..a78cf9f 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -270,4 +270,17 @@ enum { #define PISMO1_ONEN_BASE ONENAND_MAP #define DBG_MPDB_BASE DEBUG_BASE +#ifndef __ASSEMBLY__ + +/* Function prototypes */ +void mem_init(void); + +u32 is_mem_sdr(void); +u32 mem_ok(u32 cs); + +u32 get_sdr_cs_size(u32); +u32 get_sdr_cs_offset(u32); + +#endif /* __ASSEMBLY__ */ + #endif /* endif _MEM_H_ */ diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 34bd515..4608f30 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -46,8 +46,6 @@ u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void); u32 get_gpmc0_width(void); -u32 get_sdr_cs_size(u32); -u32 get_sdr_cs_offset(u32); u32 is_running_in_sdram(void); u32 is_running_in_sram(void); u32 is_running_in_flash(void); diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 7d1332f..1076de6 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -38,6 +38,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 08d79ac..e018b21 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -37,6 +37,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 88af492..af7c65a 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -42,6 +42,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_EVM 1 /* working with EVM */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index a43500b..b441831 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -29,6 +29,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_OVERO 1 /* working with overo */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 945c053..9eba003 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -32,6 +32,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_PANDORA 1 /* working with pandora */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index b4919db..d4482d3 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -42,6 +42,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index ae7ebf9..1e88dc0 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -38,6 +38,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM1 1 /* working with Zoom MDK Rev1 */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index c88c732..be9daf4 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -39,6 +39,8 @@ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ #define CONFIG_OMAP3_ZOOM2 1 /* working with Zoom II */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + #include <asm/arch/cpu.h> /* get chip and board defs */ #include <asm/arch/omap3.h> -- 1.6.2.4

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[U-Boot] OT: SD/MMC-over-SPI and speed in linux
by wolfgang＠leila.ping.de 06 May '10

06 May '10

Hi all, sorry for the off-topic question, but I seemingly did not yet find the right search string and was hoping to find experienced embedded people here to point me in the right direction. I have connected a SD card to a coldfire MCF54455 via SPI, accessible from both U-Boot and linux. The kernel is quite old, 2.6.25 from the freescale LTIB, because freescale did not push their coldfire changes back into any official tree. In U-Boot, I can get read speeds with fatload of around 400 kBytes/second, which seems reasonable as the card can handle 25 MHz SPI speed. (And, it would be sufficient for our application.) In the linux kernel, the read speed drops to around 35 kBytes/second, regardless of using a filesystem or not. This is not only quite ridiculous (as I would expect more optimized drivers in the kernel than in the bootloader), but would give us real performance problems when writing to the card. The SPI speed is detected and set correctly to 25 MHz by the driver. Does anybody know if this is a known limitation in (older) linux mmc_spi implementation, or if this issue still exists? If it is solved, can anybody point me to a patch/discussion/keyword where I can find more information which part I would have to check or back-port? Best regards, Wolfgang

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[U-Boot] [PATCH] Support for devices with FAT32 PBR
by Igor Luri 06 May '10

06 May '10

This patch adds support for devices that have a FAT32 PBR. Signed-off-by: Igor Luri <iluri(a)aotek.es> --- disk/part_dos.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/disk/part_dos.c b/disk/part_dos.c index 887b75e..d91f773 100644 --- a/disk/part_dos.c +++ b/disk/part_dos.c @@ -77,7 +77,8 @@ static int test_block_type(unsigned char *buffer) (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) ) { return (-1); } /* no DOS Signature at all */ - if(strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0) + if((strncmp((char *)&buffer[DOS_PBR_FSTYPE_OFFSET],"FAT",3)==0) || + (strncmp((char *)&buffer[DOS_PBR_FAT32_FSTYPE_OFFSET],"FAT32",5)==0) ) return DOS_PBR; /* is PBR */ return DOS_MBR; /* Is MBR */ } -- 1.5.4.3 --- disk/part_dos.h | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/disk/part_dos.h b/disk/part_dos.h index ac93f20..6383c58 100644 --- a/disk/part_dos.h +++ b/disk/part_dos.h @@ -35,6 +35,7 @@ #define DOS_PART_TBL_OFFSET 0x1be #define DOS_PART_MAGIC_OFFSET 0x1fe #define DOS_PBR_FSTYPE_OFFSET 0x36 +#define DOS_PBR_FAT32_FSTYPE_OFFSET 0x52 #define DOS_PBR_MEDIA_TYPE_OFFSET 0x15 #define DOS_MBR 0 #define DOS_PBR 1 -- 1.5.4.3 --- fs/fat/fat.c | 7 +++++-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/fs/fat/fat.c b/fs/fat/fat.c index 2445f1e..4da4351 100644 --- a/fs/fat/fat.c +++ b/fs/fat/fat.c @@ -50,6 +50,7 @@ static int cur_part = 1; #define DOS_PART_TBL_OFFSET 0x1be #define DOS_PART_MAGIC_OFFSET 0x1fe #define DOS_FS_TYPE_OFFSET 0x36 +#define DOS_FS_FAT32_TYPE_OFFSET 0x52 int disk_read (__u32 startblock, __u32 getsize, __u8 * bufptr) { @@ -94,7 +95,8 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) if (!get_partition_info (dev_desc, part_no, &info)) { part_offset = info.start; cur_part = part_no; - } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3)) { + } else if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3) || + !strncmp((char *)&buffer[DOS_FS_FAT32_TYPE_OFFSET], "FAT32", 5)) { /* ok, we assume we are on a PBR only */ cur_part = 1; part_offset = 0; @@ -105,7 +107,8 @@ fat_register_device(block_dev_desc_t *dev_desc, int part_no) } #else - if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3)) { + if (!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET],"FAT",3) || + !strncmp((char *)&buffer[DOS_FS_FAT32_TYPE_OFFSET], "FAT32", 5) ) { /* ok, we assume we are on a PBR only */ cur_part = 1; part_offset = 0; -- 1.5.4.3 -- Igor Luri R&D Software Department Fagor Aotek S. Coop. P. O. Box 144 E-20500 Mondragón-Arrasate Tel. ++34 943 71 92 00 ++34 943 71 92 01 (Ext. 44268) Fax. ++34 943 79 92 03 www.aotek.es

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[U-Boot] u-boot hangs after detecting DDR3 RAM and Flash.
by prakash bedge 06 May '10

06 May '10

Hi All, I am facing an error while porting u-boot for my platform because if exception error. After running the u-boot to detect the DDR and flash u-boot hangs after showing the serial console output. In debugger I am seeing PC at 0x00000400 address which the exception handler vector address. But when I modify the below statement in the function int interrupt_init (void) in u-boot\lib_ppc\interrupts.c, u-boot continues and I can see the u-boot prompt and I am able to run all u-boot commands. int interrupt_init (void) { int ret; /* call cpu specific function from $(CPU)/interrupts.c */ ret = interrupt_init_cpu (&decrementer_count); if (ret) return ret; set_dec (decrementer_count); --- set_msr (get_msr () | MSR_EE); //Removed this statement. ++ set_msr (get_msr ()); return (0); } It seems that there is an exception error and because of this u-boot hangs. But I didn't get any error condition till now. If someone has earlier experienced this kind of issue, please share. Regards, Prakash

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