October 2010 - U-Boot

[U-Boot] imx31 USB OTG support?
by Abbas Raza 25 Oct '10

25 Oct '10

Hello, Is there any support in uboot for USB OTG of imx31? I am trying to configure USB OTG in device mode for imx31. Any one worked on it or any ideas. Any help will be appreciated. Thanks -- Abbas Raza

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[U-Boot] [PATCH v3 2/2] Freescale 85xx/P1/P2 eSPI controller driver
by caydinc＠gmail.com 25 Oct '10

25 Oct '10

From: Can Aydin <can.aydin(a)locatacorp.com> Add support for Freescale eSPI driver in P1/P2 board configuration Signed-off-by: Can Aydin <can.aydin(a)locatacorp.com> --- Changes for v2: - Coding style cleanup - Removed modifications to common code Changes for v3: - fixed whitespace between function calls and parameters - replaced unneeded byte copy test function with memcpy - removed dead code and C++ style comments - separated board configuration patch from driver patch include/configs/P1_P2_RDB.h | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index cff0ed3..33f1b1e 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -172,6 +172,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ /* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_HARD_SPI +#define CONFIG_CMD_SPI + +/* * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ -- 1.7.0.4

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[U-Boot] [PATCH v3 1/2] Freescale 85xx/P1/P2 eSPI controller driver
by caydinc＠gmail.com 25 Oct '10

25 Oct '10

From: Can Aydin <can.aydin(a)locatacorp.com> Driver for the Freescale eSPI controller found in 85xx, P1/P2 and P4xx SoCs. Signed-off-by: Can Aydin <can.aydin(a)locatacorp.com> --- Changes for v2: - Coding style cleanup - Removed modifications to common code Changes for v3: - fixed whitespace between function calls and parameters - replaced unneeded byte copy test function with memcpy - removed dead code and C++ style comments - separated board configuration patch from driver patch drivers/spi/Makefile | 1 + drivers/spi/fsl_espi.c | 240 ++++++++++++++++++++++++++++++++++++++++++++++++ include/fsl_espi.h | 50 ++++++++++ 3 files changed, 291 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/fsl_espi.c create mode 100644 include/fsl_espi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index dfcbb8b..1aaa8e7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o COBJS-$(CONFIG_CF_SPI) += cf_spi.o COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o +COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c new file mode 100644 index 0000000..749d3f1 --- /dev/null +++ b/drivers/spi/fsl_espi.c @@ -0,0 +1,240 @@ +/* + * Freescale eSPI controller driver. + * + * Copyright 2010 Locata Corporation Pty. Ltd. + * Author: Can Aydin can.aydin(a)locatacorp.com + * Collab: Clayton Gumbrell clayton.gumbrell(a)locatacorp.com + * + * Adapted from Freescale ltib code by Mingkai Hu (Mingkai.hu(a)freescale.com) + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <malloc.h> +#include <spi.h> +#include <fsl_espi.h> +#include <asm/immap_85xx.h> + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + volatile ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + struct spi_slave *slave; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned char pm = 0; + int i; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* Enable eSPI interface */ + espi->mode = ESPI_MODE_RXTHR(3) | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN; + + espi->event = 0xffffffff; /* Clear all eSPI events */ + espi->mask = 0x00000000; /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + espi->csmode[i] = ESPI_CSMODE_INIT_VAL; + + espi->csmode[cs] &= + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(ESPI_MAX_CHARSIZE)); + + /* Set eSPI BRG clock source */ + get_sys_info(&sysinfo); + spibrg = sysinfo.freqSystemBus / 2; + if ((spibrg / max_hz) > 32) { + espi->csmode[cs] |= ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("Requested speed is too low: %d Hz" + " %u Hz is used.\n", max_hz, + (uint) (spibrg / (32 * 16))); + } + } else + pm = spibrg / (max_hz * 2); + if (pm) + pm--; + espi->csmode[cs] |= ESPI_CSMODE_PM(pm); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + espi->csmode[cs] |= ESPI_CSMODE_CP_BEGIN_EDGCLK; + if (mode & SPI_CPOL) + espi->csmode[cs] |= ESPI_CSMODE_CI_INACTIVEHIGH; + + /* Character bit order: msb first */ + espi->csmode[cs] |= ESPI_CSMODE_REV_MSB_FIRST; + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + espi->csmode[cs] |= ESPI_CSMODE_LEN(ESPI_CHARSIZE); + + return slave; +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + volatile ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + u32 com; + u32 event; + u8 wordsize = 4; /* Fifo access registers are 32 bits */ + u32 tmpdout, tmpdin; + unsigned int len, rxcount, txcount; + + if (!(flags & (SPI_XFER_BEGIN | SPI_XFER_END))) { + debug("spi_xfer: Segmented transfers not supported.\n"); + return 1; + } + + if (!bitlen) + return 0; + + len = bitlen / ESPI_CHARSIZE + ((bitlen % ESPI_CHARSIZE) ? 1 : 0); + + if (len > ESPI_MAX_TRANLEN) { + debug("spi_xfer: oversize xfer(%u), max %u(0x%X)\n", + len, ESPI_MAX_TRANLEN, ESPI_MAX_TRANLEN); + return 1; + } + + rxcount = len; + txcount = len; + debug("spi_xfer: slave %u:%u dout %08X(%08x) din %08X(%08x) len %u\n", + slave->bus, slave->cs, + *(uint *) dout, (uint) dout, *(uint *) din, (uint) din, len); + + /* Prepare eSPI transfer to slave cs with length len */ + com = 0; + com |= ESPI_COM_CS(slave->cs); + com |= ESPI_COM_TRANLEN(len); + espi->com = com; + + /* Clear all eSPI events and initiate new command */ + espi->event = 0xffffffff; + debugX(1, "spi_xfer: rxcount %08X, txcount %08X\n", rxcount, txcount); + while (rxcount) { + + event = espi->event; + debugX(4, "spi_xfer: SPIE 0x%08x\n", event); + debugX(3, "spi_xfer: SPIE (TXCNT): %u\n", + ESPI_EV_GET_TXCNT(event)); + if ((event & ESPI_EV_TNF) && (txcount)) { + /* Tx fifo not full and we still have stuff to send */ + if ((txcount >= wordsize) && + (ESPI_EV_GET_TXCNT(event) >= wordsize)) { + /* Have a full word and room to put it */ + tmpdout = *(u32 *) dout; + txcount -= wordsize; + dout += wordsize; + espi->tx = tmpdout; + } else if (ESPI_EV_GET_TXCNT(event) >= txcount) { + /* Less than a word left and room to put it */ + tmpdout = 0; + /* Avoid dout buffer read overflow */ + memcpy(&tmpdout, dout, txcount); + espi->tx = tmpdout; + txcount = 0; + } + espi->event |= ESPI_EV_TNF; + debugX(2, "*** spi_xfer: ... %08x written\n", tmpdout); + debugX(3, "spi_xfer: rxcount %08X, txcount %08X\n", + rxcount, txcount); + } + + event = espi->event; + debugX(4, "spi_xfer: SPIE 0x%08x\n", event); + debugX(3, "spi_xfer: SPIE (RXCNT): %u\n", + ESPI_EV_GET_RXCNT(event)); + if (event & ESPI_EV_RNE) { /* Rx fifo has data */ + unsigned int count = ESPI_EV_GET_RXCNT(event); + if (count >= wordsize) { + /* Have a full word to read */ + tmpdin = espi->rx; + *(u32 *) din = tmpdin; + if ((rxcount -= wordsize) > 0) { + din += wordsize; + } + } else if (count >= rxcount) { + /* Less than a word left to read */ + tmpdin = espi->rx; + /* Avoid din buffer write overflow */ + memcpy(din, &tmpdin, rxcount); + rxcount = 0; + } + debugX(2, "*** spi_xfer: ... %08x read\n", tmpdin); + debugX(3, "spi_xfer: rxcount %08X, txcount %08X\n", + rxcount, txcount); + espi->event |= ESPI_EV_RNE; + } + + } + + /* clear the RXCNT and TXCNT */ + espi->mode &= ~ESPI_MODE_EN; + espi->mode |= ESPI_MODE_EN; + + return 0; +} + +void spi_free_slave(struct spi_slave *slave) +{ + free((struct espi_slave *)slave); +} + +void spi_init(void) +{ + +} + +int spi_claim_bus(struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + +} + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < ESPI_MAX_CS_NUM; +} + +void spi_cs_activate(struct spi_slave *slave) +{ + +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + +} diff --git a/include/fsl_espi.h b/include/fsl_espi.h new file mode 100644 index 0000000..a8d6035 --- /dev/null +++ b/include/fsl_espi.h @@ -0,0 +1,50 @@ +/* + * Include header for Freescale eSPI controller + * + * Copyright 2010 Locata Corporation Pty. Ltd. + * Can Aydin can.aydin(a)locatacorp.com + * + * Adapted from Freescale ltib code by Mingkai Hu (Mingkai.hu(a)freescale.com) + * Copyright 2009 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_ESPI_H__ +#define __FSL_ESPI_H__ + +#define ESPI_MAX_CS_NUM 4 + +#define ESPI_MAX_TRANLEN 0x10000 +#define ESPI_MAX_CHARSIZE 16 + +/* TODO: Add support for character sizes other than 8-bits */ +#define ESPI_CHARSIZE 8 + +#define ESPI_EV_TNF (1 << 8) /* Tx fifo not full */ +#define ESPI_EV_RNE (1 << 9) /* Rx fifo not empty */ +#define ESPI_EV_DONE (1 << 14) /* Transfer Complete */ +#define ESPI_EV_GET_TXCNT(spie) (((spie) >> 16) & 0x3F) /* Tx count */ +#define ESPI_EV_GET_RXCNT(spie) (((spie) >> 24) & 0x3F) /* Rx count */ + +#define ESPI_MODE_EN (1 << 31) /* Enable interface */ +#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ +#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ + +#define ESPI_COM_CS(x) ((x) << 30) +#define ESPI_COM_TRANLEN(x) (((x)-1) << 0) + +#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31) +#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30) +#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29) +#define ESPI_CSMODE_DIV16 (1 << 28) +#define ESPI_CSMODE_PM(x) ((x) << 24) +#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20) +#define ESPI_CSMODE_LEN(x) (((x)-1) << 16) +#define ESPI_CSMODE_CSBEF(x) ((x) << 12) +#define ESPI_CSMODE_CSAFT(x) ((x) << 8) +#define ESPI_CSMODE_CSCG(x) ((x) << 3) + +#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \ + ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \ + ESPI_CSMODE_CSCG(1)) + +#endif /* __FSL_ESPI_H__ */ -- 1.7.0.4

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[U-Boot] ppc4xx:tftp error
by Tim Rachman 25 Oct '10

25 Oct '10

Dear ALL I have a problem in tftp on a custom board using ppc440EP processor. U-boot-2009-11 has been ported on it, using amcc/bamboo BSP as base. When i get a sample file using tftp command, some bytes has changed . I changed my tftp server, and fully tested ddr sdram. They were OK. So i tested the u-boot tftp client. I monitored *(hw_p->rx[user_index].data_ptr) data in ppc_4xx_eth_rx() function in \driver\net\4xx_enet.c , and data was incorrect too at this stage. Do you have any suggestion about next step of debugging and the error source? Thanks in advance. Tim Rachman

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[U-Boot] [PATCH v3] [NEXT] da830: fixup ARM relocation support
by Nick Thompson 25 Oct '10

25 Oct '10

Fixes build breakage in da830evm after commit 97003756249bd790910417eb66f0039bbf06a02c "da8xx: fixup ARM relocation support" The da8xx fixup commit changed da830/da850 common code to make relocation work in da850, but didn't add the required defines to da830evm_config.h resulting in build failure in the common code. This patch adds those defines for da830, but makes no sense without also referring to the commit mentioned above. Signed-off-by: Nick Thompson <nick.thompson(a)ge.com> Reviewed-by: Ben Gardiner <bengardiner(a)nanometrics.ca> --- Changes since v1: removed CONFIG_SKIP_RELOCATE_UBOOT Changes since v2: removed "#undef CONFIG_SYS_ARM_WITHOUT_RELOC" as it is not defined in the first place. include/configs/da830evm.h | 11 ++++++++--- 1 files changed, 8 insertions(+), 3 deletions(-) diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h index 160ece2..b87e90c 100644 --- a/include/configs/da830evm.h +++ b/include/configs/da830evm.h @@ -41,15 +41,13 @@ #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ /* * Memory Info */ #define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ -#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ -#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ +#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Start */ #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 /* memtest start addr */ #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 16*1024*1024) /* 16MB test */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ @@ -281,4 +279,11 @@ "mtdparts=davinci_nand.1:" PART_BOOT PART_PARAMS PART_KERNEL PART_REST #endif +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ + +/* additions for new relocation code, must be added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 0x1000 - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ -- 1.7.0.4

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[U-Boot] [PATCH] arm1176: fix relocation
by Darius Augulis 25 Oct '10

25 Oct '10

Fix relocation code for arm1176, do it like other ARM CPU's are doing. Tested only with CONFIG_SKIP_RELOCATE_UBOOT defined and using nand_spl (booting from nand). Test done on s3c6410 based board (not yet supported in main line). Signed-off-by: Darius Augulis <augulis.darius(a)gmail.com> --- arch/arm/cpu/arm1176/start.S | 139 +++++++++++++++++++++++---------------- arch/arm/cpu/arm1176/u-boot.lds | 15 +++- 2 files changed, 94 insertions(+), 60 deletions(-) diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index 24e5bf4..0d733f7 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -115,44 +115,52 @@ _armboot_start: /* * These are defined in the board-specific linker script. + * Subtracting _start from them lets the linker put their + * relative position in the executable instead of leaving + * them null. */ -.globl _bss_start -_bss_start: - .word __bss_start -.globl _bss_end -_bss_end: - .word _end +.globl _bss_start_ofs +_bss_start_ofs: + .word __bss_start - _start -#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) -/* IRQ stack memory (calculated at run-time) + 8 bytes */ -.globl IRQ_STACK_START_IN -IRQ_STACK_START_IN: - .word 0x0badc0de +.globl _bss_end_ofs +_bss_end_ofs: + .word _end - _start + +.globl _datarel_start_ofs +_datarel_start_ofs: + .word __datarel_start - _start -.globl _datarel_start -_datarel_start: - .word __datarel_start +.globl _datarelrolocal_start_ofs +_datarelrolocal_start_ofs: + .word __datarelrolocal_start - _start -.globl _datarelrolocal_start -_datarelrolocal_start: - .word __datarelrolocal_start +.globl _datarellocal_start_ofs +_datarellocal_start_ofs: + .word __datarellocal_start - _start -.globl _datarellocal_start -_datarellocal_start: - .word __datarellocal_start +.globl _datarelro_start_ofs +_datarelro_start_ofs: + .word __datarelro_start - _start -.globl _datarelro_start -_datarelro_start: - .word __datarelro_start +.globl _rel_dyn_start_ofs +_rel_dyn_start_ofs: + .word __rel_dyn_start - _start -.globl _got_start -_got_start: - .word __got_start +.globl _rel_dyn_end_ofs +_rel_dyn_end_ofs: + .word __rel_dyn_end - _start -.globl _got_end -_got_end: - .word __got_end +.globl _dynsym_start_ofs +_dynsym_start_ofs: + .word __dynsym_start - _start + +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de /* * the actual reset code @@ -274,9 +282,8 @@ stack_setup: adr r0, _start ldr r2, _TEXT_BASE - ldr r3, _bss_start - sub r2, r3, r2 /* r2 <- size of armboot */ - add r2, r0, r2 /* r2 <- source end address */ + ldr r3, _bss_start_ofs + add r2, r0, r3 /* r2 <- source end address */ cmp r0, r6 beq clear_bss @@ -288,24 +295,44 @@ copy_loop: blo copy_loop #ifndef CONFIG_PRELOADER - /* fix got entries */ - ldr r1, _TEXT_BASE /* Text base */ - mov r0, r7 /* reloc addr */ - ldr r2, _got_start /* addr in Flash */ - ldr r3, _got_end /* addr in Flash */ - sub r3, r3, r1 - add r3, r3, r0 - sub r2, r2, r1 - add r2, r2, r0 - + /* + * fix .rel.dyn relocations + */ + ldr r0, _TEXT_BASE /* r0 <- Text base */ + sub r9, r7, r0 /* r9 <- relocation offset */ + ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */ + add r10, r10, r0 /* r10 <- sym table in FLASH */ + ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */ + add r2, r2, r0 /* r2 <- rel dyn start in FLASH */ + ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */ + add r3, r3, r0 /* r3 <- rel dyn end in FLASH */ fixloop: - ldr r4, [r2] - sub r4, r4, r1 - add r4, r4, r0 - str r4, [r2] - add r2, r2, #4 + ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */ + add r0, r9 /* r0 <- location to fix up in RAM */ + ldr r1, [r2, #4] + and r8, r1, #0xff + cmp r8, #23 /* relative fixup? */ + beq fixrel + cmp r8, #2 /* absolute fixup? */ + beq fixabs + /* ignore unknown type of fixup */ + b fixnext +fixabs: + /* absolute fix: set location to (offset) symbol value */ + mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */ + add r1, r10, r1 /* r1 <- address of symbol in table */ + ldr r1, [r1, #4] /* r1 <- symbol value */ + add r1, r9 /* r1 <- relocated sym addr */ + b fixnext +fixrel: + /* relative fix: increase location by offset */ + ldr r1, [r0] + add r1, r1, r9 +fixnext: + str r1, [r0] + add r2, r2, #8 /* each rel.dyn entry is 8 bytes */ cmp r2, r3 - bne fixloop + ble fixloop #endif #endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ @@ -349,13 +376,11 @@ skip_hw_init: clear_bss: #ifndef CONFIG_PRELOADER - ldr r0, _bss_start - ldr r1, _bss_end + ldr r0, _bss_start_ofs + ldr r1, _bss_end_ofs ldr r3, _TEXT_BASE /* Text base */ mov r4, r7 /* reloc addr */ - sub r0, r0, r3 add r0, r0, r4 - sub r1, r1, r3 add r1, r1, r4 mov r2, #0x00000000 /* clear */ @@ -377,10 +402,9 @@ clbss_l:str r2, [r0] /* clear loop... */ _nand_boot: .word nand_boot #else - ldr r0, _TEXT_BASE - ldr r2, _board_init_r - sub r2, r2, r0 - add r2, r2, r7 /* position from board_init_r in RAM */ + ldr r0, _board_init_r_ofs + adr r1, _start + add r2, r0, r1 /* setup parameters for board_init_r */ mov r0, r5 /* gd_t */ mov r1, r7 /* dest_addr */ @@ -388,7 +412,8 @@ _nand_boot: .word nand_boot mov lr, r2 mov pc, lr -_board_init_r: .word board_init_r +_board_init_r_ofs: + .word board_init_r - _start #endif #else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ diff --git a/arch/arm/cpu/arm1176/u-boot.lds b/arch/arm/cpu/arm1176/u-boot.lds index fa640ee..d9ed954 100644 --- a/arch/arm/cpu/arm1176/u-boot.lds +++ b/arch/arm/cpu/arm1176/u-boot.lds @@ -51,11 +51,14 @@ SECTIONS *(.data.rel.ro) } - __got_start = .; . = ALIGN(4); - .got : { *(.got) } + __rel_dyn_start = .; + .rel.dyn : { *(.rel.dyn) } + __rel_dyn_end = .; + + __dynsym_start = .; + .dynsym : { *(.dynsym) } - __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } @@ -65,4 +68,10 @@ SECTIONS __bss_start = .; .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } _end = .; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } }

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[U-Boot] NetConsole and network API
by Stefano Babic 25 Oct '10

25 Oct '10

Hi all, I have seen an issue using netconsole and I am asking myself if there is a problem in the actual concept of a network interface in u-boot. I admit soon I have not used a "normal" network controller, but I ran NetConsole on Ethernet over USB. However, I have checked with other network drivers (smc9111.c, for example) and I can imagine there are similar problems. The assumption we have is that any network command is atomic. Any network command initializes the interface, uses it (eth_send(), ..) and at the end deactivates the interface (eth_halt()). This makes an application as netconsole simply unusable, because it is not thinkable that after any message the interface is put in a down state. Not only, it makes impossible to use network commands as TFTP inside netconsole, because they try to initialize the same interface that netconsole uses. Of course, in my case things get even worse. After any network command, the eth_halt() callback is called, making the interface disappearing on the host side. And any time the host starts to enumerate again the interface, setting MAC, etc..... Well, I have fixed this issue avoiding the interface is initialized or stopped after each command, but it seems this is a general problem. I see in other drivers that the phy is set or stop after each command, and this should generate the same problems I noted with USB. My main question to the ML is, independently from the particular problem on my target, if we should change the actual concept. For example, if we provide to stop all devices only before booting an OS, but leaving them alive after the first initialization. I understand that this generate other issues (as u-boot cannot recognize that a cable was removed and inserted again), but it makes the system usable in other circumstances. Any thought about this ? Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot] [PATCH] ARMV7: OMAP: I2C driver: Fix bug found in 37XX testing
by Steve Sakoman 25 Oct '10

25 Oct '10

On OMAP36/37XX the standard on chip pullups are not sufficient to ensure proper i2c operation without external pullups or switching to high speed mode and enabling special on chip pullups. This is an issue for Beagle xM, which does not have external pullups on the expansion board i2c lines. The issue manifests itself as an AL (arbitration lost) error when probing for a non-existent device (i.e. on a Beagle xM with no expansion boards attached). This issue does not occur on expansion boards that include pullups or on Overo 37XX COM's since they include pull-ups. This patch fixes the issue by checking for the AL bit in the i2c_probe function. Signed-off-by: Steve Sakoman <steve.sakoman(a)linaro.org> --- diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a72d1a1..fab49fd 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -329,7 +329,7 @@ int i2c_probe (uchar chip) while (1) { status = wait_for_pin(); - if (status == 0) { + if (status == 0 || status & I2C_STAT_AL) { res = 1; goto probe_exit; }

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[U-Boot] kirkwood: commands not found after elf_reloc merge
by Eric Cooper 25 Oct '10

25 Oct '10

After rebasing my dockstar patches on master (fff6ec3), none of the top level commands are found: U-Boot 2010.09-dirty (Oct 24 2010 - 21:04:07) Seagate FreeAgent DockStar U-Boot code: 00600000 -> 00659F44 BSS: -> 0069FF20 SoC: Kirkwood 88F6281_A0 monitor len: 0009FF20 ramsize: 08000000 TLB table at: 07ff0000 Top of RAM usable for U-Boot at: 07ff0000 Reserving 639k for U-Boot at: 07f50000 Reserving 1152k for malloc() at: 07e30000 Reserving 48 Bytes for Board Info at: 07e2ffd0 Reserving 92 Bytes for Global Data at: 07e2ff74 New Stack Pointer is: 07e2ff70 RAM Configuration: Bank #0: 00000000 128 MiB Bank #1: 00000000 0 Bytes Bank #2: 00000000 0 Bytes Bank #3: 00000000 0 Bytes relocation Offset is: 07950000 monitor flash len: 00059F44 Now running in RAM - U-Boot at: 07f50000 NAND: 256 MiB In: serial Out: serial Err: serial Net: egiga0 Reset Ethernet PHY 88E1116 Initialized on egiga0 Hit any key to stop autoboot: 3 2 0 DockStar> version Unknown command 'version' - try 'help' DockStar> help Unknown command 'help' - try 'help' DockStar> The previous version, based on 1ba91ba, works fine: U-Boot 2010.09-dirty (Oct 24 2010 - 21:16:34) Seagate FreeAgent DockStar U-Boot code: 00600000 -> 00658184 BSS: -> 0069E000 SoC: Kirkwood 88F6281_A0 monitor len: 0009E000 ramsize: 08000000 TLB table at: 07ff0000 Top of RAM usable for U-Boot at: 07ff0000 Reserving 632k for U-Boot at: 07f52000 Reserving 1152k for malloc() at: 07e32000 Reserving 48 Bytes for Board Info at: 07e31fd0 Reserving 92 Bytes for Global Data at: 07e31f74 New Stack Pointer is: 07e31f70 RAM Configuration: Bank #0: 00000000 128 MiB Bank #1: 00000000 0 Bytes Bank #2: 00000000 0 Bytes Bank #3: 00000000 0 Bytes relocation Offset is: 07952000 monitor flash len: 00058184 Now running in RAM - U-Boot at: 07f52000 NAND: 256 MiB In: serial Out: serial Err: serial Net: egiga0 Reset Ethernet PHY 88E1116 Initialized on egiga0 Hit any key to stop autoboot: 3 2 0 Marvell>> version U-Boot 2010.09-dirty (Oct 24 2010 - 21:16:34) Seagate FreeAgent DockStar Marvell>> I suspect something related to the recent merge with the elf_reloc branch. Does this problem occur on anyone else's kirkwood board since then? -- Eric Cooper e c c @ c m u . e d u

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[U-Boot] [PATCH v2] Freescale 85xx/P1/P2 eSPI controller driver
by Can Aydin 25 Oct '10

25 Oct '10

Driver for the Freescale eSPI controller found in 85xx, P1/P2 and P4xx SoCs. Signed-off-by: Can Aydin <can.aydin(a)locatacorp.com> --- Changes for v2: - Coding style cleanup - Removed modifications to common code drivers/spi/Makefile | 1 + drivers/spi/fsl_espi.c | 256 +++++++++++++++++++++++++++++++++++++++++++ include/configs/P1_P2_RDB.h | 7 + include/fsl_espi.h | 50 +++++++++ 4 files changed, 314 insertions(+), 0 deletions(-) create mode 100644 drivers/spi/fsl_espi.c create mode 100644 include/fsl_espi.h diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index dfcbb8b..1aaa8e7 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -31,6 +31,7 @@ COBJS-$(CONFIG_ATMEL_SPI) += atmel_spi.o COBJS-$(CONFIG_BFIN_SPI) += bfin_spi.o COBJS-$(CONFIG_CF_SPI) += cf_spi.o COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o +COBJS-$(CONFIG_FSL_ESPI) += fsl_espi.o COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c new file mode 100644 index 0000000..4adc98d --- /dev/null +++ b/drivers/spi/fsl_espi.c @@ -0,0 +1,256 @@ +/* + * Freescale eSPI controller driver. + * + * Copyright 2010 Locata Corporation Pty. Ltd. + * Author: Can Aydin can.aydin(a)locatacorp.com + * Collab: Clayton Gumbrell clayton.gumbrell(a)locatacorp.com + * + * Adapted from Freescale ltib code by Mingkai Hu (Mingkai.hu(a)freescale.com) + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <malloc.h> +#include <spi.h> +#include <fsl_espi.h> +#include <asm/immap_85xx.h> + +struct spi_slave *spi_setup_slave (unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + volatile ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + struct spi_slave *slave; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned char pm = 0; + int i; + + if (!spi_cs_is_valid (bus, cs)) + return NULL; + + slave = malloc (sizeof (struct spi_slave)); + if (!slave) + return NULL; + + slave->bus = bus; + slave->cs = cs; + + /* Enable eSPI interface */ + espi->mode = ESPI_MODE_RXTHR (3) | ESPI_MODE_TXTHR (4) | ESPI_MODE_EN; + + espi->event = 0xffffffff; /* Clear all eSPI events */ + espi->mask = 0x00000000; /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + espi->csmode[i] = ESPI_CSMODE_INIT_VAL; + + espi->csmode[cs] &= + ~(ESPI_CSMODE_PM (0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST + | ESPI_CSMODE_LEN (ESPI_MAX_CHARSIZE)); + + /* Set eSPI BRG clock source */ + get_sys_info (&sysinfo); + spibrg = sysinfo.freqSystemBus / 2; + if ((spibrg / max_hz) > 32) { + espi->csmode[cs] |= ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug ("Requested speed is too low: %d Hz" + " %u Hz is used.\n", max_hz, + (uint) (spibrg / (32 * 16))); + } + } else + pm = spibrg / (max_hz * 2); + if (pm) + pm--; + espi->csmode[cs] |= ESPI_CSMODE_PM (pm); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + espi->csmode[cs] |= ESPI_CSMODE_CP_BEGIN_EDGCLK; + if (mode & SPI_CPOL) + espi->csmode[cs] |= ESPI_CSMODE_CI_INACTIVEHIGH; + + /* Character bit order: msb first */ + espi->csmode[cs] |= ESPI_CSMODE_REV_MSB_FIRST; + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + espi->csmode[cs] |= ESPI_CSMODE_LEN (ESPI_CHARSIZE); + + return slave; +} + +static inline void write_u32_part (u32 * in, u32 * out, u8 size) +{ + int i; + u8 *ibyte = (u8 *) in; + u8 *obyte = (u8 *) out; + + for (i = 0; i < size; i++) { + obyte[i] = ibyte[i]; + } +} + +int spi_xfer (struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + volatile ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + u32 com; + u32 event; + u8 wordsize = 4; /* Fifo access registers are 32 bits */ + u32 tmpdout, tmpdin; + unsigned int len, rxcount, txcount; + + if (!(flags & (SPI_XFER_BEGIN | SPI_XFER_END))) { + debug ("spi_xfer: Segmented transfers not supported.\n"); + return 1; + } + + if (!bitlen) + return 0; + + len = bitlen / ESPI_CHARSIZE + ((bitlen % ESPI_CHARSIZE) ? 1 : 0); + + if (len > ESPI_MAX_TRANLEN) { + debug + ("spi_xfer: Transfer length (%u) too long, max is %u(0x%X)\n", + len, ESPI_MAX_TRANLEN, ESPI_MAX_TRANLEN); + return 1; + } + + rxcount = len; + txcount = len; + debug ("spi_xfer: slave %u:%u dout %08X(%08x) din %08X(%08x) len %u\n", + slave->bus, slave->cs, + *(uint *) dout, (uint) dout, *(uint *) din, (uint) din, len); + + /* Prepare eSPI transfer to slave cs with length len */ + com = 0; + com |= ESPI_COM_CS (slave->cs); + com |= ESPI_COM_TRANLEN (len); + espi->com = com; + + /* Clear all eSPI events and initiate new command */ + espi->event = 0xffffffff; + debugX (1, "spi_xfer: rxcount %08X, txcount %08X\n", rxcount, txcount); + while (rxcount) { + + event = espi->event; + debugX (4, "spi_xfer: SPIE 0x%08x\n", event); + debugX (3, "spi_xfer: SPIE (TXCNT): %u\n", + ESPI_EV_GET_TXCNT (event)); + if ((event & ESPI_EV_TNF) && (txcount)) { + /* Tx fifo not full and we still have stuff to send */ + if ((txcount >= wordsize) && + (ESPI_EV_GET_TXCNT (event) >= wordsize)) { + /* Have a full word and room to put it */ + tmpdout = *(u32 *) dout; + txcount -= wordsize; + dout += wordsize; + espi->tx = tmpdout; + } else if (ESPI_EV_GET_TXCNT (event) >= txcount) { + /* Less than a word left and room to put it */ + tmpdout = 0; + /* Avoid dout buffer read overflow */ + write_u32_part ((u32 *) dout, &tmpdout, + txcount); + //tmpdout = *(u32 *)dout; + espi->tx = tmpdout; + txcount = 0; + } + espi->event |= ESPI_EV_TNF; + debugX (2, "*** spi_xfer: ... %08x written\n", tmpdout); + debugX (3, "spi_xfer: rxcount %08X, txcount %08X\n", + rxcount, txcount); + } + + event = espi->event; + debugX (4, "spi_xfer: SPIE 0x%08x\n", event); + debugX (3, "spi_xfer: SPIE (RXCNT): %u\n", + ESPI_EV_GET_RXCNT (event)); + if (event & ESPI_EV_RNE) { /* Rx fifo has data */ + unsigned int count = ESPI_EV_GET_RXCNT (event); + if (count >= wordsize) { + /* Have a full word to read */ + tmpdin = espi->rx; + *(u32 *) din = tmpdin; + if ((rxcount -= wordsize) > 0) { + din += wordsize; + } + } else if (count >= rxcount) { + /* Less than a word left to read */ + tmpdin = espi->rx; + /* Avoid din buffer write overflow */ + write_u32_part (&tmpdin, (u32 *) din, rxcount); + //*(u32 *) din = tmpdin; + rxcount = 0; + } + debugX (2, "*** spi_xfer: ... %08x read\n", tmpdin); + debugX (3, "spi_xfer: rxcount %08X, txcount %08X\n", + rxcount, txcount); + espi->event |= ESPI_EV_RNE; + } + + } + + /* clear the RXCNT and TXCNT */ + espi->mode &= ~ESPI_MODE_EN; + espi->mode |= ESPI_MODE_EN; + + return 0; +} + +void spi_free_slave (struct spi_slave *slave) +{ + free ((struct espi_slave *)slave); +} + +void spi_init (void) +{ + +} + +int spi_claim_bus (struct spi_slave *slave) +{ + return 0; +} + +void spi_release_bus (struct spi_slave *slave) +{ + +} + +int spi_cs_is_valid (unsigned int bus, unsigned int cs) +{ + return bus == 0 && cs < ESPI_MAX_CS_NUM; +} + +void spi_cs_activate (struct spi_slave *slave) +{ + +} + +void spi_cs_deactivate (struct spi_slave *slave) +{ + +} diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index cff0ed3..33f1b1e 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -172,6 +172,13 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ /* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI +#define CONFIG_HARD_SPI +#define CONFIG_CMD_SPI + +/* * Local Bus Definitions */ #define CONFIG_SYS_FLASH_BASE 0xef000000 /* start of FLASH 16M */ diff --git a/include/fsl_espi.h b/include/fsl_espi.h new file mode 100644 index 0000000..a8d6035 --- /dev/null +++ b/include/fsl_espi.h @@ -0,0 +1,50 @@ +/* + * Include header for Freescale eSPI controller + * + * Copyright 2010 Locata Corporation Pty. Ltd. + * Can Aydin can.aydin(a)locatacorp.com + * + * Adapted from Freescale ltib code by Mingkai Hu (Mingkai.hu(a)freescale.com) + * Copyright 2009 Freescale Semiconductor, Inc. + */ + +#ifndef __FSL_ESPI_H__ +#define __FSL_ESPI_H__ + +#define ESPI_MAX_CS_NUM 4 + +#define ESPI_MAX_TRANLEN 0x10000 +#define ESPI_MAX_CHARSIZE 16 + +/* TODO: Add support for character sizes other than 8-bits */ +#define ESPI_CHARSIZE 8 + +#define ESPI_EV_TNF (1 << 8) /* Tx fifo not full */ +#define ESPI_EV_RNE (1 << 9) /* Rx fifo not empty */ +#define ESPI_EV_DONE (1 << 14) /* Transfer Complete */ +#define ESPI_EV_GET_TXCNT(spie) (((spie) >> 16) & 0x3F) /* Tx count */ +#define ESPI_EV_GET_RXCNT(spie) (((spie) >> 24) & 0x3F) /* Rx count */ + +#define ESPI_MODE_EN (1 << 31) /* Enable interface */ +#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */ +#define ESPI_MODE_RXTHR(x) ((x) << 0) /* Rx FIFO threshold */ + +#define ESPI_COM_CS(x) ((x) << 30) +#define ESPI_COM_TRANLEN(x) (((x)-1) << 0) + +#define ESPI_CSMODE_CI_INACTIVEHIGH (1 << 31) +#define ESPI_CSMODE_CP_BEGIN_EDGCLK (1 << 30) +#define ESPI_CSMODE_REV_MSB_FIRST (1 << 29) +#define ESPI_CSMODE_DIV16 (1 << 28) +#define ESPI_CSMODE_PM(x) ((x) << 24) +#define ESPI_CSMODE_POL_ASSERTED_LOW (1 << 20) +#define ESPI_CSMODE_LEN(x) (((x)-1) << 16) +#define ESPI_CSMODE_CSBEF(x) ((x) << 12) +#define ESPI_CSMODE_CSAFT(x) ((x) << 8) +#define ESPI_CSMODE_CSCG(x) ((x) << 3) + +#define ESPI_CSMODE_INIT_VAL (ESPI_CSMODE_POL_ASSERTED_LOW | \ + ESPI_CSMODE_CSBEF(0) | ESPI_CSMODE_CSAFT(0) | \ + ESPI_CSMODE_CSCG(1)) + +#endif /* __FSL_ESPI_H__ */ -- 1.7.0.4

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