September 2009 - U-Boot

[U-Boot] [PATCH v2] Reset i2c slave devices during init on mpc5xxx cpus
by Eric Millbrandt 06 Sep '09

06 Sep '09

Reset any i2c devices that may have been interrupted during a system reset. Normally this would be accomplished by clocking the line until SCL and SDA are released and then sending a start condtiion (From an Atmel datasheet). There is no direct access to the i2c pins so instead create start commands through the i2c interface. Send a start command then delay for the SDA Hold time, repeat this by disabling/enabling the bus a total of 9 times. Signed-off-by: Eric Millbrandt <emillbrandt(a)dekaresearch.com> --- changes since v1 - Fixed compiler warning README | 7 ++++++ cpu/mpc5xxx/i2c.c | 49 ++++++++++++++++++++++++++++++++++++++++++ include/configs/galaxy5200.h | 1 + 3 files changed, 57 insertions(+), 0 deletions(-) diff --git a/README b/README index 246ae2b..6ccb2fe 100644 --- a/README +++ b/README @@ -1366,6 +1366,13 @@ The following options need to be configured: therefore be cleared to 0 (See, eg, MPC823e User's Manual p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0. + CONFIG_SYS_I2C_INIT_MPC5XXX + + When a board is reset during an i2c bus transfer + chips might think that the current transfer is still + in progress. Reset the slave devices by sending start + commands until the slave device responds. + That's all that's required for CONFIG_HARD_I2C. If you use the software i2c interface (CONFIG_SOFT_I2C) diff --git a/cpu/mpc5xxx/i2c.c b/cpu/mpc5xxx/i2c.c index 2341932..4f7f716 100644 --- a/cpu/mpc5xxx/i2c.c +++ b/cpu/mpc5xxx/i2c.c @@ -207,6 +207,52 @@ static int receive_bytes(uchar chip, char *buf, int len) return 0; } +#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) + +#define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3)) +#define FDR432(x) (u8) ((x & 0x1C) >> 2) +/* + * Reset any i2c devices that may have been interrupted during a system reset. + * Normally this would be accomplished by clocking the line until SCL and SDA + * are released and then sending a start condtiion (From an Atmel datasheet). + * There is no direct access to the i2c pins so instead create start commands + * through the i2c interface. Send a start command then delay for the SDA Hold + * time, repeat this by disabling/enabling the bus a total of 9 times. + */ +static void send_reset(void) +{ + struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE; + int i; + u32 delay; + u8 fdr; + int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2}; + struct mpc5xxx_i2c_tap scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} + }; + + fdr = (u8)mpc_reg_in(&regs->mfdr); + + delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \ + scltap[FDR432(fdr)].tap2tap) + 3; + + for (i = 0; i < 9; i++) { + mpc_reg_out(&regs->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK); + udelay(delay); + mpc_reg_out(&regs->mcr, 0, I2C_INIT_MASK); + udelay(delay); + } + + mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK); +} +#endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */ + /**************** I2C API ****************/ void i2c_init(int speed, int saddr) @@ -225,6 +271,9 @@ void i2c_init(int speed, int saddr) mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK); mpc_reg_out(&regs->msr, 0, I2C_IF); +#if defined(CONFIG_SYS_I2C_INIT_MPC5XXX) + send_reset(); +#endif return; } diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h index 8d530d8..2ba5f0f 100644 --- a/include/configs/galaxy5200.h +++ b/include/configs/galaxy5200.h @@ -110,6 +110,7 @@ #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ #define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */ /* * EEPROM CAT24WC32 configuration -- 1.6.3.1

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[U-Boot] [PATCH][v2] ppc/85xx,86xx: Handling Unknown SOC version
by Poonam Aggrwal 05 Sep '09

05 Sep '09

Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- applies on git.am.freescale.net/mirrors/u-boot.git Changes over v1: Incoroprated Wolfgang's comments cpu/mpc85xx/cpu.c | 10 +++------- cpu/mpc86xx/cpu.c | 5 +---- cpu/mpc8xxx/cpu.c | 5 +++-- include/asm-ppc/processor.h | 2 ++ 4 files changed, 9 insertions(+), 13 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 6be98dc..63bdb6f 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -69,13 +69,9 @@ int checkcpu (void) cpu = gd->cpu; - if (cpu->name) { - puts(cpu->name); - if (IS_E_PROCESSOR(svr)) - puts("E"); - } else { - puts("Unknown"); - } + puts(cpu->name); + if (IS_E_PROCESSOR(svr)) + puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index 04409ce..e97ab6d 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -65,10 +65,7 @@ checkcpu(void) cpu = gd->cpu; - if (cpu->name) - puts(cpu->name); - else - puts("Unknown"); + puts(cpu->name); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); puts("Core: "); diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index 339f6d9..c73ac3c 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -79,6 +79,8 @@ struct cpu_type cpu_type_list [] = { #endif }; +struct cpu_type cpu_type_unknown = CPU_TYPE_ENTRY(Unknown, Unknown, 1); + struct cpu_type *identify_cpu(u32 ver) { int i; @@ -86,8 +88,7 @@ struct cpu_type *identify_cpu(u32 ver) if (cpu_type_list[i].soc_ver == ver) return &cpu_type_list[i]; } - - return NULL; + return &cpu_type_unknown; } int cpu_numcores() { diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index dcaf8c0..9fd9509 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1022,6 +1022,8 @@ #define SVR_8641 0x809000 #define SVR_8641D 0x809001 +#define SVR_Unknown 0xFFFFFF + #define _GLOBAL(n)\ .globl n;\ n: -- 1.5.6.5

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[U-Boot] [PATCH][v1] ppc/85x/86xxx: Device tree fixup for number of cores
by Poonam Aggrwal 05 Sep '09

05 Sep '09

Fixing the number of cores in the device tree based on the actual number of cores on the system. With this same device tree image can be used for dual core and single core members of otherwise exactly same SOC. For example P2020RDB and P2010RDB P1020RDB and P1011RDB Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- applies on git.am.freescale.net/mirrors/u-boot.git cpu/mpc85xx/fdt.c | 2 + cpu/mpc86xx/fdt.c | 3 ++ cpu/mpc8xxx/Makefile | 1 + cpu/mpc8xxx/fdt.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 61 insertions(+), 0 deletions(-) create mode 100644 cpu/mpc8xxx/fdt.c diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index a692529..4eef170 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -31,6 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; extern void ft_qe_setup(void *blob); +extern void ft_fixup_num_cores(void *blob); #ifdef CONFIG_MP #include "mp.h" @@ -324,6 +325,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); #endif + ft_fixup_num_cores(blob); ft_fixup_cache(blob); } diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index a36ee30..51f3f4c 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -13,6 +13,8 @@ DECLARE_GLOBAL_DATA_PTR; +extern void ft_fixup_num_cores(void *blob); + void ft_cpu_setup(void *blob, bd_t *bd) { #ifdef CONFIG_MP @@ -54,4 +56,5 @@ void ft_cpu_setup(void *blob, bd_t *bd) if (off < 0) printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); #endif + ft_fixup_num_cores(blob); } diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile index 430a75f..9817d1b 100644 --- a/cpu/mpc8xxx/Makefile +++ b/cpu/mpc8xxx/Makefile @@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a COBJS-y += cpu.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/mpc8xxx/fdt.c b/cpu/mpc8xxx/fdt.c new file mode 100644 index 0000000..0777231 --- /dev/null +++ b/cpu/mpc8xxx/fdt.c @@ -0,0 +1,55 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * This file is derived from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c. + * Basically this file contains cpu specific common code for 85xx/86xx + * processors. + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <libfdt.h> +#include <fdt_support.h> + +void ft_fixup_num_cores(void *blob) { + int i, off, num_cores, del_cores; + + del_cores = 0; + num_cores = cpu_numcores(); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + /* if we find a cpu node outside of what we expect delete it + * and reset the offset back to the start since we can't + * trust the offsets anymore + */ + if (*reg > num_cores-1) { + fdt_del_node(blob, off); + del_cores++; + off = -1; + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + debug ("%x core system found\n", num_cores); + debug ("deleted %d extra core entry entries from device tree\n", + del_cores); +} -- 1.5.6.5

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[U-Boot] [PATCH][v1] ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().
by Poonam Aggrwal 05 Sep '09

05 Sep '09

While in probecpu() UART is still not initialized. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Acked-by: Kumar Gala <galak(a)kernel.crashing.org> --- applies on git.am.freescale.net/mirrors/u-boot.git cpu/mpc85xx/cpu.c | 4 ++++ cpu/mpc86xx/cpu.c | 6 ++++++ cpu/mpc8xxx/cpu.c | 6 ------ 3 files changed, 10 insertions(+), 6 deletions(-) diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 63bdb6f..3b89f61 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -61,6 +61,10 @@ int checkcpu (void) minor = SVR_MIN(svr); if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index e97ab6d..f7e012d 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -61,6 +61,12 @@ checkcpu(void) major = SVR_MAJ(svr); minor = SVR_MIN(svr); + if (cpu_numcores() > 1) { +#ifndef CONFIG_MP + puts("Unicore software on multiprocessor system!!\n" + "To enable mutlticore build define CONFIG_MP\n"); +#endif + } puts("CPU: "); cpu = gd->cpu; diff --git a/cpu/mpc8xxx/cpu.c b/cpu/mpc8xxx/cpu.c index c73ac3c..00791e1 100644 --- a/cpu/mpc8xxx/cpu.c +++ b/cpu/mpc8xxx/cpu.c @@ -107,12 +107,6 @@ int probecpu (void) gd->cpu = identify_cpu(ver); -#ifndef CONFIG_MP - if (cpu_numcores() > 1) { - puts("Unicore software on multiprocessor system!!\n" - "To enable mutlticore build define CONFIG_MP\n"); - } -#endif return 0; } -- 1.5.6.5

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[U-Boot] [PATCH 2/2] fsl: add register read-back to set_law()
by Timur Tabi 05 Sep '09

05 Sep '09

After programming a new LAW, we should read-back the LAWAR register so that we sync the writes. Otherwise, code that attempts to use the new LAW-mapped memory might fail. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- drivers/misc/fsl_law.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/misc/fsl_law.c b/drivers/misc/fsl_law.c index 147fe0a..7bdd355 100644 --- a/drivers/misc/fsl_law.c +++ b/drivers/misc/fsl_law.c @@ -58,7 +58,8 @@ void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id) out_be32(lawbar, addr >> 12); out_be32(lawar, LAWAR_EN | ((u32)id << 20) | (u32)sz); - return ; + /* Read back so that we sync the writes */ + in_be32(lawar); } int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id) -- 1.6.0.6

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[U-Boot] [PATCH] ppc/8xxx: Refactor code to determine if PCI is enabled & agent/host
by Kumar Gala 05 Sep '09

05 Sep '09

Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- board/atum8548/atum8548.c | 6 +- board/freescale/mpc8536ds/mpc8536ds.c | 15 +- board/freescale/mpc8544ds/mpc8544ds.c | 14 +- board/freescale/mpc8548cds/mpc8548cds.c | 6 +- board/freescale/mpc8568mds/mpc8568mds.c | 4 +- board/freescale/mpc8569mds/mpc8569mds.c | 4 +- board/freescale/mpc8572ds/mpc8572ds.c | 17 +-- board/freescale/mpc8610hpcd/mpc8610hpcd.c | 12 +- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 5 +- board/freescale/p1_p2_rdb/pci.c | 10 +- board/freescale/p2020ds/p2020ds.c | 14 +- board/sbc8548/sbc8548.c | 6 +- board/tqc/tqm85xx/tqm85xx.c | 8 +- cpu/mpc8xxx/Makefile | 1 + cpu/mpc8xxx/pci_cfg.c | 225 +++++++++++++++++++++++++++++ include/asm-ppc/fsl_pci.h | 5 + 16 files changed, 284 insertions(+), 68 deletions(-) create mode 100644 cpu/mpc8xxx/pci_cfg.c diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 85c0adc..a220ad4 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -202,8 +202,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel & 6; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -262,7 +262,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; - uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = 33333000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index 032d732..da72916 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -216,8 +216,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 1); - int pcie_configured = (io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -265,9 +265,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = (io_sel == 2 || io_sel == 3 - || io_sel == 5 || io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -323,8 +322,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 3); - int pcie_configured = (io_sel == 5 || io_sel == 7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -381,7 +380,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; - uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = 1; uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 5a47d0a..244a197 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -125,8 +125,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 1); - int pcie_configured = io_sel >= 6; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -188,8 +188,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 5); - int pcie_configured = io_sel >= 2; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -246,8 +246,8 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 3); - int pcie_configured = io_sel >= 4; + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -306,7 +306,7 @@ pci_init_board(void) struct pci_controller *hose = &pci1_hose; struct pci_region *r = hose->regions; - uint pci_agent = (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI, host_agent); uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */ uint pci_32 = 1; uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 9df5f82..80de6f8 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -283,7 +283,7 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ @@ -361,10 +361,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index fe505b0..e2dc69e 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -422,10 +422,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index 63c21dd..cc88731 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -331,9 +331,9 @@ pci_init_board(void) pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; - pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); r = hose->regions; - pcie_configured = io_sel >= 1; + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 7da70fe..c69934c 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -186,9 +186,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; struct pci_controller *hose = &pcie3_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 3) || - (host_agent == 5) || (host_agent == 6); - int pcie_configured = (io_sel == 0x7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); struct pci_region *r = hose->regions; u32 temp32; @@ -252,9 +251,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; struct pci_controller *hose = &pcie2_hose; - int pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - int pcie_configured = (io_sel == 0x3) || (io_sel == 0x7); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ @@ -301,11 +299,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent <= 1) || (host_agent == 4) || - (host_agent == 5); - int pcie_configured = (io_sel == 0x2) || (io_sel == 0x3) || - (io_sel == 0x7) || (io_sel == 0xb) || - (io_sel == 0xc) || (io_sel == 0xf); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 45000d9..98111eb 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -248,9 +248,8 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_configured = (io_sel == 1) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 2) || - (host_agent == 5); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) { @@ -298,9 +297,8 @@ void pci_init_board(void) struct pci_controller *hose = &pcie2_hose; struct pci_region *r = hose->regions; - int pcie_configured = (io_sel == 0) || (io_sel == 4); - int pcie_ep = (host_agent == 0) || (host_agent == 1) || - (host_agent == 4); + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) { printf(" PCI-Express 2 connected to slot as %s" \ @@ -345,7 +343,7 @@ void pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - int pci_agent = (host_agent >= 4) && (host_agent <= 6); + int pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); struct pci_region *r = hose->regions; if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) { diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c index fab4fae..1a08afa 100644 --- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c +++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c @@ -155,15 +155,14 @@ void pci_init_board(void) uint devdisr = gur->devdisr; uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL) >> MPC8641_PORDEVSR_IO_SEL_SHIFT; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); #ifdef DEBUG uint host1_agent = (gur->porbmsr & MPC8641_PORBMSR_HA) >> MPC8641_PORBMSR_HA_SHIFT; uint pex1_agent = (host1_agent == 0) || (host1_agent == 1); #endif - if ((io_sel == 2 || io_sel == 3 || io_sel == 5 - || io_sel == 6 || io_sel == 7 || io_sel == 0xF) - && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { + if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) { debug("PCI-EXPRESS 1: %s \n", pex1_agent ? "Agent" : "Host"); debug("0x%08x=0x%08x ", &pci->pme_msg_det, pci->pme_msg_det); if (pci->pme_msg_det) { diff --git a/board/freescale/p1_p2_rdb/pci.c b/board/freescale/p1_p2_rdb/pci.c index 174a8a7..a3617d5 100644 --- a/board/freescale/p1_p2_rdb/pci.c +++ b/board/freescale/p1_p2_rdb/pci.c @@ -59,9 +59,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE2 SET_STD_PCIE_INFO(pci_info[num], 2); - pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - pcie_configured = (io_sel == 0xE); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE2 connected to Slot 1 as "); @@ -80,9 +79,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE1 SET_STD_PCIE_INFO(pci_info[num], 1); - pcie_ep = (host_agent <= 1) || (host_agent == 4) || - (host_agent == 5); - pcie_configured = (io_sel == 0xE); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ puts ("\n PCIE1 connected to Slot 2 as "); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 3fe72cd..7ad9be8 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -219,9 +219,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE2 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR; hose = &pcie2_hose; - pcie_ep = (host_agent == 2) || (host_agent == 4) || - (host_agent == 6) || (host_agent == 0); - pcie_configured = (io_sel == 0x2) || (io_sel == 0xe); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_2, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) { @@ -287,9 +286,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE3 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR; hose = &pcie3_hose; - pcie_ep = (host_agent == 0) || (host_agent == 3) || - (host_agent == 5) || (host_agent == 6); - pcie_configured = (io_sel == 0x2) || (io_sel == 0x4); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_3, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel); r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) { @@ -336,8 +334,8 @@ void pci_init_board(void) #ifdef CONFIG_PCIE1 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; hose = &pcie1_hose; - pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5); - pcie_configured = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF); + pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); + pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); r = hose->regions; if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) { diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1ae4cda..e5b21b5 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -363,7 +363,7 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */ - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ @@ -441,10 +441,10 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("\n PCIE connected to slot as %s (base address %x)", diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 277edcd..3931ec5 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -561,8 +561,7 @@ static inline void init_pci1(void) /* PORPLLSR[16] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; - uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || - (host_agent == 6); + uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ @@ -630,11 +629,10 @@ static inline void init_pcie1(void) uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || - (host_agent == 3); + int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions; - int pcie_configured = io_sel >= 1; + int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ printf ("PCIe: %s, base address %x", diff --git a/cpu/mpc8xxx/Makefile b/cpu/mpc8xxx/Makefile index 430a75f..5cb6814 100644 --- a/cpu/mpc8xxx/Makefile +++ b/cpu/mpc8xxx/Makefile @@ -11,6 +11,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib8xxx.a COBJS-y += cpu.o +COBJS-$(CONFIG_PCI) += pci_cfg.o SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) diff --git a/cpu/mpc8xxx/pci_cfg.c b/cpu/mpc8xxx/pci_cfg.c new file mode 100644 index 0000000..9c7d92c --- /dev/null +++ b/cpu/mpc8xxx/pci_cfg.c @@ -0,0 +1,225 @@ +/* + * Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <pci.h> + +struct pci_info { + u16 agent; + u16 cfg; +}; + +/* The agent field is a bit mask in which each bit represents the value of + * cfg_host_agt[] signal and the bit is set of the given interface would be + * in agent/end-point mode for the given interface. + * + * The same idea is true of the cfg field. The bit will be set if the + * interface would be enabled based on the value of cfg_IO_ports[] signal + * + * On MPC86xx/PQ3 based systems: + * we extract cfg_host_agt from GUTS register PORBMSR + * we extract cfg_IO_ports from GUTS register PORDEVSR + * + * cfg_IO_ports only exist on systems w/PCIe (we set cfg 0 for systems + * without PCIe) + */ + +#if defined(CONFIG_MPC8540) || defined(CONFIG_MPC8560) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 2), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0), + .cfg = 0, + }, +}; +#elif defined(CONFIG_MPC8536) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 5) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8544) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 4) | (1 << 5) | + (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 3), + .cfg = (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 1), + .cfg = (1 << 6) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8548) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCI_2] = { + .agent = (1 << 4) | (1 << 6), + .cfg = 0, + }, + /* PCI_2 is always host and we dont use iosel to determine enable/disable */ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8568) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI] = { + .agent = (1 << 0) | (1 << 4) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4), + .cfg = (1 << 3) | (1 << 4) | (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8569) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 6), + .cfg = (1 << 0) | (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | + (1 << 8) | (1 << 0xc) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_MPC8572) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 2) | (1 << 3) | (1 << 7) | + (1 << 0xb) | (1 << 0xc) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 3) | (1 << 7), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 7), + }, +}; +#elif defined(CONFIG_MPC8610) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCI_1] = { + .agent = (1 << 4) | (1 << 5) | (1 << 6), + .cfg = 0, + }, + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 2) | (1 << 5), + .cfg = (1 << 1) | (1 << 4), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4), + .cfg = (1 << 0) | (1 << 4), + }, +}; +#elif defined(CONFIG_MPC8641) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = 0, /* we dont use agent on 8641 */ + .cfg = (1 << 2) | (1 << 3) | (1 << 5) | (1 << 6) | + (1 << 7) | (1 << 0xe) | (1 << 0xf), + }, +}; +#elif defined(CONFIG_P1011) || defined(CONFIG_P1020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1), + .cfg = (1 << 0) | (1 << 6) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2), + .cfg = (1 << 0xe), + }, +}; +#elif defined(CONFIG_P2010) || defined(CONFIG_P2020) +static struct pci_info pci_config_info[] = +{ + [LAW_TRGT_IF_PCIE_1] = { + .agent = (1 << 0) | (1 << 1) | (1 << 4) | (1 << 5), + .cfg = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6) | + (1 << 0xd) | (1 << 0xe) | (1 << 0xf), + }, + [LAW_TRGT_IF_PCIE_2] = { + .agent = (1 << 0) | (1 << 2) | (1 << 4) | (1 << 6), + .cfg = (1 << 2) | (1 << 0xe), + }, + [LAW_TRGT_IF_PCIE_3] = { + .agent = (1 << 0) | (1 << 3) | (1 << 5) | (1 << 6), + .cfg = (1 << 2) | (1 << 4), + }, +}; +#else +#error Need to define pci_config_info for processor +#endif + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent) +{ + return ((1 << host_agent) & pci_config_info[trgt].agent); +} + +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel) +{ + return ((1 << io_sel) & pci_config_info[trgt].cfg); +} diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index f625d19..b9972da 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -20,6 +20,11 @@ #ifndef __FSL_PCI_H_ #define __FSL_PCI_H_ +#include <asm/fsl_law.h> + +int is_fsl_pci_agent(enum law_trgt_if trgt, u32 host_agent); +int is_fsl_pci_cfg(enum law_trgt_if trgt, u32 io_sel); + void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data); void fsl_pci_config_unlock(struct pci_controller *hose); void ft_fsl_pci_setup(void *blob, const char *pci_alias, -- 1.6.0.6

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[U-Boot] [PATCH] ppc/85xx: Cleanup makefile and related optional files
by Kumar Gala 05 Sep '09

05 Sep '09

Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases we have like PCI, CPM2, QE. Also reworked it to use one line per file for everything and sorted in alphabetical order. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/Makefile | 23 +++++++++++++++++------ cpu/mpc85xx/commproc.c | 3 --- cpu/mpc85xx/ether_fcc.c | 4 ---- cpu/mpc85xx/pci.c | 4 ++-- cpu/mpc85xx/serial_scc.c | 3 --- 5 files changed, 19 insertions(+), 18 deletions(-) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 1bd8f30..a177f42 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,10 +29,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o -SOBJS-$(CONFIG_MP) += release.o +SOBJS-$(CONFIG_MP) += release.o SOBJS = $(SOBJS-y) -COBJS-$(CONFIG_MP) += mp.o -COBJS-$(CONFIG_OF_LIBFDT) += fdt.o + +COBJS-$(CONFIG_CPM2) += commproc.o # supports ddr1 COBJS-$(CONFIG_MPC8540) += ddr-gen1.o @@ -54,10 +54,21 @@ COBJS-$(CONFIG_P1020) += ddr-gen3.o COBJS-$(CONFIG_P2010) += ddr-gen3.o COBJS-$(CONFIG_P2020) += ddr-gen3.o +COBJS-$(CONFIG_CPM2) += ether_fcc.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o +COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ - pci.o serial_scc.o commproc.o ether_fcc.o qe_io.o \ - $(COBJS-y) +COBJS-$(CONFIG_PCI) += pci.o +COBJS-$(CONFIG_QE) += qe_io.o +COBJS-$(CONFIG_CPM2) += serial_scc.o + +COBJS = $(COBJS-y) +COBJS += cpu.o +COBJS += cpu_init.o +COBJS += interrupts.o +COBJS += speed.o +COBJS += tlb.o +COBJS += traps.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc85xx/commproc.c b/cpu/mpc85xx/commproc.c index fff8dff..594aace 100644 --- a/cpu/mpc85xx/commproc.c +++ b/cpu/mpc85xx/commproc.c @@ -26,7 +26,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CPM2) /* * because we have stack and init data in dual port ram * we must reduce the size @@ -204,5 +203,3 @@ ulong post_word_load (void) } #endif /* CONFIG_POST */ - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/ether_fcc.c b/cpu/mpc85xx/ether_fcc.c index 32ad469..5f1414d 100644 --- a/cpu/mpc85xx/ether_fcc.c +++ b/cpu/mpc85xx/ether_fcc.c @@ -52,8 +52,6 @@ #include <miiphy.h> #endif -#if defined(CONFIG_CPM2) - #if defined(CONFIG_ETHER_ON_FCC) && defined(CONFIG_CMD_NET) && \ defined(CONFIG_NET_MULTI) @@ -469,5 +467,3 @@ int fec_initialize(bd_t *bis) } #endif - -#endif /* CONFIG_CPM2 */ diff --git a/cpu/mpc85xx/pci.c b/cpu/mpc85xx/pci.c index fedf1a5..75d2716 100644 --- a/cpu/mpc85xx/pci.c +++ b/cpu/mpc85xx/pci.c @@ -29,7 +29,7 @@ #include <asm/cpm_85xx.h> #include <pci.h> -#if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT) +#if !defined(CONFIG_FSL_PCI_INIT) #ifndef CONFIG_SYS_PCI1_MEM_BUS #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE @@ -227,4 +227,4 @@ pci_mpc85xx_init(struct pci_controller *board_hose) hose->last_busno = pci_hose_scan(hose); #endif } -#endif /* CONFIG_PCI */ +#endif /* !CONFIG_FSL_PCI_INIT */ diff --git a/cpu/mpc85xx/serial_scc.c b/cpu/mpc85xx/serial_scc.c index 05fb808..2dab212 100644 --- a/cpu/mpc85xx/serial_scc.c +++ b/cpu/mpc85xx/serial_scc.c @@ -37,7 +37,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CPM2) #if defined(CONFIG_CONS_ON_SCC) #if CONFIG_CONS_INDEX == 1 /* Console on SCC1 */ @@ -267,5 +266,3 @@ serial_tstc() } #endif /* CONFIG_CONS_ON_SCC */ - -#endif /* CONFIG_CPM2 */ -- 1.6.0.6

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[U-Boot] [PATCH] ppc/85xx: Add a simple function to search the TLB
by Kumar Gala 05 Sep '09

05 Sep '09

Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/tlb.c | 27 +++++++++++++++++++++++++++ include/asm-ppc/mmu.h | 7 +++++-- 2 files changed, 32 insertions(+), 2 deletions(-) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index f3d3080..0497a29 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -106,6 +106,33 @@ void init_tlbs(void) return ; } +static void tlbsx (const volatile unsigned *addr) +{ + __asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr)); +} + +/* return -1 if we didn't find anything */ +int find_tlb_idx(void *addr, u8 tlbsel) +{ + u32 _mas0, _mas1; + + /* zero out Search PID, AS */ + mtspr(MAS6, 0); + + tlbsx(addr); + + _mas0 = mfspr(MAS0); + _mas1 = mfspr(MAS1); + + /* we found something, and its in the TLB we expect */ + if ((MAS1_VALID & _mas1) && + (MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) { + return ((_mas0 & MAS0_ESEL_MSK) >> 16); + } + + return -1; +} + #ifdef CONFIG_ADDR_MAP void init_addr_map(void) { diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index fa92b90..eda2959 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -387,8 +387,10 @@ extern void print_bats(void); * FSL Book-E support */ -#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) -#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) +#define MAS0_TLBSEL_MSK 0x30000000 +#define MAS0_TLBSEL(x) ((x << 28) & MAS0_TLBSEL_MSK) +#define MAS0_ESEL_MSK 0x0FFF0000 +#define MAS0_ESEL(x) ((x << 16) & MAS0_ESEL_MSK) #define MAS0_NV(x) ((x) & 0x00000FFF) #define MAS1_VALID 0x80000000 @@ -474,6 +476,7 @@ extern void set_tlb(u8 tlb, u32 epn, u64 rpn, extern void disable_tlb(u8 esel); extern void invalidate_tlb(u8 tlb); extern void init_tlbs(void); +extern int find_tlb_idx(void *addr, u8 tlbsel); extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg); -- 1.6.0.6

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[U-Boot] s3c24x0 code changes
by kevin.morfitt＠fearnside-systems.co.uk 05 Sep '09

05 Sep '09

I submitted patches in the last merge window to add support for the Embest SBC2440-II Board but ran out of time to deal with all of the comments on the patches. Because it was a series of 7 patches comments on the early patches in the series meant I had to re-work all other patches. I'd like to try again in this merge window but do it in stages, waiting until the patches of each stage get accepted before starting the next stage. The stages would be: 1. re-format the existing s3c24x0 code to meet the u-boot code style guidelines 2. add support for the s3c2440 cpu 3. add support for the Embest SBC2440-II Board I'm aware that other changes are required to the s3c24x0 code such as moving all driver code to the drivers directory, using a shared start.S for all s3c24x0 cpu's, and cleaning up the #ifdef's that check which s3c24x0 cpu we're building for, and I could do these and/or other changes before step 3 if anyone would prefer. I guess that when a dedicated Samsung SoC custodian starts work they may have other ideas as well. I'm more concerned to make it manageable than to get the SBC2440-II supported quickly. Anyway, the code style changes in the original patch generated a few comments so I thought I'd describe what I intend to do in case anyone has any comments before I submit the patches. My plan is to make the following changes: - run "Lindent -kr -i8 -l80" on all s3c24x0 code then manually clean up the resulting files - change the existing S3C24X0 register struct's to use lower case names instead of upper case names - make the code use the readx/writex access functions - submit the s3c24x0 NAND driver changes as a separate patch Is there anything else anyone would like to see done in the code style changes?

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[U-Boot] [PATCH] AT91: Add support for blue_LED_* and add coloured_LED_init to at91/led.c
by Albin Tonnerre 05 Sep '09

05 Sep '09

Currently, at91/led.c only provides _on and _off functions for green, yellow and red LEDs. This patch provides a generic coloured_LED_init function, which is a first step towards getting rid of the board-specific (and duplicated) board/*/*/led.c files on at91 This patch alos adds similar support for blue LEDs, mostly for the sake of completeness. Signed-off-by: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> --- cpu/arm926ejs/at91/led.c | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c index be68f59..f6b1912 100644 --- a/cpu/arm926ejs/at91/led.c +++ b/cpu/arm926ejs/at91/led.c @@ -27,6 +27,26 @@ #include <asm/arch/gpio.h> #include <asm/arch/io.h> +void coloured_LED_init(void) +{ +#ifdef CONFIG_RED_LED + at91_set_gpio_output(CONFIG_RED_LED, 0); + red_LED_off(); +#endif +#ifdef CONFIG_GREEN_LED + at91_set_gpio_output(CONFIG_GREEN_LED, 0); + green_LED_off(); +#endif +#ifdef CONFIG_YELLOW_LED + at91_set_gpio_output(CONFIG_YELLOW_LED, 0); + yellow_LED_off(); +#endif +#ifdef CONFIG_BLUE_LED + at91_set_gpio_output(CONFIG_BLUE_LED, 0); + blue_LED_off(); +#endif +} + #ifdef CONFIG_RED_LED void red_LED_on(void) { @@ -62,3 +82,15 @@ void yellow_LED_off(void) at91_set_gpio_value(CONFIG_YELLOW_LED, 1); } #endif + +#ifdef CONFIG_BLUE_LED +void blue_LED_on(void) +{ + at91_set_gpio_value(CONFIG_BLUE_LED, 0); +} + +void blue_LED_off(void) +{ + at91_set_gpio_value(CONFIG_BLUE_LED, 1); +} +#endif -- 1.6.0.4

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