September 2009 - U-Boot

[U-Boot] Hanging in kmalloc of nand_scan_tail() function
by J.Hwan.Kim 15 Nov '10

15 Nov '10

Hi, everyone I'm using U-boot 2009-03. U-boot hangs in nand_init() function. I found the routine kmalloc in nand_scan_tail() cause U-boot reset. int nand_scan_tail(struct mtd_info *mtd) { int i; struct nand_chip *chip = mtd->priv; if (!(chip->options & NAND_OWN_BUFFERS)) { chip->buffers = kmalloc(sizeof(*chip->buffers), GFP_KERNEL); } if (!chip->buffers) return -ENOMEM; ........ U-boot displays message as follows : NAND: data abort pc : [<31f902b4>]\0x09 lr : [<31fa084c>] sp : 31f5bee0 ip : 00000076\0x09 fp : 00000000 r10: 00001188 r9 : 00020000\0x09 r8 : 31f5bfdc r7 : 00000001 r6 : 00000000\0x09 r5 : 31fa42b8 r4 : 31fa4364 r3 : 31fa052c r2 : 00000064\0x09 r1 : 00000063 r0 : ffffffff Flags: NzCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Where the malloc function is defined? Why the kmalloc() hangs the u-boot? Is there any configuation definition needed? Thanks in advance. Regards, J.Hwan Kim

4 10

[U-Boot] [PATCH] cmd_elf: CONFIG_ELF_SIMPLE_LOAD: load ELFs according to PHDRs
by Mike Frysinger 06 Oct '10

06 Oct '10

The current ELF loading function does a lot of work above and beyond a simple "loading". It ignores the real load addresses and loads things into their virtual (runtime) address. This is undesirable when we just want it to load an ELF and let the ELF do the actual C runtime init. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/cmd_elf.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 3ebb6d9..7b82749 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -276,6 +276,32 @@ int valid_elf_image (unsigned long addr) * A very simple elf loader, assumes the image is valid, returns the * entry point address. * ====================================================================== */ +#ifdef CONFIG_ELF_SIMPLE_LOAD +unsigned long load_elf_image (unsigned long addr) +{ + Elf32_Ehdr *ehdr; + Elf32_Phdr *phdr; + unsigned long entry; + size_t i; + + ehdr = (Elf32_Ehdr *) addr; + phdr = (Elf32_Phdr *) (addr + ehdr->e_phoff); + + entry = ehdr->e_entry; + + /* Load each program header */ + for (i = 0; i < ehdr->e_phnum; ++i) { + void *dst = (void *) phdr->p_paddr; + void *src = (void *) addr + phdr->p_offset; + printf ("Loading phdr %i to 0x%p (%i bytes)\n", + i, dst, phdr->p_filesz); + memcpy (dst, src, phdr->p_filesz); + ++phdr; + } + + return entry; +} +#else unsigned long load_elf_image (unsigned long addr) { Elf32_Ehdr *ehdr; /* Elf header structure pointer */ @@ -327,6 +353,7 @@ unsigned long load_elf_image (unsigned long addr) return ehdr->e_entry; } +#endif /* ====================================================================== */ U_BOOT_CMD( -- 1.6.0.3

2 5

[U-Boot-Users] how to u-boot in LPC2468 board using uClinux
by anand 28 Sep '10

28 Sep '10

do any one have u-boot.bin file for LPC2468 i downloaded u-boot-1.1.6 but i din't get the u-boot prombt in the terminal window its gets struck in the starting display itself anyone pls help thanks in advance

3 2

[U-Boot-Users] [PATCH, resend] Support dynamic/patched NAND ENV offset
by Harald Welte 18 Sep '10

18 Sep '10

Hi! I've first sent this on Feb 17, 2007. Unfortunately no reply was received. I think this is a quite useful feature, since a compile time offset into the NAND flash for the environment just doesn't work well with bad blocks ;) This is the current version of the patch. I'd love to see it included. Thanks! --- This patch adds support for CFG_ENV_OFFSET_PATCHED and CFG_ENV_OFFSET_OOB. Both try to solve the problem of fixing the environment location in NAND flash at compile time, which doesn't work well if the NAND flash has a bad block at exactly that location. CFG_ENV_OFFSET_PATCHED puts the environment in a global variable. You can then use the linker script to put that variable to a fixed location in the u-boot image. Then you can use bianry patching during the production flash process. The idea of CFG_ENV_OFFSET_OOB is to store the environment offset in the NAND OOB data of block 0. We can do this in case the vendor makes a guarantee that block 0 never is a factory-default bad block. Signed-off-by: Harald Welte <laforge(a)openmoko.org> Index: u-boot/common/Makefile =================================================================== --- u-boot.orig/common/Makefile +++ u-boot/common/Makefile @@ -55,6 +55,7 @@ COBJS-$(CONFIG_CMD_DISPLAY) += cmd_display.o COBJS-$(CONFIG_CMD_DOC) += cmd_doc.o COBJS-$(CONFIG_CMD_DTT) += cmd_dtt.o +COBJS-y += cmd_dynenv.o COBJS-y += cmd_eeprom.o COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o Index: u-boot/common/cmd_dynenv.c =================================================================== --- /dev/null +++ u-boot/common/cmd_dynenv.c @@ -0,0 +1,106 @@ +/* + * (C) Copyright 2006-2007 OpenMoko, Inc. + * Author: Harald Welte <laforge(a)openmoko.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <environment.h> +#include <nand.h> +#include <asm/errno.h> +#include "cmd_nand.h" + +#if defined(CFG_ENV_OFFSET_OOB) + +int do_dynenv(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + struct mtd_info *mtd = &nand_info[0]; + int ret, size = 8; + uint8_t *buf; + + char *cmd = argv[1]; + + buf = malloc(mtd->oobsize); + if (!buf) + return -ENOMEM; + + ret = mtd->read_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); + if (!strcmp(cmd, "get")) { + + if (buf[0] == 'E' && buf[1] == 'N' && + buf[2] == 'V' && buf[3] == '0') + printf("0x%08x\n", *((u_int32_t *) &buf[4])); + else + printf("No dynamic environment marker in OOB block 0\n"); + + } else if (!strcmp(cmd, "set")) { + unsigned long addr, dummy; + + if (argc < 3) + goto usage; + + buf[0] = 'E'; + buf[1] = 'N'; + buf[2] = 'V'; + buf[3] = '0'; + + if (arg_off_size(argc-2, argv+2, mtd, &addr, &dummy) < 0) { + printf("Offset or partition name expected\n"); + goto fail; + } + if (!ret) { + uint8_t tmp[4]; + int i; + + memcpy(&tmp, &addr, 4); + for (i = 0; i != 4; i++) + if (tmp[i] & ~buf[i+4]) { + printf("ERROR: erase OOB block to " + "write this value\n"); + goto fail; + } + } + memcpy(buf+4, &addr, 4); + + printf("%02x %02x %02x %02x - %02x %02x %02x %02x\n", + buf[0], buf[1], buf[2], buf[3], + buf[4], buf[5], buf[6], buf[7]); + + ret = mtd->write_oob(mtd, 8, size, (size_t *) &size, (u_char *) buf); + if (!ret) + CFG_ENV_OFFSET = addr; + } else + goto usage; + + free(buf); + return ret; + +usage: + printf("Usage:\n%s\n", cmdtp->usage); +fail: + free(buf); + return 1; +} + +U_BOOT_CMD(dynenv, 3, 1, do_dynenv, + "dynenv - dynamically placed (NAND) environment\n", + "dynenv set off - set enviromnent offset\n" + "dynenv get - get environment offset\n"); + +#endif /* CFG_ENV_OFFSET_OOB */ Index: u-boot/common/env_nand.c =================================================================== --- u-boot.orig/common/env_nand.c +++ u-boot/common/env_nand.c @@ -292,6 +292,33 @@ int crc1_ok = 0, crc2_ok = 0; env_t *tmp_env1, *tmp_env2; +#if defined(CFG_ENV_OFFSET_OOB) + struct mtd_info *mtd = &nand_info[0]; + struct nand_chip *this = mtd->priv; + int buf_len; + uint8_t *buf; + + buf_len = (1 << this->bbt_erase_shift); + buf_len += (buf_len >> this->page_shift) * mtd->oobsize; + buf = malloc(buf_len); + if (!buf) + return; + + nand_read_raw(mtd, buf, 0, mtd->oobblock, mtd->oobsize); + if (buf[mtd->oobblock + 8 + 0] == 'E' && + buf[mtd->oobblock + 8 + 1] == 'N' && + buf[mtd->oobblock + 8 + 2] == 'V' && + buf[mtd->oobblock + 8 + 3] == '0') { + CFG_ENV_OFFSET = *((unsigned long *) &buf[mtd->oobblock + 8 + 4]); + /* fall through to the normal environment reading code below */ + free(buf); + puts("Found Environment offset in OOB..\n"); + } else { + free(buf); + return use_default(); + } +#endif + total = CFG_ENV_SIZE; tmp_env1 = (env_t *) malloc(CFG_ENV_SIZE); Index: u-boot/common/environment.c =================================================================== --- u-boot.orig/common/environment.c +++ u-boot/common/environment.c @@ -29,6 +29,12 @@ #undef __ASSEMBLY__ #include <environment.h> +#if defined(CFG_ENV_OFFSET_PATCHED) +unsigned long env_offset = CFG_ENV_OFFSET_PATCHED; +#elif defined(CFG_ENV_OFFSET_OOB) +unsigned long env_offset = CFG_ENV_OFFSET_OOB; +#endif + /* * Handle HOSTS that have prepended * crap on symbol names, not TARGETS. Index: u-boot/include/environment.h =================================================================== --- u-boot.orig/include/environment.h +++ u-boot/include/environment.h @@ -70,6 +70,10 @@ #endif /* CFG_ENV_IS_IN_FLASH */ #if defined(CFG_ENV_IS_IN_NAND) +#if defined(CFG_ENV_OFFSET_PATCHED) || defined(CFG_ENV_OFFSET_OOB) +extern unsigned long env_offset; +#define CFG_ENV_OFFSET env_offset +#else # ifndef CFG_ENV_OFFSET # error "Need to define CFG_ENV_OFFSET when using CFG_ENV_IS_IN_NAND" # endif @@ -82,6 +86,7 @@ # ifdef CFG_ENV_IS_EMBEDDED # define ENV_IS_EMBEDDED 1 # endif +#endif /* CFG_ENV_NAND_PATCHED */ #endif /* CFG_ENV_IS_IN_NAND */ #ifdef USE_HOSTCC Index: u-boot/common/cmd_nand.h =================================================================== --- /dev/null +++ u-boot/common/cmd_nand.h @@ -0,0 +1,33 @@ +/* + * cmd_nand.h - Convenience functions + * + * (C) Copyright 2006-2007 OpenMoko, Inc. + * Author: Werner Almesberger <werner(a)openmoko.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef CMD_NAND_H +#define CMD_NAND_H + +#include <nand.h> + + +/* common/cmd_nand.c */ +int arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, + ulong *size); + +#endif /* CMD_NAND_H */ Index: u-boot/common/cmd_nand.c =================================================================== --- u-boot.orig/common/cmd_nand.c +++ u-boot/common/cmd_nand.c @@ -90,7 +90,7 @@ return (*p != '\0' && *endptr == '\0') ? 1 : 0; } -static int +int arg_off_size(int argc, char *argv[], nand_info_t *nand, ulong *off, size_t *size) { int idx = nand_curr_device; -- - Harald Welte <laforge(a)openmoko.org> http://openmoko.org/ ============================================================================ Software for the world's first truly open Free Software mobile phone

7 98

[U-Boot] [PATCH v2] AT91: Add SD/MMC controller support
by Albin Tonnerre 26 May '10

26 May '10

This patch allows to use the atmel_mci SD/MMC driver on the at91 architecture. It contains: - initialization code for the MCI controller for all the supported AT91. It allows the use of only one controller even if a SoC has two controllers (anyway there's no support for it in atmel_mci as of now) - the necessary get_mci_clk_rate function - definition of MMCI_BASE for use in atmel_mci - the cpu_mmc_init function. As of now this is not used, but will be required when atmel_mci is ported to the new generic mmc API. Signed-off-by: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> --- Changes since v1 (http://lists.denx.de/pipermail/u-boot/2009-September/059665.html): - Fix the MCI controller ID in the init code for CAP9, SAM9263 and SAM9G45 - Move AT91_BASE_MCI* define to soc header - define AT91_BASE_MCI{0,1} instead of AT91_BASE_MCI for boards which have 2 controllers - rework the way MMCI_BASE is defined accordingly Note: I am fully aware that MMCI0_BASE and MMCI1_BASE should be defined, instead of MMCI_BASE. However, I'd rather wait until the patch that switches atmel_mci to the generic mmc API is accepted, as it will be easier to do it then. cpu/arm926ejs/at91/at91cap9_devices.c | 37 ++++++++++++++++++ cpu/arm926ejs/at91/at91sam9260_devices.c | 27 +++++++++++++ cpu/arm926ejs/at91/at91sam9261_devices.c | 18 +++++++++ cpu/arm926ejs/at91/at91sam9263_devices.c | 55 +++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 55 +++++++++++++++++++++++++++ cpu/arm926ejs/at91/at91sam9rl_devices.c | 22 +++++++++++ cpu/arm926ejs/at91/cpu.c | 7 +++ include/asm-arm/arch-at91/at91_common.h | 2 + include/asm-arm/arch-at91/at91cap9.h | 3 + include/asm-arm/arch-at91/at91sam9260.h | 2 + include/asm-arm/arch-at91/at91sam9261.h | 1 + include/asm-arm/arch-at91/at91sam9263.h | 3 + include/asm-arm/arch-at91/at91sam9g45.h | 3 + include/asm-arm/arch-at91/at91sam9rl.h | 1 + include/asm-arm/arch-at91/clk.h | 5 ++ include/asm-arm/arch-at91/memory-map.h | 6 +++ 16 files changed, 247 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 39e405f..53a58a9 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -79,6 +79,43 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } +} +#endif +#ifdef CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_MCI1); + at91_set_A_periph(AT91_PIN_PA16, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA17, 1); + at91_set_A_periph(AT91_PIN_PA18, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + at91_set_A_periph(AT91_PIN_PA21, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index f86cb99..ea22030 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -75,6 +75,33 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + at91_set_A_periph(AT91_PIN_PA8, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA6, 1); + at91_set_A_periph(AT91_PIN_PA7, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + } + } +} +#endif /* ATMEL_MCI */ + #if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI) void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 16d411f..7ee573c 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -75,6 +75,24 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_MCI); + at91_set_B_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + at91_set_B_periph(AT91_PIN_PA6, 1); + } + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index f72efdf..6a89fab 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -79,6 +79,61 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA12, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } + if (mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PA16, 1); + at91_set_A_periph(AT91_PIN_PA17, 1); + if (mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA18, 1); + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + } + } +} +#endif +#ifdef CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_MCI1); + at91_set_A_periph(AT91_PIN_PA6, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA21, 1); + at91_set_B_periph(AT91_PIN_PA22, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA23, 1); + at91_set_B_periph(AT91_PIN_PA24, 1); + at91_set_B_periph(AT91_PIN_PA25, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 98d90f2..c4db5f4 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -75,6 +75,61 @@ void at91_serial_hw_init(void) #endif } +#ifdef CONFIG_ATMEL_MCI +#ifdef CONFIG_AT91_MCI0 +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_MCI0); + at91_set_A_periph(AT91_PIN_PA12, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } + if (mask & (1 << 2)) { + at91_set_A_periph(AT91_PIN_PA16, 1); + at91_set_A_periph(AT91_PIN_PA17, 1); + if (mask & (1 << 3)) { + at91_set_A_periph(AT91_PIN_PA18, 1); + at91_set_A_periph(AT91_PIN_PA19, 1); + at91_set_A_periph(AT91_PIN_PA20, 1); + } + } +} +#endif +#ifdef CONFIG_AT91_MCI1 +void at91_mci1_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_MCI1); + at91_set_A_periph(AT91_PIN_PA6, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA7, 1); + at91_set_A_periph(AT91_PIN_PA8, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA9, 1); + at91_set_A_periph(AT91_PIN_PA10, 1); + at91_set_A_periph(AT91_PIN_PA11, 1); + } + } + if (mask & (1 << 2)) { + at91_set_B_periph(AT91_PIN_PA0, 1); + at91_set_B_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 3)) { + at91_set_B_periph(AT91_PIN_PA3, 1); + at91_set_B_periph(AT91_PIN_PA4, 1); + at91_set_B_periph(AT91_PIN_PA5, 1); + } + } +} +#endif +#endif + #ifdef CONFIG_ATMEL_SPI void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index ebed193..41ae4a8 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -75,6 +75,28 @@ void at91_serial_hw_init(void) #endif } +/* + * The AT91SAM9RL64 is said to have 2 slots, but the datasheet doesn't + * seem to mention to what pins the second slot is assigned + */ +#ifdef CONFIG_ATMEL_MCI +void at91_mci0_hw_init(unsigned long mask) +{ + at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_MCI); + at91_set_A_periph(AT91_PIN_PA2, 0); + + if (mask & (1 << 0)) { + at91_set_A_periph(AT91_PIN_PA0, 1); + at91_set_A_periph(AT91_PIN_PA1, 1); + if (mask & (1 << 1)) { + at91_set_A_periph(AT91_PIN_PA3, 1); + at91_set_A_periph(AT91_PIN_PA4, 1); + at91_set_A_periph(AT91_PIN_PA5, 1); + } + } +} +#endif /* ATMEL_MCI */ + #ifdef CONFIG_HAS_DATAFLASH void at91_spi0_hw_init(unsigned long cs_mask) { diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c index f2f7b62..f96b715 100644 --- a/cpu/arm926ejs/at91/cpu.c +++ b/cpu/arm926ejs/at91/cpu.c @@ -52,3 +52,10 @@ int print_cpuinfo(void) return 0; } #endif + +#ifdef CONFIG_GENERIC_MMC +int cpu_mmc_init(bd_t *bis) +{ + atmel_mci_init(bis); +} +#endif /* GENERIC_MMC */ diff --git a/include/asm-arm/arch-at91/at91_common.h b/include/asm-arm/arch-at91/at91_common.h index 01840ee..01fcdd6 100644 --- a/include/asm-arm/arch-at91/at91_common.h +++ b/include/asm-arm/arch-at91/at91_common.h @@ -32,6 +32,8 @@ void at91_serial0_hw_init(void); void at91_serial1_hw_init(void); void at91_serial2_hw_init(void); void at91_serial3_hw_init(void); +void at91_mci0_hw_init(unsigned long mask); +void at91_mci1_hw_init(unsigned long mask); void at91_spi0_hw_init(unsigned long cs_mask); void at91_spi1_hw_init(unsigned long cs_mask); void at91_uhp_hw_init(void); diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h index b128ac5..2ad3280 100644 --- a/include/asm-arm/arch-at91/at91cap9.h +++ b/include/asm-arm/arch-at91/at91cap9.h @@ -109,6 +109,9 @@ #define AT91_USART1 AT91CAP9_BASE_US1 #define AT91_USART2 AT91CAP9_BASE_US2 +#define AT91_BASE_MCI0 AT91CAP9_BASE_MCI0 +#define AT91_BASE_MCI1 AT91CAP9_BASE_MCI1 + /* * SCKCR flags */ diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h index 73975f4..b92f0ee 100644 --- a/include/asm-arm/arch-at91/at91sam9260.h +++ b/include/asm-arm/arch-at91/at91sam9260.h @@ -105,6 +105,8 @@ #define AT91_USART4 AT91SAM9260_BASE_US4 #define AT91_USART5 AT91SAM9260_BASE_US5 +#define AT91_BASE_MCI0 AT91SAM9260_BASE_MCI + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h index b303e07..11fdc3e 100644 --- a/include/asm-arm/arch-at91/at91sam9261.h +++ b/include/asm-arm/arch-at91/at91sam9261.h @@ -88,6 +88,7 @@ #define AT91_USART1 AT91SAM9261_BASE_US1 #define AT91_USART2 AT91SAM9261_BASE_US2 +#define AT91_BASE_MCI0 AT91SAM9261_BASE_MCI /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h index 966a683..6bf124b 100644 --- a/include/asm-arm/arch-at91/at91sam9263.h +++ b/include/asm-arm/arch-at91/at91sam9263.h @@ -108,6 +108,9 @@ #define AT91_SMC AT91_SMC0 #define AT91_SDRAMC AT91_SDRAMC0 +#define AT91_BASE_MCI0 AT91SAM9263_BASE_MCI0 +#define AT91_BASE_MCI1 AT91SAM9263_BASE_MCI1 + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9g45.h b/include/asm-arm/arch-at91/at91sam9g45.h index 0feed9c..16deadc 100644 --- a/include/asm-arm/arch-at91/at91sam9g45.h +++ b/include/asm-arm/arch-at91/at91sam9g45.h @@ -114,6 +114,9 @@ #define AT91_USART2 AT91SAM9G45_BASE_US2 #define AT91_USART3 AT91SAM9G45_BASE_US3 +#define AT91_BASE_MCI0 AT91SAM9G45_BASE_MCI0 +#define AT91_BASE_MCI1 AT91SAM9G45_BASE_MCI1 + /* * Internal Memory. */ diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h index 4dd8037..f0da7a2 100644 --- a/include/asm-arm/arch-at91/at91sam9rl.h +++ b/include/asm-arm/arch-at91/at91sam9rl.h @@ -99,6 +99,7 @@ #define AT91_USART2 AT91SAM9RL_BASE_US2 #define AT91_USART3 AT91SAM9RL_BASE_US3 +#define AT91_BASE_MCI0 AT91SAM9RL_BASE_MCI /* * Internal Memory. diff --git a/include/asm-arm/arch-at91/clk.h b/include/asm-arm/arch-at91/clk.h index f642dd9..457e6c9 100644 --- a/include/asm-arm/arch-at91/clk.h +++ b/include/asm-arm/arch-at91/clk.h @@ -59,5 +59,10 @@ static inline unsigned long get_twi_clk_rate(unsigned int dev_id) return get_mck_clk_rate(); } +static inline unsigned long get_mci_clk_rate(void) +{ + return get_mck_clk_rate(); +} + int at91_clock_init(unsigned long main_clock); #endif /* __ASM_ARM_ARCH_CLK_H__ */ diff --git a/include/asm-arm/arch-at91/memory-map.h b/include/asm-arm/arch-at91/memory-map.h index f605f37..445d128 100644 --- a/include/asm-arm/arch-at91/memory-map.h +++ b/include/asm-arm/arch-at91/memory-map.h @@ -32,4 +32,10 @@ #define USART3_BASE (AT91_BASE_SYS + AT91_DBGU) #define SPI0_BASE AT91_BASE_SPI +#ifndef (CONFIG_AT91_MCI1) +# define MMCI_BASE AT91_BASE_MCI0 +#else +# define MMCI_BASE AT91_BASE_MCI1 +#endif + #endif /* __ASM_ARM_ARCH_MEMORYMAP_H__ */ -- 1.6.3.3

5 10

[U-Boot] [PATCH 2/5]P2020RDB Second UART port added for MPC85xx, MPC83xx, MPC86xx processors
by Poonam Aggrwal 09 Apr '10

09 Apr '10

Defining the next two configs allows to switch the serial port from the console using the setenv stdin and stdout 1. #define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */ 2. #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout(a)freescale.com> --- common/serial.c | 3 ++- include/serial.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/common/serial.c b/common/serial.c index dd80e7c..5d0a73c 100644 --- a/common/serial.c +++ b/common/serial.c @@ -40,7 +40,8 @@ struct serial_device *__default_serial_console (void) return &serial_scc_device; #elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ - || defined(CONFIG_MPC5xxx) + || defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) \ + || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #if defined(CONFIG_CONS_INDEX) && defined(CONFIG_SYS_NS16550_SERIAL) #if (CONFIG_CONS_INDEX==1) return &eserial1_device; diff --git a/include/serial.h b/include/serial.h index aca5221..5722337 100644 --- a/include/serial.h +++ b/include/serial.h @@ -24,7 +24,8 @@ extern struct serial_device * default_serial_console (void); #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || \ defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_MPC5xxx) + defined(CONFIG_MPC5xxx) || defined(CONFIG_MPC83xx) || \ + defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) extern struct serial_device serial0_device; extern struct serial_device serial1_device; #if defined(CONFIG_SYS_NS16550_SERIAL) -- 1.5.6.3

3 2

[U-Boot] [RFC] 83xx: uec: miiphybb: Added support for bitBang SMI and uec SMI enabled at the same time.
by Richard Retanubun 05 Apr '10

05 Apr '10

Greetings, Our board have one PHY's SMI attached via GPIO (bitBang SMI) and the other network device (a switch) connected to the 8360e's real SMI controller. This patch aims to make u-boot able to use both at the same time. I am checking if I am on the right track and if I have missed something. The board-specific header file #define looks like this (similar to the FIXED_PHY) method [snip] #define CONFIG_SYS_BITBANG_PHY_PORT(devnum) devnum, #define CONFIG_SYS_BITBANG_PHY_PORTS \ CONFIG_SYS_BITBANG_PHY_PORT(10) [/snip] My code's baseline is at commit 57fe30194d3c15c37d9ff06dbd2a4c1ffccda018 (post v2009.06) Thank you for everyone's time. - Richard From 644a9cd7b9d9331989a3cf59d920a072c9dafe05 Mon Sep 17 00:00:00 2001 From: Richard Retanubun <RichardRetanubun(a)RuggedCom.com> Date: Wed, 17 Jun 2009 16:00:41 -0400 Subject: [PATCH] 83xx: UEC: Added support for bitBang MII driver access to PHYs This patch enabled support for having PHYs on bitBang MII and uec MII operating at the same time. --- drivers/net/phy/miiphybb.c | 28 ++++++++++++++++++++++------ drivers/net/phy/miiphybb.h | 26 ++++++++++++++++++++++++++ drivers/qe/uec.c | 6 ++---- drivers/qe/uec_phy.c | 34 ++++++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+), 10 deletions(-) create mode 100644 drivers/net/phy/miiphybb.h diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index e3c163a..1a15707 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -29,6 +29,7 @@ #include <common.h> #include <ioports.h> #include <ppc_asm.tmpl> +#include "miiphybb.h" /***************************************************************************** * @@ -38,8 +39,13 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) { int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \ + && !defined(CONFIG_MPC83XX) + volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); +#elif defined(CONFIG_MPC83XX) + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]); #endif /* @@ -123,8 +129,13 @@ int bb_miiphy_read (char *devname, unsigned char addr, { short rdreg; /* register working value */ int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \ + && !defined(CONFIG_MPC83XX) + volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); +#elif defined(CONFIG_MPC83XX) + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]); #endif miiphy_pre (1, addr, reg); @@ -190,8 +201,13 @@ int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value) { int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); +#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) \ + && !defined(CONFIG_MPC83XX) + volatile gpio_n_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); +#elif defined(CONFIG_MPC83XX) + volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + volatile gpio_n_t *iop = &(par_io->ioport[MDIO_PORT]); #endif miiphy_pre (0, addr, reg); diff --git a/drivers/net/phy/miiphybb.h b/drivers/net/phy/miiphybb.h new file mode 100644 index 0000000..4fff40d --- /dev/null +++ b/drivers/net/phy/miiphybb.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2006-2009 RuggedCom, Inc. + * + * Richard Retanubun <richardretanubun(a)ruggedcom.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +int bb_miiphy_read (char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); + +int bb_miiphy_write (char *devname, unsigned char addr, + unsigned char reg, unsigned short value); diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index 63fede9..a9bac99 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -579,8 +579,7 @@ static void phy_change(struct eth_device *dev) adjust_link(dev); } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ - && !defined(BITBANGMII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /*&& !defined(BITBANGMII)*/ /* * Find a device index from the devlist by name @@ -1383,8 +1382,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info) return err; } -#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ - && !defined(BITBANGMII) +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) /* && !defined(CONFIG_BITBANGMII) */ miiphy_register(dev->name, uec_miiphy_read, uec_miiphy_write); #endif diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index d613f3e..c7c7439 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -25,6 +25,7 @@ #include "uec.h" #include "uec_phy.h" #include "miiphy.h" +#include "../net/phy/miiphybb.h" #define ugphy_printk(format, arg...) \ printf(format "\n", ## arg) @@ -92,6 +93,15 @@ static const struct fixed_phy_port fixed_phy_port[] = { CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ }; +/* BitBang MII support for ethernet ports */ +#ifndef CONFIG_SYS_BITBANG_PHY_PORTS +#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */ +#endif + +static const unsigned short bitbang_phy_port[] = { + CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */ +}; + static void config_genmii_advert (struct uec_mii_info *mii_info); static void genmii_setup_forced (struct uec_mii_info *mii_info); static void genmii_restart_aneg (struct uec_mii_info *mii_info); @@ -112,6 +122,18 @@ void uec_write_phy_reg (struct eth_device *dev, int mii_id, int regnum, int valu enet_tbi_mii_reg_e mii_reg = (enet_tbi_mii_reg_e) regnum; u32 tmp_reg; + +#if defined(CONFIG_BITBANGMII) + u8 i = 0; + + for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { + if (mii_id == bitbang_phy_port[i]) { + (void)bb_miiphy_write(NULL, mii_id, regnum, value); + return; + } + } +#endif /* CONFIG_BITBANGMII */ + ug_regs = ugeth->uec_mii_regs; /* Stop the MII management read cycle */ @@ -139,6 +161,18 @@ int uec_read_phy_reg (struct eth_device *dev, int mii_id, int regnum) u32 tmp_reg; u16 value; + +#if defined(CONFIG_BITBANGMII) + u8 i = 0; + + for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) { + if (mii_id == bitbang_phy_port[i]) { + (void)bb_miiphy_read(NULL, mii_id, regnum, &value); + return (value); + } + } +#endif /* CONFIG_BITBANGMII */ + ug_regs = ugeth->uec_mii_regs; /* Setting up the MII Mangement Address Register */ -- 1.6.2.4

4 6

[U-Boot] PATCH - Added support to YANU Nios2 uart (02)
by Renato Andreola 16 Mar '10

16 Mar '10

From d7a79fc4e5a3ebc6a1ca5c23500e3f2f1c3b33c2 Mon Sep 17 00:00:00 2001 From: Renato Andreola <renato.andreola(a)imagos.it> Date: Mon, 24 Aug 2009 16:03:51 +0200 Subject: [PATCH] Yanu Support for U-Boot with this patch YANU uart (from opencores) support will be added to u-boot. Remember to modify properly your board files for defining physical address etc etc Sign-off-by: Renato Andreola <renato.andreola(a)imagos.it> --- cpu/nios2/serial.c | 165 +++++++++++++++++++++++++++++++++++++++++++++++++- include/nios2-yanu.h | 115 +++++++++++++++++++++++++++++++++++ 2 files changed, 279 insertions(+), 1 deletions(-) create mode 100644 include/nios2-yanu.h diff --git a/cpu/nios2/serial.c b/cpu/nios2/serial.c index 8bbb803..467df4c 100644 --- a/cpu/nios2/serial.c +++ b/cpu/nios2/serial.c @@ -26,6 +26,7 @@ #include <watchdog.h> #include <asm/io.h> #include <nios2-io.h> +#include <nios2-yanu.h> DECLARE_GLOBAL_DATA_PTR; @@ -74,10 +75,172 @@ int serial_getc (void) return (c); } +#elif defined(CONFIG_CONSOLE_YANU) +/*-----------------------------------------------------------------*/ +/* YANU Imagos serial port */ +/*-----------------------------------------------------------------*/ + +static yanu_uart_t *uart = (yanu_uart_t *)CONFIG_SYS_NIOS_CONSOLE; + +#if defined(CONFIG_NIOS_FIXEDBAUD) + +/* Everything's already setup for fixed-baud PTF assignment*/ + +void serial_setbrg (void) +{ + int n, k; + const unsigned max_uns = 0xFFFFFFFF; + unsigned best_n, best_m, baud; + + /* compute best N and M couple */ + best_n = YANU_MAX_PRESCALER_N; + for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { + if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= + (unsigned)CONFIG_BAUDRATE) { + best_n = n; + break; + } + } + for (k = 0;; k++) { + if ((unsigned)CONFIG_BAUDRATE <= (max_uns >> (15+n-k))) + break; + } + best_m = + ((unsigned)CONFIG_BAUDRATE * (1 << (15 + n - k))) / + ((unsigned)CONFIG_SYS_CLK_FREQ >> k); + + baud = best_m + best_n * YANU_BAUDE; + writel(&uart->baud, baud); + + return; +} + +#else + +void serial_setbrg (void) +{ + int n, k; + const unsigned max_uns = 0xFFFFFFFF; + unsigned best_n, best_m, baud; + + /* compute best N and M couple */ + best_n = YANU_MAX_PRESCALER_N; + for (n = YANU_MAX_PRESCALER_N; n >= 0; n--) { + if ((unsigned)CONFIG_SYS_CLK_FREQ / (1 << (n + 4)) >= + gd->baudrate) { + best_n = n; + break; + } + } + for (k = 0;; k++) { + if (gd->baudrate <= (max_uns >> (15+n-k))) + break; + } + best_m = + (gd->baudrate * (1 << (15 + n - k))) / + ((unsigned)CONFIG_SYS_CLK_FREQ >> k); + + baud = best_m + best_n * YANU_BAUDE; + writel(&uart->baud, baud); + + return; +} + + +#endif /* CFG_NIOS_FIXEDBAUD */ + +int serial_init (void) +{ + unsigned action,control; + + /* status register cleanup */ + action = YANU_ACTION_RRRDY | + YANU_ACTION_RTRDY | + YANU_ACTION_ROE | + YANU_ACTION_RBRK | + YANU_ACTION_RFE | + YANU_ACTION_RPE | + YANU_ACTION_RFE | YANU_ACTION_RFIFO_CLEAR | YANU_ACTION_TFIFO_CLEAR; + + writel(&uart->action, action); + + /* control register cleanup */ + /* no interrupts enabled */ + /* one stop bit */ + /* hardware flow control disabled */ + /* 8 bits */ + control = (0x7 << YANU_CONTROL_BITS_POS); + /* enven parity just to be clean */ + control |= YANU_CONTROL_PAREVEN; + /* we set threshold for fifo */ + control |= YANU_CONTROL_RDYDLY * YANU_RXFIFO_DLY; + control |= YANU_CONTROL_TXTHR * YANU_TXFIFO_THR; + + writel(&uart->control, control); + + /* to set baud rate */ + serial_setbrg(); + + return (0); +} + + +/*----------------------------------------------------------------------- + * YANU CONSOLE + *---------------------------------------------------------------------*/ +void serial_putc (char c) +{ + int tx_chars; + unsigned status; + + if (c == '\n') + serial_putc ('\r'); + + while (1) { + status = readl(&uart->status); + tx_chars = (status>>YANU_TFIFO_CHARS_POS) + & ((1<<YANU_TFIFO_CHARS_N)-1); + if (tx_chars < YANU_TXFIFO_SIZE-1) + break; + WATCHDOG_RESET (); + } + + writel(&uart->data, (unsigned char)c); +} + +void serial_puts (const char *s) +{ + while (*s != 0) { + serial_putc (*s++); + } +} + + +int serial_tstc(void) +{ + unsigned status ; + + status = readl(&uart->status); + return (((status >> YANU_RFIFO_CHARS_POS) & + ((1 << YANU_RFIFO_CHARS_N) - 1)) > 0); +} + +int serial_getc (void) +{ + while (serial_tstc() == 0) + WATCHDOG_RESET (); + + /* first we pull the char */ + writel(&uart->action, YANU_ACTION_RFIFO_PULL); + + return(readl(&uart->data) & YANU_DATA_CHAR_MASK); +} + +#else /*CONFIG_CONSOLE_YANU*/ + /*------------------------------------------------------------------ * UART the serial port *-----------------------------------------------------------------*/ -#else static nios_uart_t *uart = (nios_uart_t *) CONFIG_SYS_NIOS_CONSOLE; diff --git a/include/nios2-yanu.h b/include/nios2-yanu.h new file mode 100644 index 0000000..e44aa69 --- /dev/null +++ b/include/nios2-yanu.h @@ -0,0 +1,115 @@ +/* + * (C) Copyright 2006, Imagos S.a.s <www.imagos.it> + * Renato Andreola <renato.andreola(a)imagos.it> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************* + * Altera NiosII YANU serial interface by Imagos + * please see http://www.opencores.org/project,yanu for + * information/downloads + ************************************************************************/ + +#ifndef __NIOS2_YANU_H__ +#define __NIOS2_YANU_H__ + +#define YANU_MAX_PRESCALER_N ((1 << 4) - 1) /* 15 */ +#define YANU_MAX_PRESCALER_M ((1 << 11) -1) /* 2047 */ +#define YANU_FIFO_SIZE (16) +#define YANU_RXFIFO_SIZE (YANU_FIFO_SIZE) +#define YANU_TXFIFO_SIZE (YANU_FIFO_SIZE) + +#define YANU_RXFIFO_DLY (10*11) +#define YANU_TXFIFO_THR (10) +#define YANU_DATA_CHAR_MASK (0xFF) + +/* data register */ +#define YANU_DATA_OFFSET (0) /* data register offset */ + +#define YANU_CONTROL_OFFSET (4) /* control register offset */ +/* interrupt enable */ +#define YANU_CONTROL_IE_RRDY (1<<0) /* ie on received character ready */ +#define YANU_CONTROL_IE_OE (1<<1) /* ie on rx overrun */ +#define YANU_CONTROL_IE_BRK (1<<2) /* ie on break detect */ +#define YANU_CONTROL_IE_FE (1<<3) /* ie on framing error */ +#define YANU_CONTROL_IE_PE (1<<4) /* ie on parity error */ +#define YANU_CONTROL_IE_TRDY (1<<5) /* ie interrupt on tranmitter ready */ +/* control bits */ +#define YANU_CONTROL_BITS_POS (6) /* bits number pos */ +#define YANU_CONTROL_BITS (1<<YANU_CONTROL_BITS_POS) /* number of rx/tx bits per word. 3 bit unsigned integer */ +#define YANU_CONTROL_BITS_N (3) /* ... its bit filed length */ +#define YANU_CONTROL_PARENA (1<<9) /* enable parity bit transmission/reception */ +#define YANU_CONTROL_PAREVEN (1<<10) /* parity even */ +#define YANU_CONTROL_STOPS (1<<11) /* number of stop bits */ +#define YANU_CONTROL_HHENA (1<<12) /* Harware Handshake enable... */ +#define YANU_CONTROL_FORCEBRK (1<<13) /* if set than txd = active (0) */ +/* tuning part */ +#define YANU_CONTROL_RDYDLY (1<<14) /* delay from "first" before setting rrdy (in bit) */ +#define YANU_CONTROL_RDYDLY_N (8) /* ... its bit filed length */ +#define YANU_CONTROL_TXTHR (1<<22) /* tx interrupt threshold: the trdy set if txfifo_chars<= txthr (chars) */ +#define YANU_CONTROL_TXTHR_N (4) /* ... its bit field length */ + +#define YANU_BAUD_OFFSET (8) /* baud register offset */ +#define YANU_BAUDM (1<<0) /* baud mantissa lsb */ +#define YANU_BAUDM_N (12) /* ...its bit filed length */ +#define YANU_BAUDE (1<<12) /* baud exponent lsb */ +#define YANU_BAUDE_N (4) /* ...its bit field length */ + +#define YANU_ACTION_OFFSET (12) /* action register... write only */ +#define YANU_ACTION_RRRDY (1<<0) /* reset rrdy */ +#define YANU_ACTION_ROE (1<<1) /* reset oe */ +#define YANU_ACTION_RBRK (1<<2) /* reset brk */ +#define YANU_ACTION_RFE (1<<3) /* reset fe */ +#define YANU_ACTION_RPE (1<<4) /* reset pe */ +#define YANU_ACTION_SRRDY (1<<5) /* set rrdy */ +#define YANU_ACTION_SOE (1<<6) /* set oe */ +#define YANU_ACTION_SBRK (1<<7) /* set brk */ +#define YANU_ACTION_SFE (1<<8) /* set fe */ +#define YANU_ACTION_SPE (1<<9) /* set pe */ +#define YANU_ACTION_RFIFO_PULL (1<<10) /* pull a char from rx fifo we MUST do it before taking a char */ +#define YANU_ACTION_RFIFO_CLEAR (1<<11) /* clear rx fifo */ +#define YANU_ACTION_TFIFO_CLEAR (1<<12) /* clear tx fifo */ +#define YANU_ACTION_RTRDY (1<<13) /* clear trdy */ +#define YANU_ACTION_STRDY (1<<14) /* set trdy */ + +#define YANU_STATUS_OFFSET (16) +#define YANU_STATUS_RRDY (1<<0) /* rxrdy flag */ +#define YANU_STATUS_TRDY (1<<1) /* txrdy flag */ +#define YANU_STATUS_OE (1<<2) /* rx overrun error */ +#define YANU_STATUS_BRK (1<<3) /* rx break detect flag */ +#define YANU_STATUS_FE (1<<4) /* rx framing error flag */ +#define YANU_STATUS_PE (1<<5) /* rx parity erro flag */ +#define YANU_RFIFO_CHARS_POS (6) +#define YANU_RFIFO_CHARS (1<<RFIFO_CHAR_POS) /* number of chars into rx fifo */ +#define YANU_RFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ +#define YANU_TFIFO_CHARS_POS (11) +#define YANU_TFIFO_CHARS (1<<TFIFO_CHAR_POS) /* number of chars into tx fifo */ +#define YANU_TFIFO_CHARS_N (5) /* ...its bit field length: 32 chars */ + +typedef volatile struct yanu_uart_t { + volatile unsigned data; + volatile unsigned control; /* control register (RW) 32-bit */ + volatile unsigned baud; /* baud/prescaler register (RW) 32-bit */ + volatile unsigned action; /* action register (W) 32-bit */ + volatile unsigned status; /* status register (R) 32-bit */ + volatile unsigned magic; /* magic register (R) 32-bit */ +} yanu_uart_t; + +#endif -- 1.5.5

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[U-Boot-Users] [PATCH] add explicit bbt creation to commandline
by Harald Welte 17 Feb '10

17 Feb '10

[PATCH] add explicit bbt creation to commandline ("nand createbbt" command) This patch adds user-requested BBT creation. It includes the following changes: - common/cmd_nand.c: move yes/no decision to separate function - do_nand: ask for confirmation for "nand erase" - do_nand: add command "nand createbbt" to erase NAND and create a new BBT Signed-off-by: Werner Almesberger <werner(a)openmoko.org> Signed-off-by: Harald Welte <laforge(a)openmoko.org> --- diff --git a/common/cmd_nand.c b/common/cmd_nand.c index bb46f34..2f41157 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -162,6 +162,17 @@ out: return 0; } +static int yes(void) +{ + char c; + + c = getc(); + if (c != 'y' && c != 'Y') + return 0; + c = getc(); + return c == '\r' || c == '\n'; +} + int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) { int i, dev, ret; @@ -231,7 +242,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) strncmp(cmd, "read", 4) != 0 && strncmp(cmd, "write", 5) != 0 && strcmp(cmd, "scrub") != 0 && strcmp(cmd, "markbad") != 0 && strcmp(cmd, "biterr") != 0 && - strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 ) + strcmp(cmd, "lock") != 0 && strcmp(cmd, "unlock") != 0 && + strcmp(cmd, "createbbt") != 0 ) goto usage; /* the following commands operate on the current device */ @@ -286,13 +298,23 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) "are sure of what you are doing!\n" "\nReally scrub this NAND flash? <y/N>\n"); - if (getc() == 'y' && getc() == '\r') { + if (yes()) { opts.scrub = 1; } else { puts("scrub aborted\n"); return -1; } } + else { + if (opts.length == nand->size) { + puts("Really erase everything ? <y/N>\n"); + if (!yes()) { + puts("erase aborted\n"); + return -1; + } + } + } + ret = nand_erase_opts(nand, &opts); printf("%s\n", ret ? "ERROR" : "OK"); @@ -461,6 +483,33 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 0; } + if (strcmp(cmd, "createbbt") == 0) { + struct nand_chip *nand_chip = nand->priv; + nand_erase_options_t opts; + + puts("Create BBT and erase everything ? <y/N>\n"); + if (!yes()) { + puts("createbbt aborted\n"); + return -1; + } + memset(&opts, 0, sizeof(opts)); + opts.length = nand->size; + if (nand_erase_opts(nand, &opts)) { + puts("Erase failed\n"); + return 1; + } + nand_chip->options &= ~NAND_DONT_CREATE_BBT; + puts("Creating BBT. Please wait ..."); + if (nand_default_bbt(nand)) { + puts("\nFailed\n"); + return 1; + } + else { + puts("\n"); + return 0; + } + } + usage: printf("Usage:\n%s\n", cmdtp->usage); return 1; @@ -481,7 +530,8 @@ U_BOOT_CMD(nand, 5, 1, do_nand, "nand markbad off - mark bad block at offset (UNSAFE)\n" "nand biterr off - make a bit error at offset (UNSAFE)\n" "nand lock [tight] [status] - bring nand to lock state or display locked pages\n" - "nand unlock [offset] [size] - unlock section\n"); + "nand unlock [offset] [size] - unlock section\n" + "nand createbbt - create bad block table\n"); static int nand_load_image(cmd_tbl_t *cmdtp, nand_info_t *nand, ulong offset, ulong addr, char *cmd) diff --git a/drivers/mtd/nand/nand_bbt.c b/drivers/mtd/nand/nand_bbt.c index 27d5988..3fdc25a 100644 --- a/drivers/mtd/nand/nand_bbt.c +++ b/drivers/mtd/nand/nand_bbt.c @@ -795,7 +795,8 @@ int nand_scan_bbt (struct mtd_info *mtd, struct nand_bbt_descr *bd) len = mtd->size >> (this->bbt_erase_shift + 2); /* Allocate memory (2bit per block) */ - this->bbt = kmalloc (len, GFP_KERNEL); + if (!this->bbt) + this->bbt = kmalloc (len, GFP_KERNEL); if (!this->bbt) { printk (KERN_ERR "nand_scan_bbt: Out of memory\n"); return -ENOMEM; -- - Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)

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[U-Boot] [patch 0/2] Some more USB-OHCI bugfixes [V2]
by Remy Bohmer 01 Feb '10

01 Feb '10

This is version 2 of these series! Only patch 1 of 2 has changed, some pedantic Coding Style issues updated that were not detected by Linux/scripts/checkpatch.pl. The USB OHCI init procedure sets the maximum message length the wrong way. A max of 64 bits should not be done by writing '64' in maxpacketsize, but '3'. While fixing this problem it turned out that there is more wrong here in this code it turned out that the wrong bits were checked to determine if the pipe was of type PIPE_INTERRUPT. This series fixes those errors also. I made it 2 seperate patches. The 1st of this series is fully tested and correct on at least the AT91SAM9261 cores. The 2nd patch, however, is created by search-for-the-same-errors-and-replace. I am not able to test that patch, I do not have the boards, so that needs to be done by others or by review. It is clear that code there is buggy in the first place. These patches require my previous series called 'Improve stability USB memory sticks for the common OHCI USB layer.' to be applied before this series. So they should apply on the u-boot-usb git tree. --> git://git.denx.de/u-boot-usb.git I want to mention also, that everytime I look deeper into this code, I find new bugs. It appears that several parts of this code is written with interrupt handling in mind, while we have no interrupt handling at all. Assumptions are done that a interrupt handler does things asynchronous, causing long loops that have no real use at all... So, no guarantees that _all_ problems are solved by now... --

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