September 2009 - U-Boot

[U-Boot] [PATCH] sbc8349: tidy up Makefile to use new configuration script.
by Paul Gortmaker 26 Sep '09

26 Sep '09

Commit 804d83a5 allows us to move all the configuration variation tweaks out of the top level Makefile and down into the board config header. This takes advantage of that for the sbc8349 board. Signed-off-by: Paul Gortmaker <paul.gortmaker(a)windriver.com> --- Makefile | 15 +-------------- include/configs/sbc8349.h | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/Makefile b/Makefile index 0b61d05..b90be69 100644 --- a/Makefile +++ b/Makefile @@ -2403,20 +2403,7 @@ MVBLM7_config: unconfig sbc8349_config \ sbc8349_PCI_33_config \ sbc8349_PCI_66_config: unconfig - @mkdir -p $(obj)include - @if [ "$(findstring _PCI_,$@)" ] ; then \ - $(XECHO) -n "... PCI HOST at " ; \ - echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _33_,$@)" ] ; then \ - $(XECHO) -n "33MHz... " ; \ - echo "#define PCI_33M" >>$(obj)include/config.h ; \ - fi ; \ - if [ "$(findstring _66_,$@)" ] ; then \ - $(XECHO) -n "66MHz... " ; \ - echo "#define PCI_66M" >>$(obj)include/config.h ; \ - fi ; - @$(MKCONFIG) -a sbc8349 ppc mpc83xx sbc8349 + @$(MKCONFIG) -t $(@:_config=) sbc8349 ppc mpc83xx sbc8349 SIMPC8313_LP_config \ SIMPC8313_SP_config: unconfig diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index e961bb3..6f574ca 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -32,6 +32,21 @@ #define __CONFIG_H /* + * Top level Makefile configuration choices + */ +#ifdef CONFIG_MK_PCI +#define CONFIG_PCI +#endif + +#ifdef CONFIG_MK_66 +#define PCI_66M +#endif + +#ifdef CONFIG_MK_33 +#define PCI_33M +#endif + +/* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -- 1.6.4.1

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[U-Boot] [PATCH] Stay with memory ordering of MDDRC config registers to unbreak mpc5121ads patch
by Martha M Stan 25 Sep '09

25 Sep '09

Used #Defined IDX values so as not to confuse those not familiar with the naming and ordering of the MDDRC config registers. Signed-off-by: Martha M Stan <mmarx(a)silicontkx.com> --- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- cpu/mpc512x/fixed_sdram.c | 26 +++++++++++++++----------- include/asm-ppc/immap_512x.h | 6 ++++++ 3 files changed, 22 insertions(+), 12 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 13bd73c..a5be586 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -170,10 +170,10 @@ phys_size_t initdram(int board_type) * to the Default Micron ones for all but the earliest Rev 4 boards */ u32 elpida_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG0, CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, - CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, }; u32 elpida_init_sequence[] = { diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 673d61e..d92f738 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -26,13 +26,13 @@ #include <asm/mpc512x.h> /* - * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + * MDDRC Config Runtime Settings in MEMORY order of the 4 MDDRC cfg registers */ -u32 default_mddrc_config[4] = { +u32 default_mddrc_regs[4] = { + CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ - CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ - CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ + CONFIG_SYS_MDDRC_TIME_CFG2 /* time_config2 */ }; u32 default_init_seq[] = { @@ -79,11 +79,12 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); + u32 *mddrc_regs; u32 i; /* take default settings and init sequence if necessary */ if (mddrc_config == NULL) - mddrc_config = default_mddrc_config; + mddrc_regs = default_mddrc_regs; if (dram_init_seq == NULL) { dram_init_seq = default_init_seq; seq_sz = sizeof(default_init_seq)/sizeof(u32); @@ -130,18 +131,21 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) * put MDDRC in CMD mode and * set the max time between refreshes to 0 during init process */ - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); - out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); + + out_be32(&im->mddrc.ddr_sys_config, mddrc_regs[MDDRC_SYS_CFG_IDX] + | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, mddrc_regs[MDDRC_TIME_CFG0_IDX] + & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, mddrc_regs[MDDRC_TIME_CFG1_IDX]); + out_be32(&im->mddrc.ddr_time_config2, mddrc_regs[MDDRC_TIME_CFG2_IDX]); /* Initialize DDR with either default or supplied init sequence */ for (i = 0; i < seq_sz; i++) out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_regs[MDDRC_TIME_CFG0_IDX]); + out_be32(&im->mddrc.ddr_sys_config, mddrc_regs[MDDRC_SYS_CFG_IDX]); return msize; } diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 79cdd80..2294b78 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -346,6 +346,12 @@ typedef struct ddr512x { #define MDDRC_SYS_CFG_CMD_MASK 0x10000000 #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF +/* MDDRC registers in memory order */ +#define MDDRC_SYS_CFG_IDX 0 +#define MDDRC_TIME_CFG0_IDX 1 +#define MDDRC_TIME_CFG1_IDX 2 +#define MDDRC_TIME_CFG2_IDX 3 + /* * DMA/Messaging Unit */ -- 1.5.2.4

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Re: [U-Boot] [PATCH] Fixed ordering of MDDRC config registers to unbreak mpc5121ads patch
by m marx 25 Sep '09

25 Sep '09

Then please go back to the original patch where they are in memory order ... it confuses me (or anyone reading the manual) to see it this way since that is not the order of the registers. Very Best Regards, Martha -----Original Message----- From: Wolfgang Denk wd(a)denx.de Sent 9/25/2009 10:17:22 AM To: Martha M Stan mmarx(a)silicontkx.com Cc: u-boot(a)lists.denx.de Subject: Re: [U-Boot] [PATCH] Fixed ordering of MDDRC config registers to unbreak mpc5121ads patch Dear Martha M Stan, In message 1253885565511-git-send-email-mmarx(a)silicontkx.com you wrote: No errors this time Please consider these NAKed, too. Mapping an array on top of a strucxt is just calling for trouble. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de f u cn rd ths, u cn gt a gd jb n cmptr prgrmmng. ��

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[U-Boot] [RFC] Detecting coldstart on kirkwood CPUs
by Simon Kagstrom 25 Sep '09

25 Sep '09

Hi (mostly Prafulla)! I'm looking at detecting cold starts on the OpenRD board (and also maintain the bootcounter via this). I've come up with a slight hack which works in practice for me, but which feels a bit unsafe. What I do is basically to reset the SYSRST duration counter just before doing the soft reset in reset_cpu() (see patch below, I do a similar thing in Linux). I've then added the following function to the board code: #if defined(CONFIG_MISC_INIT_R) # define MS_TO_COUNT(x) ( ((x) * 1000 * 1000) / 40) int misc_init_r (void) { u32 rst_count = 0x1fffffff & readl(KW_REG_SYSRST_CNT); struct uboot_com *p = (struct uboot_com *)CONFIG_BOOTCOUNT_ADDR; /* clear the counter for next valid read*/ writel(1 << 31, KW_REG_SYSRST_CNT); /* If the reset has been held for over 20ms it's a cold-start, * wait for 40 to be sure * * FIXME! This should rely one some more safe metric for the future */ if ( rst_count > MS_TO_COUNT(40) ) { printf("Start type: cold\n"); p->bootcount_magic = 0x12345678; /* Clear the bootcount magic */ p->is_coldstart = is_coldstart = 1; } else { printf("Start type: warm\n"); p->is_coldstart = is_coldstart = 0; } return 0; } #endif i.e., just check how long the reset was held at startup. If it's longer than an empirically determined value (~40ms), then it's a cold start. Pressing the reset button, I always get cold starts (even when tapping as fast as I can), while soft resets are always warm. But... Isn't there some better way of checking this on Kirkwood? // Simon [PATCH] Reset sysrst count before restarting Signed-off-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> --- cpu/arm926ejs/kirkwood/cpu.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/cpu/arm926ejs/kirkwood/cpu.c b/cpu/arm926ejs/kirkwood/cpu.c index bab5faf..d0cdaf6 100644 --- a/cpu/arm926ejs/kirkwood/cpu.c +++ b/cpu/arm926ejs/kirkwood/cpu.c @@ -37,6 +37,7 @@ void reset_cpu(unsigned long ignored) writel(readl(&cpureg->rstoutn_mask) | (1 << 2), &cpureg->rstoutn_mask); + writel(1 << 31, KW_REG_SYSRST_CNT); writel(readl(&cpureg->sys_soft_rst) | 1, &cpureg->sys_soft_rst); while (1) ; -- 1.6.0.4

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[U-Boot] [PATCH] Fixed ordering of MDDRC config registers to unbreak mpc5121ads patch
by Martha M Stan 25 Sep '09

25 Sep '09

No errors this time Signed-off-by: Martha M Stan <mmarx(a)silicontkx.com> --- cpu/mpc512x/fixed_sdram.c | 29 ++++++++++++++++++++--------- 1 files changed, 20 insertions(+), 9 deletions(-) diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 673d61e..1f6295f 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -26,13 +26,13 @@ #include <asm/mpc512x.h> /* - * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + * MDDRC Config Runtime Settings in MEMORY order of the 4 MDDRC cfg registers */ u32 default_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ - CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ - CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ + CONFIG_SYS_MDDRC_TIME_CFG2 /* time_config2 */ }; u32 default_init_seq[] = { @@ -79,6 +79,12 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); + struct ddr512x_4regs { + u32 ddr_sys_config; + u32 ddr_time_config0; + u32 ddr_time_config1; + u32 ddr_time_config2; + } *mddrc_4regs; u32 i; /* take default settings and init sequence if necessary */ @@ -130,18 +136,23 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) * put MDDRC in CMD mode and * set the max time between refreshes to 0 during init process */ - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); - out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); + + /* using mddrc's first 4 regs only */ + mddrc_4regs = (struct ddr512x_4regs *)mddrc_config; + out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config + | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0 + & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, mddrc_4regs->ddr_time_config1); + out_be32(&im->mddrc.ddr_time_config2, mddrc_4regs->ddr_time_config2); /* Initialize DDR with either default or supplied init sequence */ for (i = 0; i < seq_sz; i++) out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0); + out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config); return msize; } -- 1.5.2.4

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[U-Boot] [PATCH] Fixed ordering of MDDRC config registers to unbreak mpc5121ads patch
by Martha M Stan 25 Sep '09

25 Sep '09

3rd time's a charm -- Wolfgang had also changed the Elpida patch one so I fixed the reg ordering in it too. Signed-off-by: Martha M Stan <mmarx(a)silicontkx.com> --- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- cpu/mpc512x/fixed_sdram.c | 29 ++++++++++++++++++++--------- 2 files changed, 21 insertions(+), 10 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 13bd73c..a5be586 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -170,10 +170,10 @@ phys_size_t initdram(int board_type) * to the Default Micron ones for all but the earliest Rev 4 boards */ u32 elpida_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG0, CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, - CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, }; u32 elpida_init_sequence[] = { diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 673d61e..1f6295f 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -26,13 +26,13 @@ #include <asm/mpc512x.h> /* - * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + * MDDRC Config Runtime Settings in MEMORY order of the 4 MDDRC cfg registers */ u32 default_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ - CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ - CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ + CONFIG_SYS_MDDRC_TIME_CFG2 /* time_config2 */ }; u32 default_init_seq[] = { @@ -79,6 +79,12 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); + struct ddr512x_4regs { + u32 ddr_sys_config; + u32 ddr_time_config0; + u32 ddr_time_config1; + u32 ddr_time_config2; + } *mddrc_4regs; u32 i; /* take default settings and init sequence if necessary */ @@ -130,18 +136,23 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) * put MDDRC in CMD mode and * set the max time between refreshes to 0 during init process */ - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); - out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); + + /* using mddrc's first 4 regs only */ + mddrc_4regs = (struct ddr512x_4regs *)mddrc_config; + out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config + | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0 + & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, mddrc_4regs->ddr_time_config1); + out_be32(&im->mddrc.ddr_time_config2, mddrc_4regs->ddr_time_config2); /* Initialize DDR with either default or supplied init sequence */ for (i = 0; i < seq_sz; i++) out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0); + out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config); return msize; } -- 1.5.2.4

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Re: [U-Boot] Broken board: mpc5121ads
by m marx 25 Sep '09

25 Sep '09

Hi Wolfgang, I really don't like the ordering of those registers the way you fixed it last night. My comment before the array was "in order of the 4 mddrc registers" I recommented to "in memory order" If you change it to your way then you should recomment at least. I redid it to save this ordering AND not have confusing array indexes. Please reconsider. -Martha PS - the last patch is the good one ... got flustered and sent the wrong one first and then forgot to fix the reordered ELPIDA settings so I hgad to redo again. -----Original Message----- From: Wolfgang Denk wd(a)denx.de Sent 9/25/2009 8:22:09 AM To: Jerry Van Baren gvb.uboot(a)gmail.com Cc: U-Boot u-boot(a)lists.denx.de, mmarx(a)silicontkx.com Subject: Re: [U-Boot] Broken board: mpc5121ads Dear Jerry Van Baren, In message 4ABC9BCC.9060801(a)gmail.com you wrote: A couple of lines got scrambled (exchanged!?) on the mpc5121. I did not have the time to do a "git bisect" or "blame" to figure out where it happened. The error is: $ cat LOG/mpc5121ads.ERR mpc5121ads.c: In function 'initdram': mpc5121ads.c:176: error: expected '}' before numeric constant make[1]: *** [mpc5121ads.o] Error 1 make: *** [board/freescale/mpc5121ads/libmpc5121ads.a] Error 2 The problem is the list is re-ordered in ./board/freescale/mpc5121ads/mpc5121ads.c u32 elpida_mddrc_config[4] = { CONFIG_SYS_MDDRC_TIME_CFG0, CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA -- should be last? CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, D*mn. I did fix this. I though. And I did run MAKEALL after that. I thought. Doing a quick search in gmain, the code in question was added by Martha M Stan (CC:ed): http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/68478 No, this was not Martha's fault, it was mine. I reordered the array, and messed it up. Sorry. If someone fixes it, that would be great, otherwise I'll look at it tonight. Done. Thanks for pointing out. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de The biggest difference between time and space is that you can't reuse time. - Merrick Furst ��

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[U-Boot] [PATCH] Fixed ordering of MDDRC config registers to unbreak mpc5121ads patch
by Martha M Stan 25 Sep '09

25 Sep '09

Signed-off-by: Martha M Stan <mmarx(a)silicontkx.com> --- cpu/mpc512x/fixed_sdram.c | 23 +++++++++++++++-------- 1 files changed, 15 insertions(+), 8 deletions(-) diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 673d61e..7617e31 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -26,13 +26,14 @@ #include <asm/mpc512x.h> /* - * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + * MDDRC Config Runtime Settings in MEMORY order of the 4 MDDRC cfg registers */ u32 default_mddrc_config[4] = { + CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ - CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ + }; u32 default_init_seq[] = { @@ -79,6 +80,7 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2(msize); + struct ddr512x_t *ddr_cfg_4regs; u32 i; /* take default settings and init sequence if necessary */ @@ -130,18 +132,23 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) * put MDDRC in CMD mode and * set the max time between refreshes to 0 during init process */ - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); - out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); + + /* using struct's first 4 regs only */ + mddrc_4regs = (struct ddr512x_t *)mddrc_config; + out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config + | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0 + & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, mddrc_4regs->ddr_time_config1); + out_be32(&im->mddrc.ddr_time_config2, mddrc_4regs->ddr_time_config2); /* Initialize DDR with either default or supplied init sequence */ for (i = 0; i < seq_sz; i++) out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_4regs->ddr_time_config0); + out_be32(&im->mddrc.ddr_sys_config, mddrc_4regs->ddr_sys_config); return msize; } -- 1.5.2.4

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[U-Boot] Broken board: mpc5121ads
by Jerry Van Baren 25 Sep '09

25 Sep '09

Hi Martha, list, A couple of lines got scrambled (exchanged!?) on the mpc5121. I did not have the time to do a "git bisect" or "blame" to figure out where it happened. The error is: $ cat LOG/mpc5121ads.ERR mpc5121ads.c: In function 'initdram': mpc5121ads.c:176: error: expected '}' before numeric constant make[1]: *** [mpc5121ads.o] Error 1 make: *** [board/freescale/mpc5121ads/libmpc5121ads.a] Error 2 The problem is the list is re-ordered in ./board/freescale/mpc5121ads/mpc5121ads.c u32 elpida_mddrc_config[4] = { CONFIG_SYS_MDDRC_TIME_CFG0, CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA <-- should be last? CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, }; Doing a quick search in gmain, the code in question was added by Martha M Stan (CC:ed): <http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/68478> If someone fixes it, that would be great, otherwise I'll look at it tonight. Thanks, gvb

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[U-Boot] [PATCH] mpc5121ads: fix breakage introduced when reordering elpida_mddrc_config[]
by Wolfgang Denk 25 Sep '09

25 Sep '09

Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- board/freescale/mpc5121ads/mpc5121ads.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 3323d66..13bd73c 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -172,7 +172,7 @@ phys_size_t initdram(int board_type) u32 elpida_mddrc_config[4] = { CONFIG_SYS_MDDRC_TIME_CFG0, CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, - CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA + CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, }; -- 1.6.0.6

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