August 2009 - U-Boot

[U-Boot] PATCH Nios2 kernel bootstrap error due to missing processor data cache flush: fix
by Renato Andreola 06 Aug '09

06 Aug '09

From caddbcecc99d7f96fdf7ca9c3d89ffac9cb999e1 Mon Sep 17 00:00:00 2001 From: Renato Andreola <renato.andreola(a)imagos.it> Date: Thu, 6 Aug 2009 11:03:19 +0200 Subject: Nios2: do_boom_linux(): kernel gunzip input data integrity problem due to mi ssing cache flush Added instruction and data caches flush Signed-off-by: Renato Andreola <renato.andreola(a)imagos.it> --- lib_nios2/bootm.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c index 53fd569..65bb4cb 100644 --- a/lib_nios2/bootm.c +++ b/lib_nios2/bootm.c @@ -24,6 +24,7 @@ #include <common.h> #include <command.h> #include <asm/byteorder.h> +#include <asm/cache.h> int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { @@ -32,6 +33,10 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; + /* flushes data and instruction caches before calling the kernel */ + flush_dcache (0,CONFIG_SYS_DCACHE_SIZE ); + flush_icache (0,CONFIG_SYS_ICACHE_SIZE); + /* For now we assume the Microtronix linux ... which only * needs to be called ;-) */ -- 1.5.5

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[U-Boot] [PATCH] stx: create common vendor hierarchy for Silicon Turnkey boards
by oakad＠yahoo.com 06 Aug '09

06 Aug '09

From: Alex Dubov <oakad(a)yahoo.com> Move board definition files for STx XTC, GP3 and SSA boards into common subdirectory and factor out common code. "-mno-spe" flag common to all MPC85xx configurations does not work so change it to "-mspe=no" which does (GCC bug 37759). Signed-off-by: Alex Dubov <oakad(a)yahoo.com> --- Makefile | 6 +- board/{stxgp3 => stx/common}/Makefile | 20 +++-- board/{stxssa => stx/common}/ddr.c | 46 ++++++++--- board/{stxssa => stx/common}/law.c | 30 ++++--- board/{stxssa => stx/common}/tlb.c | 72 ++++++++++------- board/{ => stx}/stxgp3/Makefile | 3 - board/{ => stx}/stxgp3/config.mk | 0 board/{ => stx}/stxgp3/flash.c | 0 board/{ => stx}/stxgp3/stxgp3.c | 0 board/{ => stx}/stxgp3/u-boot.lds | 0 board/{ => stx}/stxssa/Makefile | 3 - board/{ => stx}/stxssa/config.mk | 0 board/{ => stx}/stxssa/stxssa.c | 0 board/{ => stx}/stxssa/u-boot.lds | 0 board/{ => stx}/stxxtc/Makefile | 0 board/{ => stx}/stxxtc/config.mk | 0 board/{ => stx}/stxxtc/stxxtc.c | 0 board/{ => stx}/stxxtc/u-boot.lds | 0 board/{ => stx}/stxxtc/u-boot.lds.debug | 0 board/stxgp3/ddr.c | 76 ------------------ board/stxgp3/law.c | 58 -------------- board/stxgp3/tlb.c | 130 ------------------------------- cpu/mpc85xx/config.mk | 2 +- include/configs/stxgp3.h | 21 +++-- include/configs/stxssa.h | 28 ++++--- 25 files changed, 135 insertions(+), 360 deletions(-) copy board/{stxgp3 => stx/common}/Makefile (82%) rename board/{stxssa => stx/common}/ddr.c (57%) rename board/{stxssa => stx/common}/law.c (74%) rename board/{stxssa => stx/common}/tlb.c (59%) rename board/{ => stx}/stxgp3/Makefile (95%) rename board/{ => stx}/stxgp3/config.mk (100%) rename board/{ => stx}/stxgp3/flash.c (100%) rename board/{ => stx}/stxgp3/stxgp3.c (100%) rename board/{ => stx}/stxgp3/u-boot.lds (100%) rename board/{ => stx}/stxssa/Makefile (95%) rename board/{ => stx}/stxssa/config.mk (100%) rename board/{ => stx}/stxssa/stxssa.c (100%) rename board/{ => stx}/stxssa/u-boot.lds (100%) rename board/{ => stx}/stxxtc/Makefile (100%) rename board/{ => stx}/stxxtc/config.mk (100%) rename board/{ => stx}/stxxtc/stxxtc.c (100%) rename board/{ => stx}/stxxtc/u-boot.lds (100%) rename board/{ => stx}/stxxtc/u-boot.lds.debug (100%) delete mode 100644 board/stxgp3/ddr.c delete mode 100644 board/stxgp3/law.c delete mode 100644 board/stxgp3/tlb.c diff --git a/Makefile b/Makefile index 8096f91..a445eba 100644 --- a/Makefile +++ b/Makefile @@ -1129,7 +1129,7 @@ SPD823TS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx spd8xx stxxtc_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc + @$(MKCONFIG) $(@:_config=) ppc mpc8xx stxxtc stx svm_sc8xx_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8xx svm_sc8xx @@ -2526,7 +2526,7 @@ socrates_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx socrates stxgp3_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 + @$(MKCONFIG) $(@:_config=) ppc mpc85xx stxgp3 stx stxssa_config \ stxssa_4M_config: unconfig @@ -2535,7 +2535,7 @@ stxssa_4M_config: unconfig echo "#define CONFIG_STXSSA_4M" >>$(obj)include/config.h ; \ $(XECHO) "... with 4 MiB flash memory" ; \ fi - @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa + @$(MKCONFIG) -a stxssa ppc mpc85xx stxssa stx TQM8540_config \ TQM8541_config \ diff --git a/board/stxgp3/Makefile b/board/stx/common/Makefile similarity index 82% copy from board/stxgp3/Makefile copy to board/stx/common/Makefile index 5a68f11..08cc2f9 100644 --- a/board/stxgp3/Makefile +++ b/board/stx/common/Makefile @@ -1,5 +1,5 @@ # -# (C) Copyright 2001-2006 +# (C) Copyright 2006 # Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. # # See file CREDITS for list of people who contributed to this @@ -23,23 +23,25 @@ include $(TOPDIR)/config.mk -LIB = $(obj)lib$(BOARD).a +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif -COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-y += flash.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o +LIB = $(obj)lib$(VENDOR).a + +COBJS-${CONFIG_MPC85xx} += ddr.o +COBJS-${CONFIG_MPC85xx} += law.o +COBJS-${CONFIG_MPC85xx} += tlb.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) -$(LIB): $(obj).depend $(OBJS) $(SOBJS) +$(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) clean: - rm -f $(OBJS) $(SOBJS) + rm -f $(SOBJS) $(OBJS) distclean: clean rm -f $(LIB) core *.bak $(obj).depend diff --git a/board/stxssa/ddr.c b/board/stx/common/ddr.c similarity index 57% rename from board/stxssa/ddr.c rename to board/stx/common/ddr.c index 93d1100..5e7b184 100644 --- a/board/stxssa/ddr.c +++ b/board/stx/common/ddr.c @@ -1,5 +1,6 @@ /* * Copyright 2008 Freescale Semiconductor, Inc. + * Copyright 2009 Alex Dubov <oakad(a)yahoo.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -13,31 +14,33 @@ #include <asm/fsl_ddr_dimm_params.h> static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) +get_spd(ddr2_spd_eeprom_t *spd, unsigned char i2c_address) { +#if defined(CONFIG_FSL_DDR2) + i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr2_spd_eeprom_t)); +#elif defined(CONFIG_FSL_DDR1) i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); +#else +#error DDR type is not defined +#endif } - -unsigned int -fsl_ddr_get_mem_data_rate(void) +unsigned int fsl_ddr_get_mem_data_rate(void) { return get_ddr_freq(0); } - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) +void fsl_ddr_get_spd(ddr2_spd_eeprom_t *ctrl_dimms_spd, unsigned int ctrl_num) { unsigned int i; - unsigned int i2c_address = 0; + + if (ctrl_num) { + printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); + return; + } for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); + get_spd(&(ctrl_dimms_spd[i]), SPD_EEPROM_ADDRESS); } } @@ -46,11 +49,28 @@ void fsl_ddr_board_options(memctl_options_t *popts, unsigned int ctrl_num) { /* + * Factors to consider for clock adjust: + * - number of chips on bus + * - position of slot + * - DDR1 vs. DDR2? + * - ??? + * + * This needs to be determined on a board-by-board basis. + * 0110 3/4 cycle late + * 0111 7/8 cycle late + */ + popts->clk_adjust = 6; + + /* * Factors to consider for CPO: * - frequency * - ddr1 vs. ddr2 */ +#if defined(CONFIG_FSL_DDR2) + popts->cpo_override = 7; +#else popts->cpo_override = 0; +#endif /* * Factors to consider for write data delay: diff --git a/board/stxssa/law.c b/board/stx/common/law.c similarity index 74% rename from board/stxssa/law.c rename to board/stx/common/law.c index 55dde66..a82c99f 100644 --- a/board/stxssa/law.c +++ b/board/stx/common/law.c @@ -1,9 +1,9 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. - * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * + * Copyright 2009 Alex Dubov <oakad(a)yahoo.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,30 +31,34 @@ * LAW(Local Access Window) configuration: * * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xa000_0000 0xbfff_ffff PCI2 MEM 512M + * 0x8000_0000 0x9fff_ffff PCI1 512M + * 0xa000_0000 0xbfff_ffff PCI2 512M + * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff PCI2 IO 16M - * 0xf000_0000 0xfaff_ffff Local bus 128M - * 0xfb00_0000 0xfb00_ffff Config Latch 64K - * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M + * 0xf000_0000 0xffff_ffff LBC options + FLASH 256M * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. + * + * LAW 0 is reserved for boot mapping */ struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), +#ifdef CONFIG_SYS_PCI1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1), +#ifdef CONFIG_SYS_PCI2_MEM_PHYS SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1), SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2), - /* Map the whole localbus, including flash and reset latch. */ - SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC), +#endif +#ifdef CONFIG_SYS_RIO_MEM_PHYS + SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO), +#endif + SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC) }; int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxssa/tlb.c b/board/stx/common/tlb.c similarity index 59% rename from board/stxssa/tlb.c rename to board/stx/common/tlb.c index 0386432..6298eaa 100644 --- a/board/stxssa/tlb.c +++ b/board/stx/common/tlb.c @@ -1,9 +1,9 @@ /* - * Copyright 2008 Freescale Semiconductor, Inc. - * * (C) Copyright 2000 * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. * + * Copyright 2009 Alex Dubov <oakad(a)yahoo.com> + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,76 +31,90 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0), /* - * TLB 0: 64M Non-cacheable, guarded - * 0xfc000000 6M4 FLASH + * TLB 0: 256M Non-cacheable, guarded + * 0xf0000000 256M LBC (FLASH included) * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, + CONFIG_SYS_LBC_OPTION_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), + 0, 0, BOOKE_PAGESZ_256M, 1), /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * TLB 1: 64M Non-cacheable, guarded + * 0xe000_0000 1M CCSRBAR + * 0xe200_0000 1M PCI1 IO + * 0xe210_0000 1M PCI2 IO + * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), + 0, 1, BOOKE_PAGESZ_64M, 1), +#ifdef CONFIG_SYS_RIO_MEM_PHYS /* * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT, CONFIG_SYS_RIO_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), /* * TLB 3: 256M Non-cacheable, guarded - * 0xa0000000 256M PCI2 MEM First half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_VIRT + 0x10000000, + CONFIG_SYS_RIO_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1), +#endif +#ifdef CONFIG_SYS_PCI1_MEM_PHYS /* * TLB 4: 256M Non-cacheable, guarded - * 0xb0000000 256M PCI2 MEM Second half */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_256M, 1), /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - * 0xe300_0000 16M PCI2 IO + * TLB 5: 256M Non-cacheable, guarded */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 5, BOOKE_PAGESZ_256M, 1), +#endif +#ifdef CONFIG_SYS_PCI2_MEM_PHYS /* * TLB 6: 256M Non-cacheable, guarded - * 0xf0000000 Local bus expansion option. - * 0xfb000000 Configuration Latch register (one word) - * 0xfc000000 Up to 64M flash */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT, CONFIG_SYS_PCI2_MEM_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 7: 256M Non-cacheable, guarded + */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_VIRT + 0x10000000, + CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_256M, 1), +#endif }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/stxgp3/Makefile b/board/stx/stxgp3/Makefile similarity index 95% rename from board/stxgp3/Makefile rename to board/stx/stxgp3/Makefile index 5a68f11..dce320c 100644 --- a/board/stxgp3/Makefile +++ b/board/stx/stxgp3/Makefile @@ -26,10 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o COBJS-y += flash.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/stxgp3/config.mk b/board/stx/stxgp3/config.mk similarity index 100% rename from board/stxgp3/config.mk rename to board/stx/stxgp3/config.mk diff --git a/board/stxgp3/flash.c b/board/stx/stxgp3/flash.c similarity index 100% rename from board/stxgp3/flash.c rename to board/stx/stxgp3/flash.c diff --git a/board/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c similarity index 100% rename from board/stxgp3/stxgp3.c rename to board/stx/stxgp3/stxgp3.c diff --git a/board/stxgp3/u-boot.lds b/board/stx/stxgp3/u-boot.lds similarity index 100% rename from board/stxgp3/u-boot.lds rename to board/stx/stxgp3/u-boot.lds diff --git a/board/stxssa/Makefile b/board/stx/stxssa/Makefile similarity index 95% rename from board/stxssa/Makefile rename to board/stx/stxssa/Makefile index 9ab41ec..c0e9798 100644 --- a/board/stxssa/Makefile +++ b/board/stx/stxssa/Makefile @@ -26,9 +26,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS-y += $(BOARD).o -COBJS-y += law.o -COBJS-y += tlb.o -COBJS-$(CONFIG_FSL_DDR1) += ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/stxssa/config.mk b/board/stx/stxssa/config.mk similarity index 100% rename from board/stxssa/config.mk rename to board/stx/stxssa/config.mk diff --git a/board/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c similarity index 100% rename from board/stxssa/stxssa.c rename to board/stx/stxssa/stxssa.c diff --git a/board/stxssa/u-boot.lds b/board/stx/stxssa/u-boot.lds similarity index 100% rename from board/stxssa/u-boot.lds rename to board/stx/stxssa/u-boot.lds diff --git a/board/stxxtc/Makefile b/board/stx/stxxtc/Makefile similarity index 100% rename from board/stxxtc/Makefile rename to board/stx/stxxtc/Makefile diff --git a/board/stxxtc/config.mk b/board/stx/stxxtc/config.mk similarity index 100% rename from board/stxxtc/config.mk rename to board/stx/stxxtc/config.mk diff --git a/board/stxxtc/stxxtc.c b/board/stx/stxxtc/stxxtc.c similarity index 100% rename from board/stxxtc/stxxtc.c rename to board/stx/stxxtc/stxxtc.c diff --git a/board/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds similarity index 100% rename from board/stxxtc/u-boot.lds rename to board/stx/stxxtc/u-boot.lds diff --git a/board/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug similarity index 100% rename from board/stxxtc/u-boot.lds.debug rename to board/stx/stxxtc/u-boot.lds.debug diff --git a/board/stxgp3/ddr.c b/board/stxgp3/ddr.c deleted file mode 100644 index 93d1100..0000000 --- a/board/stxgp3/ddr.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * Version 2 as published by the Free Software Foundation. - */ - -#include <common.h> -#include <i2c.h> - -#include <asm/fsl_ddr_sdram.h> -#include <asm/fsl_ddr_dimm_params.h> - -static void -get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address) -{ - i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t)); -} - - -unsigned int -fsl_ddr_get_mem_data_rate(void) -{ - return get_ddr_freq(0); -} - - -void -fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd, - unsigned int ctrl_num) -{ - unsigned int i; - unsigned int i2c_address = 0; - - for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) { - if (ctrl_num == 0 && i == 0) { - i2c_address = SPD_EEPROM_ADDRESS; - } - get_spd(&(ctrl_dimms_spd[i]), i2c_address); - } -} - -void fsl_ddr_board_options(memctl_options_t *popts, - dimm_params_t *pdimm, - unsigned int ctrl_num) -{ - /* - * Factors to consider for CPO: - * - frequency - * - ddr1 vs. ddr2 - */ - popts->cpo_override = 0; - - /* - * Factors to consider for write data delay: - * - number of DIMMs - * - * 1 = 1/4 clock delay - * 2 = 1/2 clock delay - * 3 = 3/4 clock delay - * 4 = 1 clock delay - * 5 = 5/4 clock delay - * 6 = 3/2 clock delay - */ - popts->write_data_delay = 3; - - /* 2T timing enable */ - popts->twoT_en = 1; - - /* - * Factors to consider for half-strength driver enable: - * - number of DIMMs installed - */ - popts->half_strength_driver_enable = 0; -} diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c deleted file mode 100644 index ba89f0e..0000000 --- a/board/stxgp3/law.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_law.h> -#include <asm/mmu.h> - -/* - * LAW(Local Access Window) configuration: - * - * 0x0000_0000 0x7fff_ffff DDR 2G - * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M - * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M - * 0xfc00_0000 0xfc00_ffff Config Latch 64K - * 0xff00_0000 0xffff_ffff FLASH (boot bank) 16M - * - * Notes: - * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. - * If flash is 8M at default position (last 8M), no LAW needed. - */ - -struct law_entry law_table[] = { -#ifndef CONFIG_SPD_EEPROM - SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR), -#endif - SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), -}; - -int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c deleted file mode 100644 index aa11a5d..0000000 --- a/board/stxgp3/tlb.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * Copyright 2008 Freescale Semiconductor, Inc. - * - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/mmu.h> - -struct fsl_e_tlb_entry tlb_table[] = { - /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - - /* - * TLB 0: 16M Non-cacheable, guarded - * 0xff000000 16M FLASH - * Out of reset this entry is only 4K. - */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), - - /* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Non-cacheable, guarded - * 0xc0000000 256M Rapid IO MEM First half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 4: 256M Non-cacheable, guarded - * 0xd0000000 256M Rapid IO MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 5: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO - */ - SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 7: 16K Non-cacheable, guarded - * 0xfc000000 16K Configuration Latch register - */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif -}; - -int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/cpu/mpc85xx/config.mk b/cpu/mpc85xx/config.mk index 9e574a2..a7d948d 100644 --- a/cpu/mpc85xx/config.mk +++ b/cpu/mpc85xx/config.mk @@ -25,4 +25,4 @@ PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx -DCONFIG_E500 -ffixed-r2 \ -Wa,-me500 -msoft-float -mno-string -PLATFORM_CPPFLAGS +=$(call cc-option,-mno-spe) +PLATFORM_CPPFLAGS +=$(call cc-option,-mspe=no) diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 0424e29..12df277 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -78,6 +78,7 @@ */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_OPTION_BASE 0xf0000000 #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ @@ -195,18 +196,20 @@ /* RapdIO Map configuration, mapped 1:1. */ -#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 -#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE -#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ +#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 +#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_VIRT CONFIG_SYS_RIO_MEM_BASE +#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ /* Standard 8560 PCI addressing, mapped 1:1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 -#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 +#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ #if defined(CONFIG_PCI) /* PCI Ethernet card */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 2783f9e..1d2a52d 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -220,19 +220,21 @@ * Standard 8555 PCI mapping. * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ - -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ +#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ + +#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_VIRT CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 +#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ #if defined(CONFIG_PCI) /* PCI Ethernet card */ #define CONFIG_MPC85XX_PCI2 1 -- 1.5.6.4

5 15

[U-Boot] floating point operation in powerpc
by prathika 06 Aug '09

06 Aug '09

hi all i am porting u-boot on powerpc 440. i am also running a simple hello world application on it and I want to use floating point unit. i have declared a floating point variable like this : /float ftemp; / i am trying to print the floating point value like this: /printf("ftemp=%f\n",ftemp); / i have included "float.h" but still it doesnt print me the exact floating point value. my output is like this: /ftemp=%f / i have not edited MSR register. should i set the bit 18 for using the FPU in PPC? where am I going wrong in using floating point? is there any switch or library that i should include while compiling the hello_world.c? this might be seem very silly, but please help in sorting out this issue. -- Regards, Prathika R

2 1

[U-Boot] IXP425 ethernet & NPE microcode
by Teh Kok How 06 Aug '09

06 Aug '09

Hi; My ixdp425 board boots without Ethernet. The only piece missing is the NPE ucode. Where can I download the NPE microcode that works with u-boot-2009.08-rc1? Thanks. Regards, Teh

1 0

[U-Boot] [PATCH 1/3] A320: driver for FTMAC100 ethernet controller
by Po-Yu Chuang 06 Aug '09

06 Aug '09

This patch adds an FTMAC100 ethernet driver for Faraday A320 evaluation board. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- Index: drivers/net/Makefile =================================================================== RCS file: /usr/local/cvsroot/ctd/u-boot-2009.06/drivers/net/Makefile,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- drivers/net/Makefile 15 Jun 2009 06:47:50 -0000 1.1.1.1 +++ drivers/net/Makefile 16 Jun 2009 13:45:55 -0000 1.2 @@ -38,6 +38,7 @@ COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +COBJS-$(CONFIG_DRIVER_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o Index: drivers/net/ftmac100.c =================================================================== RCS file: drivers/net/ftmac100.c diff -N drivers/net/ftmac100.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ drivers/net/ftmac100.c 23 Jun 2009 06:11:38 -0000 1.4 @@ -0,0 +1,266 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#undef DEBUG + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include "ftmac100.h" + +struct ftmac100_data { + volatile struct ftmac100_txdes txdes[1]; + volatile struct ftmac100_rxdes rxdes[PKTBUFSRX]; + int rx_index; +}; + +/* + * Reset MAC + */ +static void ftmac100_reset (struct eth_device *dev) +{ + volatile struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + ftmac100->maccr = cpu_to_le32 (FTMAC100_MACCR_SW_RST); + + while (le32_to_cpu (ftmac100->maccr) & FTMAC100_MACCR_SW_RST) ; +} + +/* + * Set MAC address + */ +static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac) +{ + volatile struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug ("%s(%x %x)\n", __func__, maddr, laddr); + + ftmac100->mac_madr = cpu_to_le32 (maddr); + ftmac100->mac_ladr = cpu_to_le32 (laddr); +} + +/* + * disable transmitter, receiver + */ +static void ftmac100_halt (struct eth_device *dev) +{ + volatile struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + ftmac100->maccr = cpu_to_le32 (0); +} + +static int ftmac100_init (struct eth_device *dev, bd_t * bd) +{ + volatile struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_txdes *txdes = priv->txdes; + volatile struct ftmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug ("%s()\n", __func__); + + ftmac100_reset (dev); + + /* set the ethernet address */ + + ftmac100_set_mac (dev, dev->enetaddr); + + /* disable all interrupts */ + + ftmac100->imr = cpu_to_le32 (0); + + /* initialize descriptors */ + + priv->rx_index = 0; + + txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR; + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes2 = (unsigned int)NetRxPackets[i]; + rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN); + rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN; + } + + /* transmit ring */ + + ftmac100->txr_badr = cpu_to_le32 (txdes); + + /* receive ring */ + + ftmac100->rxr_badr = cpu_to_le32 (rxdes); + + /* poll receive descriptor automatically */ + + ftmac100->aptc = cpu_to_le32 (FTMAC100_APTC_RXPOLL_CNT (1)); + + /* enable transmitter, receiver */ + + maccr = FTMAC100_MACCR_XMT_EN | + FTMAC100_MACCR_RCV_EN | + FTMAC100_MACCR_XDMA_EN | + FTMAC100_MACCR_RDMA_EN | + FTMAC100_MACCR_CRC_APD | + FTMAC100_MACCR_ENRX_IN_HALFTX | + FTMAC100_MACCR_RX_RUNT | + FTMAC100_MACCR_RX_BROADPKT; + + ftmac100->maccr = cpu_to_le32 (maccr); + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftmac100_recv (struct eth_device *dev) +{ + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN) + return -1; + + if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR | + FTMAC100_RXDES0_CRC_ERR | + FTMAC100_RXDES0_FTL | + FTMAC100_RXDES0_RUNT | + FTMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0); + + debug ("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + + NetReceive ((void *)curr_des->rxdes2, rxlen); + + /* release buffer to DMA */ + + curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int +ftmac100_send (struct eth_device *dev, volatile void *packet, int length) +{ + volatile struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_txdes *curr_des = priv->txdes; + int tmo; + + if (curr_des->txdes0 & FTMAC100_TXDES0_TXPKT_TXDMA_OWN) { + debug ("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug ("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < 64) ? 64 : length; + + /* initiate a transmit sequence */ + + curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */ + + curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR; + curr_des->txdes1 |= FTMAC100_TXDES1_FTS | + FTMAC100_TXDES1_LTS | + FTMAC100_TXDES1_TXBUF_SIZE (length); + + curr_des->txdes0 = FTMAC100_TXDES0_TXPKT_TXDMA_OWN; + + /* start transmit */ + + ftmac100->txpd = cpu_to_le32 (1); + + /* wait for transfer to succeed */ + + tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; + while (curr_des->txdes0 & FTMAC100_TXDES0_TXPKT_TXDMA_OWN) { + if (get_timer (0) >= tmo) { + debug ("%s(): timed out\n", __func__); + return -1; + } + } + + debug ("%s(): packet sent\n", __func__); + + return 0; +} + +int ftmac100_initialize (bd_t * bd) +{ + struct eth_device *dev; + struct ftmac100_data *priv; + + if (!(dev = malloc (sizeof *dev))) { + printf ("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + + if (!(priv = memalign (16, sizeof (struct ftmac100_data)))) { + printf ("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset (dev, 0, sizeof (*dev)); + memset (priv, 0, sizeof (*priv)); + + sprintf (dev->name, "FTMAC100"); + dev->iobase = CONFIG_SYS_MAC100_BASE; + dev->init = ftmac100_init; + dev->halt = ftmac100_halt; + dev->send = ftmac100_send; + dev->recv = ftmac100_recv; + dev->priv = priv; + + eth_register (dev); + + return 1; + +free_dev: + free (dev); +out: + return 0; +} Index: drivers/net/ftmac100.h =================================================================== RCS file: drivers/net/ftmac100.h diff -N drivers/net/ftmac100.h --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ drivers/net/ftmac100.h 23 Jun 2009 06:11:38 -0000 1.3 @@ -0,0 +1,154 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __FTMAC100_H +#define __FTMAC100_H + +struct ftmac100 { + unsigned int isr; /* 0x00 */ + unsigned int imr; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int itc; /* 0x28 */ + unsigned int aptc; /* 0x2c */ + unsigned int dblac; /* 0x30 */ + unsigned int pad1[3]; /* 0x34 - 0x3c */ + unsigned int pad2[16]; /* 0x40 - 0x7c */ + unsigned int pad3[2]; /* 0x80 - 0x84 */ + unsigned int maccr; /* 0x88 */ + unsigned int macsr; /* 0x8c */ + unsigned int phycr; /* 0x90 */ + unsigned int phywdata; /* 0x94 */ + unsigned int fcr; /* 0x98 */ + unsigned int bpr; /* 0x9c */ + unsigned int pad4[8]; /* 0xa0 - 0xbc */ + unsigned int pad5; /* 0xc0 */ + unsigned int ts; /* 0xc4 */ + unsigned int dmafifos; /* 0xc8 */ + unsigned int tm; /* 0xcc */ + unsigned int pad6; /* 0xd0 */ + unsigned int tx_mcol_scol; /* 0xd4 */ + unsigned int rpf_aep; /* 0xd8 */ + unsigned int xm_pg; /* 0xdc */ + unsigned int runt_tlcc; /* 0xe0 */ + unsigned int crcer_ftl; /* 0xe4 */ + unsigned int rlc_rcc; /* 0xe8 */ + unsigned int broc; /* 0xec */ + unsigned int mulca; /* 0xf0 */ + unsigned int rp; /* 0xf4 */ + unsigned int xp; /* 0xf8 */ +}; + +/* + * Interrupt status register & interrupt mask register + */ +#define FTMAC100_INT_RPKT_FINISH (1 << 0) +#define FTMAC100_INT_NORXBUF (1 << 1) +#define FTMAC100_INT_XPKT_FINISH (1 << 2) +#define FTMAC100_INT_NOTXBUF (1 << 3) +#define FTMAC100_INT_XPKT_OK (1 << 4) +#define FTMAC100_INT_XPKT_LOST (1 << 5) +#define FTMAC100_INT_RPKT_SAV (1 << 6) +#define FTMAC100_INT_RPKT_LOST (1 << 7) +#define FTMAC100_INT_AHB_ERR (1 << 8) +#define FTMAC100_INT_PHYSTS_CHG (1 << 9) + +/* + * Automatic polling timer control register + */ +#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * MAC control register + */ +#define FTMAC100_MACCR_XDMA_EN (1 << 0) +#define FTMAC100_MACCR_RDMA_EN (1 << 1) +#define FTMAC100_MACCR_SW_RST (1 << 2) +#define FTMAC100_MACCR_LOOP_EN (1 << 3) +#define FTMAC100_MACCR_CRC_DIS (1 << 4) +#define FTMAC100_MACCR_XMT_EN (1 << 5) +#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) +#define FTMAC100_MACCR_RCV_EN (1 << 8) +#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) +#define FTMAC100_MACCR_RX_RUNT (1 << 10) +#define FTMAC100_MACCR_RX_FTL (1 << 11) +#define FTMAC100_MACCR_RCV_ALL (1 << 12) +#define FTMAC100_MACCR_CRC_APD (1 << 14) +#define FTMAC100_MACCR_FULLDUP (1 << 15) +#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTMAC100_MACCR_RX_BROADPKT (1 << 17) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* TXBUF_BADR */ + unsigned int txdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) +#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) +#define FTMAC100_TXDES0_TXPKT_TXDMA_OWN (1 << 31) + +#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_TXDES1_LTS (1 << 27) +#define FTMAC100_TXDES1_FTS (1 << 28) +#define FTMAC100_TXDES1_TX2FIC (1 << 29) +#define FTMAC100_TXDES1_TXIC (1 << 30) +#define FTMAC100_TXDES1_EDOTR (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* RXBUF_BADR */ + unsigned int rxdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) +#define FTMAC100_RXDES0_MULTICAST (1 << 16) +#define FTMAC100_RXDES0_BROADCAST (1 << 17) +#define FTMAC100_RXDES0_RX_ERR (1 << 18) +#define FTMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTMAC100_RXDES0_FTL (1 << 20) +#define FTMAC100_RXDES0_RUNT (1 << 21) +#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTMAC100_RXDES0_LRS (1 << 28) +#define FTMAC100_RXDES0_FRS (1 << 29) +#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) + +#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_RXDES1_EDORR (1 << 31) + +#endif /* __FTMAC100_H */ Index: include/netdev.h =================================================================== RCS file: /usr/local/cvsroot/ctd/u-boot-2009.06/include/netdev.h,v retrieving revision 1.1.1.1 retrieving revision 1.2 diff -u -r1.1.1.1 -r1.2 --- include/netdev.h 15 Jun 2009 06:48:01 -0000 1.1.1.1 +++ include/netdev.h 16 Jun 2009 13:45:56 -0000 1.2 @@ -49,6 +49,7 @@ int eepro100_initialize(bd_t *bis); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); +int ftmac100_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); int inca_switch_initialize(bd_t *bis);

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[U-Boot] Updating u-boot through tftp
by alex889 06 Aug '09

06 Aug '09

Hi, I'm running u-boot on TI's davinci DM365, I'm trying to update the u-boot from the u-boot, using these commands: tftp 0x80700000 u-boot-1.3.4_ipnc_dm36x_xxx.bin nand erase 0x2C000 0x20000 nand write 0x80700000 0x2C000 0x20000 but when i try to run the erase command, i'm getting this error: DM365 EVM :>nand erase 0x2c000 0x20000 NAND erase: device 0 offset 0x2c000, size 0x20000 NAND 256MiB 3,3V 8-bit: MTD Erase failure: -22 How can i do it? is this part locked? Thanks, Alex -- View this message in context: http://www.nabble.com/-U-Boot--Updating-u-boot-through-tftp-tp24825617p2482… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] [PATCH 1/2] 85xx: CONFIG_MP Boot Page Translation update
by Peter Tyser 05 Aug '09

05 Aug '09

Previously, when CONFIG_MP was defined Boot Page Translation was unconditionally enabled and secondary cores were put in a spin loop at address 0xfffff000. The 0xfffffxxx address range (ie the Boot Page) was being remapped to SDRAM via the BPTR register. This change puts secondary cores into spin loops at their 'true' address in SDRAM and doesn't require Boot Page Translation to always be enabled. The main advantage of this change is that Boot Page Translation can be disabled after the secondary cores are brought up which allows the memory region at 0xfffffxxx to be used for other peripherals, etc. By default, Boot Page Translation remains enabled while U-Boot executes. A new CONFIG_MPC8xxx_DISABLE_BPTR define has been added which causes Boot Page Translation to be disabled for those boards which wish to use the 0xfffffxxx address range as part of their normal memory map. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- This is very similar to "85xx: Fix mapping of 0xfffffxxx when CONFIG_MP" The 2 differences are: - Boot page translation is only disabled when CONFIG_MPC8xxx_DISABLT_BPTR is defined. - Instead of zeroing out BPTR when disabling translation, this patch only disables translation, but maintins the translation address. This should make it easier to properly re-enable translation if need be. cpu/mpc85xx/mp.c | 22 ++++++++++++++++++++-- cpu/mpc85xx/release.S | 30 +++++++++++++++++++++++++----- 2 files changed, 45 insertions(+), 7 deletions(-) diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c index 76f02a4..53fc3be 100644 --- a/cpu/mpc85xx/mp.c +++ b/cpu/mpc85xx/mp.c @@ -129,7 +129,7 @@ ulong get_spin_addr(void) ulong addr = (ulong)&__spin_table - (ulong)&__secondary_start_page; - addr += 0xfffff000; + addr += determine_mp_bootpg(); return addr; } @@ -137,7 +137,8 @@ ulong get_spin_addr(void) static void pq3_mp_up(unsigned long bootpg) { u32 up, cpu_up_mask, whoami; - u32 *table = (u32 *)get_spin_addr(); + /* The table is at 0xfffffxxx due to boot page translation below */ + u32 *table = (u32 *)(0xfffff000 | get_spin_addr()); volatile u32 bpcr; volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -146,6 +147,8 @@ static void pq3_mp_up(unsigned long bootpg) int timeout = 10; whoami = in_be32(&pic->whoami); + + /* Translate 0xfffffxxx 'bootpg' address range to SDRAM */ out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); /* disable time base at the platform */ @@ -194,6 +197,17 @@ static void pq3_mp_up(unsigned long bootpg) devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); out_be32(&gur->devdisr, devdisr); + +#ifdef CONFIG_MPC8xxx_DISABLE_BPTR + /* + * Disabling Boot Page Translation allows the memory region 0xfffff000 + * to 0xffffffff to be used normally. Leaving Boot Page Translation + * enabled remaps 0xfffff000 to SDRAM which makes that memory region + * unusable for normal operation but it does allow OSes to easily + * reset a processor core to put it back into U-Boot's spinloop. + */ + out_be32(&ecm->bptr, in_be32(&ecm->bptr) & ~0x80000000); +#endif } void cpu_mp_lmb_reserve(struct lmb *lmb) @@ -206,9 +220,13 @@ void cpu_mp_lmb_reserve(struct lmb *lmb) void setup_mp(void) { extern ulong __secondary_start_page; + extern ulong __bootpg_addr; ulong fixup = (ulong)&__secondary_start_page; u32 bootpg = determine_mp_bootpg(); + /* Store the bootpg's SDRAM address for use by secondary CPU cores */ + __bootpg_addr = bootpg; + memcpy((void *)bootpg, (void *)fixup, 4096); flush_cache(bootpg, 4096); diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S index fbefc2c..6799633 100644 --- a/cpu/mpc85xx/release.S +++ b/cpu/mpc85xx/release.S @@ -114,23 +114,38 @@ __secondary_start_page: stw r3,ENTRY_R6_UPPER(r10) stw r3,ENTRY_R6_LOWER(r10) + /* load r13 with the address of the 'bootpg' in SDRAM */ + lis r13,toreset(__bootpg_addr)@h + ori r13,r13,toreset(__bootpg_addr)@l + lwz r13,0(r13) + /* setup mapping for AS = 1, and jump there */ lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h mtspr SPRN_MAS0,r11 lis r11,(MAS1_VALID|MAS1_IPROT)@h ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l mtspr SPRN_MAS1,r11 - lis r11,(0xfffff000|MAS2_I)@h - ori r11,r11,(0xfffff000|MAS2_I)@l + oris r11,r13,(MAS2_I)@h + ori r11,r13,(MAS2_I)@l mtspr SPRN_MAS2,r11 - lis r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@h - ori r11,r11,(0xfffff000|MAS3_SX|MAS3_SW|MAS3_SR)@l + oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h + ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l mtspr SPRN_MAS3,r11 tlbwe bl 1f 1: mflr r11 - addi r11,r11,28 + /* + * OR in 0xfff to create a mask of the bootpg SDRAM address. We use + * this mask to fixup the cpu spin table and the address that we want + * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the + * bootpg is at 0x7ffff000 in SDRAM. + */ + ori r13,r13,0xfff + and r11, r11, r13 + and r10, r10, r13 + + addi r11,r11,(2f-1b) mfmsr r13 ori r12,r13,MSR_IS|MSR_DS@l @@ -200,6 +215,11 @@ __secondary_start_page: mtspr SPRN_SRR1,r13 rfi + /* Allocate some space for the SDRAM address of the bootpg */ + .globl __bootpg_addr +__bootpg_addr: + .long 0 + .align L1_CACHE_SHIFT .globl __spin_table __spin_table: -- 1.6.2.1

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Re: [U-Boot] [PATCH 1/3 v3] arm: A320: driver for FTMAC100 ethernet controller
by Po-Yu Chuang 05 Aug '09

05 Aug '09

This patch adds an FTMAC100 Ethernet driver for Faraday A320 evaluation board. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- drivers/net/Makefile | 1 + drivers/net/ftmac100.c | 278 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/net/ftmac100.h | 154 ++++++++++++++++++++++++++ include/netdev.h | 1 + 4 files changed, 434 insertions(+), 0 deletions(-) create mode 100644 drivers/net/ftmac100.c create mode 100644 drivers/net/ftmac100.h diff --git a/drivers/net/Makefile b/drivers/net/Makefile index c6097c3..8edf529 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -38,6 +38,7 @@ COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o +COBJS-$(CONFIG_DRIVER_FTMAC100) += ftmac100.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_KIRKWOOD_EGIGA) += kirkwood_egiga.o diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c new file mode 100644 index 0000000..3f2b111 --- /dev/null +++ b/drivers/net/ftmac100.c @@ -0,0 +1,278 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#undef DEBUG + +#include <config.h> +#include <common.h> +#include <malloc.h> +#include <net.h> +#include <asm/io.h> + +#include "ftmac100.h" + +struct ftmac100_data { + volatile struct ftmac100_txdes txdes[1]; + volatile struct ftmac100_rxdes rxdes[PKTBUFSRX]; + int rx_index; +}; + +/* + * Reset MAC + */ +static void ftmac100_reset (struct eth_device *dev) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + writel (FTMAC100_MACCR_SW_RST, &ftmac100->maccr); + + while (readl (&ftmac100->maccr) & FTMAC100_MACCR_SW_RST) + ; +} + +/* + * Set MAC address + */ +static void ftmac100_set_mac (struct eth_device *dev, const unsigned char *mac) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + unsigned int maddr = mac[0] << 8 | mac[1]; + unsigned int laddr = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5]; + + debug ("%s(%x %x)\n", __func__, maddr, laddr); + + writel (maddr, &ftmac100->mac_madr); + writel (laddr, &ftmac100->mac_ladr); +} + +static void ftmac100_set_mac_from_env (struct eth_device *dev) +{ + eth_getenv_enetaddr ("ethaddr", dev->enetaddr); + + ftmac100_set_mac (dev, dev->enetaddr); +} + +/* + * disable transmitter, receiver + */ +static void ftmac100_halt (struct eth_device *dev) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + + debug ("%s()\n", __func__); + + writel (0, &ftmac100->maccr); +} + +static int ftmac100_init (struct eth_device *dev, bd_t *bd) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_txdes *txdes = priv->txdes; + volatile struct ftmac100_rxdes *rxdes = priv->rxdes; + unsigned int maccr; + int i; + + debug ("%s()\n", __func__); + + ftmac100_reset (dev); + + /* set the ethernet address */ + + ftmac100_set_mac_from_env (dev); + + /* disable all interrupts */ + + writel (0, &ftmac100->imr); + + /* initialize descriptors */ + + priv->rx_index = 0; + + txdes[0].txdes1 = FTMAC100_TXDES1_EDOTR; + rxdes[PKTBUFSRX - 1].rxdes1 = FTMAC100_RXDES1_EDORR; + + for (i = 0; i < PKTBUFSRX; i++) { + /* RXBUF_BADR */ + rxdes[i].rxdes2 = (unsigned int)NetRxPackets[i]; + rxdes[i].rxdes1 |= FTMAC100_RXDES1_RXBUF_SIZE (PKTSIZE_ALIGN); + rxdes[i].rxdes0 = FTMAC100_RXDES0_RXDMA_OWN; + } + + /* transmit ring */ + + writel ((unsigned int)txdes, &ftmac100->txr_badr); + + /* receive ring */ + + writel ((unsigned int)rxdes, &ftmac100->rxr_badr); + + /* poll receive descriptor automatically */ + + writel (FTMAC100_APTC_RXPOLL_CNT (1), &ftmac100->aptc); + + /* enable transmitter, receiver */ + + maccr = FTMAC100_MACCR_XMT_EN | + FTMAC100_MACCR_RCV_EN | + FTMAC100_MACCR_XDMA_EN | + FTMAC100_MACCR_RDMA_EN | + FTMAC100_MACCR_CRC_APD | + FTMAC100_MACCR_ENRX_IN_HALFTX | + FTMAC100_MACCR_RX_RUNT | + FTMAC100_MACCR_RX_BROADPKT; + + writel (maccr, &ftmac100->maccr); + + return 0; +} + +/* + * Get a data block via Ethernet + */ +static int ftmac100_recv (struct eth_device *dev) +{ + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_rxdes *curr_des; + unsigned short rxlen; + + curr_des = &priv->rxdes[priv->rx_index]; + + if (curr_des->rxdes0 & FTMAC100_RXDES0_RXDMA_OWN) + return -1; + + if (curr_des->rxdes0 & (FTMAC100_RXDES0_RX_ERR | + FTMAC100_RXDES0_CRC_ERR | + FTMAC100_RXDES0_FTL | + FTMAC100_RXDES0_RUNT | + FTMAC100_RXDES0_RX_ODD_NB)) { + return -1; + } + + rxlen = FTMAC100_RXDES0_RFL (curr_des->rxdes0); + + debug ("%s(): RX buffer %d, %x received\n", + __func__, priv->rx_index, rxlen); + + /* pass the packet up to the protocol layers. */ + + NetReceive ((void *)curr_des->rxdes2, rxlen); + + /* release buffer to DMA */ + + curr_des->rxdes0 |= FTMAC100_RXDES0_RXDMA_OWN; + + priv->rx_index = (priv->rx_index + 1) % PKTBUFSRX; + + return 0; +} + +/* + * Send a data block via Ethernet + */ +static int +ftmac100_send (struct eth_device *dev, volatile void *packet, int length) +{ + struct ftmac100 *ftmac100 = (struct ftmac100 *)dev->iobase; + struct ftmac100_data *priv = dev->priv; + volatile struct ftmac100_txdes *curr_des = priv->txdes; + int tmo; + + if (curr_des->txdes0 & FTMAC100_TXDES0_TXPKT_TXDMA_OWN) { + debug ("%s(): no TX descriptor available\n", __func__); + return -1; + } + + debug ("%s(%x, %x)\n", __func__, (int)packet, length); + + length = (length < 64) ? 64 : length; + + /* initiate a transmit sequence */ + + curr_des->txdes2 = (unsigned int)packet; /* TXBUF_BADR */ + + curr_des->txdes1 &= FTMAC100_TXDES1_EDOTR; + curr_des->txdes1 |= FTMAC100_TXDES1_FTS | + FTMAC100_TXDES1_LTS | + FTMAC100_TXDES1_TXBUF_SIZE (length); + + curr_des->txdes0 = FTMAC100_TXDES0_TXPKT_TXDMA_OWN; + + /* start transmit */ + + writel (1, &ftmac100->txpd); + + /* wait for transfer to succeed */ + + tmo = get_timer (0) + 5 * CONFIG_SYS_HZ; + while (curr_des->txdes0 & FTMAC100_TXDES0_TXPKT_TXDMA_OWN) { + if (get_timer (0) >= tmo) { + debug ("%s(): timed out\n", __func__); + return -1; + } + } + + debug ("%s(): packet sent\n", __func__); + + return 0; +} + +int ftmac100_initialize (bd_t *bd) +{ + struct eth_device *dev; + struct ftmac100_data *priv; + + dev = malloc (sizeof *dev); + if (!dev) { + printf ("%s(): failed to allocate dev\n", __func__); + goto out; + } + + /* Transmit and receive descriptors should align to 16 bytes */ + + priv = memalign (16, sizeof (struct ftmac100_data)); + if (!priv) { + printf ("%s(): failed to allocate priv\n", __func__); + goto free_dev; + } + + memset (dev, 0, sizeof (*dev)); + memset (priv, 0, sizeof (*priv)); + + sprintf (dev->name, "FTMAC100"); + dev->iobase = CONFIG_SYS_MAC100_BASE; + dev->init = ftmac100_init; + dev->halt = ftmac100_halt; + dev->send = ftmac100_send; + dev->recv = ftmac100_recv; + dev->priv = priv; + + eth_register (dev); + + return 1; + +free_dev: + free (dev); +out: + return 0; +} diff --git a/drivers/net/ftmac100.h b/drivers/net/ftmac100.h new file mode 100644 index 0000000..49c508e --- /dev/null +++ b/drivers/net/ftmac100.h @@ -0,0 +1,154 @@ +/* + * Faraday FTMAC100 Ethernet + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __FTMAC100_H +#define __FTMAC100_H + +struct ftmac100 { + unsigned int isr; /* 0x00 */ + unsigned int imr; /* 0x04 */ + unsigned int mac_madr; /* 0x08 */ + unsigned int mac_ladr; /* 0x0c */ + unsigned int maht0; /* 0x10 */ + unsigned int maht1; /* 0x14 */ + unsigned int txpd; /* 0x18 */ + unsigned int rxpd; /* 0x1c */ + unsigned int txr_badr; /* 0x20 */ + unsigned int rxr_badr; /* 0x24 */ + unsigned int itc; /* 0x28 */ + unsigned int aptc; /* 0x2c */ + unsigned int dblac; /* 0x30 */ + unsigned int pad1[3]; /* 0x34 - 0x3c */ + unsigned int pad2[16]; /* 0x40 - 0x7c */ + unsigned int pad3[2]; /* 0x80 - 0x84 */ + unsigned int maccr; /* 0x88 */ + unsigned int macsr; /* 0x8c */ + unsigned int phycr; /* 0x90 */ + unsigned int phywdata; /* 0x94 */ + unsigned int fcr; /* 0x98 */ + unsigned int bpr; /* 0x9c */ + unsigned int pad4[8]; /* 0xa0 - 0xbc */ + unsigned int pad5; /* 0xc0 */ + unsigned int ts; /* 0xc4 */ + unsigned int dmafifos; /* 0xc8 */ + unsigned int tm; /* 0xcc */ + unsigned int pad6; /* 0xd0 */ + unsigned int tx_mcol_scol; /* 0xd4 */ + unsigned int rpf_aep; /* 0xd8 */ + unsigned int xm_pg; /* 0xdc */ + unsigned int runt_tlcc; /* 0xe0 */ + unsigned int crcer_ftl; /* 0xe4 */ + unsigned int rlc_rcc; /* 0xe8 */ + unsigned int broc; /* 0xec */ + unsigned int mulca; /* 0xf0 */ + unsigned int rp; /* 0xf4 */ + unsigned int xp; /* 0xf8 */ +}; + +/* + * Interrupt status register & interrupt mask register + */ +#define FTMAC100_INT_RPKT_FINISH (1 << 0) +#define FTMAC100_INT_NORXBUF (1 << 1) +#define FTMAC100_INT_XPKT_FINISH (1 << 2) +#define FTMAC100_INT_NOTXBUF (1 << 3) +#define FTMAC100_INT_XPKT_OK (1 << 4) +#define FTMAC100_INT_XPKT_LOST (1 << 5) +#define FTMAC100_INT_RPKT_SAV (1 << 6) +#define FTMAC100_INT_RPKT_LOST (1 << 7) +#define FTMAC100_INT_AHB_ERR (1 << 8) +#define FTMAC100_INT_PHYSTS_CHG (1 << 9) + +/* + * Automatic polling timer control register + */ +#define FTMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) +#define FTMAC100_APTC_RXPOLL_TIME_SEL (1 << 4) +#define FTMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) +#define FTMAC100_APTC_TXPOLL_TIME_SEL (1 << 12) + +/* + * MAC control register + */ +#define FTMAC100_MACCR_XDMA_EN (1 << 0) +#define FTMAC100_MACCR_RDMA_EN (1 << 1) +#define FTMAC100_MACCR_SW_RST (1 << 2) +#define FTMAC100_MACCR_LOOP_EN (1 << 3) +#define FTMAC100_MACCR_CRC_DIS (1 << 4) +#define FTMAC100_MACCR_XMT_EN (1 << 5) +#define FTMAC100_MACCR_ENRX_IN_HALFTX (1 << 6) +#define FTMAC100_MACCR_RCV_EN (1 << 8) +#define FTMAC100_MACCR_HT_MULTI_EN (1 << 9) +#define FTMAC100_MACCR_RX_RUNT (1 << 10) +#define FTMAC100_MACCR_RX_FTL (1 << 11) +#define FTMAC100_MACCR_RCV_ALL (1 << 12) +#define FTMAC100_MACCR_CRC_APD (1 << 14) +#define FTMAC100_MACCR_FULLDUP (1 << 15) +#define FTMAC100_MACCR_RX_MULTIPKT (1 << 16) +#define FTMAC100_MACCR_RX_BROADPKT (1 << 17) + +/* + * Transmit descriptor, aligned to 16 bytes + */ +struct ftmac100_txdes { + unsigned int txdes0; + unsigned int txdes1; + unsigned int txdes2; /* TXBUF_BADR */ + unsigned int txdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_TXDES0_TXPKT_LATECOL (1 << 0) +#define FTMAC100_TXDES0_TXPKT_EXSCOL (1 << 1) +#define FTMAC100_TXDES0_TXPKT_TXDMA_OWN (1 << 31) + +#define FTMAC100_TXDES1_TXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_TXDES1_LTS (1 << 27) +#define FTMAC100_TXDES1_FTS (1 << 28) +#define FTMAC100_TXDES1_TX2FIC (1 << 29) +#define FTMAC100_TXDES1_TXIC (1 << 30) +#define FTMAC100_TXDES1_EDOTR (1 << 31) + +/* + * Receive descriptor, aligned to 16 bytes + */ +struct ftmac100_rxdes { + unsigned int rxdes0; + unsigned int rxdes1; + unsigned int rxdes2; /* RXBUF_BADR */ + unsigned int rxdes3; /* not used by HW */ +} __attribute__ ((aligned(16))); + +#define FTMAC100_RXDES0_RFL(des) ((des) & 0x7ff) +#define FTMAC100_RXDES0_MULTICAST (1 << 16) +#define FTMAC100_RXDES0_BROADCAST (1 << 17) +#define FTMAC100_RXDES0_RX_ERR (1 << 18) +#define FTMAC100_RXDES0_CRC_ERR (1 << 19) +#define FTMAC100_RXDES0_FTL (1 << 20) +#define FTMAC100_RXDES0_RUNT (1 << 21) +#define FTMAC100_RXDES0_RX_ODD_NB (1 << 22) +#define FTMAC100_RXDES0_LRS (1 << 28) +#define FTMAC100_RXDES0_FRS (1 << 29) +#define FTMAC100_RXDES0_RXDMA_OWN (1 << 31) + +#define FTMAC100_RXDES1_RXBUF_SIZE(x) ((x) & 0x7ff) +#define FTMAC100_RXDES1_EDORR (1 << 31) + +#endif /* __FTMAC100_H */ diff --git a/include/netdev.h b/include/netdev.h index aed5c4c..88e286f 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -50,6 +50,7 @@ int e1000_initialize(bd_t *bis); int eepro100_initialize(bd_t *bis); int eth_3com_initialize (bd_t * bis); int fec_initialize (bd_t *bis); +int ftmac100_initialize(bd_t *bits); int greth_initialize(bd_t *bis); void gt6426x_eth_initialize(bd_t *bis); int inca_switch_initialize(bd_t *bis); -- 1.6.3.3

2 1

[U-Boot] [PATCH v4] Add support for KMC KZM-ARM11-01 board
by Tomohiro Masubuchi 05 Aug '09

05 Aug '09

Hi, This patch adds support for KMC KZM-ARM11-01. It was rebased to "next" branch. Regards, Tomohiro Signed-off-by: Atsuo Igarashi <atsuo_igarashi(a)tripeaks.co.jp> Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi(a)tripeaks.co.jp> ---- Add support for KMC KZM-ARM11-01 board. MAKEALL | 1 + Makefile | 3 + board/kzm_arm11_01/Makefile | 49 +++++++ board/kzm_arm11_01/config.mk | 1 + board/kzm_arm11_01/kzm_arm11_01.c | 84 +++++++++++ board/kzm_arm11_01/lowlevel_init.S | 281 ++++++++++++++++++++++++++++++++++++ board/kzm_arm11_01/u-boot.lds | 72 +++++++++ include/configs/kzm_arm11_01.h | 184 +++++++++++++++++++++++ 8 files changed, 675 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index 9ccb9ac..22f65ed 100755 --- a/MAKEALL +++ b/MAKEALL @@ -522,6 +522,7 @@ LIST_ARM11=" \ apollon \ imx31_litekit \ imx31_phycore \ + kzm_arm11_01 \ mx31ads \ smdk6400 \ " diff --git a/Makefile b/Makefile index 017e4db..f334c57 100644 --- a/Makefile +++ b/Makefile @@ -2805,6 +2805,9 @@ imx31_litekit_config : unconfig imx31_phycore_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 +kzm_arm11_01_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 kzm_arm11_01 NULL mx31 + mx31ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31 diff --git a/board/kzm_arm11_01/Makefile b/board/kzm_arm11_01/Makefile new file mode 100644 index 0000000..7e2f8ca --- /dev/null +++ b/board/kzm_arm11_01/Makefile @@ -0,0 +1,49 @@ +# +# Derived from mx31ads +# +# Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := kzm_arm11_01.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/kzm_arm11_01/config.mk b/board/kzm_arm11_01/config.mk new file mode 100644 index 0000000..d34dc02 --- /dev/null +++ b/board/kzm_arm11_01/config.mk @@ -0,0 +1 @@ +TEXT_BASE = 0x87f00000 diff --git a/board/kzm_arm11_01/kzm_arm11_01.c b/board/kzm_arm11_01/kzm_arm11_01.c new file mode 100644 index 0000000..ed253d7 --- /dev/null +++ b/board/kzm_arm11_01/kzm_arm11_01.c @@ -0,0 +1,84 @@ +/* + * Derived from mx31ads + * + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init (void) +{ + int i; + + /* CS0 & CS1: Nor Flash */ + /* + * CS0L, CS0A and CS0U values are from the RedBoot sources. + */ + __REG(CSCR_U(0)) = 0x00001801; + __REG(CSCR_L(0)) = 0x45450D01; + __REG(CSCR_A(0)) = 0x00450000; + + __REG(CSCR_U(1)) = 0x00001801; + __REG(CSCR_L(1)) = 0x45450D01; + __REG(CSCR_A(1)) = 0x00450000; + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); + + /* SPI2 */ + mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); + mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); + mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); + mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); + mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); + mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); + mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); + + /* start SPI2 clock */ + __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); + + gd->bd->bi_arch_number = MACH_TYPE_KZM_ARM11_01;/* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ + + return 0; +} + +int checkboard (void) +{ + printf("Board: KZM-ARM11-01\n"); + return 0; +} diff --git a/board/kzm_arm11_01/lowlevel_init.S b/board/kzm_arm11_01/lowlevel_init.S new file mode 100644 index 0000000..f2032a5 --- /dev/null +++ b/board/kzm_arm11_01/lowlevel_init.S @@ -0,0 +1,281 @@ +/* + * Derived from mx31ads + * + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/mx31-regs.h> + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + +/* RedBoot: AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =0x43F00000 + ldr r1, =0x77777777 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =0x53F00000 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =0x43F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] + + ldr r0, =0x53F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] +.endm /* init_aips */ + +/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =0x43F04000 + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =0x00302154 + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =0x10 + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =0x0 + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm /* init_max */ + +/* RedBoot: M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =0xB8003000 + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =0x00000040 + str r0, [r1] /* M3IF control reg */ +.endm /* init_m3if */ + +/* RedBoot: To support 133MHz DDR */ +.macro init_drive_strength + /* + * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits + * in SW_PAD_CTL registers + */ + + /* SDCLK */ + ldr r1, =0x43FAC200 + ldr r0, [r1, #0x6C] + bic r0, r0, #(1 << 12) + str r0, [r1, #0x6C] + + /* CAS */ + ldr r0, [r1, #0x70] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x70] + + /* RAS */ + ldr r0, [r1, #0x74] + bic r0, r0, #(1 << 2) + str r0, [r1, #0x74] + + /* CS2 (CSD0) */ + ldr r0, [r1, #0x7C] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x7C] + + /* DQM3 */ + ldr r0, [r1, #0x84] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x84] + + /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ + ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ +pad_loop: + ldr r0, [r1, #0x88] + bic r0, r0, #(1 << 22) + bic r0, r0, #(1 << 12) + bic r0, r0, #(1 << 2) + str r0, [r1, #0x88] + add r1, r1, #4 + subs r2, r2, #0x1 + bne pad_loop +.endm /* init_drive_strength */ + +/* CPLD on CS4 setup */ +.macro init_cs4 + ldr r0, =WEIM_BASE + ldr r1, =0x00001003 + str r1, [r0, #0x40] + ldr r1, =0x74741B01 + str r1, [r0, #0x44] + ldr r1, =0x00740000 + str r1, [r0, #0x48] +.endm /* init_cs4 */ + +/* LAN on CS5 setup */ +.macro init_cs5 + ldr r0, =WEIM_BASE + ldr r1, =0x00001403 + str r1, [r0, #0x50] + ldr r1, =0x44340D01 + str r1, [r0, #0x54] + ldr r1, =0x00340000 + str r1, [r0, #0x58] +.endm /* init_cs5 */ + +.globl lowlevel_init +lowlevel_init: + + /* Redboot initializes very early AIPS, what for? + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF */ + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_drive_strength + + init_cs4 + + /* Image Processing Unit: */ + /* Too early to switch display on? */ + REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ + /* Clock Control Module: */ + REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ + + /* 532-133-66.5 */ + ldr r0, =CCM_BASE + ldr r1, =0xFF872660 + /* PDR0 */ + str r1, [r0, #0x4] + ldreq r1, MPCTL_PARAM_532 + ldrne r1, MPCTL_PARAM_532_27 + /* MPCTL */ + str r1, [r0, #0x10] + + ldreq r1, UPCTL_PARAM_240 + ldrne r1, UPCTL_PARAM_240_27 + /* UPCTL */ + str r1, [r0, #0x14] + /* default CLKO to 1/8 of the ARM core */ + mov r1, #0x000002C0 + add r1, r1, #0x00000006 + /* COSR */ + str r1, [r0, #0x1c] + + /* Default: 1, 4, 12, 1 */ + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ + REG 0xB8001010, 0x00000004 + REG 0xB8001004, 0x0079d72a + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x81000020, 0x00 + REG8 0x80000033, 0xda + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + + init_cs5 + + mov pc, lr + +MPCTL_PARAM_532: + .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) +MPCTL_PARAM_532_27: + .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) +UPCTL_PARAM_240: + .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) +UPCTL_PARAM_240_27: + .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/kzm_arm11_01/u-boot.lds b/board/kzm_arm11_01/u-boot.lds new file mode 100644 index 0000000..aa87fcb --- /dev/null +++ b/board/kzm_arm11_01/u-boot.lds @@ -0,0 +1,72 @@ +/* + * Derived from mx31ads + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/arm1136/start.o (.text) + board/kzm_arm11_01/libkzm_arm11_01.a (.text) + lib_arm/libarm.a (.text) + net/libnet.a (.text) + drivers/mtd/libmtd.a (.text) + + . = DEFINED(env_offset) ? env_offset : .; + common/env_embedded.o(.text) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/include/configs/kzm_arm11_01.h b/include/configs/kzm_arm11_01.h new file mode 100644 index 0000000..72f7b5a --- /dev/null +++ b/include/configs/kzm_arm11_01.h @@ -0,0 +1,184 @@ +/* + * Derived from mx31ads + * + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * Configuration settings for the KMC KZM-ARM11-01 board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx31-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ +#define CONFIG_MX31_CLK32 32768 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#define CONFIG_MX31_UART 1 +#define CONFIG_SYS_MX31_UART1 1 + +#define CONFIG_HARD_SPI 1 +#define CONFIG_MXC_SPI 1 +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_2 | SPI_CS_HIGH) + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_SPI +#define CONFIG_CMD_FLASH + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot_addr=0xa0000000\0" \ + "uboot=kzm-arm11/u-boot.bin\0" \ + "kernel=kzm-arm11/uImage\0" \ + "nfsroot=${serverip}:${rootpath}\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "prg_uboot=tftpboot ${loadaddr} ${uboot}; " \ + "protect off ${uboot_addr} 0xa007ffff; " \ + "erase ${uboot_addr} 0xa007ffff; " \ + "cp.b ${loadaddr} ${uboot_addr} ${filesize}; " \ + "setenv filesize; saveenv\0" + +#define CONFIG_DRIVER_SMC911X 1 +#define CONFIG_DRIVER_SMC911X_BASE 0xb6020300 +#define CONFIG_DRIVER_SMC911X_32_BIT 1 + +/* + * The KZM-ARM11-01 board seems to have a hardware "peculiarity" confirmed under + * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the SMC9118 + * controller inverted. The controller is capable of detecting and correcting + * this, but it needs a few hundred milliseconds wait for that after the + * initialization. Which means, at startup, you will not receive answers + * during the first few hundred milliseconds, unless there have been some + * broadcasts on the network, or your board is on a hub. Reducing the ARP + * timeout from default 5 seconds to 200ms we speed up the initial TFTP + * transfer, should the user wish one, significantly. + */ +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE CS0_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256KiB */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +/* S29GL512N NOR flash has 512 128KiB big sectors. */ +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE) + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */

2 1

[U-Boot] [RFC PATCH] Add support for Raidsonic ICYBOX NAS4220 board
by Darius Augulis 05 Aug '09

05 Aug '09

This board is based on Cortina Systems networking processor CS3516. It has FA526 core, which is ARMv4 compatible. Many SoC specific definitions may be used for similar processors CS3512 and dual-core CS3518. This processor family has Gemini name. Signed-off-by: Darius Augulis <augulis.darius(a)gmail.com> --- MAINTAINERS | 4 + MAKEALL | 1 Makefile | 3 board/nas4220/Makefile | 43 +++++ board/nas4220/config.mk | 14 ++ board/nas4220/lowlevel_init.S | 96 ++++++++++++ board/nas4220/nas4220.c | 75 +++++++++ board/nas4220/u-boot.lds | 48 ++++++ cpu/arm920t/gemini/Makefile | 38 +++++ cpu/arm920t/gemini/timer.c | 93 ++++++++++++ cpu/arm920t/start.S | 11 + include/asm-arm/arch-gemini/gemini.h | 271 ++++++++++++++++++++++++++++++++++ include/configs/nas4220.h | 116 +++++++++++++++ 13 files changed, 811 insertions(+), 2 deletions(-) create mode 100644 board/nas4220/Makefile create mode 100644 board/nas4220/config.mk create mode 100644 board/nas4220/lowlevel_init.S create mode 100644 board/nas4220/nas4220.c create mode 100644 board/nas4220/u-boot.lds create mode 100644 cpu/arm920t/gemini/Makefile create mode 100644 cpu/arm920t/gemini/timer.c create mode 100644 include/asm-arm/arch-gemini/gemini.h create mode 100644 include/configs/nas4220.h diff --git a/MAINTAINERS b/MAINTAINERS index 9379c7e..ade43ed 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -671,6 +671,10 @@ Sergey Lapin <slapin(a)ossfans.org> afeb9260 ARM926EJS (AT91SAM9260 SoC) +Darius Augulis <augulis.darius(a)gmail.com> + + nas4220 CS3516 + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index f4599d6..8d28e36 100755 --- a/MAKEALL +++ b/MAKEALL @@ -511,6 +511,7 @@ LIST_ARM9=" \ lpd7a400 \ mx1ads \ mx1fs2 \ + nas4220 \ netstar \ nmdk8815 \ omap1510inn \ diff --git a/Makefile b/Makefile index bcc81c9..99c59c3 100644 --- a/Makefile +++ b/Makefile @@ -2836,6 +2836,9 @@ mx1ads_config : unconfig mx1fs2_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm920t mx1fs2 NULL imx +nas4220_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t nas4220 NULL gemini + netstar_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm925t netstar diff --git a/board/nas4220/Makefile b/board/nas4220/Makefile new file mode 100644 index 0000000..8299ffd --- /dev/null +++ b/board/nas4220/Makefile @@ -0,0 +1,43 @@ +# +# (c) Copyright 2009 +# Linkodas, Inc. +# http://www.linkodas.com +# +# Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := nas4220.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/nas4220/config.mk b/board/nas4220/config.mk new file mode 100644 index 0000000..5b418ba --- /dev/null +++ b/board/nas4220/config.mk @@ -0,0 +1,14 @@ +# +# (c) Copyright 2009 +# Linkodas, Inc. +# http://www.linkodas.com +# +# Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. + +TEXT_BASE = 0x10400000 +LDSCRIPT := $(SRCTREE)/board/$(BOARDDIR)/u-boot.lds diff --git a/board/nas4220/lowlevel_init.S b/board/nas4220/lowlevel_init.S new file mode 100644 index 0000000..d51a5a2 --- /dev/null +++ b/board/nas4220/lowlevel_init.S @@ -0,0 +1,96 @@ +/* + * (c) Copyright 2009 + * Linkodas, Inc. + * http://www.linkodas.com + * + * Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/gemini.h> + +#define DRAM_SET_MODE GEMINI_SET_MODE | GEMINI_MODE_DDRAM | \ + GEMINI_CAS_3 | GEMINI_BL_4 +#define DRAM_SET_TYPE GEMINI_BUS_32b | GEMINI_RAM_15x10_16x10 + +#define DRAM_IOCAP GEMINI_IOCAP_DRAM_CLOCK | GEMINI_IOCAP_DRAM_DATA | \ + GEMINI_IOCAP_DRAM_CTRL +#define DRAM_TIMING GEMINI_RRATE_AREF8 | GEMINI_RTIMER(195) | \ + GEMINI_TRFC(11) | GEMINI_TRAS(6) | GEMINI_TWR(3) | \ + GEMINI_TRP(3) | GEMINI_TRCD(3) | GEMINI_TCAS(3) +#define DRAM_READ_DLL GEMINI_RDLL_BYTE3(8) | GEMINI_RDLL_BYTE2(8) | \ + GEMINI_RDLL_BYTE1(8) | GEMINI_RDLL_BYTE0(8) +#define DRAM_WRITE_DLL GEMINI_WDLL(26) +#define DRAM_MEM_CTRL GEMINI_TRAINING_MODE | GEMINI_DQS_N_FALLING | \ + GEMINI_BUF_IN_4rd | (1 << 6) + +.globl lowlevel_init +lowlevel_init: + + /* DRAM init */ + ldr r0, =GEMINI_DRAM_TYPE /* DRAM set type */ + ldr r1, =DRAM_SET_TYPE /* 32bit, 64 Mbytes total */ + str r1, [r0] + + ldr r0, =GEMINI_DRAM_MODE /* DRAM set mode */ + ldr r1, =DRAM_SET_MODE /* DDRAM, CAS 3, Burst 4 */ + str r1, [r0] + + ldr r3, =GEMINI_GLOBAL_ID /* Global ID reg */ + ldr r4, [r3] + ldr r5, =0xFF /* Chip revision mask */ + and r4, r4, r5 + cmp r4, #0xc0 /* Test if chip rev. is 'c0' */ + bne end_prefetch + + /* Fix for rev. 'c0' chip */ + ldr r0, =GEMINI_DRAM_AHB_CTRL /* AHB control */ + ldr r5, =GEMINI_WRITE_FLUSH_READ + str r5, [r0] + +end_prefetch: + ldr r3, =GEMINI_GLOBAL_PLL /* Mistery PLL config */ + ldr r4, [r3] + orr r4, r4, #GEMINI_PLL_CHARGE_PUMP2 + str r4, [r3] + + ldr r3, =GEMINI_GLOBAL_IO_PAD /* Mistery IO pad config */ + ldr r4, [r3] + ldr r5, =DRAM_IOCAP + orr r4, r4, r5 + str r4, [r3] + + ldr r0, =GEMINI_DRAM_TIMING /* DRAM set timing */ + ldr r1, =DRAM_TIMING + str r1, [r0] + + ldr r0, =GEMINI_DRAM_RD_DLL /* DRAM set Read DLL delay */ + ldr r1, =DRAM_READ_DLL + str r1, [r0] + + ldr r0, =GEMINI_DRAM_WR_DLL /* DRAM set Write DLL delay */ + ldr r1, =DRAM_WRITE_DLL + str r1, [r0] + + ldr r0, =GEMINI_DRAM_MEM_CTRL /* DRAM training mode, timing */ + ldr r1, =DRAM_MEM_CTRL + str r1, [r0] + + ldr r2, =GEMINI_DRAM_BASE + mov r4, #0xa0 + +read_loop: + ldr r3, [r2] /* Read data */ + subs r4, r4, #1 /* Decrement loop count */ + bge read_loop + + bic r1, r1, #GEMINI_TRAINING_MODE /* Disable train mode */ + str r1, [r0] + + mov pc, lr diff --git a/board/nas4220/nas4220.c b/board/nas4220/nas4220.c new file mode 100644 index 0000000..784a249 --- /dev/null +++ b/board/nas4220/nas4220.c @@ -0,0 +1,75 @@ +/* + * (c) Copyright 2009 + * Linkodas, Inc. + * http://www.linkodas.com + * + * Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/gemini.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PINS (GEMINI_PIN_UART_RX | GEMINI_PIN_UART_TX) +#define MISC_CTRL (GEMINI_PAD_SFLASH_DIS | GEMINI_PAD_NAND_DIS) + +int board_init(void) +{ + /* Bypass UART pins */ + GEMINI_GPIO_BYPASS(0) |= UART_PINS; + + /* Enable: parallel flash pins, disable: serial, nand pins */ + GEMINI_GLOBAL_MISC = MISC_CTRL; + + /* Enable parallel flash direct write mode */ + GEMINI_FLASH_PAR_ACCESS |= GEMINI_PFLASH_DWR; + + return 0; +} + +int board_late_init(void) +{ + int cpu_id, cpu_rev, cpu_clk, ahb_clk; + + cpu_id = GEMINI_CHIP_ID; + cpu_rev = GEMINI_CHIP_REV; + ahb_clk = GEMINI_AHB_CLK; + + switch (GEMINI_CPU_AHB_RATIO) { + case 0: + cpu_clk = ahb_clk; + break; + case 1: + cpu_clk = (ahb_clk * 3) / 2; + break; + case 2: + cpu_clk = (ahb_clk * 24) / 13; + break; + case 3: + cpu_clk = ahb_clk * 2; + break; + default: + cpu_clk = 0; + break; + } + + printf("\nRaidsonic ICYBOX NAS4220 board\n"); + printf("CPU: Gemini CS%X, REV: %X\n", cpu_id, cpu_rev); + printf("CPU Speed: %d MHz, AHB Speed: %d MHz, APB Speed: %d MHz\n\n", cpu_clk / 1000000, ahb_clk / 1000000, ahb_clk / 6000000); + + return 0; +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} diff --git a/board/nas4220/u-boot.lds b/board/nas4220/u-boot.lds new file mode 100644 index 0000000..7d249c3 --- /dev/null +++ b/board/nas4220/u-boot.lds @@ -0,0 +1,48 @@ +/* + * (c) Copyright 2009 + * Linkodas, Inc. + * http://www.linkodas.com + * + * Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm920t/start.o (.text) + board/nas4220/libnas4220.a (.text) + lib_arm/libarm.a (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm920t/gemini/Makefile b/cpu/arm920t/gemini/Makefile new file mode 100644 index 0000000..ca262e3 --- /dev/null +++ b/cpu/arm920t/gemini/Makefile @@ -0,0 +1,38 @@ +# +# (c) Copyright 2009 +# Linkodas, Inc. +# http://www.linkodas.com +# +# Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS += timer.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm920t/gemini/timer.c b/cpu/arm920t/gemini/timer.c new file mode 100644 index 0000000..ec24cd8 --- /dev/null +++ b/cpu/arm920t/gemini/timer.c @@ -0,0 +1,93 @@ +/* + * (c) Copyright 2009 + * Linkodas, Inc. + * http://www.linkodas.com + * + * Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> + +#ifdef CONFIG_GEMINI + +#include <asm/arch/gemini.h> + +static ulong gemini_usec; +static ulong timestamp; +static ulong extraticks; + +int timer_init(void) +{ + gemini_usec = GEMINI_APB_CLK / 1000000; + timestamp = extraticks = 0; + + GEMINI_TIMER_COUNT(0) = 0; + GEMINI_TIMER_LOAD(0) = 0; + GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0); + + return 0; +} + +void reset_timer(void) +{ + GEMINI_TIMER_CR &= ~TIMER_CR_ENABLE(0); + GEMINI_TIMER_COUNT(0) = 0x0; + GEMINI_TIMER_LOAD(0) = 0x0; + GEMINI_TIMER_CR = TIMER_CR_UP(0) | TIMER_CR_ENABLE(0); + + timestamp = extraticks = 0; +} + +unsigned long long get_usecs(void) +{ + ulong timenow = GEMINI_TIMER_COUNT(0); + + if (timenow >= timestamp) + timestamp += timenow - extraticks; + else + timestamp += 0xFFFFFFFF - extraticks + timenow; + extraticks = timenow; + + return timestamp / gemini_usec; +} + +ulong get_timer(ulong base) +{ + return (get_usecs() / 1000) - base; +} + +void set_timer(ulong t) +{ +} + +void udelay(unsigned long usec) +{ + signed long elapsed; + ulong timestart = get_usecs(); + + do { + ulong timenow = get_usecs(); + elapsed = timenow - timestart; + } while (elapsed < usec); +} + +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + + return tbclk; +} + +void reset_cpu(ulong ignored) +{ + GEMINI_GLOBAL_RESET = GEMINI_SOFT_RESET | GEMINI_CPU1_RESET; +} + +#endif /* defined (CONFIG_GEMINI) */ diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S index 475cdaf..761753e 100644 --- a/cpu/arm920t/start.S +++ b/cpu/arm920t/start.S @@ -115,8 +115,10 @@ start_code: orr r0,r0,#0xd3 msr cpsr,r0 - bl coloured_LED_init - bl red_LED_on +#ifndef CONFIG_GEMINI + bl coloured_LED_init + bl red_LED_on +#endif #if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) /* @@ -189,6 +191,11 @@ relocate: /* relocate U-Boot to RAM */ sub r2, r3, r2 /* r2 <- size of armboot */ add r2, r0, r2 /* r2 <- source end address */ +#ifdef CONFIG_GEMINI + orr r0, r0, #CONFIG_SYS_FLASH_BASE + orr r2, r2, #CONFIG_SYS_FLASH_BASE +#endif + copy_loop: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ diff --git a/include/asm-arm/arch-gemini/gemini.h b/include/asm-arm/arch-gemini/gemini.h new file mode 100644 index 0000000..e4fa91a --- /dev/null +++ b/include/asm-arm/arch-gemini/gemini.h @@ -0,0 +1,271 @@ +/* + * (c) Copyright 2009 + * Linkodas, Inc. + * http://www.linkodas.com + * + * Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#ifndef __ASSEMBLY__ +# define REG8(x) (*(volatile u8 *)(x)) +# define REG16(x) (*(volatile u16 *)(x)) +# define REG32(x) (*(volatile u32 *)(x)) +#else +# define REG8(x) (x) +# define REG16(x) (x) +# define REG32(x) (x) +#endif + +/* + * Memory Map definitions + */ +#define GEMINI_SRAM_BASE 0x00000000 +#define GEMINI_DRAM_BASE 0x10000000 +#define GEMINI_FLASH_BASE 0x30000000 + +/* + * Register Map definitions + */ +#define GEMINI_GLOBAL_BASE 0x40000000 +#define GEMINI_WAQTCHDOG_BASE 0x41000000 +#define GEMINI_UART_BASE 0x42000000 +#define GEMINI_TIMER_BASE 0x43000000 +#define GEMINI_LCD_BASE 0x44000000 +#define GEMINI_RTC_BASE 0x45000000 +#define GEMINI_SATA_BASE 0x46000000 +#define GEMINI_LPC_HOST_BASE 0x47000000 +#define GEMINI_LPC_IO_BASE 0x47800000 +#define GEMINI_INTERRUPT_BASE 0x48000000 +#define GEMINI_SSP_CTRL_BASE 0x4A000000 +#define GEMINI_POWER_CTRL_BASE 0x4B000000 +#define GEMINI_CIR_BASE 0x4C000000 +#define GEMINI_GPIO_BASE 0x4D000000 +#define GEMINI_PCI_IO_BASE 0x50000000 +#define GEMINI_PCI_MEM_BASE 0x58000000 +#define GEMINI_TOE_BASE 0x60000000 +#define GEMINI_GMAC0_BASE 0x6000A000 +#define GEMINI_GMAC1_BASE 0x6000E000 +#define GEMINI_SECURITY_BASE 0x62000000 +#define GEMINI_IDE0_BASE 0x63000000 +#define GEMINI_IDE1_BASE 0x63400000 +#define GEMINI_RAID_BASE 0x64000000 +#define GEMINI_FLASH_CTRL_BASE 0x65000000 +#define GEMINI_DRAM_CTRL_BASE 0x66000000 +#define GEMINI_GENERAL_DMA_BASE 0x67000000 +#define GEMINI_USB0_BASE 0x68000000 +#define GEMINI_USB1_BASE 0x69000000 +#define GEMINI_BIG_ENDIAN_BASE 0x80000000 + +/* + * Global Module definitions + */ + +/* Global registers */ +#define GEMINI_GLOBAL_ID REG32(GEMINI_GLOBAL_BASE + 0x00) +#define GEMINI_GLOBAL_STATUS REG32(GEMINI_GLOBAL_BASE + 0x04) +#define GEMINI_GLOBAL_PLL REG32(GEMINI_GLOBAL_BASE + 0x08) +#define GEMINI_GLOBAL_RESET REG32(GEMINI_GLOBAL_BASE + 0x0C) +#define GEMINI_GLOBAL_IO_PAD REG32(GEMINI_GLOBAL_BASE + 0x10) +#define GEMINI_GLOBAL_MISC REG32(GEMINI_GLOBAL_BASE + 0x30) + +/* GEMINI_GLOBAL_ID bitfields */ +#define GEMINI_CHIP_ID ((GEMINI_GLOBAL_ID & 0xFFFFFF00) >> 8) +#define GEMINI_CHIP_REV (GEMINI_GLOBAL_ID & 0xFF) + +/* GEMINI_GLOBAL_STATUS bitfields */ + +/* GEMINI_GLOBAL_PLL bitfields */ +#define GEMINI_PLL_CHARGE_PUMP2 (7 << 12) + +/* GEMINI_GLOBAL_RESET bitfields */ +#define GEMINI_SOFT_RESET (1 << 31) +#define GEMINI_CPU1_RESET (1 << 30) + +/* GEMINI_GLOBAL_IO_PAD bitfields */ +#define GEMINI_IOCAP_DRAM_CLOCK (0xF << 8) +#define GEMINI_IOCAP_DRAM_DATA (0xF << 4) +#define GEMINI_IOCAP_DRAM_CTRL (0xF << 0) + +/* GEMINI_GLOBAL_MISC bitfields */ +#define GEMINI_PAD_SFLASH_DIS (1 << 0) +#define GEMINI_PAD_PFLASH_DIS (1 << 1) +#define GEMINI_PAD_NAND_DIS (1 << 2) +#define GEMINI_PAD_DRAM_PD_EN (1 << 3) +#define GEMINI_PAD_IDE_EN (1 << 4) +#define GEMINI_PAD_PCI_EN (1 << 5) +#define GEMINI_PAD_LPC_EN (1 << 6) +#define GEMINI_PAD_LCD_EN (1 << 7) +#define GEMINI_PAD_SSP_EN (1 << 8) +#define GEMINI_PAD_TVC_EN (1 << 9) +#define GEMINI_PCI_IDLE_DETECT(x) (x << 11) /* PCI Clocks: 0 - 256, 1 - 128, 2 - 64, 3 - 32 */ +#define GEMINI_USB0_WAKE_EN (1 << 14) +#define GEMINI_USB1_WAKE_EN (1 << 15) +#define GEMINI_CLOCK_LPC_EN (1 << 16) +#define GEMINI_CLOCK_PCI_EN (1 << 17) +#define GEMINI_CLOCK_PCI66_EN (1 << 18) +#define GEMINI_CLOCK_EXT_EN (1 << 19) +#define GEMINI_CLOCK_TVC_EN (1 << 20) +#define GEMINI_CLOCK_APB_EN (1 << 21) +#define GEMINI_USB0_VBUS_EN (1 << 22) +#define GEMINI_USB1_VBUS_EN (1 << 23) +#define GEMINI_IDE_IO_0 (0 << 24) +#define GEMINI_IDE_IO_1 (1 << 24) +#define GEMINI_IDE_IO_2 (2 << 24) +#define GEMINI_IDE_IO_3 (3 << 24) +#define GEMINI_GMAC_IO_0 (0 << 27) +#define GEMINI_GMAC_IO_1 (1 << 27) +#define GEMINI_GMAC_IO_2 (2 << 27) +#define GEMINI_USB0_PLUG (1 << 29) /* 0 - miniA, 1 - miniB */ +#define GEMINI_USB1_PLUG (1 << 30) /* 0 - miniA, 1 - miniB */ +#define GEMINI_MEMORY_SWAP (1 << 31) + +/* + * DRAM Module definitions + */ + +/* DRAM registers */ +#define GEMINI_DRAM_MODE REG32(GEMINI_DRAM_CTRL_BASE + 0x00) +#define GEMINI_DRAM_TIMING REG32(GEMINI_DRAM_CTRL_BASE + 0x04) +#define GEMINI_DRAM_MEM_CTRL REG32(GEMINI_DRAM_CTRL_BASE + 0x08) +#define GEMINI_DRAM_TYPE REG32(GEMINI_DRAM_CTRL_BASE + 0x0C) +#define GEMINI_DRAM_ARBITER REG32(GEMINI_DRAM_CTRL_BASE + 0x10) +#define GEMINI_DRAM_RD_DLL REG32(GEMINI_DRAM_CTRL_BASE + 0x14) +#define GEMINI_DRAM_WR_DLL REG32(GEMINI_DRAM_CTRL_BASE + 0x18) +#define GEMINI_DRAM_AHB_CTRL REG32(GEMINI_DRAM_CTRL_BASE + 0x1C) +#define GEMINI_DRAM_CPU_REMAP REG32(GEMINI_DRAM_CTRL_BASE + 0x40) + +/* GEMINI_DRAM_MODE bitfields */ +#define GEMINI_BL_4 (2 << 0) /* Burst lenght 4 */ +#define GEMINI_BL_8 (3 << 0) /* Burst lenght 8 */ +#define GEMINI_BT_INT (1 << 3) /* Burst type interleave */ +#define GEMINI_CAS_2 (2 << 4) /* CAS latency 2 */ +#define GEMINI_CAS_3 (3 << 4) /* CAS latency 3 */ +#define GEMINI_CAS_25 (6 << 4) /* CAS latency 2.5 */ +#define GEMINI_MODE_SDRAM (0 << 7) /* Mode SDRAM */ +#define GEMINI_MODE_DDRAM (2 << 7) /* Mode DDRAM */ +#define GEMINI_WBL_BURST (0 << 9) /* Write Burst */ +#define GEMINI_WBL_SINGLE (1 << 9) /* Write Single */ +#define GEMINI_DLL_DISABLE (1 << 16) /* DLL disable */ +#define GEMINI_DRIVING_REDUCED (1 << 17) /* Driving Strength */ +#define GEMINI_SET_MODE (1 << 31) /* Set Mode Register */ + +/* GEMINI_DRAM_TIMING bitfields */ +#define GEMINI_RRATE_AREF8 (1 << 31) /* Refresh rate AREF 8 */ +#define GEMINI_RRATE_AREF4 (0 << 31) /* Refresh rate AREF 4 */ +#define GEMINI_RTIMER(x) (x << 16) /* Refresh timer cycles 0...0x7FFF */ +#define GEMINI_TRFC(x) (x << 12) /* SDRAM Auto-refresh cycles 0...15 */ +#define GEMINI_TRAS(x) (x << 8) /* SDRAM TRAS cycles 0...15 */ +#define GEMINI_TWR(x) (x << 6) /* SDRAM TWR cycles 0...3 */ +#define GEMINI_TRP(x) (x << 4) /* SDRAM TRP cycles 0...3 */ +#define GEMINI_TRCD(x) (x << 2) /* SDRAM TRCD cycles 0...3 */ +#define GEMINI_TCAS(x) (x << 0) /* SDRAM TCAS cycles 0...3 */ + +/* GEMINI_DRAM_MEM_CTRL bitfields */ +#define GEMINI_TRAINING_MODE (1 << 0) /* DRAM training mode */ +#define GEMINI_DQS_N_RISING (0 << 1) /* Read DQS Lock Window for CL 2, 3 */ +#define GEMINI_DQS_L_RISING (1 << 1) /* Read DQS Lock Window for CL 3 */ +#define GEMINI_DQS_N_FALLING (2 << 1) /* Read DQS Lock Window for CL 2.5 */ +#define GEMINI_DQS_L_FALLING (3 << 1) /* Read DQS Lock Window for CL 2.5 */ + +#define GEMINI_BUF_IN_3rd (0 << 4) /* capture at 3rd T after read command */ +#define GEMINI_BUF_IN_4rd (1 << 4) /* capture at 4rd T after read command */ +#define GEMINI_BUF_IN_5rd (2 << 4) /* capture at 5rd T after read command */ +#define GEMINI_BUF_IN_6rd (3 << 4) /* capture at 6rd T after read command */ + +/* GEMINI_DRAM_TYPE bitfields */ +#define GEMINI_BUS_16b (1 << 30) /* DRAM bus is 16 bit */ +#define GEMINI_BUS_32b (0 << 30) /* DRAM bus is 32 bit */ + +/* (bank address + row address) x (column address) */ +#define GEMINI_RAM_14x8 (0 << 0) +#define GEMINI_RAM_14x9_15x9 (1 << 0) +#define GEMINI_RAM_15x10_16x10 (2 << 0) +#define GEMINI_RAM_15x11_16x11 (3 << 0) + +/* GEMINI_DRAM_RD_DLL bitfields */ +#define GEMINI_RDLL_BYTE3(x) (x << 24) /* Delay of byte 3 cycles 0...63 */ +#define GEMINI_RDLL_BYTE2(x) (x << 16) /* Delay of byte 2 cycles 0...63 */ +#define GEMINI_RDLL_BYTE1(x) (x << 8) /* Delay of byte 1 cycles 0...63 */ +#define GEMINI_RDLL_BYTE0(x) (x << 0) /* Delay of byte 0 cycles 0...63 */ + +/* GEMINI_DRAM_WR_DLL bitfields */ +#define GEMINI_WDLL(x) (x << 0) /* Delay cycles 0...63 */ + +/* GEMINI_DRAM_AHB_CTRL definitions */ +#define GEMINI_WRITE_FLUSH_READ (1 << 0) + +/* + * GPIO Module definitions + */ + +/* GPIO registers */ +#define GEMINI_GPIO_X_BASE(x) (GEMINI_GPIO_BASE + (x) * 0x1000000) +#define GEMINI_GPIO_DOUT(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x00) +#define GEMINI_GPIO_DIN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x04) +#define GEMINI_GPIO_DIR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x08) +#define GEMINI_GPIO_BYPASS(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x0C) +#define GEMINI_GPIO_DSET(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x10) +#define GEMINI_GPIO_DCLEAR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x14) +#define GEMINI_GPIO_PULL_EN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x18) +#define GEMINI_GPIO_PULL_DIR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x1C) +#define GEMINI_GPIO_INT_EN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x20) +#define GEMINI_GPIO_INT_RAW(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x24) +#define GEMINI_GPIO_INT_MASK_ST(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x28) +#define GEMINI_GPIO_INTR_MASK(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x2C) +#define GEMINI_GPIO_INT_CLR(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x30) +#define GEMINI_GPIO_INT_TRIG(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x34) +#define GEMINI_GPIO_INTR_BOTH(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x38) +#define GEMINI_GPIO_INTR_EDGE(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x3C) +#define GEMINI_GPIO_BNC_EN(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x40) +#define GEMINI_GPIO_BNC_PRESC(x) REG32(GEMINI_GPIO_X_BASE(x) + 0x44) + +/* GPIO pins definitions */ +#define GEMINI_PIN_UART_RX (1 << 9) +#define GEMINI_PIN_UART_TX (1 << 10) + +/* + * FLASH Module definitions + */ + +/* FLASH registers */ +#define GEMINI_FLASH_PAR_ACCESS REG32(GEMINI_FLASH_CTRL_BASE + 0x20) + +/* GEMINI_FLASH_PAR_ACCESS */ +#define GEMINI_PFLASH_DWR (1 << 14) + +/* + * TIMER Module definitions + */ + +/* Timer registers */ +#define GEMINI_TIMER_X_BASE(x) (GEMINI_TIMER_BASE + (0 + x * 0x10)) +#define GEMINI_TIMER_COUNT(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x00) +#define GEMINI_TIMER_LOAD(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x04) +#define GEMINI_TIMER_MATCH1(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x08) +#define GEMINI_TIMER_MATCH2(x) REG32(GEMINI_TIMER_X_BASE(x) + 0x0C) +#define GEMINI_TIMER_CR REG32(GEMINI_TIMER_BASE + 0x30) + +/* Timer bitfields */ +#define TIMER_CR_ENABLE(x) (1 << (0 + x * 3)) +#define TIMER_CR_CLOCK(x) (1 << (1 + x * 3)) +#define TIMER_CR_INT(x) (1 << (2 + x * 3)) +#define TIMER_CR_UP(x) (1 << (9 + x)) + +/* + * Helper Macros + */ +#define REG_TO_AHB_SPEED(reg) ((((reg) >> 15) & 0x7) * 10 + 130) + +/* System clocks */ +#define GEMINI_SYS_CLK (REG_TO_AHB_SPEED(GEMINI_GLOBAL_STATUS) * 1000000) +#define GEMINI_CPU_AHB_RATIO ((GEMINI_GLOBAL_STATUS >> 18) & 3) + +#define GEMINI_AHB_CLK GEMINI_SYS_CLK +#define GEMINI_APB_CLK (GEMINI_SYS_CLK / 6) +#define GEMINI_UART_CLK 48000000 + diff --git a/include/configs/nas4220.h b/include/configs/nas4220.h new file mode 100644 index 0000000..7f089c6 --- /dev/null +++ b/include/configs/nas4220.h @@ -0,0 +1,116 @@ +/* + * (c) Copyright 2009 + * Linkodas, Inc. + * http://www.linkodas.com + * + * Author: Darius Augulis <daugulis(a)linkodas.com> <augulis.darius(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +/* This is U-boot configuration for Raidsonic ICYBOX NAS4220 board. + * More information about this device is available on websites: + * http://en.nas-4220.org + * http://wiki.gpl-devices.org/wiki/Raidsonic_ICY-BOX_IB-NAS4220-B + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/gemini.h> +#include <asm-arm/sizes.h> + +/* High Level Configuration Options */ +#define CONFIG_ARM920T 1 +#define CONFIG_GEMINI 1 +#define CONFIG_NAS4220 1 +#undef CONFIG_USE_IRQ + +/* NS16550 Configuration */ +#define CONFIG_SYS_NS16550 1 +#define CONFIG_SYS_NS16550_SERIAL 1 +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK GEMINI_UART_CLK +#define CONFIG_SYS_NS16550_COM1 GEMINI_UART_BASE +#define CONFIG_CONS_INDEX 1 + +/* Select serial console configuration */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* Command line configuration */ +#define CONFIG_CMD_BDI /* bdinfo */ +#define CONFIG_CMD_BOOTD /* bootd */ +#define CONFIG_CMD_CONSOLE /* coninfo */ +#define CONFIG_CMD_ECHO /* echo arguments */ +#define CONFIG_CMD_SAVEENV /* saveenv */ +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ +#define CONFIG_CMD_IMLS /* List all found images */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ +#define CONFIG_CMD_LOADB /* loadb */ +#define CONFIG_CMD_LOADS /* loads */ +#define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ +#define CONFIG_CMD_MISC /* Misc functions like sleep etc */ +#define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SOURCE /* "source" command support */ +#define CONFIG_CMD_XIMG /* Load part of Multi Image */ + +#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 mem=64M" +#define CONFIG_BOOTFILE "nas4220" +#define CONFIG_BOOTCOMMAND "bootm" + +/* Miscellaneous configurable options */ +#define BOARD_LATE_INIT 1 +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_SYS_PROMPT "NAS4220$ " + +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR 0x10500000 +#define CONFIG_SYS_HZ 1000 + +/* Stack size */ +#define CONFIG_STACKSIZE SZ_512K + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 GEMINI_DRAM_BASE +#define PHYS_SDRAM_1_SIZE SZ_64M /* 64 MB DRAM */ + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + SZ_4M) /* 60 MB test */ +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE) + +/* FLASH configuration */ +#define CONFIG_SYS_FLASH_BASE GEMINI_FLASH_BASE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 128 + +/* Environment configuration + * We have 128 flash sectors, each of 128 KB. + * Environment is stored in last 8 KB on the flash + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN SZ_128K + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_OFFSET 0xFFE000 /* Last 8K on the flash */ +#define CONFIG_ENV_SIZE SZ_8K +#define CONFIG_ENV_SECT_SIZE SZ_128K + +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* CFI FLASH driver setup */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#endif /* __CONFIG_H */

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