August 2009 - U-Boot

[U-Boot-Users] [PATCH] mtd: SPI Flash: Winbond W25X16/WX2532/WX2564 support
by Jason McMullan 22 Nov '09

22 Nov '09

Add support for the Winbond W25X16/32/64 series of SPI Flash devices. --- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/spi_flash.c | 5 + drivers/mtd/spi/spi_flash_internal.h | 1 + drivers/mtd/spi/winbond.c | 331 ++++++++++++++++++++++++++++++++++ 4 files changed, 338 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spi/winbond.c diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index 01b288a..5941235 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -28,6 +28,7 @@ LIB := $(obj)libspi_flash.a COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o +COBJS-$(CONFIG_SPI_FLASH_WINBOND) += winbond.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index 35ce822..e81b1be 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -134,6 +134,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, flash = spi_flash_probe_atmel(spi, idcode); break; #endif +#ifdef CONFIG_SPI_FLASH_WINBOND + case 0xef: + flash = spi_flash_probe_winbond(spi, idcode); + break; +#endif #ifdef CONFIG_SPI_FLASH_STMICRO case 0x00: case 0xff: diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index e5f758e..1eacb5c 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -44,3 +44,4 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/winbond.c b/drivers/mtd/spi/winbond.c new file mode 100644 index 0000000..85e5b80 --- /dev/null +++ b/drivers/mtd/spi/winbond.c @@ -0,0 +1,331 @@ +/* + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan(a)netapp.com> + * + */ + +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_W25_WREN 0x06 /* Write Enable */ +#define CMD_W25_WRDI 0x04 /* Write Disable */ +#define CMD_W25_RDSR 0x05 /* Read Status Register */ +#define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_READ 0x03 /* Read Data Bytes */ +#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_W25_PP 0x02 /* Page Program */ +#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_W25_CE 0xc7 /* Chip Erase */ +#define CMD_W25_DP 0xb9 /* Deep Power-down */ +#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ + +#define WINBOND_ID_W25X16 0x3015 +#define WINBOND_ID_W25X32 0x3016 +#define WINBOND_ID_W25X64 0x3017 + +#define WINBOND_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct winbond_spi_flash_params { + uint16_t id; + /* Log2 of page size in power-of-two mode */ + uint8_t l2_page_size; + uint16_t pages_per_sector; + uint16_t sectors_per_block; + uint8_t nr_blocks; + const char *name; +}; + +struct winbond_spi_flash { + const struct winbond_spi_flash_params *params; + struct spi_flash flash; +}; + +static inline struct winbond_spi_flash * +to_winbond_spi_flash(struct spi_flash *flash) +{ + return container_of(flash, struct winbond_spi_flash, flash); +} + +static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { + { + .id = WINBOND_ID_W25X16, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 32, + .name = "W25X16", + }, + { + .id = WINBOND_ID_W25X32, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "W25X32", + }, + { + .id = WINBOND_ID_W25X64, + .l2_page_size = 8, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 128, + .name = "W25X64", + }, +}; + +static int winbond_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 status; + u8 cmd[4] = { CMD_W25_RDSR, 0xff, 0xff, 0xff }; + + ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN); + if (ret) { + debug("SF: Failed to send command %02x: %d\n", cmd, ret); + return ret; + } + + timebase = get_timer(0); + do { + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) { + debug("SF: Failed to get status for cmd %02x: %d\n", cmd, ret); + return -1; + } + + if ((status & WINBOND_SR_WIP) == 0) + break; + + } while (get_timer(timebase) < timeout); + + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if ((status & WINBOND_SR_WIP) == 0) + return 0; + + debug("SF: Timed out on command %02x: %d\n", cmd, ret); + /* Timed out */ + return -1; +} + +/* + * Assemble the address part of a command for Winbond devices in + * non-power-of-two page size mode. + */ +static void winbond_build_address(struct winbond_spi_flash *stm, u8 *cmd, u32 offset) +{ + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + + /* + * The "extra" space per page is the power-of-two page size + * divided by 32. + */ + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + cmd[0] = page_addr >> (16 - page_shift); + cmd[1] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[2] = byte_addr; +} + +static int winbond_read_fast(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + u8 cmd[5]; + + cmd[0] = CMD_READ_ARRAY_FAST; + winbond_build_address(stm, cmd + 1, offset); + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int winbond_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + unsigned int page_shift; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_shift = stm->params->l2_page_size; + page_size = (1 << page_shift); + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_W25_PP; + cmd[1] = page_addr >> (16 - page_shift); + cmd[2] = page_addr << (page_shift - 8) | (byte_addr >> 8); + cmd[3] = byte_addr; + debug("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", + buf + actual, + cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: Winbond Page Program failed\n"); + goto out; + } + + ret = winbond_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: Winbond page programming timed out\n"); + goto out; + } + + page_addr++; + byte_addr = 0; + } + + debug("SF: Winbond: Successfully programmed %u bytes @ 0x%x\n", + len, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +int winbond_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + struct winbond_spi_flash *stm = to_winbond_spi_flash(flash); + unsigned long sector_size; + unsigned int page_shift; + size_t actual; + int ret; + u8 cmd[4]; + + /* + * This function currently uses sector erase only. + * probably speed things up by using bulk erase + * when possible. + */ + + page_shift = stm->params->l2_page_size; + sector_size = (1 << page_shift) * stm->params->pages_per_sector; + + if (offset % sector_size || len % sector_size) { + debug("SF: Erase offset/length not multiple of sector size\n"); + return -1; + } + + len /= sector_size; + cmd[0] = CMD_W25_SE; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + for (actual = 0; actual < len; actual++) { + winbond_build_address(stm, &cmd[1], offset + actual * sector_size); + printf("Erase: %02x %02x %02x %02x\n", + cmd[0], cmd[1], cmd[2], cmd[3]); + + ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + goto out; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: Winbond sector erase failed\n"); + goto out; + } + + ret = winbond_wait_ready(flash, 2 * CFG_HZ); /* Up to 2 seconds */ + if (ret < 0) { + debug("SF: Winbond sector erase timed out\n"); + goto out; + } + } + + debug("SF: Winbond: Successfully erased %u bytes @ 0x%x\n", + len * sector_size, offset); + ret = 0; + +out: + spi_release_bus(flash->spi); + return ret; +} + +struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode) +{ + const struct winbond_spi_flash_params *params; + unsigned long page_size; + struct winbond_spi_flash *stm; + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(winbond_spi_flash_table); i++) { + params = &winbond_spi_flash_table[i]; + if (params->id == ((idcode[1] << 8) | idcode[2])) + break; + } + + if (i == ARRAY_SIZE(winbond_spi_flash_table)) { + debug("SF: Unsupported Winbond ID %02x%02x\n", + idcode[1], idcode[2]); + return NULL; + } + + stm = malloc(sizeof(struct winbond_spi_flash)); + if (!stm) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + /* Assuming power-of-two page size initially. */ + page_size = 1 << params->l2_page_size; + + stm->flash.write = winbond_write; + stm->flash.erase = winbond_erase; + stm->flash.read = winbond_read_fast; + stm->flash.size = page_size * params->pages_per_sector + * params->sectors_per_block + * params->nr_blocks; + + debug("SF: Detected %s with page size %u, total %u bytes\n", + params->name, page_size, stm->flash.size); + + return &stm->flash; +} -- 1.5.4.3

3 6

[U-Boot] [PATCH] MIMC200: set default fbmem value
by Mark Jackson 22 Nov '09

22 Nov '09

This patch adds a default bootargs "fbmem" value to the CONFIG_BOOTARGS string for the MIMC200 board. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- include/configs/mimc200.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 8f71664..36488b3 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -74,7 +74,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ - "root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS1" + "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1" #define CONFIG_BOOTCOMMAND \ "fsload boot/uImage; bootm"

2 1

[U-Boot] [PATCH 01/03 v2] Add inverted clock polarity support for Atmel LCD driver
by Dimitar Dimitrov 22 Nov '09

22 Nov '09

This is my second try for Olimex SAM9-L9260/61 board support patches. I deleted the board ethernet initialization and hopefully will add it later in a state that can be accepted. Here follows the first patch. --- Boards utilizing the Atmel LCD driver can now specify that the LCD clock must be inverted by defining the macro CONFIG_ATMEL_LCD_INVCLK. Signed-off-by: Dimitar Dimitrov <dinuxbg(a)gmail.com> --- drivers/video/atmel_lcdfb.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index db86763..64f8e87 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -112,6 +112,9 @@ void lcd_ctrl_init(void *lcdbase) value |= panel_info.vl_sync; value |= (panel_info.vl_bpix << 5); +#if defined(CONFIG_ATMEL_LCD_INVCLK) + value |= ATMEL_LCDC_INVCLK_INVERTED; +#endif lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value); /* Vertical timing */ -- 1.5.6.1

2 4

[U-Boot] [PATCH] Added preliminary support to EHCI USB FSL controller for platform MPC5121
by Rendine Francesco 22 Nov '09

22 Nov '09

Hi all, I would like to submit you a patch to add a preliminary support to EHCI USB Freescale controller integrated on MPC5121. There is still much job to do..for now, this patch add support for USB0 on UTMI phy. I've personally tested this feature with mass storage and it does work. Could be a base for future development..I'm available to possible improvement of source code with your suggestions. Summary: - introduced ehci_hcd_init and ehci_hcd_stop functions for MPC5121 integrated EHCI USB controller - introduced enable of EHCI USB controller in include/mpc5121ads.h - introduced many defines and struct ehci fields to be able to provvide OTG feature Regards, Francesco Rendine. Signed-off-by: Francesco Rendine <francesco.rendine(a)valueteam.com> diff -Naur u-boot.orig/board/freescale/mpc5121ads/mpc5121ads.c u-boot.usb/board/freescale/mpc5121ads/mpc5121ads.c --- u-boot.orig/board/freescale/mpc5121ads/mpc5121ads.c 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/board/freescale/mpc5121ads/mpc5121ads.c 2009-06-24 18:12:06.000000000 +0200 @@ -54,7 +54,8 @@ #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ CLOCK_SCCR2_I2C_EN | \ CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN) + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_USB1_EN) #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) diff -Naur u-boot.orig/drivers/usb/host/ehci-fsl.c u-boot.usb/drivers/usb/host/ehci-fsl.c --- u-boot.orig/drivers/usb/host/ehci-fsl.c 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/drivers/usb/host/ehci-fsl.c 2009-06-25 01:14:34.000000000 +0200 @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009, Value Team S.p.A. + * Francesco Rendine, <francesco.rendine(a)valueteam.com> + * * (C) Copyright 2009 Freescale Semiconductor, Inc. * * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB @@ -30,6 +33,7 @@ #include "ehci.h" #include "ehci-core.h" +#ifndef CONFIG_MPC512X /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -38,34 +42,93 @@ */ int ehci_hcd_init(void) { - struct usb_ehci *ehci; + struct usb_ehci *ehci; - ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR; - hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength); - hcor = (struct ehci_hcor *)((uint32_t) hccr + - HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - /* Set to Host mode */ - setbits_le32((void *)ehci->usbmode, CM_HOST); + /* Set to Host mode */ + setbits_le32((void *)ehci->usbmode, CM_HOST); - out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB); - out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); - /* Init phy */ - if (!strcmp(getenv("usb_phy_type"), "utmi")) - out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); - else - out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); + /* Init phy */ + if (!strcmp(getenv("usb_phy_type"), "utmi")) + out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + else + out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); - /* Enable interface. */ - setbits_be32((void *)ehci->control, USB_EN); + /* Enable interface. */ + setbits_be32((void *)ehci->control, USB_EN); - out_be32((void *)ehci->prictrl, 0x0000000c); - out_be32((void *)ehci->age_cnt_limit, 0x00000040); - out_be32((void *)ehci->sictrl, 0x00000001); + out_be32((void *)ehci->prictrl, 0x0000000c); + out_be32((void *)ehci->age_cnt_limit, 0x00000040); + out_be32((void *)ehci->sictrl, 0x00000001); + + in_le32((void *)ehci->usbmode); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + return 0; +} +#else +/* + * Initialize SOC FSL EHCI Controller + * + * This code is derived from EHCI FSL USB Linux driver for MPC5121 + * + */ +int ehci_hcd_init(void) +{ + struct usb_ehci *ehci; + u32 temp; - in_le32((void *)ehci->usbmode); + /* Hook the memory mapped registers for EHCI-Controller */ + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + hccr = (struct ehci_hccr *)(&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + /* Confgure interface for UTMI_WIDE */ + temp = in_be32(&ehci->isiphyctrl); + out_be32(&ehci->isiphyctrl, temp | PHYCTRL_PHYE | PHYCTRL_PXE); + + temp = in_be32(&ehci->usbgenctrl); + out_be32(&ehci->usbgenctrl, temp | GC_PPP | GC_PFP ); + + /* Workaround: disable ULPI phy */ + temp = 0x60000000 | 0x0C << 16 | 0x20 ; + temp = cpu_to_hc32(temp); + out_be32(&ehci->ulpi_viewpoint, temp); + + /* Configure interrupt */ + temp = ehci_readl(&hcor->or_usbintr); + temp |= (INTR_UE | INTR_UEE | INTR_PCE | INTR_SEE | INTR_AAE); + ehci_writel(&hcor->or_usbintr, temp); + + /* Init phy USB0 to UTMI+ */ + temp = ehci_readl(&hcor->or_portsc[0]); + temp &= ~(PORT_PTS_MSK | PORT_PTS_PTW); + temp |= (PORT_PTS_UTMI | PORT_PTS_PTW); + ehci_writel(&hcor->or_portsc[0], temp); + + /* Set to Host mode */ +#ifdef CONFIG_EHCI_DESC_BIG_ENDIAN + setbits_be32(&ehci->usbmode, CM_HOST | ES_BE); +#else + setbits_be32(&ehci->usbmode, CM_HOST); +#endif + return 0; } @@ -75,5 +138,16 @@ */ int ehci_hcd_stop(void) { + u32 temp; + + /* Disable phy USB0 */ + temp = ehci_readl(&hcor->or_portsc[0]); + temp &= ~(PORT_PTS_MSK | PORT_PTS_PTW | PORT_PP | PORT_PR); + ehci_writel(&hcor->or_portsc[0], temp); + + /* Unhook struct */ + hccr = hcor = NULL; + return 0; } +#endif diff -Naur u-boot.orig/drivers/usb/host/ehci.h u-boot.usb/drivers/usb/host/ehci.h --- u-boot.orig/drivers/usb/host/ehci.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/drivers/usb/host/ehci.h 2009-06-24 16:13:40.000000000 +0200 @@ -71,6 +71,11 @@ #define STD_ASS (1 << 15) #define STS_HALT (1 << 12) uint32_t or_usbintr; +#define INTR_UE (1 << 0) /* USB interrupt enable */ +#define INTR_UEE (1 << 1) /* USB error interrupt enable */ +#define INTR_PCE (1 << 2) /* Port change detect enable */ +#define INTR_SEE (1 << 4) /* system error enable */ +#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ uint32_t or_frindex; uint32_t or_ctrldssegment; uint32_t or_periodiclistbase; diff -Naur u-boot.orig/include/asm-ppc/immap_512x.h u-boot.usb/include/asm-ppc/immap_512x.h --- u-boot.orig/include/asm-ppc/immap_512x.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/asm-ppc/immap_512x.h 2009-06-24 18:28:29.000000000 +0200 @@ -1228,4 +1228,8 @@ } #endif /* __ASSEMBLY__ */ +#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000 +#define CONFIG_SYS_MPC512x_USB_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) + #endif /* __IMMAP_512x__ */ diff -Naur u-boot.orig/include/configs/mpc5121ads.h u-boot.usb/include/configs/mpc5121ads.h --- u-boot.orig/include/configs/mpc5121ads.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/configs/mpc5121ads.h 2009-06-25 01:38:29.000000000 +0200 @@ -342,6 +342,21 @@ #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +/* USB Support */ +#define CONFIG_USB + +#ifdef CONFIG_USB + #define CONFIG_USB_EHCI +#endif + +#ifdef CONFIG_USB_EHCI + #define CONFIG_USB_EHCI_FSL + #define CONFIG_EHCI_MMIO_BIG_ENDIAN + #define CONFIG_EHCI_DESC_BIG_ENDIAN + #define CONFIG_SYS_USB_EHCI_REGS_BASE 0x80004000 + #define CONFIG_EHCI_IS_TDI +#endif + /* * Environment */ @@ -387,6 +402,16 @@ #define CONFIG_ISO_PARTITION #endif /* defined(CONFIG_CMD_IDE) */ +#if defined(CONFIG_USB) +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_SUPPORT_VFAT +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif + /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set @@ -484,6 +509,7 @@ "rootpath=/opt/eldk/ppc_6xx\n" \ "netdev=eth0\0" \ "consdev=ttyPSC0\0" \ + "usb_phy_type=utmi\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ diff -Naur u-boot.orig/include/usb/ehci-fsl.h u-boot.usb/include/usb/ehci-fsl.h --- u-boot.orig/include/usb/ehci-fsl.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/usb/ehci-fsl.h 2009-06-24 16:22:15.000000000 +0200 @@ -35,12 +35,16 @@ #define PORT_PTS_ULPI (2 << 30) #define PORT_PTS_SERIAL (3 << 30) #define PORT_PTS_PTW (1 << 28) +#define PORT_PTS_PHCD (1 << 23) +#define PORT_PP (1 << 12) +#define PORT_PR (1 << 8) /* USBMODE Register bits */ #define CM_IDLE (0 << 0) #define CM_RESERVED (1 << 0) #define CM_DEVICE (2 << 0) #define CM_HOST (3 << 0) +#define ES_BE (1 << 2) /* Big Endian Select, default is LE */ #define USBMODE_RESERVED_2 (0 << 2) #define SLOM (1 << 3) #define SDIS (1 << 4) @@ -70,7 +74,74 @@ #define PHY_CLK_VALID (1 << 17) #define FSL_SOC_USB_PORTSC2 0x188 + +/* OTG Status Control Register bits */ +#define FSL_SOC_USB_OTGSC 0x1a4 +#define CTRL_VBUS_DISCHARGE (0x1<<0) +#define CTRL_VBUS_CHARGE (0x1<<1) +#define CTRL_OTG_TERMINATION (0x1<<3) +#define CTRL_DATA_PULSING (0x1<<4) +#define CTRL_ID_PULL_EN (0x1<<5) +#define HA_DATA_PULSE (0x1<<6) +#define HA_BA (0x1<<7) +#define STS_USB_ID (0x1<<8) +#define STS_A_VBUS_VALID (0x1<<9) +#define STS_A_SESSION_VALID (0x1<<10) +#define STS_B_SESSION_VALID (0x1<<11) +#define STS_B_SESSION_END (0x1<<12) +#define STS_1MS_TOGGLE (0x1<<13) +#define STS_DATA_PULSING (0x1<<14) +#define INTSTS_USB_ID (0x1<<16) +#define INTSTS_A_VBUS_VALID (0x1<<17) +#define INTSTS_A_SESSION_VALID (0x1<<18) +#define INTSTS_B_SESSION_VALID (0x1<<19) +#define INTSTS_B_SESSION_END (0x1<<20) +#define INTSTS_1MS (0x1<<21) +#define INTSTS_DATA_PULSING (0x1<<22) +#define INTR_USB_ID_EN (0x1<<24) +#define INTR_A_VBUS_VALID_EN (0x1<<25) +#define INTR_A_SESSION_VALID_EN (0x1<<26) +#define INTR_B_SESSION_VALID_EN (0x1<<27) +#define INTR_B_SESSION_END_EN (0x1<<28) +#define INTR_1MS_TIMER_EN (0x1<<29) +#define INTR_DATA_PULSING_EN (0x1<<30) +#define INTSTS_MASK (0x00ff0000) + +#define INTERRUPT_ENABLE_BITS_MASK \ + (INTR_USB_ID_EN | \ + INTR_1MS_TIMER_EN | \ + INTR_A_VBUS_VALID_EN | \ + INTR_A_SESSION_VALID_EN | \ + INTR_B_SESSION_VALID_EN | \ + INTR_B_SESSION_END_EN | \ + INTR_DATA_PULSING_EN) + +#define INTERRUPT_STATUS_BITS_MASK \ + (INTSTS_USB_ID | \ + INTR_1MS_TIMER_EN | \ + INTSTS_A_VBUS_VALID | \ + INTSTS_A_SESSION_VALID | \ + INTSTS_B_SESSION_VALID | \ + INTSTS_B_SESSION_END | \ + INTSTS_DATA_PULSING) + #define FSL_SOC_USB_USBMODE 0x1a8 + +#define USBGENCTRL 0x200 /* NOTE: big endian */ +#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ +#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ +#define GC_PPP (1 << 3) /* Port Power Polarity */ +#define GC_PFP (1 << 2) /* Power Fault Polarity */ +#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ +#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ + +#define ISIPHYCTRL 0x204 /* NOTE: big endian */ +#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ +#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ +#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ +#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ +#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ + #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ @@ -86,43 +157,59 @@ #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 #if defined(CONFIG_MPC83XX) -#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR #elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR +#elif defined(CONFIG_MPC512X) +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR #endif + /* * USB Registers */ struct usb_ehci { - u8 res1[0x100]; + u32 id; /* 0x000 - Identification register */ + u32 hwgeneral; /* 0x004 - General hardware parameters */ + u32 hwhost; /* 0x008 - Host hardware parameters */ + u32 hwdevice; /* 0x00C - Device hardware parameters */ + u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */ + u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */ + u8 res1[0x68]; + u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */ + u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */ + u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ + u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ + u32 sbuscfg; /* 0x090 - System Bus Interface Control */ + u8 res2[0x6C]; u16 caplength; /* 0x100 - Capability Register Length */ u16 hciversion; /* 0x102 - Host Interface Version */ u32 hcsparams; /* 0x104 - Host Structural Parameters */ u32 hccparams; /* 0x108 - Host Capability Parameters */ - u8 res2[0x14]; + u8 res3[0x14]; u32 dciversion; /* 0x120 - Device Interface Version */ u32 dciparams; /* 0x124 - Device Controller Params */ - u8 res3[0x18]; + u8 res4[0x18]; u32 usbcmd; /* 0x140 - USB Command */ u32 usbsts; /* 0x144 - USB Status */ u32 usbintr; /* 0x148 - USB Interrupt Enable */ u32 frindex; /* 0x14C - USB Frame Index */ - u8 res4[0x4]; + u8 res5[0x4]; u32 perlistbase; /* 0x154 - Periodic List Base - USB Device Address */ u32 ep_list_addr; /* 0x158 - Next Asynchronous List - End Point Address */ - u8 res5[0x4]; + u8 res6[0x4]; u32 burstsize; /* 0x160 - Programmable Burst Size */ u32 txfilltuning; /* 0x164 - Host TT Transmit pre-buffer packet tuning */ - u8 res6[0x8]; + u8 res7[0x8]; u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ - u8 res7[0xc]; + u8 res8[0xc]; u32 config_flag; /* 0x180 - Configured Flag Register */ u32 portsc; /* 0x184 - Port status/control */ - u8 res8[0x20]; + u8 res9[0x1C]; + u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */ u32 usbmode; /* 0x1a8 - USB Device Mode */ u32 epsetupstat; /* 0x1ac - End Point Setup Status */ u32 epprime; /* 0x1b0 - End Point Init Status */ @@ -135,15 +222,18 @@ u32 epctrl3; /* 0x1cc - End Point Control 3 */ u32 epctrl4; /* 0x1d0 - End Point Control 4 */ u32 epctrl5; /* 0x1d4 - End Point Control 5 */ - u8 res9[0x228]; + u8 res10[0x28]; + u32 usbgenctrl; /* 0x200 - USB General Control */ + u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */ + u8 res11[0x1F8]; u32 snoop1; /* 0x400 - Snoop 1 */ u32 snoop2; /* 0x404 - Snoop 2 */ u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ u32 prictrl; /* 0x40c - Priority Control */ u32 sictrl; /* 0x410 - System Interface Control */ - u8 res10[0xEC]; + u8 res12[0xEC]; u32 control; /* 0x500 - Control */ - u8 res11[0xafc]; + u8 res13[0xafc]; }; #endif /* _EHCI_FSL_H */

2 3

[U-Boot] [PATCH] 85xx: Enable the DDR3 SPD support for P2020DS board
by Dave Liu 22 Nov '09

22 Nov '09

* The ELPIDA 2GB unbuffered DDR3 SDRAM DIMMs - EBJ21EE8BAFA-AE-E 600MT/s, 667MT/s and 800MT/s passed on P2020DS * Micron 1GB unbuffered DDR3 SDRAM DIMMs - MT9JSF12872AY-1G4D1 600MT/s, 667MT/s and 800MT/s passed on P2020DS Signed-off-by: Dave Liu <daveliu(a)freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley(a)freescale.com> --- board/freescale/p2020ds/ddr.c | 34 ++++++++++++++++------------------ include/configs/P2020DS.h | 6 ++++-- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index b9c0cb2..aaff6e8 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -51,27 +51,21 @@ typedef struct { * cpo 2-0x1E (30) */ - -/* XXX: these values need to be checked for all interleaving modes. */ -/* XXX: No reliable dual-rank 800 MHz setting has been found. It may - * seem reliable, but errors will appear when memory intensive - * program is run. */ -/* XXX: Single rank at 800 MHz is OK. */ const board_specific_parameters_t board_specific_parameters[][20] = { { /* memory controller 0 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 2, 6, 7, 3, 0}, - {334, 400, 2, 6, 9, 3, 0}, - {401, 549, 2, 6, 11, 3, 0}, - {550, 680, 2, 1, 10, 5, 0}, - {681, 850, 2, 1, 12, 5, 1}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 10, 5, 0}, - {681, 850, 1, 1, 12, 5, 0} + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 2, 4, 0x1f, 2, 0}, + {334, 400, 2, 4, 0x1f, 2, 0}, + {401, 549, 2, 4, 0x1f, 2, 0}, + {550, 680, 2, 4, 0x1f, 3, 0}, + {681, 850, 2, 4, 0x1f, 4, 0}, + { 0, 333, 1, 4, 0x1f, 2, 0}, + {334, 400, 1, 4, 0x1f, 2, 0}, + {401, 549, 1, 4, 0x1f, 2, 0}, + {550, 680, 1, 4, 0x1f, 3, 0}, + {681, 850, 1, 4, 0x1f, 4, 0} }, }; @@ -127,4 +121,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; + /* + * Disable write leveling + */ + popts->wrlvl_en = 0; } diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index e4119e3..0564242 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -82,8 +82,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* @@ -121,6 +121,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CONFIG_SPD_EEPROM +#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -- 1.5.4

2 1

[U-Boot] [PATCH 2/2] 85xx: add the nfsboot/ramboot to default environment
by Dave Liu 22 Nov '09

22 Nov '09

Give the MPC8569MDS board one default environment var. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/configs/MPC8569MDS.h | 72 ++++++++++++++++++++++++------------------ 1 files changed, 41 insertions(+), 31 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b0af5dc..7fd2b56 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -409,46 +409,56 @@ extern unsigned long get_clock_freq(void); * Environment Configuration */ #define CONFIG_HOSTNAME mpc8569mds -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage +#define CONFIG_ROOTPATH /tftpboot +#define CONFIG_BOOTFILE uImage.8569 +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:85:69:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:85:69:02 + +#define CONFIG_IPADDR 192.168.1.100 #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.254 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "run nfsargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "run ramargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=u-boot.8569\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=ramdisk.8569\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=dtb.8569\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #endif /* __CONFIG_H */ -- 1.5.4

2 2

[U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board
by Ilya Yanok 19 Nov '09

19 Nov '09

This patch set adds support for LogicPD i.MX27-LITEKIT development board. It contains support for i.MX27 CPU, support for serial console, FEC ethernet controller, NFC NAND controller and SDHC controller. Signed-off-by: Ilya Yanok <yanok(a)emcraft.com>

10 33

[U-Boot] [PATCH/RFC] Better I2C support for OMAP3
by Hugo Vincent 31 Oct '09

31 Oct '09

Hi everyone, This patch improves I2C support on OMAP3 platforms, including supporting the second and third I2C controllers (mainline only supports the first controller), and supporting writes where alen=0 (i.e. no register address - this was needed for some I2C devices I needed to drive from u-boot). Tested on Gumstix Overo with several I2C devices, on I2C1 and 3. The multi-bus support is mostly from this patch: http://www.beagleboard.org/gitweb/?p=u-boot-arm.git;a=commit;h=52eddcd07c2e… Best regards, Hugo Vincent Signed-off-by: Hugo Vincent <hugo.vincent(a)gmail.com> diff --git a/board/omap3/common/power.c b/board/omap3/common/power.c index 4908e5b..efc5dd4 100644 --- a/board/omap3/common/power.c +++ b/board/omap3/common/power.c @@ -42,6 +42,7 @@ void power_init_r(void) unsigned char byte; #ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_set_bus_num(0); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 16439ac..6332965 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1324,6 +1324,7 @@ U_BOOT_CMD( #endif ); #endif /* CONFIG_I2C_CMD_TREE */ +#if !defined(CONFIG_I2C_CMD_TREE) U_BOOT_CMD( imd, 4, 1, do_i2c_md, \ "i2c memory display", \ @@ -1378,6 +1379,7 @@ U_BOOT_CMD( " (valid chip values 50..57)\n" ); #endif +#endif /* !defined(CONFIG_I2C_CMD_TREE) */ #if defined(CONFIG_I2C_MUX) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 6784603..424f172 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -1,7 +1,7 @@ /* * Basic I2C functions * - * Copyright (c) 2004 Texas Instruments + * Copyright (c) 2004, 2009 Texas Instruments * * This package is free software; you can redistribute it and/or * modify it under the terms of the license found in the file @@ -18,6 +18,7 @@ * * Adapted for OMAP2420 I2C, r-woodruff2(a)ti.com * + * Some additions by Hugo Vincent <hugo.vincent(a)gmail.com> June 2009 */ #include <common.h> @@ -25,40 +24,44 @@ #include <asm/arch/i2c.h> #include <asm/io.h> +#ifdef CONFIG_OMAP34XX +#define I2C_NUM_IF 3 +#else +#define I2C_NUM_IF 2 +#endif + static void wait_for_bb (void); static u16 wait_for_pin (void); static void flush_fifo(void); +static i2c_t *i2c = (i2c_t *)I2C_DEFAULT_BASE; + void i2c_init (int speed, int slaveadd) { - u16 scl; - - writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, &i2c->sysc); /* for ES2 after soft reset */ udelay(1000); - writew(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, &i2c->sysc); /* will probably self clear but */ - if (readw (I2C_CON) & I2C_CON_EN) { - writew (0, I2C_CON); - udelay (50000); + if (readw (&i2c->con) & I2C_CON_EN) { + writew (0, &i2c->con); + udelay (10000); } - /* 12MHz I2C module clock */ - writew (0, I2C_PSC); - speed = speed/1000; /* 100 or 400 */ - scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ - writew (scl, I2C_SCLL); - writew (scl, I2C_SCLH); + /* Timings from TRM, tested with scope - 100 kHz standard speed */ + writew (23, &i2c->psc); + writew (13, &i2c->scll); + writew (15, &i2c->sclh); /* own address */ - writew (slaveadd, I2C_OA); - writew (I2C_CON_EN, I2C_CON); + writew (slaveadd, &i2c->oa); + writew (I2C_CON_EN, &i2c->con); /* have to enable intrrupts or OMAP i2c module doesn't work */ writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c->ie); udelay (1000); flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -70,19 +77,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) wait_for_bb (); /* one byte only */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* no stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c- >con); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - writeb (regoffset, I2C_DATA); + writeb (regoffset, &i2c->data); udelay (20000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -91,28 +98,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - writew (0, I2C_CON); - while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (0, &i2c->con); + while (readw (&i2c->stat) || (readw (&i2c->con) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); } wait_for_bb (); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* read one byte from slave */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* need stop bit here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + &i2c->con); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = readb (I2C_DATA); + *value = readb (&i2c->data); #else - *value = readw (I2C_DATA); + *value = readw (&i2c->data); #endif udelay (20000); } else { @@ -120,17 +127,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) } if (!i2c_error) { - writew (I2C_CON_EN, I2C_CON); - while (readw (I2C_STAT) - || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c->con); + while (readw (&i2c->stat) + || (readw (&i2c->con) & I2C_CON_MST)) { udelay (10000); - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); } } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); return i2c_error; } @@ -143,12 +150,12 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) wait_for_bb (); /* two bytes */ - writew (2, I2C_CNT); + writew (2, &i2c->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + I2C_CON_STP, &i2c->con); /* wait until state change */ status = wait_for_pin (); @@ -156,24 +163,78 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* send out 1 byte */ - writeb (regoffset, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (regoffset, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); status = wait_for_pin (); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ - writeb (value, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (value, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); } else { i2c_error = 1; } #else /* send out two bytes */ - writew ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, &i2c->data); #endif /* must have enough delay to allow BB bit to go low */ - udelay (50000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + udelay (1000); + if (readw (&i2c->stat) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + int eout = 200; + + writew (I2C_CON_EN, &i2c->con); + while ((stat = readw (&i2c->stat)) || (readw (&i2c->con) & I2C_CON_MST)) { + udelay (1000); + /* have to read to clear intrrupt */ + writew (0xFFFF, &i2c->stat); + if(--eout == 0) /* better leave with error than hang */ + break; + } + } + flush_fifo(); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); + return i2c_error; +} + +/* Write just one byte (no reg offset) */ +static int i2c_write_byte_raw (u8 devaddr, u8 value) +{ + int i2c_error = 0; + u16 status, stat; + + /* wait until bus not busy */ + wait_for_bb (); + + /* one bytes */ + writew (1, &i2c->cnt); + /* set slave address */ + writew (devaddr, &i2c->sa); + /* stop bit needed here */ + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c->con); + + /* wait until state change */ + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* send out 1 byte */ + writeb (value, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); + + status = wait_for_pin (); + + /* must have enough delay to allow BB bit to go low */ + udelay (1000); + if (readw (&i2c->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -183,18 +244,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (!i2c_error) { int eout = 200; - writew (I2C_CON_EN, I2C_CON); - while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c->con); + while ((stat = readw (&i2c->stat)) || (readw (&i2c->con) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); return i2c_error; } @@ -205,14 +266,14 @@ static void flush_fifo(void) * you get a bus error */ while(1){ - stat = readw(I2C_STAT); + stat = readw(&i2c->stat); if(stat == I2C_STAT_RRDY){ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - readb(I2C_DATA); + readb(&i2c->data); #else - readw(I2C_DATA); + readw(&i2c->data); #endif - writew(I2C_STAT_RRDY,I2C_STAT); + writew(I2C_STAT_RRDY,&i2c->stat); udelay(1000); }else break; @@ -223,7 +284,7 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == readw (I2C_OA)) { + if (chip == readw (&i2c->oa)) { return res; } @@ -231,27 +292,27 @@ int i2c_probe (uchar chip) wait_for_bb (); /* try to read one byte */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* set slave address */ - writew (chip, I2C_SA); + writew (chip, &i2c->sa); /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c- >con); /* enough delay for the NACK bit set */ - udelay (50000); + udelay (1000); - if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (&i2c->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); - writew(0xFFFF, I2C_STAT); + writew(0xFFFF, &i2c->stat); } else { - writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ - writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, &i2c->stat); /* failue, clear sources*/ + writew (readw (&i2c->con) | I2C_CON_STP, &i2c->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - writew(0xFFFF, I2C_STAT); + writew (0, &i2c->cnt); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, &i2c->stat); return res; } @@ -284,23 +345,34 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) { int i; - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); + if (alen > 1 || alen < 0) { + printf ("I2C write: addr len %d not supported\n", alen); return 1; } if (addr + len > 256) { - printf ("I2C read: address out of range\n"); + printf ("I2C write: address out of range\n"); return 1; } - for (i = 0; i < len; i++) { - if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; + if (alen == 1) + for (i = 0; i < len; i++) + { + if (i2c_write_byte (chip, addr + i, buffer[i])) { + printf ("I2C write: I/O error\n"); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + return 1; + } + } + else if (alen == 0) + for (i = 0; i < len; i++) + { + if (i2c_write_byte_raw (chip, buffer[i])) { + printf ("I2C write: I/O error\n"); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + return 1; + } } - } return 0; } @@ -310,17 +382,17 @@ static void wait_for_bb (void) int timeout = 10; u16 stat; - writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - writew (stat, I2C_STAT); - udelay (50000); + writew(0xFFFF, &i2c->stat); /* clear current interruts...*/ + while ((stat = readw (&i2c->stat) & I2C_STAT_BB) && timeout--) { + writew (stat, &i2c->stat); + udelay (1000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - readw (I2C_STAT)); + readw (&i2c->stat)); } - writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + writew(0xFFFF, &i2c->stat); /* clear delayed stuff*/ } static u16 wait_for_pin (void) @@ -330,7 +402,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = readw (I2C_STAT); + status = readw (&i2c->stat); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -338,8 +410,55 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - readw (I2C_STAT)); - writew(0xFFFF, I2C_STAT); + readw (&i2c->stat)); + writew(0xFFFF, &i2c->stat); } return status; } + +int i2c_set_bus_num(unsigned int bus) +{ + if ((bus < 0) || (bus >= I2C_NUM_IF)) { + printf("Bad bus: %d\n", bus); + return -1; + } + +#ifdef CONFIG_OMAP34XX + if (bus == 2) + i2c = (i2c_t *)I2C_BASE3; + else +#endif + if (bus == 1) + i2c = (i2c_t *)I2C_BASE2; + else + i2c = (i2c_t *)I2C_BASE1; + + return 0; +} + +int i2c_get_bus_num(void) +{ +#ifdef CONFIG_OMAP34XX + if (i2c == (i2c_t *)I2C_BASE3) + return 2; + else +#endif + if (i2c == (i2c_t *)I2C_BASE2) + return 1; + else if (i2c == (i2c_t *)I2C_BASE1) + return 0; + else + return -1; +} + +int i2c_get_bus_speed() +{ + return 100000; +} + +int i2c_set_bus_speed(int speed) +{ + printf("Not yet implemented\n"); + return -1; +} + diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index e90db7e..234fddf 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -62,6 +62,9 @@ void twl4030_mmc_config(void) { unsigned char data; + i2c_set_bus_num(0); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + data = DEV_GRP_P1; i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEV_GRP, 1, &data, 1); data = VMMC1_VSEL_30; diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch- omap3/i2c.h index 3937f35..9638abc 100644 --- a/include/asm-arm/arch-omap3/i2c.h +++ b/include/asm-arm/arch-omap3/i2c.h @@ -25,21 +25,24 @@ #define I2C_DEFAULT_BASE I2C_BASE1 -#define I2C_REV (I2C_DEFAULT_BASE + 0x00) -#define I2C_IE (I2C_DEFAULT_BASE + 0x04) -#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) -#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) -#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) -#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) -#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) -#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) -#define I2C_CON (I2C_DEFAULT_BASE + 0x24) -#define I2C_OA (I2C_DEFAULT_BASE + 0x28) -#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) -#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) -#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) -#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) -#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) +typedef struct i2c { + unsigned int rev; /* 0x00 */ + unsigned int ie; /* 0x04 */ + unsigned int stat; /* 0x08 */ + unsigned int iv; /* 0x0c */ + unsigned int res1; /* 0x10 */ + unsigned int buf; /* 0x14 */ + unsigned int cnt; /* 0x18 */ + unsigned int data; /* 0x1c */ + unsigned int sysc; /* 0x20 */ + unsigned int con; /* 0x24 */ + unsigned int oa; /* 0x28 */ + unsigned int sa; /* 0x2c */ + unsigned int psc; /* 0x30 */ + unsigned int scll; /* 0x34 */ + unsigned int sclh; /* 0x38 */ + unsigned int systest; /* 0x3c */ +} i2c_t; /* I2C masks */ diff --git a/include/configs/omap3_overo.h b/include/configs/ omap3_overo.h index b2c42fa..d8f7a9e 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -103,6 +103,7 @@ "4m(kernel),-(fs)" #define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_I2C_CMD_TREE /* New-style command interface */ #define CONFIG_CMD_MMC /* MMC support */ #define CONFIG_CMD_NAND /* NAND support */ @@ -113,6 +114,7 @@ #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1

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[U-Boot] Question about M29W128G CFI QRY bug
by Richard Retanubun 27 Oct '09

27 Oct '09

Hi Stefan, I'm trying to get u-boot 2009.03 on coldfire to boot on flash part M29W128G. I think I am getting hit by this bug in the flash chip http://lists.infradead.org/pipermail/linux-mtd/2008-July/022252.html The debug output is as follows: U-Boot 2009.03dvl-00087-gd53876a-dirty (Apr 09 2009 - 19:00:37) CPU: Freescale ColdFire MCF5270 rev. 1, at 150 MHz Board: Ruggedcom MCF5270 I2C: ready DRAM: 8 MB Top of RAM usable for U-Boot at: 00800000 Reserving 172k for U-Boot at: 007d4000 Reserving 256k for malloc() at: 00794000 Reserving 58 Bytes for Board Info at: 00793fc6 Reserving 56 Bytes for Global Data at: 00793f8e Reserving 64k for boot parameters at: 00783f8e Stack Pointer at: 00783f68 Start relocate of code from ff000400 to 007d4000 Now running in RAM - U-Boot at: 007d4000 FLASH: flash detect cfi fwc addr ff000000 cmd f0 f0f0 16bit x 8 bit fwc addr ff000000 cmd ff ffff 16bit x 8 bit fwc addr ff0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= ff00 5151 [snip] Note that we suffer from the same bug, where QRY is not being setup properly. The notes there offers a remedy by sending ff before f0. (or skipping ff altogether). Am I on the right track here and if so, how can I make the same fix in u-boot? Thanks for your time - Richard <Raw debug output> U-Boot 2009.03dvl-00087-gd53876a-dirty (Apr 09 2009 - 19:00:37) CPU: Freescale ColdFire MCF5270 rev. 1, at 150 MHz Board: Ruggedcom MCF5270 I2C: ready DRAM: 8 MB Top of RAM usable for U-Boot at: 00800000 Reserving 172k for U-Boot at: 007d4000 Reserving 256k for malloc() at: 00794000 Reserving 58 Bytes for Board Info at: 00793fc6 Reserving 56 Bytes for Global Data at: 00793f8e Reserving 64k for boot parameters at: 00783f8e Stack Pointer at: 00783f68 Start relocate of code from ff000400 to 007d4000 Now running in RAM - U-Boot at: 007d4000 FLASH: flash detect cfi fwc addr ff000000 cmd f0 f0f0 16bit x 8 bit fwc addr ff000000 cmd ff ffff 16bit x 8 bit fwc addr ff0000aa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= ff00 5151 fwc addr ff000aaa cmd 98 9898 16bit x 8 bit is= cmd 51(Q) addr ff000020 is= ff00 5151 fwc addr ff000000 cmd f0 00f0 16bit x 16 bit fwc addr ff000000 cmd ff 00ff 16bit x 16 bit fwc addr ff0000aa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr ff000020 is= ff00 0051 fwc addr ff000aaa cmd 98 0098 16bit x 16 bit is= cmd 51(Q) addr ff000020 is= ff00 0051 fwc addr ff000000 cmd f0 f0f0f0f0 32bit x 8 bit fwc addr ff000000 cmd ff ffffffff 32bit x 8 bit fwc addr ff000154 cmd 98 98989898 32bit x 8 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 51515151 fwc addr ff001554 cmd 98 98989898 32bit x 8 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 51515151 fwc addr ff000000 cmd f0 00f000f0 32bit x 16 bit fwc addr ff000000 cmd ff 00ff00ff 32bit x 16 bit fwc addr ff000154 cmd 98 00980098 32bit x 16 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00510051 fwc addr ff001554 cmd 98 00980098 32bit x 16 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00510051 fwc addr ff000000 cmd f0 000000f0 32bit x 32 bit fwc addr ff000000 cmd ff 000000ff 32bit x 32 bit fwc addr ff000154 cmd 98 00000098 32bit x 32 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00000051 fwc addr ff001554 cmd 98 00000098 32bit x 32 bit is= cmd 51(Q) addr ff000040 is= ff0004b4 00000051 fwrite addr ff000000 cmd f0 fffffffffffffffffffff0 64 bit x 8 bit fwrite addr ff000000 cmd ff ffffffffffffffffffffff 64 bit x 8 bit fwrite addr ff0002a8 cmd 98 ffffffffffffffffffff98 64 bit x 8 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005151515151 fwrite addr ff002aa8 cmd 98 ffffffffffffffffffff98 64 bit x 8 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005151515151 fwrite addr ff000000 cmd f0 00ff00ff00ff00fffffff0 64 bit x 16 bit fwrite addr ff000000 cmd ff 00ff00ff00ff00ffffffff 64 bit x 16 bit fwrite addr ff0002a8 cmd 98 00ff00ff00ff00ffffff98 64 bit x 16 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100510051 fwrite addr ff002aa8 cmd 98 00ff00ff00ff00ffffff98 64 bit x 16 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100510051 fwrite addr ff000000 cmd f0 000000ff000000fffffff0 64 bit x 32 bit fwrite addr ff000000 cmd ff 000000ff000000ffffffff 64 bit x 32 bit fwrite addr ff0002a8 cmd 98 000000ff000000ffffff98 64 bit x 32 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100000051 fwrite addr ff002aa8 cmd 98 000000ff000000ffffff98 64 bit x 32 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234005100000051 fwrite addr ff000000 cmd f0 00000000000000fffffff0 64 bit x 64 bit fwrite addr ff000000 cmd ff 00000000000000ffffffff 64 bit x 64 bit fwrite addr ff0002a8 cmd 98 00000000000000ffffff98 64 bit x 64 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234000000000051 fwrite addr ff002aa8 cmd 98 00000000000000ffffff98 64 bit x 64 bit is= cmd 51(Q) addr ff000080 is= ff0004ffff0004ffffffb4 6234000000000051 not found ## Unknown FLASH on Bank 1 - Size = 0x00000000 = 0 MB flash_protect ON: from 0xFF000400 to 0xFF0231FF flash_protect ON: from 0xFF004000 to 0xFF005FFF *** failed *** Ignoring flash failure, see if we boot In: serial Out: serial Err: serial MAC: ethaddr 00:00:00:00:01:00 U-Boot relocated to 007d4000 Net: FEC0 [PRIME] ### main_loop entered: bootdelay=0

3 11

[U-Boot] [PATCH/RFC] env: always build env_embedded and envcrc
by Mike Frysinger 27 Oct '09

27 Oct '09

The envcrc utility is only called when it is actually needed, so having the internal code depend on ENV_IS_EMBEDDED isn't necessary. Plus, by always building it, external utils can manipulate the environment blob without having to mess around with defines. Same logic holds for env_embedded. It is already compiled for the majority of boards into a 0 byte file, so enabling it all the time shouldn't cause noticable change in overhead. The difference now is that we link it into U-Boot itself only when CONFIG_ENV_IS_EMBEDDED is defined. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- common/Makefile | 7 ++----- common/env_embedded.c | 7 ------- tools/Makefile | 10 +--------- tools/envcrc.c | 11 +---------- 4 files changed, 4 insertions(+), 31 deletions(-) diff --git a/common/Makefile b/common/Makefile index 3781738..2ace329 100644 --- a/common/Makefile +++ b/common/Makefile @@ -49,12 +49,9 @@ COBJS-y += cmd_nvedit.o # environment COBJS-y += env_common.o +COBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o COBJS-$(CONFIG_ENV_IS_IN_DATAFLASH) += env_dataflash.o COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_eeprom.o -COBJS-$(CONFIG_ENV_IS_EMBEDDED) += env_embedded.o -COBJS-$(CONFIG_ENV_IS_IN_EEPROM) += env_embedded.o -COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_embedded.o -COBJS-$(CONFIG_ENV_IS_IN_NVRAM) += env_embedded.o COBJS-$(CONFIG_ENV_IS_IN_FLASH) += env_flash.o COBJS-$(CONFIG_ENV_IS_IN_MG_DISK) += env_mgdisk.o COBJS-$(CONFIG_ENV_IS_IN_NAND) += env_nand.o @@ -168,7 +165,7 @@ OBJS := $(addprefix $(obj),$(AOBJS) $(COBJS)) CPPFLAGS += -I.. -all: $(LIB) $(AOBJS) +all: $(LIB) $(AOBJS) $(obj)env_embedded.o $(LIB): $(obj).depend $(OBJS) $(AR) $(ARFLAGS) $@ $(OBJS) diff --git a/common/env_embedded.c b/common/env_embedded.c index ae6cac4..e27e1cd 100644 --- a/common/env_embedded.c +++ b/common/env_embedded.c @@ -41,11 +41,6 @@ #endif /* - * Generate embedded environment table - * inside U-Boot image, if needed. - */ -#if defined(ENV_IS_EMBEDDED) -/* * Only put the environment in it's own section when we are building * U-Boot proper. The host based program "tools/envcrc" does not need * a seperate section. Note that ENV_CRC is only defined when building @@ -210,5 +205,3 @@ unsigned long env_size __PPCTEXT__ = sizeof(env_t); * Add in absolutes. */ GEN_ABS(env_offset, CONFIG_ENV_OFFSET); - -#endif /* ENV_IS_EMBEDDED */ diff --git a/tools/Makefile b/tools/Makefile index b5a1e39..d24f114 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -68,14 +68,7 @@ include $(TOPDIR)/config.mk # Generated executable files BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX) BIN_FILES-y += mkimage$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_DATAFLASH) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_EEPROM) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_FLASH) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_ONENAND) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_NAND) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_NVRAM) += envcrc$(SFX) -BIN_FILES-$(CONFIG_ENV_IS_IN_SPI_FLASH) += envcrc$(SFX) +BIN_FILES-y += envcrc$(SFX) BIN_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX) BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX) BIN_FILES-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX) @@ -93,7 +86,6 @@ EXT_OBJ_FILES-y += common/image.o # Source files located in the tools directory OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o OBJ_FILES-y += mkimage.o -OBJ_FILES-$(CONFIG_ENV_IS_EMBEDDED) += envcrc.o OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o diff --git a/tools/envcrc.c b/tools/envcrc.c index 5b0f7cd..d02a7db 100644 --- a/tools/envcrc.c +++ b/tools/envcrc.c @@ -50,10 +50,6 @@ # if defined(CONFIG_ENV_ADDR_REDUND) && !defined(CONFIG_ENV_SIZE_REDUND) # define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE # endif -# if (CONFIG_ENV_ADDR >= CONFIG_SYS_MONITOR_BASE) && \ - ((CONFIG_ENV_ADDR + CONFIG_ENV_SIZE) <= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) -# define ENV_IS_EMBEDDED 1 -# endif # if defined(CONFIG_ENV_ADDR_REDUND) || defined(CONFIG_ENV_OFFSET_REDUND) # define CONFIG_SYS_REDUNDAND_ENVIRONMENT 1 # endif @@ -70,14 +66,11 @@ extern uint32_t crc32 (uint32_t, const unsigned char *, unsigned int); -#ifdef ENV_IS_EMBEDDED extern unsigned int env_size; extern unsigned char environment; -#endif /* ENV_IS_EMBEDDED */ int main (int argc, char **argv) { -#ifdef ENV_IS_EMBEDDED unsigned char pad = 0x00; uint32_t crc; unsigned char *envptr = &environment, @@ -131,8 +124,6 @@ int main (int argc, char **argv) } else { printf ("0x%08X\n", crc); } -#else - printf ("0\n"); -#endif + return EXIT_SUCCESS; } -- 1.6.3.3

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