August 2009 - U-Boot

[U-Boot] [PATCH v2 0/6] Clean up top-level directory structure
by Peter Tyser 08 Dec '09

08 Dec '09

Changes since v1: - squashed lib_<ARCH> move into 1 commit - moved examples to examples/standalone - moved api_examples to examples/api This series moves api_examples to api/examples and moves all lib* directories into a common lib/ directory. It also moves the <ARCH>_config.mk files into their corresponding lib directory. Seeing 12 lib_<ARCH> directories and 12 <ARCH>_config.mk files in U-Boot's top level always annoyed me, and I finally had some time to reorganize:) I compile tested on all PPC boards and verified an out of tree build. This series needs the api_examples Make cleanup applied: http://www.mail-archive.com/u-boot@lists.denx.de/msg16032.html Peter Tyser (6): Move architecture specific config.mk files into subdirs Move lib_<ARCH> directories to lib/<ARCH> Move lib_generic to lib/generic Move libfdt to lib/libfdt Move examples/ to examples/standalone Move api_examples to examples/api Makefile | 36 +++++++++++--------- README | 24 ++++++------ board/BuS/EB+MCF-EV123/u-boot.lds | 8 ++-- board/LEOX/elpt860/u-boot.lds | 18 +++++----- board/LEOX/elpt860/u-boot.lds.debug | 4 +- board/RPXClassic/u-boot.lds | 8 ++-- board/RPXClassic/u-boot.lds.debug | 4 +- board/RPXlite/u-boot.lds | 8 ++-- board/RPXlite/u-boot.lds.debug | 4 +- board/RPXlite_dw/u-boot.lds | 8 ++-- board/RPXlite_dw/u-boot.lds.debug | 4 +- board/RRvision/u-boot.lds | 12 +++--- board/actux1/u-boot.lds | 6 ++-- board/actux2/u-boot.lds | 6 ++-- board/actux3/u-boot.lds | 6 ++-- board/amirix/ap1000/u-boot.lds | 6 ++-- board/atum8548/u-boot.lds | 6 ++-- board/bf518f-ezbrd/config.mk | 2 +- board/bf526-ezbrd/config.mk | 2 +- board/bf527-ezkit/config.mk | 2 +- board/bf533-ezkit/config.mk | 2 +- board/bf533-stamp/config.mk | 2 +- board/bf537-stamp/config.mk | 2 +- board/bf538f-ezkit/config.mk | 2 +- board/bf548-ezkit/config.mk | 2 +- board/bf561-ezkit/config.mk | 2 +- board/c2mon/u-boot.lds | 8 ++-- board/c2mon/u-boot.lds.debug | 4 +- board/cm-bf527/config.mk | 2 +- board/cm-bf533/config.mk | 2 +- board/cm-bf537e/config.mk | 2 +- board/cm-bf548/config.mk | 2 +- board/cm-bf561/config.mk | 2 +- board/cobra5272/u-boot.lds | 4 +- board/cogent/u-boot.lds.debug | 4 +- board/cray/L1/u-boot.lds | 6 ++-- board/cray/L1/u-boot.lds.debug | 6 ++-- board/csb272/u-boot.lds | 8 ++-- board/csb472/u-boot.lds | 8 ++-- board/dave/PPChameleonEVB/u-boot.lds | 6 ++-- board/eltec/mhpc/u-boot.lds.debug | 4 +- board/emk/top860/u-boot.lds.debug | 6 ++-- board/eric/u-boot.lds | 6 ++-- board/esd/ocrtc/u-boot.lds | 6 ++-- board/esd/tasreg/u-boot.lds | 4 +- board/esteem192e/u-boot.lds | 8 ++-- board/etx094/u-boot.lds | 4 +- board/etx094/u-boot.lds.debug | 8 ++-- board/exbitgen/u-boot.lds | 6 ++-- board/fads/u-boot.lds.debug | 6 ++-- board/flagadm/u-boot.lds.debug | 4 +- board/freescale/m52277evb/u-boot.spa | 4 +- board/freescale/m5235evb/u-boot.16 | 6 ++-- board/freescale/m5235evb/u-boot.32 | 4 +- board/freescale/m5249evb/u-boot.lds | 4 +- board/freescale/m5253demo/u-boot.lds | 4 +- board/freescale/m5253evbe/u-boot.lds | 4 +- board/freescale/m5271evb/u-boot.lds | 4 +- board/freescale/m5272c3/u-boot.lds | 4 +- board/freescale/m5275evb/u-boot.lds | 4 +- board/freescale/m5282evb/u-boot.lds | 6 ++-- board/freescale/m53017evb/u-boot.lds | 4 +- board/freescale/m5329evb/u-boot.lds | 6 ++-- board/freescale/m5373evb/u-boot.lds | 6 ++-- board/freescale/m54451evb/u-boot.spa | 6 ++-- board/freescale/m54451evb/u-boot.stm | 4 +- board/freescale/m54455evb/u-boot.atm | 6 ++-- board/freescale/m54455evb/u-boot.int | 6 ++-- board/freescale/m547xevb/u-boot.lds | 4 +- board/freescale/m548xevb/u-boot.lds | 4 +- board/freescale/mpc7448hpc2/tsi108_init.c | 2 +- board/freescale/mpc8610hpcd/u-boot.lds | 6 ++-- board/freescale/mpc8641hpcn/u-boot.lds | 6 ++-- board/freescale/mx31ads/u-boot.lds | 2 +- board/genietv/u-boot.lds | 8 ++-- board/genietv/u-boot.lds.debug | 8 ++-- board/hermes/u-boot.lds | 8 ++-- board/hermes/u-boot.lds.debug | 6 ++-- board/hymod/u-boot.lds | 8 ++-- board/hymod/u-boot.lds.debug | 4 +- board/icu862/u-boot.lds | 8 ++-- board/icu862/u-boot.lds.debug | 6 ++-- board/idmr/u-boot.lds | 4 +- board/ip860/u-boot.lds | 6 ++-- board/ip860/u-boot.lds.debug | 6 ++-- board/ivm/u-boot.lds.debug | 6 ++-- board/jse/jse.c | 6 ++-- board/jse/sdram.c | 2 +- board/keymile/km8xx/u-boot.lds | 12 +++--- board/kup/kup4k/u-boot.lds | 8 ++-- board/kup/kup4k/u-boot.lds.debug | 4 +- board/kup/kup4x/u-boot.lds | 8 ++-- board/kup/kup4x/u-boot.lds.debug | 4 +- board/lantec/u-boot.lds | 8 ++-- board/lantec/u-boot.lds.debug | 4 +- board/lwmon/u-boot.lds.debug | 6 ++-- board/mbx8xx/u-boot.lds.debug | 6 ++-- board/ml2/u-boot.lds | 6 ++-- board/ml2/u-boot.lds.debug | 6 ++-- board/mousse/u-boot.lds | 10 +++--- board/mousse/u-boot.lds.rom | 8 ++-- board/mpc8540eval/u-boot.lds | 6 ++-- board/mpl/mip405/u-boot.lds | 6 ++-- board/mpl/pip405/u-boot.lds | 6 ++-- board/mpl/pip405/u-boot.lds.debug | 6 ++-- board/netphone/u-boot.lds | 12 +++--- board/netphone/u-boot.lds.debug | 4 +- board/netstal/hcu4/hcu4.c | 2 +- board/netstal/hcu5/README.txt | 6 ++-- board/netstal/hcu5/hcu5.c | 2 +- board/netstal/mcu25/mcu25.c | 2 +- board/netstar/Makefile | 4 +- board/netta/u-boot.lds | 12 +++--- board/netta/u-boot.lds.debug | 4 +- board/netta2/u-boot.lds | 12 +++--- board/netta2/u-boot.lds.debug | 4 +- board/netvia/u-boot.lds | 12 +++--- board/netvia/u-boot.lds.debug | 4 +- board/nx823/u-boot.lds.debug | 4 +- board/pcs440ep/u-boot.lds | 2 +- board/pm854/u-boot.lds | 6 ++-- board/pm856/u-boot.lds | 6 ++-- board/purple/u-boot.lds | 2 +- board/quantum/u-boot.lds | 8 ++-- board/quantum/u-boot.lds.debug | 4 +- board/rbc823/u-boot.lds | 8 ++-- board/rmu/u-boot.lds | 8 ++-- board/rmu/u-boot.lds.debug | 4 +- board/sandburst/karef/u-boot.lds | 6 ++-- board/sandburst/karef/u-boot.lds.debug | 6 ++-- board/sandburst/metrobox/u-boot.lds | 6 ++-- board/sandburst/metrobox/u-boot.lds.debug | 6 ++-- board/sbc405/u-boot.lds | 6 ++-- board/sbc8548/u-boot.lds | 6 ++-- board/sbc8560/u-boot.lds | 6 ++-- board/sbc8641d/u-boot.lds | 6 ++-- board/sc3/u-boot.lds | 6 ++-- board/siemens/CCM/u-boot.lds | 8 ++-- board/siemens/CCM/u-boot.lds.debug | 4 +- board/siemens/IAD210/u-boot.lds | 4 +- board/siemens/pcu_e/u-boot.lds.debug | 6 ++-- board/snmc/qs850/u-boot.lds | 12 +++--- board/snmc/qs860t/u-boot.lds | 12 +++--- board/socrates/u-boot.lds | 6 ++-- board/spc1920/u-boot.lds | 12 +++--- board/spd8xx/u-boot.lds.debug | 6 ++-- board/stxgp3/u-boot.lds | 6 ++-- board/stxssa/stxssa.c | 2 +- board/stxssa/u-boot.lds | 6 ++-- board/stxxtc/u-boot.lds | 12 +++--- board/stxxtc/u-boot.lds.debug | 4 +- board/svm_sc8xx/u-boot.lds | 12 +++--- board/svm_sc8xx/u-boot.lds.debug | 4 +- board/tcm-bf537/config.mk | 2 +- board/tqc/tqm85xx/u-boot.lds | 6 ++-- board/tqc/tqm8xx/u-boot.lds | 10 +++--- board/tqc/tqm8xx/u-boot.lds.debug | 4 +- board/trab/Makefile | 6 ++-- board/trab/u-boot.lds | 8 ++-- board/uc100/u-boot.lds | 12 +++--- board/uc100/u-boot.lds.debug | 4 +- board/v37/u-boot.lds | 12 +++--- board/voiceblue/Makefile | 2 +- board/w7o/u-boot.lds.debug | 6 ++-- board/westel/amx860/u-boot.lds | 8 ++-- board/westel/amx860/u-boot.lds.debug | 6 ++-- board/xes/xpedite5170/u-boot.lds | 6 ++-- board/xilinx/ml300/u-boot.lds | 6 ++-- board/xilinx/ml300/u-boot.lds.debug | 6 ++-- board/xpedite1k/u-boot.lds | 6 ++-- board/xpedite1k/u-boot.lds.debug | 6 ++-- config.mk | 2 +- cpu/mpc5xxx/u-boot-customlayout.lds | 6 ++-- doc/README.LED | 2 +- doc/README.alaska8220 | 2 +- doc/README.m52277evb | 12 +++--- doc/README.m53017evb | 12 +++--- doc/README.m5373evb | 12 +++--- doc/README.m54455evb | 12 +++--- doc/README.m5475evb | 10 +++--- doc/README.mpc5xx | 6 ++-- doc/README.nios | 2 +- doc/TODO-i386 | 2 +- {api_examples => examples/api}/.gitignore | 0 {api_examples => examples/api}/Makefile | 22 ++++++------ {api_examples => examples/api}/crt0.S | 0 {api_examples => examples/api}/demo.c | 0 {api_examples => examples/api}/glue.c | 0 {api_examples => examples/api}/glue.h | 0 {api_examples => examples/api}/libgenwrap.c | 2 +- examples/{ => standalone}/.gitignore | 0 examples/{ => standalone}/82559_eeprom.c | 0 examples/{ => standalone}/Makefile | 0 examples/{ => standalone}/README.smc91111_eeprom | 0 examples/{ => standalone}/eepro100_eeprom.c | 0 examples/{ => standalone}/hello_world.c | 0 examples/{ => standalone}/interrupt.c | 0 examples/{ => standalone}/mem_to_mem_idma2intr.c | 0 examples/{ => standalone}/mips.lds | 0 examples/{ => standalone}/nios.lds | 0 examples/{ => standalone}/nios2.lds | 0 examples/{ => standalone}/ppc_longjmp.S | 0 examples/{ => standalone}/ppc_setjmp.S | 0 examples/{ => standalone}/sched.c | 0 examples/{ => standalone}/smc91111_eeprom.c | 0 examples/{ => standalone}/smc911x_eeprom.c | 0 examples/{ => standalone}/sparc.lds | 0 examples/{ => standalone}/stubs.c | 0 examples/{ => standalone}/test_burst.c | 0 examples/{ => standalone}/test_burst.h | 0 examples/{ => standalone}/test_burst_lib.S | 0 examples/{ => standalone}/timer.c | 0 examples/{ => standalone}/x86-testapp.c | 0 include/asm-i386/interrupt.h | 2 +- include/asm-i386/u-boot-i386.h | 4 +- include/common.h | 14 ++++---- include/configs/B2.h | 2 +- include/configs/bf533-stamp.h | 2 +- include/configs/bf537-pnav.h | 2 +- include/configs/bf537-stamp.h | 2 +- include/configs/bf538f-ezkit.h | 2 +- include/configs/bf561-ezkit.h | 4 +- include/configs/cm-bf537e.h | 2 +- include/configs/ibf-dsp561.h | 4 +- include/configs/tcm-bf537.h | 2 +- include/lzma/LzmaDecode.h | 2 +- include/lzma/LzmaTools.h | 2 +- include/lzma/LzmaTypes.h | 2 +- {lib_arm => lib/arm}/Makefile | 0 {lib_arm => lib/arm}/_ashldi3.S | 0 {lib_arm => lib/arm}/_ashrdi3.S | 0 {lib_arm => lib/arm}/_divsi3.S | 0 {lib_arm => lib/arm}/_modsi3.S | 0 {lib_arm => lib/arm}/_udivsi3.S | 0 {lib_arm => lib/arm}/_umodsi3.S | 0 {lib_arm => lib/arm}/board.c | 0 {lib_arm => lib/arm}/bootm.c | 0 {lib_arm => lib/arm}/cache-cp15.c | 0 {lib_arm => lib/arm}/cache.c | 0 arm_config.mk => lib/arm/config.mk | 0 {lib_arm => lib/arm}/div0.c | 0 {lib_arm => lib/arm}/interrupts.c | 0 {lib_arm => lib/arm}/reset.c | 0 {lib_avr32 => lib/avr32}/Makefile | 0 {lib_avr32 => lib/avr32}/board.c | 0 {lib_avr32 => lib/avr32}/bootm.c | 0 avr32_config.mk => lib/avr32/config.mk | 0 {lib_avr32 => lib/avr32}/interrupts.c | 0 {lib_avr32 => lib/avr32}/memset.S | 0 {lib_blackfin => lib/blackfin}/.gitignore | 0 {lib_blackfin => lib/blackfin}/Makefile | 0 {lib_blackfin => lib/blackfin}/board.c | 0 {lib_blackfin => lib/blackfin}/boot.c | 0 {lib_blackfin => lib/blackfin}/cache.c | 0 {lib_blackfin => lib/blackfin}/clocks.c | 0 blackfin_config.mk => lib/blackfin/config.mk | 2 +- {lib_blackfin => lib/blackfin}/memcmp.S | 0 {lib_blackfin => lib/blackfin}/memcpy.S | 0 {lib_blackfin => lib/blackfin}/memmove.S | 0 {lib_blackfin => lib/blackfin}/memset.S | 0 {lib_blackfin => lib/blackfin}/muldi3.c | 0 {lib_blackfin => lib/blackfin}/post.c | 0 {lib_blackfin => lib/blackfin}/string.c | 0 {lib_blackfin => lib/blackfin}/tests.c | 0 {lib_blackfin => lib/blackfin}/u-boot.lds.S | 0 {lib_generic => lib/generic}/Makefile | 0 {lib_generic => lib/generic}/addr_map.c | 0 {lib_generic => lib/generic}/bzlib.c | 0 {lib_generic => lib/generic}/bzlib_crctable.c | 0 {lib_generic => lib/generic}/bzlib_decompress.c | 0 {lib_generic => lib/generic}/bzlib_huffman.c | 0 {lib_generic => lib/generic}/bzlib_private.h | 0 {lib_generic => lib/generic}/bzlib_randtable.c | 0 {lib_generic => lib/generic}/crc16.c | 0 {lib_generic => lib/generic}/crc32.c | 0 {lib_generic => lib/generic}/ctype.c | 0 {lib_generic => lib/generic}/display_options.c | 0 {lib_generic => lib/generic}/div64.c | 0 {lib_generic => lib/generic}/gunzip.c | 0 {lib_generic => lib/generic}/ldiv.c | 0 {lib_generic => lib/generic}/lmb.c | 0 {lib_generic => lib/generic}/lzma/LGPL.txt | 0 {lib_generic => lib/generic}/lzma/LzmaDecode.c | 0 {lib_generic => lib/generic}/lzma/LzmaDecode.h | 0 {lib_generic => lib/generic}/lzma/LzmaTools.c | 0 {lib_generic => lib/generic}/lzma/LzmaTools.h | 0 {lib_generic => lib/generic}/lzma/LzmaTypes.h | 0 {lib_generic => lib/generic}/lzma/Makefile | 0 {lib_generic => lib/generic}/lzma/README.txt | 0 {lib_generic => lib/generic}/lzma/history.txt | 0 .../generic}/lzma/import_lzmasdk.sh | 0 {lib_generic => lib/generic}/lzma/lzma.txt | 0 {lib_generic => lib/generic}/lzo/Makefile | 0 .../generic}/lzo/lzo1x_decompress.c | 0 {lib_generic => lib/generic}/lzo/lzodefs.h | 0 {lib_generic => lib/generic}/md5.c | 0 {lib_generic => lib/generic}/rbtree.c | 0 {lib_generic => lib/generic}/sha1.c | 0 {lib_generic => lib/generic}/sha256.c | 0 {lib_generic => lib/generic}/string.c | 0 {lib_generic => lib/generic}/strmhz.c | 0 {lib_generic => lib/generic}/vsprintf.c | 0 {lib_generic => lib/generic}/zlib.c | 0 {lib_i386 => lib/i386}/Makefile | 0 {lib_i386 => lib/i386}/bios.S | 0 {lib_i386 => lib/i386}/bios.h | 0 {lib_i386 => lib/i386}/bios_pci.S | 0 {lib_i386 => lib/i386}/bios_setup.c | 0 {lib_i386 => lib/i386}/board.c | 0 {lib_i386 => lib/i386}/bootm.c | 0 i386_config.mk => lib/i386/config.mk | 0 {lib_i386 => lib/i386}/interrupts.c | 0 {lib_i386 => lib/i386}/pcat_interrupts.c | 0 {lib_i386 => lib/i386}/pcat_timer.c | 0 {lib_i386 => lib/i386}/pci.c | 0 {lib_i386 => lib/i386}/pci_type1.c | 0 {lib_i386 => lib/i386}/realmode.c | 0 {lib_i386 => lib/i386}/realmode_switch.S | 0 {lib_i386 => lib/i386}/timer.c | 0 {lib_i386 => lib/i386}/video.c | 0 {lib_i386 => lib/i386}/video_bios.c | 0 {lib_i386 => lib/i386}/zimage.c | 0 {libfdt => lib/libfdt}/Makefile | 0 {libfdt => lib/libfdt}/README | 0 {libfdt => lib/libfdt}/fdt.c | 0 {libfdt => lib/libfdt}/fdt_ro.c | 0 {libfdt => lib/libfdt}/fdt_rw.c | 0 {libfdt => lib/libfdt}/fdt_strerror.c | 0 {libfdt => lib/libfdt}/fdt_sw.c | 0 {libfdt => lib/libfdt}/fdt_wip.c | 0 {libfdt => lib/libfdt}/libfdt_internal.h | 0 {lib_m68k => lib/m68k}/Makefile | 0 {lib_m68k => lib/m68k}/board.c | 0 {lib_m68k => lib/m68k}/bootm.c | 0 {lib_m68k => lib/m68k}/cache.c | 0 m68k_config.mk => lib/m68k/config.mk | 0 {lib_m68k => lib/m68k}/interrupts.c | 0 {lib_m68k => lib/m68k}/time.c | 0 {lib_m68k => lib/m68k}/traps.c | 0 {lib_microblaze => lib/microblaze}/Makefile | 0 {lib_microblaze => lib/microblaze}/board.c | 0 {lib_microblaze => lib/microblaze}/bootm.c | 0 {lib_microblaze => lib/microblaze}/cache.c | 0 microblaze_config.mk => lib/microblaze/config.mk | 0 {lib_microblaze => lib/microblaze}/time.c | 0 {lib_mips => lib/mips}/Makefile | 0 {lib_mips => lib/mips}/board.c | 0 {lib_mips => lib/mips}/bootm.c | 0 {lib_mips => lib/mips}/bootm_qemu_mips.c | 0 mips_config.mk => lib/mips/config.mk | 0 {lib_mips => lib/mips}/time.c | 0 {lib_nios => lib/nios}/Makefile | 0 {lib_nios => lib/nios}/board.c | 0 {lib_nios => lib/nios}/bootm.c | 0 {lib_nios => lib/nios}/cache.c | 0 nios_config.mk => lib/nios/config.mk | 0 {lib_nios => lib/nios}/divmod.c | 0 {lib_nios => lib/nios}/math.h | 0 {lib_nios => lib/nios}/mult.c | 0 {lib_nios => lib/nios}/time.c | 0 {lib_nios2 => lib/nios2}/Makefile | 0 {lib_nios2 => lib/nios2}/board.c | 0 {lib_nios2 => lib/nios2}/bootm.c | 0 {lib_nios2 => lib/nios2}/cache.S | 0 nios2_config.mk => lib/nios2/config.mk | 0 {lib_nios2 => lib/nios2}/divmod.c | 0 {lib_nios2 => lib/nios2}/math.h | 0 {lib_nios2 => lib/nios2}/mult.c | 0 {lib_nios2 => lib/nios2}/time.c | 0 {lib_ppc => lib/ppc}/Makefile | 0 {lib_ppc => lib/ppc}/bat_rw.c | 0 {lib_ppc => lib/ppc}/board.c | 0 {lib_ppc => lib/ppc}/bootm.c | 0 {lib_ppc => lib/ppc}/cache.c | 0 ppc_config.mk => lib/ppc/config.mk | 0 {lib_ppc => lib/ppc}/extable.c | 0 {lib_ppc => lib/ppc}/interrupts.c | 0 {lib_ppc => lib/ppc}/kgdb.c | 0 {lib_ppc => lib/ppc}/ppccache.S | 0 {lib_ppc => lib/ppc}/ppcstring.S | 0 {lib_ppc => lib/ppc}/ticks.S | 0 {lib_ppc => lib/ppc}/time.c | 0 {lib_sh => lib/sh}/Makefile | 0 {lib_sh => lib/sh}/board.c | 0 {lib_sh => lib/sh}/bootm.c | 0 sh_config.mk => lib/sh/config.mk | 0 {lib_sh => lib/sh}/time.c | 0 {lib_sh => lib/sh}/time_sh2.c | 0 {lib_sparc => lib/sparc}/Makefile | 0 {lib_sparc => lib/sparc}/board.c | 0 {lib_sparc => lib/sparc}/bootm.c | 0 {lib_sparc => lib/sparc}/cache.c | 0 sparc_config.mk => lib/sparc/config.mk | 0 {lib_sparc => lib/sparc}/interrupts.c | 0 {lib_sparc => lib/sparc}/time.c | 0 nand_spl/board/freescale/mpc8313erdb/Makefile | 6 ++-- nand_spl/board/sheldon/simpc8313/Makefile | 6 ++-- tools/Makefile | 12 +++--- tools/env/Makefile | 2 +- tools/imls/Makefile | 14 ++++---- 400 files changed, 617 insertions(+), 613 deletions(-) rename {api_examples => examples/api}/.gitignore (100%) rename {api_examples => examples/api}/Makefile (80%) rename {api_examples => examples/api}/crt0.S (100%) rename {api_examples => examples/api}/demo.c (100%) rename {api_examples => examples/api}/glue.c (100%) rename {api_examples => examples/api}/glue.h (100%) rename {api_examples => examples/api}/libgenwrap.c (96%) rename examples/{ => standalone}/.gitignore (100%) rename examples/{ => standalone}/82559_eeprom.c (100%) rename examples/{ => standalone}/Makefile (100%) rename examples/{ => standalone}/README.smc91111_eeprom (100%) rename examples/{ => standalone}/eepro100_eeprom.c (100%) rename examples/{ => standalone}/hello_world.c (100%) rename examples/{ => standalone}/interrupt.c (100%) rename examples/{ => standalone}/mem_to_mem_idma2intr.c (100%) rename examples/{ => standalone}/mips.lds (100%) rename examples/{ => standalone}/nios.lds (100%) rename examples/{ => standalone}/nios2.lds (100%) rename examples/{ => standalone}/ppc_longjmp.S (100%) rename examples/{ => standalone}/ppc_setjmp.S (100%) rename examples/{ => standalone}/sched.c (100%) rename examples/{ => standalone}/smc91111_eeprom.c (100%) rename examples/{ => standalone}/smc911x_eeprom.c (100%) rename examples/{ => standalone}/sparc.lds (100%) rename examples/{ => standalone}/stubs.c (100%) rename examples/{ => standalone}/test_burst.c (100%) rename examples/{ => standalone}/test_burst.h (100%) rename examples/{ => standalone}/test_burst_lib.S (100%) rename examples/{ => standalone}/timer.c (100%) rename examples/{ => standalone}/x86-testapp.c (100%) rename {lib_arm => lib/arm}/Makefile (100%) rename {lib_arm => lib/arm}/_ashldi3.S (100%) rename {lib_arm => lib/arm}/_ashrdi3.S (100%) rename {lib_arm => lib/arm}/_divsi3.S (100%) rename {lib_arm => lib/arm}/_modsi3.S (100%) rename {lib_arm => lib/arm}/_udivsi3.S (100%) rename {lib_arm => lib/arm}/_umodsi3.S (100%) rename {lib_arm => lib/arm}/board.c (100%) rename {lib_arm => lib/arm}/bootm.c (100%) rename {lib_arm => lib/arm}/cache-cp15.c (100%) rename {lib_arm => lib/arm}/cache.c (100%) rename arm_config.mk => lib/arm/config.mk (100%) rename {lib_arm => lib/arm}/div0.c (100%) rename {lib_arm => lib/arm}/interrupts.c (100%) rename {lib_arm => lib/arm}/reset.c (100%) rename {lib_avr32 => lib/avr32}/Makefile (100%) rename {lib_avr32 => lib/avr32}/board.c (100%) rename {lib_avr32 => lib/avr32}/bootm.c (100%) rename avr32_config.mk => lib/avr32/config.mk (100%) rename {lib_avr32 => lib/avr32}/interrupts.c (100%) rename {lib_avr32 => lib/avr32}/memset.S (100%) rename {lib_blackfin => lib/blackfin}/.gitignore (100%) rename {lib_blackfin => lib/blackfin}/Makefile (100%) rename {lib_blackfin => lib/blackfin}/board.c (100%) rename {lib_blackfin => lib/blackfin}/boot.c (100%) rename {lib_blackfin => lib/blackfin}/cache.c (100%) rename {lib_blackfin => lib/blackfin}/clocks.c (100%) rename blackfin_config.mk => lib/blackfin/config.mk (98%) rename {lib_blackfin => lib/blackfin}/memcmp.S (100%) rename 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lib/ppc/config.mk (100%) rename {lib_ppc => lib/ppc}/extable.c (100%) rename {lib_ppc => lib/ppc}/interrupts.c (100%) rename {lib_ppc => lib/ppc}/kgdb.c (100%) rename {lib_ppc => lib/ppc}/ppccache.S (100%) rename {lib_ppc => lib/ppc}/ppcstring.S (100%) rename {lib_ppc => lib/ppc}/ticks.S (100%) rename {lib_ppc => lib/ppc}/time.c (100%) rename {lib_sh => lib/sh}/Makefile (100%) rename {lib_sh => lib/sh}/board.c (100%) rename {lib_sh => lib/sh}/bootm.c (100%) rename sh_config.mk => lib/sh/config.mk (100%) rename {lib_sh => lib/sh}/time.c (100%) rename {lib_sh => lib/sh}/time_sh2.c (100%) rename {lib_sparc => lib/sparc}/Makefile (100%) rename {lib_sparc => lib/sparc}/board.c (100%) rename {lib_sparc => lib/sparc}/bootm.c (100%) rename {lib_sparc => lib/sparc}/cache.c (100%) rename sparc_config.mk => lib/sparc/config.mk (100%) rename {lib_sparc => lib/sparc}/interrupts.c (100%) rename {lib_sparc => lib/sparc}/time.c (100%)

9 36

[U-Boot] [PATCH] Add inverted clock polarity support for Atmel LCD driver
by Dimitar Dimitrov 05 Dec '09

05 Dec '09

This is my third try for Olimex SAM9-L9260/61 board support patches. Here follows the first patch. --- Boards utilizing the Atmel LCD driver can now specify that the LCD clock must be inverted by defining the macro CONFIG_LCD_INVERTED_CLOCK. --- README | 5 +++++ drivers/video/atmel_lcdfb.c | 3 +++ 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/README b/README index de700bd..d7c0afe 100644 --- a/README +++ b/README @@ -1063,6 +1063,11 @@ The following options need to be configured: Normally display is black on white background; define CONFIG_SYS_WHITE_ON_BLACK to get it inverted. + CONFIG_LCD_INVERTED_CLOCK + Define this if your LCD needs inverted clock polarity. Note + that this feature will work only if the selected LCD driver + and hardware controller support it. + - Splash Screen Support: CONFIG_SPLASH_SCREEN If this option is set, the environment is checked for diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index db86763..d3e988e 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -112,6 +112,9 @@ void lcd_ctrl_init(void *lcdbase) value |= panel_info.vl_sync; value |= (panel_info.vl_bpix << 5); +#if defined(CONFIG_LCD_INVERTED_CLOCK) + value |= ATMEL_LCDC_INVCLK_INVERTED; +#endif lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value); /* Vertical timing */ -- 1.5.6.1

4 12

[U-Boot] [PATCH 1/1] avr32/hsdramc: Move conditional compilation to Makefile
by Jean-Christophe PLAGNIOL-VILLARD 26 Nov '09

26 Nov '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> Cc: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> --- cpu/at32ap/Makefile | 2 +- cpu/at32ap/hsdramc.c | 3 --- 2 files changed, 1 insertions(+), 4 deletions(-) diff --git a/cpu/at32ap/Makefile b/cpu/at32ap/Makefile index e08f273..60899c7 100644 --- a/cpu/at32ap/Makefile +++ b/cpu/at32ap/Makefile @@ -30,7 +30,7 @@ LIB := $(obj)lib$(CPU).a START-y += start.o COBJS-y += cpu.o -COBJS-y += hsdramc.o +COBJS-$(CONFIG_SYS_HSDRAMC) += hsdramc.o COBJS-y += exception.o COBJS-y += cache.o COBJS-y += interrupts.o diff --git a/cpu/at32ap/hsdramc.c b/cpu/at32ap/hsdramc.c index f74121c..b6eae66 100644 --- a/cpu/at32ap/hsdramc.c +++ b/cpu/at32ap/hsdramc.c @@ -21,7 +21,6 @@ */ #include <common.h> -#ifdef CONFIG_SYS_HSDRAMC #include <asm/io.h> #include <asm/sdram.h> @@ -116,5 +115,3 @@ unsigned long sdram_init(void *sdram_base, const struct sdram_config *config) return sdram_size; } - -#endif /* CONFIG_SYS_HSDRAMC */ -- 1.6.3.1

4 3

[U-Boot] [PATCH] AT91: revise serial lines pullup configuration,
by Andrzej Wolski 26 Nov '09

26 Nov '09

Currently pullups are incorrectly set for all AT91 SoCs: pullup for TXD line is enabled, what is not necessary, but pullup for RXD line, what may be necessary for some boards, is disabled. This patch fixes it: it enables pullup only for RXD line. Signed-off-by: Andrzej Wolski <awolski(a)poczta.fm> --- cpu/arm926ejs/at91/at91cap9_devices.c | 16 ++++++++-------- cpu/arm926ejs/at91/at91sam9260_devices.c | 16 ++++++++-------- cpu/arm926ejs/at91/at91sam9261_devices.c | 16 ++++++++-------- cpu/arm926ejs/at91/at91sam9263_devices.c | 16 ++++++++-------- cpu/arm926ejs/at91/at91sam9m10g45_devices.c | 16 ++++++++-------- cpu/arm926ejs/at91/at91sam9rl_devices.c | 16 ++++++++-------- 6 files changed, 48 insertions(+), 48 deletions(-) diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c index 39e405f..681a8c1 100644 --- a/cpu/arm926ejs/at91/at91cap9_devices.c +++ b/cpu/arm926ejs/at91/at91cap9_devices.c @@ -34,29 +34,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA22, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA23, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PA22, 0); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA23, 1); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PD0, 0); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 1); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PD2, 0); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 1); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_set_A_periph(AT91_PIN_PC30, 1); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 0); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } diff --git a/cpu/arm926ejs/at91/at91sam9260_devices.c b/cpu/arm926ejs/at91/at91sam9260_devices.c index 5309ba2..674fc88 100644 --- a/cpu/arm926ejs/at91/at91sam9260_devices.c +++ b/cpu/arm926ejs/at91/at91sam9260_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB5, 1); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PB6, 0); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB7, 1); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PB8, 0); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PB9, 1); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */ + at91_set_A_periph(AT91_PIN_PB14, 1); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB15, 0); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c index 16d411f..56a22c4 100644 --- a/cpu/arm926ejs/at91/at91sam9261_devices.c +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC8, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PC9, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PC8, 0); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PC9, 1); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC12, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PC13, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PC12, 0); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PC13, 1); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC14, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PC15, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PC14, 0); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PC15, 1); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA9, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA10, 1); /* DTXD */ + at91_set_A_periph(AT91_PIN_PA9, 1); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA10, 0); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c index f72efdf..6e7275d 100644 --- a/cpu/arm926ejs/at91/at91sam9263_devices.c +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c @@ -34,29 +34,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PA26, 0); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA27, 1); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PD0, 0); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PD1, 1); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PD2, 0); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD3, 1); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */ + at91_set_A_periph(AT91_PIN_PC30, 1); /* DRXD */ + at91_set_A_periph(AT91_PIN_PC31, 0); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c index 98d90f2..f413855 100644 --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PB19, 0); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PB18, 1); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PB4, 0); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PB5, 1); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PD6, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PD7, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PD6, 0); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PD7, 1); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */ + at91_set_A_periph(AT91_PIN_PB12, 1); /* DRXD */ + at91_set_A_periph(AT91_PIN_PB13, 0); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);; } diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c index ebed193..82d1c63 100644 --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c @@ -30,29 +30,29 @@ void at91_serial0_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */ - at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */ + at91_set_A_periph(AT91_PIN_PA6, 0); /* TXD0 */ + at91_set_A_periph(AT91_PIN_PA7, 1); /* RXD0 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US0); } void at91_serial1_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */ - at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */ + at91_set_A_periph(AT91_PIN_PA11, 0); /* TXD1 */ + at91_set_A_periph(AT91_PIN_PA12, 1); /* RXD1 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US1); } void at91_serial2_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */ - at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */ + at91_set_A_periph(AT91_PIN_PA13, 0); /* TXD2 */ + at91_set_A_periph(AT91_PIN_PA14, 1); /* RXD2 */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9RL_ID_US2); } void at91_serial3_hw_init(void) { - at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */ - at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */ + at91_set_A_periph(AT91_PIN_PA21, 1); /* DRXD */ + at91_set_A_periph(AT91_PIN_PA22, 0); /* DTXD */ at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS); } ---------------------------------------------------------------------- Rowerem do pracy? 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3 3

[U-Boot] [PATCH 0/3] DMA ECC update
by Peter Tyser 24 Nov '09

24 Nov '09

These changes bring the 83xx SDRAM ECC initialization in line with the 85xx/86xx boards and also fixes a minor bug in fsl_dma.c. I don't have any 83xx boards to test on, so it would be appreciated if someone with 83xx hardware that uses ECC could give the patches a shot. It'd be nice if SDRAM could be initialized via the DDR controller with CONFIG_ECC_INIT_VIA_DDRCONTROLLER on the 83xx platform too, but I'm not going to tackle it:) The patches also resolve the compile error Stefan brought up with non-freescale boards with CONFIG_ECC. Peter Tyser (3): 83xx: Default to using DMA to initialize SDRAM 83xx: Added CONFIG_MEM_INIT_VALUE for boards with ECC fsl_dma: Fix SDRAM initial value cpu/mpc83xx/spd_sdram.c | 57 +++-------------------------------------- drivers/dma/fsl_dma.c | 9 ++---- include/asm-ppc/config.h | 7 ++--- include/configs/MPC8349EMDS.h | 1 + include/configs/MPC8360EMDS.h | 1 + include/configs/MPC8360ERDK.h | 1 + include/configs/MPC837XEMDS.h | 1 + include/configs/MPC837XERDB.h | 1 + include/configs/TQM834x.h | 1 + include/configs/kmeter1.h | 1 + include/configs/sbc8349.h | 1 + 11 files changed, 18 insertions(+), 63 deletions(-)

4 11

[U-Boot] PATCH Nios2 kernel bootstrap error due to missing processor data cache flush: fix
by Renato Andreola 23 Nov '09

23 Nov '09

From b75bd27f89ac6c105cebb6507cf082b6f5fffc7d Mon Sep 17 00:00:00 2001 From: Renato Andreola <renato.andreola(a)imagos.it> Date: Fri, 10 Apr 2009 12:32:29 +0200 Subject: Nios2: do_boom_linux(): kernel gunzip input data integrity problem due to mi ssing cache flush Added instruction and data caches flush Signed-off-by: Renato Andreola <renato.andreola(a)imagos.it> --- lib_nios2/bootm.c | 8 +++++++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/lib_nios2/bootm.c b/lib_nios2/bootm.c index 53fd569..1e8034b 100644 --- a/lib_nios2/bootm.c +++ b/lib_nios2/bootm.c @@ -2,6 +2,9 @@ * (C) Copyright 2003, Psyent Corporation <www.psyent.com> * Scott McNutt <smcnutt(a)psyent.com> * + * (C) Copyright 2009, Imagos sas <www.imagos.it> + * Renato Andreola <renato.andreola(a)imagos.it> + * * See file CREDITS for list of people who contributed to this * project. * @@ -24,6 +27,7 @@ #include <common.h> #include <command.h> #include <asm/byteorder.h> +#include <asm/cache.h> int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) { @@ -31,7 +35,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) return 1; - + /* flushes data and instruction caches before calling the kernel */ + flush_dcache (0,CONFIG_SYS_DCACHE_SIZE ); + flush_icache (0,CONFIG_SYS_ICACHE_SIZE); /* For now we assume the Microtronix linux ... which only * needs to be called ;-) */ -- 1.5.5

4 11

[U-Boot] PATCH mtd CFI flash: timeout calculation underflow if imprecise 1kHz timer: fix
by Renato Andreola 23 Nov '09

23 Nov '09

From 21d84ab72266f118794233176bd356d8b1cfdf35 Mon Sep 17 00:00:00 2001 From: Renato Andreola <renato.andreola(a)imagos.it> Date: Fri, 21 Aug 2009 18:05:51 +0200 Subject: [PATCH] drivers/mtd/cfi_flash: precision and underflow problem in tout calculation With old configuration it could happen tout=0 if CONFIG_SYS_HZ<1000. Signed-off-by: Alessandro Rubini <rubini(a)gnudd.com> Renato Andreola <renato.andreola(a)imagos.it> --- drivers/mtd/cfi_flash.c | 8 +++++--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 81ac5d3..0d8fc54 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -660,9 +660,11 @@ static int flash_status_check (flash_info_t * info, flash_sect_t sector, ulong start; #if CONFIG_SYS_HZ != 1000 - tout *= CONFIG_SYS_HZ/1000; -#endif - + if ((ulong)CONFIG_SYS_HZ > 100000) + tout *= (ulong)CONFIG_SYS_HZ/1000; /* for a big HZ, avoid overflow */ + else + tout = DIV_ROUND_UP(tout*(ulong)CONFIG_SYS_HZ, 1000); +#endif /* Wait for command completion */ start = get_timer (0); while (flash_is_busy (info, sector)) { -- 1.5.5

4 7

[U-Boot] [RFC/PATCH 0/2]
by Simon Kagstrom 23 Nov '09

23 Nov '09

Hejsan! I'm going on vacation for one month on wednesday, so I thought I'd post the OpenRD base patches as they are today. I can fix issues tomorrow as well, but after that I will be offline. I've tried to integrate the comments posted on the last series (thanks!), although for the split-out-phy support and configure-MAC-for-linux the discussion hasn't really converged yet so I just picked an implementation :-). Other dependencies: ------------------- * Fix UBIFS build on arm: http://lists.denx.de/pipermail/u-boot/2009-July/055594.html * Various Kirkwood egiga fixes: http://lists.denx.de/pipermail/u-boot/2009-July/055724.html (except the first which is worked around in the board support) Changes since last patch series: -------------------------------- * Copyrights have been fixed up: moved functions retain copyrights, attribute originating source where the implementation is based on another file. * Some MPP pins have been corrected * The configuration has been extended to include UBIFS support (this is a prototype board after all so I think it makes sense to have a "fat" configuration which can be stripped down) * I moved mv88e1116.c to drivers/net/phy/ instead. I understand this issue is not settled yet (with generic PHY framework missing etc). * NAND flash partitions have been corrected * MPP correction patch has been removed (already applied upstream) and mach-types.h is also untouched. * Added Maintainer and MAKEALL * Board ID has been registered at http://www.arm.linux.org.uk/developer/machines/ (2325), although it's not integrated in Linux yet. This will obviously need to be merged before the OpenRD base board support can go in. // Simon

3 7

[U-Boot] [PATCH] at91: Extended soft_i2c driver for AT91SAM9263 SoC
by Daniel Gorsulowski 23 Nov '09

23 Nov '09

While hard_i2c support is not available (see http://lists.denx.de/pipermail/u-boot/2009-March/049751.html), this patch enables soft_i2c on AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski(a)esd.eu> --- drivers/i2c/soft_i2c.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index 59883a5..9a48783 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -34,6 +34,11 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #endif +#ifdef CONFIG_AT91SAM9263 /* only valid for AT91SAM9263 */ +#include <asm/arch/at91_pmc.h> +#include <asm/arch/gpio.h> +#include <asm/arch/io.h> +#endif #ifdef CONFIG_IXP425 /* only valid for IXP425 */ #include <asm/arch/ixp425.h> #endif -- 1.6.1

5 13

[U-Boot] [U-boot][PATCH] AMCC ppc440SPe PCIe PLL lock error
by Rupjyoti Sarmah 23 Nov '09

23 Nov '09

u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of PLL lock. This fix touches only one file 4xx_pcie.c Signed off by Rupjyoti Sarmah < rsarmah(a)amcc.com > from Applied Micro ---------------------------------------------------- diff --git a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c old mode 100644 new mode 100755 index 07fbb0e..51a5fd2 --- a/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c +++ b/u-boot-2009.06/cpu/ppc4xx/4xx_pcie.c @@ -1,1171 +1,1179 @@ +/* + * (C) Copyright 2006 - 2008 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Roland Dreier <rolandd(a)cisco.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +/* define DEBUG for debugging output (obviously ;-)) */ +#if 0 +#define DEBUG +#endif + +#include <common.h> +#include <pci.h> +#include <ppc4xx.h> +#include <asm/processor.h> +#include <asm-ppc/io.h> + +#if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ + defined(CONFIG_PCI) && !defined(CONFIG_PCI_DISABLE_PCIE) + +#include <asm/4xx_pcie.h> + +enum { + PTYPE_ENDPOINT = 0x0, + PTYPE_LEGACY_ENDPOINT = 0x1, + PTYPE_ROOT_PORT = 0x4, + + LNKW_X1 = 0x1, + LNKW_X4 = 0x4, + LNKW_X8 = 0x8 +}; + +static int validate_endpoint(struct pci_controller *hose) +{ + if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE0_CFGBASE) + return (is_end_point(0)); + else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE1_CFGBASE) + return (is_end_point(1)); +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + else if (hose->cfg_data == (u8 *)CONFIG_SYS_PCIE2_CFGBASE) + return (is_end_point(2)); +#endif + + return 0; +} + +static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn) +{ + u8 *base = (u8*)hose->cfg_data; + + /* use local configuration space for the first bus */ + if (PCI_BUS(devfn) == 0) { + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE0_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE0_XCFGBASE; + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE1_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE1_XCFGBASE; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + if (hose->cfg_data == (u8*)CONFIG_SYS_PCIE2_CFGBASE) + base = (u8*)CONFIG_SYS_PCIE2_XCFGBASE; +#endif + } + + return base; +} + +static void pcie_dmer_disable(void) +{ + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) | GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) | GPL_DMER_MASK_DISA); +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) | GPL_DMER_MASK_DISA); +#endif +} + +static void pcie_dmer_enable(void) +{ + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE0_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE)) & ~GPL_DMER_MASK_DISA); + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE1_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE1_BASE)) & ~GPL_DMER_MASK_DISA); +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + mtdcr (DCRN_PEGPL_CFG (DCRN_PCIE2_BASE), + mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA); +#endif +} + +static int pcie_read_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 *val) { + + u8 *address; + *val = 0; + + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * NOTICE: configuration space ranges are currenlty mapped only for + * the first 16 buses, so such limit must be imposed. In case more + * buses are required the TLB settings in board/amcc/<board>/init.S + * need to be altered accordingly (one bus takes 1 MB of memory space). + */ + if (PCI_BUS(devfn) >= 16) + return 0; + + /* + * Only single device/single function is supported for the primary and + * secondary buses of the 440SPe host bridge. + */ + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); + offset += devfn << 4; + + /* + * Reading from configuration space of non-existing device can + * generate transaction errors. For the read duration we suppress + * assertion of machine check exceptions to avoid those. + */ + pcie_dmer_disable (); + + debug("%s: cfg_data=%08x offset=%08x\n", __func__, hose->cfg_data, offset); + switch (len) { + case 1: + *val = in_8(hose->cfg_data + offset); + break; + case 2: + *val = in_le16((u16 *)(hose->cfg_data + offset)); + break; + default: + *val = in_le32((u32*)(hose->cfg_data + offset)); + break; + } + + pcie_dmer_enable (); + + return 0; +} + +static int pcie_write_config(struct pci_controller *hose, unsigned int devfn, + int offset, int len, u32 val) { + + u8 *address; + + if (validate_endpoint(hose)) + return 0; /* No upstream config access */ + + /* + * Bus numbers are relative to hose->first_busno + */ + devfn -= PCI_BDF(hose->first_busno, 0, 0); + + /* + * Same constraints as in pcie_read_config(). + */ + if (PCI_BUS(devfn) >= 16) + return 0; + + if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) && + ((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1))) + return 0; + + address = pcie_get_base(hose, devfn); + offset += devfn << 4; + + /* + * Suppress MCK exceptions, similar to pcie_read_config() + */ + pcie_dmer_disable (); + + switch (len) { + case 1: + out_8(hose->cfg_data + offset, val); + break; + case 2: + out_le16((u16 *)(hose->cfg_data + offset), val); + break; + default: + out_le32((u32 *)(hose->cfg_data + offset), val); + break; + } + + pcie_dmer_enable (); + + return 0; +} + +int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 1, &v); + *val = (u8)v; + return rv; +} + +int pcie_read_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 2, &v); + *val = (u16)v; + return rv; +} + +int pcie_read_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 *val) +{ + u32 v; + int rv; + + rv = pcie_read_config(hose, dev, offset, 3, &v); + *val = (u32)v; + return rv; +} + +int pcie_write_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u8 val) +{ + return pcie_write_config(hose,(u32)dev,offset,1,val); +} + +int pcie_write_config_word(struct pci_controller *hose,pci_dev_t dev,int offset,u16 val) +{ + return pcie_write_config(hose,(u32)dev,offset,2,(u32 )val); +} + +int pcie_write_config_dword(struct pci_controller *hose,pci_dev_t dev,int offset,u32 val) +{ + return pcie_write_config(hose,(u32)dev,offset,3,(u32 )val); +} + +#if defined(CONFIG_440SPE) +static void ppc4xx_setup_utl(u32 port) { + + volatile void *utl_base = NULL; + + /* + * Map UTL registers + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), 0x20000000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0x68782800); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), 0x20001000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0x68782800); + break; + + case 2: + mtdcr(DCRN_PEGPL_REGBAH(PCIE2), 0x0000000c); + mtdcr(DCRN_PEGPL_REGBAL(PCIE2), 0x20002000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE2), 0x00007001); + mtdcr(DCRN_PEGPL_SPECIAL(PCIE2), 0x68782800); + break; + } + utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_PBBSZ, 0x53000000); + out_be32(utl_base + PEUTL_IPHBSZ, 0x08000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x10000000); + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); +} + +static int check_error(void) +{ + u32 valPE0, valPE1, valPE2; + int err = 0; + + /* SDR0_PEGPLLLCT1 reset */ + if (!(valPE0 = SDR_READ(PESDR0_PLLLCT1) & 0x01000000)) + printf("PCIE: SDR0_PEGPLLLCT1 reset error 0x%x\n", valPE0); + + valPE0 = SDR_READ(PESDR0_RCSSET); + valPE1 = SDR_READ(PESDR1_RCSSET); + valPE2 = SDR_READ(PESDR2_RCSSET); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & 0x01000000) || + !(valPE1 & 0x01000000) || + !(valPE2 & 0x01000000)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & 0x00010000) || + !(valPE1 & 0x00010000) || + !(valPE2 & 0x00010000)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & 0x00001000) || + (valPE1 & 0x00001000) || + (valPE2 & 0x00001000)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & 0x10000000) || + (valPE1 & 0x10000000) || + (valPE2 & 0x10000000)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & 0x00100000) || + (valPE1 & 0x00100000) || + (valPE2 & 0x00100000)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + /* SDR0_PExRCSSET shutdown */ + if ((valPE0 & 0x00000100) || + (valPE1 & 0x00000100) || + (valPE2 & 0x00000100)) { + printf("PCIE: SDR0_PExRCSSET shutdown error\n"); + err = -1; + } + return err; +} + +/* + * Initialize PCI Express core + */ +int ppc4xx_init_pcie(void) +{ + int time_out = 20; /* PCIe PLL lock retry count */ + + /* Set PLL clock receiver to LVPECL */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) | 1 << 28); + + if (check_error()) + { + printf("ERROR: ppc4xx_init_pcie(): PCIe setting reference clock receiver failed: PESDR0_PLLLCT1 = (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT1)); + return -1; + } + + /* Did resistance calibration work? */ + if (!(SDR_READ(PESDR0_PLLLCT2) & 0x10000)) + { + printf("ERROR: ppc4xx_init_pcie(): PCIe resistance calibration failed (bit 15=0): PESDR0_PLLLCT2 = (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT2)); + return -1; + } + + /* Take PCIe PLL out of reset, wait for lock */ + SDR_WRITE(PESDR0_PLLLCT1, SDR_READ(PESDR0_PLLLCT1) & ~(1 << 24)); + udelay(300); /* 300 uS is maximum time lock should take, per 440SPe user's manual */ + + while (time_out) { + if (!(SDR_READ(PESDR0_PLLLCT3) & 0x10000000)) { /* Read PLL lock status register PLLLCTS in user's manual */ + time_out--; + udelay(20); /* Wait 20 uS more if needed */ + } else + break; + } + if (!time_out) { + printf("ERROR: ppc4xx_init_pcie(): PCIe - PCIe PLL VCO output not locked to reference clock (bit 3=0): PESDR0_PLLLCTS = (0x%08x)\n", + SDR_READ(PESDR0_PLLLCT3)); + return -1; + } + return 0; +} +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +static void ppc4xx_setup_utl(u32 port) +{ + volatile void *utl_base = NULL; + + /* + * Map UTL registers at 0x0801_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* BAM 11100000=4KB */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), U64_TO_U32_HIGH(CONFIG_SYS_PCIE0_UTLBASE)); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), U64_TO_U32_LOW(CONFIG_SYS_PCIE0_UTLBASE) + + 0x1000); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* BAM 11100000=4KB */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + break; + } + utl_base = (unsigned int *)(CONFIG_SYS_PCIE_BASE + 0x1000 * port); + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32(utl_base + PEUTL_PBCTL, 0x0800000c); /* PLBME, CRRE */ + out_be32(utl_base + PEUTL_OUTTR, 0x08000000); + out_be32(utl_base + PEUTL_INTR, 0x02000000); + out_be32(utl_base + PEUTL_OPDBSZ, 0x04000000); /* OPD = 512 Bytes */ + out_be32(utl_base + PEUTL_PBBSZ, 0x00000000); /* Max 512 Bytes */ + out_be32(utl_base + PEUTL_IPHBSZ, 0x02000000); + out_be32(utl_base + PEUTL_IPDBSZ, 0x04000000); /* IPD = 512 Bytes */ + out_be32(utl_base + PEUTL_RCIRQEN, 0x00f00000); + out_be32(utl_base + PEUTL_PCTL, 0x80800066); /* VRB,TXE,timeout=default */ +} + +/* + * TODO: double check PCI express SDR based on the latest user manual + * Some registers specified here no longer exist.. has to be + * updated based on the final EAS spec. + */ +static int check_error(void) +{ + u32 valPE0, valPE1; + int err = 0; + + valPE0 = SDR_READ(SDRN_PESDR_RCSSET(0)); + valPE1 = SDR_READ(SDRN_PESDR_RCSSET(1)); + + /* SDR0_PExRCSSET rstgu */ + if (!(valPE0 & PESDRx_RCSSET_RSTGU) || !(valPE1 & PESDRx_RCSSET_RSTGU)) { + printf("PCIE: SDR0_PExRCSSET rstgu error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstdl */ + if (!(valPE0 & PESDRx_RCSSET_RSTDL) || !(valPE1 & PESDRx_RCSSET_RSTDL)) { + printf("PCIE: SDR0_PExRCSSET rstdl error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rstpyn */ + if ((valPE0 & PESDRx_RCSSET_RSTPYN) || (valPE1 & PESDRx_RCSSET_RSTPYN)) { + printf("PCIE: SDR0_PExRCSSET rstpyn error\n"); + err = -1; + } + + /* SDR0_PExRCSSET hldplb */ + if ((valPE0 & PESDRx_RCSSET_HLDPLB) || (valPE1 & PESDRx_RCSSET_HLDPLB)) { + printf("PCIE: SDR0_PExRCSSET hldplb error\n"); + err = -1; + } + + /* SDR0_PExRCSSET rdy */ + if ((valPE0 & PESDRx_RCSSET_RDY) || (valPE1 & PESDRx_RCSSET_RDY)) { + printf("PCIE: SDR0_PExRCSSET rdy error\n"); + err = -1; + } + + return err; +} + +/* + * Initialize PCI Express core as described in User Manual + * TODO: double check PE SDR PLL Register with the updated user manual. + */ +int ppc4xx_init_pcie(void) +{ + if (check_error()) + return -1; + + return 0; +} +#endif /* CONFIG_460EX */ + +#if defined(CONFIG_405EX) +static void ppc4xx_setup_utl(u32 port) +{ + u32 utl_base; + + /* + * Map UTL registers at 0xef4f_n000 (4K 0xfff mask) PEGPLn_REGMSK + */ + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_REGBAH(PCIE0), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE0), CONFIG_SYS_PCIE0_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE0), 0x00007001); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE0), 0); + break; + + case 1: + mtdcr(DCRN_PEGPL_REGBAH(PCIE1), 0x00000000); + mtdcr(DCRN_PEGPL_REGBAL(PCIE1), CONFIG_SYS_PCIE1_UTLBASE); + mtdcr(DCRN_PEGPL_REGMSK(PCIE1), 0x00007001); /* 4k region, valid */ + mtdcr(DCRN_PEGPL_SPECIAL(PCIE1), 0); + + break; + } + utl_base = (port==0) ? CONFIG_SYS_PCIE0_UTLBASE : CONFIG_SYS_PCIE1_UTLBASE; + + /* + * Set buffer allocations and then assert VRB and TXE. + */ + out_be32((u32 *)(utl_base + PEUTL_OUTTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_INTR), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_OPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_PBBSZ), 0x21000000); + out_be32((u32 *)(utl_base + PEUTL_IPHBSZ), 0x02000000); + out_be32((u32 *)(utl_base + PEUTL_IPDBSZ), 0x04000000); + out_be32((u32 *)(utl_base + PEUTL_RCIRQEN), 0x00f00000); + out_be32((u32 *)(utl_base + PEUTL_PCTL), 0x80800066); + + out_be32((u32 *)(utl_base + PEUTL_PBCTL), 0x0800000c); + out_be32((u32 *)(utl_base + PEUTL_RCSTA), + in_be32((u32 *)(utl_base + PEUTL_RCSTA)) | 0x000040000); +} + +int ppc4xx_init_pcie(void) +{ + /* + * Nothing to do on 405EX + */ + return 0; +} +#endif /* CONFIG_405EX */ + +/* + * Board-specific pcie initialization + * Platform code can reimplement ppc4xx_init_pcie_port_hw() if needed + */ + +/* + * Initialize various parts of the PCI Express core for our port: + * + * - Set as a root port and enable max width + * (PXIE0 -> X8, PCIE1 and PCIE2 -> X4). + * - Set up UTL configuration. + * - Increase SERDES drive strength to levels suggested by AMCC. + * - De-assert RSTPYN, RSTDL and RSTGU. + * + * NOTICE for 440SPE revB chip: PESDRn_UTLSET2 is not set - we leave it + * with default setting 0x11310000. The register has new fields, + * PESDRn_UTLSET2[LKINE] in particular: clearing it leads to PCIE core + * hang. + */ +#if defined(CONFIG_440SPE) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val = 1 << 24; + u32 utlset1; + + if (rootport) { + val = PTYPE_ROOT_PORT << 20; + utlset1 = 0x21222222; + } else { + val = PTYPE_LEGACY_ENDPOINT << 20; + utlset1 = 0x20222222; + } + + if (port == 0) + val |= LNKW_X8 << 12; + else + val |= LNKW_X4 << 12; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); + if (!ppc440spe_revB()) + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x11000000); + SDR_WRITE(SDRN_PESDR_HSSL0SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL1SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL2SET1(port), 0x35000000); + SDR_WRITE(SDRN_PESDR_HSSL3SET1(port), 0x35000000); + if (port == 0) { + SDR_WRITE(PESDR0_HSSL4SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL5SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL6SET1, 0x35000000); + SDR_WRITE(PESDR0_HSSL7SET1, 0x35000000); + } + SDR_WRITE(SDRN_PESDR_RCSSET(port), (SDR_READ(SDRN_PESDR_RCSSET(port)) & + ~(1 << 24 | 1 << 16)) | 1 << 12); + + return 0; +} +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val; + u32 utlset1; + + if (rootport) + val = PTYPE_ROOT_PORT << 20; + else + val = PTYPE_LEGACY_ENDPOINT << 20; + + if (port == 0) { + val |= LNKW_X1 << 12; + utlset1 = 0x20000000; + } else { + val |= LNKW_X4 << 12; + utlset1 = 0x20101101; + } + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), utlset1); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01210000); + + switch (port) { + case 0: + SDR_WRITE(PESDR0_L0CDRCTL, 0x00003230); + SDR_WRITE(PESDR0_L0DRV, 0x00000130); + SDR_WRITE(PESDR0_L0CLK, 0x00000006); + + SDR_WRITE(PESDR0_PHY_CTL_RST,0x10000000); + break; + + case 1: + SDR_WRITE(PESDR1_L0CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L1CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L2CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L3CDRCTL, 0x00003230); + SDR_WRITE(PESDR1_L0DRV, 0x00000130); + SDR_WRITE(PESDR1_L1DRV, 0x00000130); + SDR_WRITE(PESDR1_L2DRV, 0x00000130); + SDR_WRITE(PESDR1_L3DRV, 0x00000130); + SDR_WRITE(PESDR1_L0CLK, 0x00000006); + SDR_WRITE(PESDR1_L1CLK, 0x00000006); + SDR_WRITE(PESDR1_L2CLK, 0x00000006); + SDR_WRITE(PESDR1_L3CLK, 0x00000006); + + SDR_WRITE(PESDR1_PHY_CTL_RST,0x10000000); + break; + } + + SDR_WRITE(SDRN_PESDR_RCSSET(port), SDR_READ(SDRN_PESDR_RCSSET(port)) | + (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN)); + + /* Poll for PHY reset */ + switch (port) { + case 0: + while (!(SDR_READ(PESDR0_RSTSTA) & 0x1)) + udelay(10); + break; + case 1: + while (!(SDR_READ(PESDR1_RSTSTA) & 0x1)) + udelay(10); + break; + } + + SDR_WRITE(SDRN_PESDR_RCSSET(port), + (SDR_READ(SDRN_PESDR_RCSSET(port)) & + ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) | + PESDRx_RCSSET_RSTPYN); + + return 0; +} +#endif /* CONFIG_440SPE */ + +#if defined(CONFIG_405EX) +int __ppc4xx_init_pcie_port_hw(int port, int rootport) +{ + u32 val; + + if (rootport) + val = 0x00401000; + else + val = 0x00101000; + + SDR_WRITE(SDRN_PESDR_DLPSET(port), val); + SDR_WRITE(SDRN_PESDR_UTLSET1(port), 0x00000000); + SDR_WRITE(SDRN_PESDR_UTLSET2(port), 0x01010000); + SDR_WRITE(SDRN_PESDR_PHYSET1(port), 0x720F0000); + SDR_WRITE(SDRN_PESDR_PHYSET2(port), 0x70600003); + + /* Assert the PE0_PHY reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01010000); + udelay(1000); + + /* deassert the PE0_hotreset */ + if (is_end_point(port)) + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01111000); + else + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x01101000); + + /* poll for phy !reset */ + while (!(SDR_READ(SDRN_PESDR_PHYSTA(port)) & 0x00001000)) + ; + + /* deassert the PE0_gpl_utl_reset */ + SDR_WRITE(SDRN_PESDR_RCSSET(port), 0x00101000); + + if (port == 0) + mtdcr(DCRN_PEGPL_CFG(PCIE0), 0x10000000); /* guarded on */ + else + mtdcr(DCRN_PEGPL_CFG(PCIE1), 0x10000000); /* guarded on */ + + return 0; +} +#endif /* CONFIG_405EX */ + +int ppc4xx_init_pcie_port_hw(int port, int rootport) +__attribute__((weak, alias("__ppc4xx_init_pcie_port_hw"))); + +/* + * We map PCI Express configuration access into the 512MB regions + * + * NOTICE: revB is very strict about PLB real addressess and ranges to + * be mapped for config space; it seems to only work with d_nnnn_nnnn + * range (hangs the core upon config transaction attempts when set + * otherwise) while revA uses c_nnnn_nnnn. + * + * For 440SPe revA: + * PCIE0: 0xc_4000_0000 + * PCIE1: 0xc_8000_0000 + * PCIE2: 0xc_c000_0000 + * + * For 440SPe revB: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + * PCIE2: 0xd_4000_0000 + * + * For 405EX: + * PCIE0: 0xa000_0000 + * PCIE1: 0xc000_0000 + * + * For 460EX/GT: + * PCIE0: 0xd_0000_0000 + * PCIE1: 0xd_2000_0000 + */ +static inline u64 ppc4xx_get_cfgaddr(int port) +{ +#if defined(CONFIG_405EX) + if (port == 0) + return (u64)CONFIG_SYS_PCIE0_CFGBASE; + else + return (u64)CONFIG_SYS_PCIE1_CFGBASE; +#endif +#if defined(CONFIG_440SPE) + if (ppc440spe_revB()) { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000d00000000ULL; + case 1: + return 0x0000000d20000000ULL; + case 2: + return 0x0000000d40000000ULL; + } + } else { + switch (port) { + default: /* to satisfy compiler */ + case 0: + return 0x0000000c40000000ULL; + case 1: + return 0x0000000c80000000ULL; + case 2: + return 0x0000000cc0000000ULL; + } + } +#endif +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) + if (port == 0) + return 0x0000000d00000000ULL; + else + return 0x0000000d20000000ULL; +#endif +} + +/* + * 4xx boards as end point and root point setup + * and + * testing inbound and out bound windows + * + * 4xx boards can be plugged into another 4xx boards or you can get PCI-E + * cable which can be used to setup loop back from one port to another port. + * Please rememeber that unless there is a endpoint plugged in to root port it + * will not initialize. It is the same in case of endpoint , unless there is + * root port attached it will not initialize. + * + * In this release of software all the PCI-E ports are configured as either + * endpoint or rootpoint.In future we will have support for selective ports + * setup as endpoint and root point in single board. + * + * Once your board came up as root point , you can verify by reading + * /proc/bus/pci/devices. Where you can see the configuration registers + * of end point device attached to the port. + * + * Enpoint cofiguration can be verified by connecting 4xx board to any + * host or another 4xx board. Then try to scan the device. In case of + * linux use "lspci" or appripriate os command. + * + * How do I verify the inbound and out bound windows ? (4xx to 4xx) + * in this configuration inbound and outbound windows are setup to access + * sram memroy area. SRAM is at 0x4 0000 0000 , on PLB bus. This address + * is mapped at 0x90000000. From u-boot prompt write data 0xb000 0000, + * This is waere your POM(PLB out bound memory window) mapped. then + * read the data from other 4xx board's u-boot prompt at address + * 0x9000 0000(SRAM). Data should match. + * In case of inbound , write data to u-boot command prompt at 0xb000 0000 + * which is mapped to 0x4 0000 0000. Now on rootpoint yucca u-boot prompt check + * data at 0x9000 0000(SRAM).Data should match. + */ +int ppc4xx_init_pcie_port(int port, int rootport) +{ + static int core_init; + volatile u32 val = 0; + int attempts; + u64 addr; + u32 low, high; + + if (!core_init) { + if (ppc4xx_init_pcie()) + return -1; + ++core_init; + } + + /* + * Initialize various parts of the PCI Express core for our port + */ + ppc4xx_init_pcie_port_hw(port, rootport); + + /* + * Notice: the following delay has critical impact on device + * initialization - if too short (<50ms) the link doesn't get up. + */ + mdelay(100); + + val = SDR_READ(SDRN_PESDR_RCSSTS(port)); + if (val & (1 << 20)) { + printf("PCIE%d: PGRST failed %08x\n", port, val); + return -1; + } + + /* + * Verify link is up + */ + val = SDR_READ(SDRN_PESDR_LOOP(port)); + if (!(val & 0x00001000)) { + printf("PCIE%d: link is not up.\n", port); + return -1; + } + + /* + * Setup UTL registers - but only on revA! + * We use default settings for revB chip. + */ + if (!ppc440spe_revB()) + ppc4xx_setup_utl(port); + + /* + * We map PCI Express configuration access into the 512MB regions + */ + addr = ppc4xx_get_cfgaddr(port); + low = U64_TO_U32_LOW(addr); + high = U64_TO_U32_HIGH(addr); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE0), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE0), low); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE0), 0xe0000001); /* 512MB region, valid */ + break; + case 1: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE1), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE1), low); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE1), 0xe0000001); /* 512MB region, valid */ + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mtdcr(DCRN_PEGPL_CFGBAH(PCIE2), high); + mtdcr(DCRN_PEGPL_CFGBAL(PCIE2), low); + mtdcr(DCRN_PEGPL_CFGMSK(PCIE2), 0xe0000001); /* 512MB region, valid */ + break; +#endif + } + + /* + * Check for VC0 active and assert RDY. + */ + attempts = 10; + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 16))) { + if (!(attempts--)) { + printf("PCIE%d: VC0 not active\n", port); + return -1; + } + mdelay(1000); + } + SDR_WRITE(SDRN_PESDR_RCSSET(port), + SDR_READ(SDRN_PESDR_RCSSET(port)) | 1 << 20); + mdelay(100); + + return 0; +} + +int ppc4xx_init_pcie_rootport(int port) +{ + return ppc4xx_init_pcie_port(port, 1); +} + +int ppc4xx_init_pcie_endport(int port) +{ + return ppc4xx_init_pcie_port(port, 0); +} + +void ppc4xx_setup_pcie_rootpoint(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + volatile void *rmbase = NULL; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch (port) { + case 0: + mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE0_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE1_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; + rmbase = (u32 *)CONFIG_SYS_PCIE2_CFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; + break; +#endif + } + + /* + * Set bus numbers on our root port + */ + out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0); + out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1); + out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1); + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00000000); + out_le32(mbase + PECFG_POM0LAL, CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + debug("PECFG_POM0LA=%08x.%08x\n", in_le32(mbase + PECFG_POM0LAH), + in_le32(mbase + PECFG_POM0LAL)); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + debug("0:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE0)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE0))); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + debug("1:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE1)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE1))); + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + debug("2:PEGPL_OMR1BA=%08x.%08x MSK=%08x.%08x\n", + mfdcr(DCRN_PEGPL_OMR1BAH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1BAL(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKH(PCIE2)), + mfdcr(DCRN_PEGPL_OMR1MSKL(PCIE2))); + break; +#endif + } + + /* Set up 4GB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + out_le32(mbase + PECFG_BAR0HMPA, 0x7ffffff); + out_le32(mbase + PECFG_BAR0LMPA, 0); + + out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); + out_le32(mbase + PECFG_PIM01SAL, 0x00000000); + out_le32(mbase + PECFG_PIM0LAL, 0); + out_le32(mbase + PECFG_PIM0LAH, 0); + out_le32(mbase + PECFG_PIM1LAL, 0x00000000); + out_le32(mbase + PECFG_PIM1LAH, 0x00000004); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + + /* Set Device and Vendor Id */ + out_le16(mbase + 0x200, 0xaaa0 + port); + out_le16(mbase + 0x202, 0xbed0 + port); + + /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */ + out_le32(mbase + 0x208, 0x06040001); + + printf("PCIE%d: successfully set as root-complex\n", port); +} + +int ppc4xx_setup_pcie_endpoint(struct pci_controller *hose, int port) +{ + volatile void *mbase = NULL; + int attempts = 0; + + pci_set_ops(hose, + pcie_read_config_byte, + pcie_read_config_word, + pcie_read_config_dword, + pcie_write_config_byte, + pcie_write_config_word, + pcie_write_config_dword); + + switch (port) { + case 0: + mbase = (u32 *)CONFIG_SYS_PCIE0_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE0_CFGBASE; + break; + case 1: + mbase = (u32 *)CONFIG_SYS_PCIE1_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE1_CFGBASE; + break; +#if defined(CONFIG_SYS_PCIE2_CFGBASE) + case 2: + mbase = (u32 *)CONFIG_SYS_PCIE2_XCFGBASE; + hose->cfg_data = (u8 *)CONFIG_SYS_PCIE2_CFGBASE; + break; +#endif + } + + /* + * Set up outbound translation to hose->mem_space from PLB + * addresses at an offset of 0xd_0000_0000. We set the low + * bits of the mask to 11 to turn off splitting into 8 + * subregions and to enable the outbound translation. + */ + out_le32(mbase + PECFG_POM0LAH, 0x00001ff8); + out_le32(mbase + PECFG_POM0LAL, 0x00001000); + + switch (port) { + case 0: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE0), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE0), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE0), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE0), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + break; + case 1: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE1), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE1), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE1), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE1), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + break; +#if CONFIG_SYS_PCIE_NR_PORTS > 2 + case 2: + mtdcr(DCRN_PEGPL_OMR1BAH(PCIE2), CONFIG_SYS_PCIE_ADDR_HIGH); + mtdcr(DCRN_PEGPL_OMR1BAL(PCIE2), CONFIG_SYS_PCIE_MEMBASE + + port * CONFIG_SYS_PCIE_MEMSIZE); + mtdcr(DCRN_PEGPL_OMR1MSKH(PCIE2), 0x7fffffff); + mtdcr(DCRN_PEGPL_OMR1MSKL(PCIE2), + ~(CONFIG_SYS_PCIE_MEMSIZE - 1) | 3); + break; +#endif + } + + /* Set up 64MB inbound memory window at 0 */ + out_le32(mbase + PCI_BASE_ADDRESS_0, 0); + out_le32(mbase + PCI_BASE_ADDRESS_1, 0); + + out_le32(mbase + PECFG_PIM01SAH, 0xffffffff); + out_le32(mbase + PECFG_PIM01SAL, 0xfc000000); + + /* Setup BAR0 */ + out_le32(mbase + PECFG_BAR0HMPA, 0x7fffffff); + out_le32(mbase + PECFG_BAR0LMPA, 0xfc000000 | PCI_BASE_ADDRESS_MEM_TYPE_64); + + /* Disable BAR1 & BAR2 */ + out_le32(mbase + PECFG_BAR1MPA, 0); + out_le32(mbase + PECFG_BAR2HMPA, 0); + out_le32(mbase + PECFG_BAR2LMPA, 0); + + out_le32(mbase + PECFG_PIM0LAL, U64_TO_U32_LOW(CONFIG_SYS_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIM0LAH, U64_TO_U32_HIGH(CONFIG_SYS_PCIE_INBOUND_BASE)); + out_le32(mbase + PECFG_PIMEN, 0x1); + + /* Enable I/O, Mem, and Busmaster cycles */ + out_le16((u16 *)(mbase + PCI_COMMAND), + in_le16((u16 *)(mbase + PCI_COMMAND)) | + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + out_le16(mbase + 0x200, 0xcaad); /* Setting vendor ID */ + out_le16(mbase + 0x202, 0xfeed); /* Setting device ID */ + + /* Set Class Code to Processor/PPC */ + out_le32(mbase + 0x208, 0x0b200001); + + attempts = 10; + while(!(SDR_READ(SDRN_PESDR_RCSSTS(port)) & (1 << 8))) { + if (!(attempts--)) { + printf("PCIE%d: BME not active\n", port); + return -1; + } + mdelay(1000); + } + + printf("PCIE%d: successfully set as endpoint\n", port); + + return 0; +} +#endif /* CONFIG_440SPE && CONFIG_PCI */

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