August 2009 - U-Boot

[U-Boot] [PATCH] net: kirkwood: updates: used eth_setenv_enetaddr api
by Prafulla Wadaskar 15 Aug '09

15 Aug '09

eth_setenv_enetaddr is avaible by upper layer using this saves 204 bytes on total image size Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- drivers/net/kirkwood_egiga.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 3d908f8..1a208f2 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -606,7 +606,7 @@ int kirkwood_egiga_initialize(bd_t * bis) struct kwgbe_device *dkwgbe; struct eth_device *dev; int devnum; - char *s, buf[NAMESIZE * 2]; + char *s; u8 used_ports[MAX_KWGBE_DEVS] = CONFIG_KIRKWOOD_EGIGA_PORTS; for (devnum = 0; devnum < MAX_KWGBE_DEVS; devnum++) { @@ -665,10 +665,13 @@ int kirkwood_egiga_initialize(bd_t * bis) while (!eth_getenv_enetaddr(s, dev->enetaddr)) { /* Generate Ramdom MAC addresses if not set */ - sprintf(buf, "00:50:43:%02x:%02x:%02x", - get_random_hex(), get_random_hex(), - get_random_hex()); - setenv(s, buf); + dev->enetaddr[0] = 0x00; + dev->enetaddr[1] = 0x50; + dev->enetaddr[2] = 0x43; + dev->enetaddr[3] = get_random_hex(); + dev->enetaddr[4] = get_random_hex(); + dev->enetaddr[5] = get_random_hex(); + eth_setenv_enetaddr(s, dev->enetaddr); } dev->init = (void *)kwgbe_init; -- 1.5.3.3

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[U-Boot] [PATCH] 85xx: Fix addrmap to include memory
by Kumar Gala 15 Aug '09

15 Aug '09

When we init the addrmap based on the TLB we will not end up getting the TLB that covers memory if we are using SPD. The reason is we haven't relocated at the point that we setup the memory TLB and thus it will not get setup in the addrmap. Instead we can just walk over the TLB array after we've relocated and see all the TLBs that have been set and use that information to populate the initial addrmap. By doing this we insure that we get the TLB entries that cover memory. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/tlb.c | 28 ++++++++++++++++++++++------ 1 files changed, 22 insertions(+), 6 deletions(-) diff --git a/cpu/mpc85xx/tlb.c b/cpu/mpc85xx/tlb.c index 46925f1..43ef1ff 100644 --- a/cpu/mpc85xx/tlb.c +++ b/cpu/mpc85xx/tlb.c @@ -110,15 +110,31 @@ void init_tlbs(void) void init_addr_map(void) { int i; + unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xff; - for (i = 0; i < num_tlb_entries; i++) { - if (tlb_table[i].tlb == 0) + /* walk all the entries */ + for (i = 0; i < max_cam; i++) { + unsigned long epn; + u32 tsize, _mas1; + phys_addr_t rpn; + + mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0)); + + asm volatile("tlbre;isync"); + _mas1 = mfspr(MAS1); + + /* if the entry isn't valid skip it */ + if (!(_mas1 & MAS1_VALID)) continue; - addrmap_set_entry(tlb_table[i].epn, - tlb_table[i].rpn, - (1UL << ((tlb_table[i].tsize * 2) + 10)), - tlb_table[i].esel); + tsize = (_mas1 >> 8) & 0xf; + epn = mfspr(MAS2) & MAS2_EPN; + rpn = mfspr(MAS3) & MAS3_RPN; +#ifdef CONFIG_ENABLE_36BIT_PHYS + rpn |= ((phys_addr_t)mfspr(MAS7)) << 32; +#endif + + addrmap_set_entry(epn, rpn, (1UL << ((tsize * 2) + 10)), i); } return ; -- 1.6.0.6

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[U-Boot] [PATCH v2] 85xx: Init pci ethernet cards if we enable any on MPC8572DS
by Kumar Gala 14 Aug '09

14 Aug '09

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- * Make it build by include netdev.h board/freescale/mpc8572ds/mpc8572ds.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 59d7519..7da70fe 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -34,6 +34,7 @@ #include <libfdt.h> #include <fdt_support.h> #include <tsec.h> +#include <netdev.h> #include "../common/pixis.h" #include "../common/sgmii_riser.h" @@ -562,7 +563,7 @@ int board_eth_init(bd_t *bis) tsec_eth_init(bis, tsec_info, num); - return 0; + return pci_eth_init(bis); } #endif -- 1.6.0.6

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[U-Boot] How do you print/view avaliable devices?
by dbrazeau 14 Aug '09

14 Aug '09

I am trying to run a standalone program from flash but I keep receiving ** Invalid boot device ** when I attempt to load it into memory. I think I'm just using the wrong device number. I was wondering if there was any way to print the devices that U-boot can see, so I can figure out dev:part numbers of my onboard flash and compact flash. -- View this message in context: http://www.nabble.com/How-do-you-print-view-avaliable-devices--tp24943649p2… Sent from the Uboot - Users mailing list archive at Nabble.com.

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Re: [U-Boot] NAND issues
by alfred steele 14 Aug '09

14 Aug '09

Just realised that i dis reply instead of "reply all". > We have been using 2009.1 based version.. We have been using "nand > read.e/write.e". Is that fine? After skimming through the u-boot code, > it seems though. > Please confirm. Apart from this, what does the "CONFIG_JFFS2_NAND" do? Thanks, Alfred.

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[U-Boot] [PATCH] omap3: Fixed a problem with hwecc
by Ben Goska 14 Aug '09

14 Aug '09

In commit 187af954cf7958c24efcf0fd62289bbdb4f1f24e there was a typo that offset all the ecc registers by 4 bytes, fixed that. Signed-off-by Dirk Behme --- include/asm-arm/arch-omap3/cpu.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index 7a032b8..8ab2e39 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -120,9 +120,9 @@ struct gpmc { u8 res4[0xC]; u32 config; /* 0x50 */ u32 status; /* 0x54 */ - u8 res5[0x8]; + u8 res5[0x8]; /* 0x58 */ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x18]; + u8 res6[0x14]; /* 0x1E0 */ u32 ecc_config; /* 0x1F4 */ u32 ecc_control; /* 0x1F8 */ u32 ecc_size_config; /* 0x1FC */ -- 1.6.3.3

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Re: [U-Boot] [PATCH 2/2] MTD:NAND: ADD new ECC mode NAND_ECC_HW_OOB_FIRST
by Scott Wood 14 Aug '09

14 Aug '09

On Wed, Aug 12, 2009 at 11:48:27AM -0500, Paulraj, Sandeep wrote: > There are other issues. The NAND manufacturers have changed the format > of the 4Th ID byte and some other are supporting ONFI. Current NAND > driver has no support for these There are always other issues. :-) Unless the issues show up on hardware I'm working with, there's not much I can do other than apply patches from others. > Shrinking the footprint will first need to be done in the MTD GIT and > then the changes should trickle down to other trees including U-Boot. That would be preferable, but we are not obligated to follow Linux's lead if they aren't interested. > So I take it that you will add these 2 patches to the u-boot-nand-flash/next git soon. Assuming no other issues, yes. -Scott

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[U-Boot] omap3: HW ECC issue
by Ben Goska 14 Aug '09

14 Aug '09

After commit [1] I noticed a problem with the HW ECC no longer working. After looking into it I found that there was a typo that caused the ecc registers to be shifted by 4 bytes. The patch attached corrects the issue, I have verified this on an OSWALD board (for more information about OSWALD see [2]). [1] http://git.denx.de/?p=u-boot.git;a=commit;h=187af954cf7958c24efcf0fd62289bb… [2] http://beaversource.oregonstate.edu/projects/cspfl Ben Goska Oregon State University goskab(a)onid.oregonstate.edu >From aca1e8e7bfeb02e3ac5a5e5eb3704144e43dbc5b Mon Sep 17 00:00:00 2001 From: Ben Goska <goskab(a)onid.oregonstate.edu> Date: Thu, 13 Aug 2009 10:32:56 -0700 Subject: [PATCH] omap3: Fixed a problem with hwecc In commit 187af954cf7958c24efcf0fd62289bbdb4f1f24e there was a typo that offset all the ecc registers by 4 bytes, fixed that. (cherry picked from commit f06dc3609e73f496a21699b54d37e93af5de9418) --- include/asm-arm/arch-omap3/cpu.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/asm-arm/arch-omap3/cpu.h b/include/asm-arm/arch-omap3/cpu.h index 7a032b8..8ab2e39 100644 --- a/include/asm-arm/arch-omap3/cpu.h +++ b/include/asm-arm/arch-omap3/cpu.h @@ -120,9 +120,9 @@ struct gpmc { u8 res4[0xC]; u32 config; /* 0x50 */ u32 status; /* 0x54 */ - u8 res5[0x8]; + u8 res5[0x8]; /* 0x58 */ struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */ - u8 res6[0x18]; + u8 res6[0x14]; /* 0x1E0 */ u32 ecc_config; /* 0x1F4 */ u32 ecc_control; /* 0x1F8 */ u32 ecc_size_config; /* 0x1FC */ -- 1.6.3.3

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[U-Boot] PCIe switch questions
by dbrazeau 14 Aug '09

14 Aug '09

Hi. I'm planning on using a IDT PCIe switch on our custom board with a PPC_460 cpu. I have searched the internet and haven't found much in the way of references of using a IDT PCIe switch and a PPC with U-boot. I was just wondering if I should expect any issue with U-Boot/Linux communicating with devices connected to the PCIe switch. Are there special U-boot configuration requirement when using a PCIe switch? I've looked online and in U-boot documentation and haven't seen a whole lot of PCI configuration options except for the environment variable pcie_mode and disabling the PCI bus altogether. I just wanted to get some input and thoughts on what I should expect once I get the hardware. Thanks. -- View this message in context: http://www.nabble.com/PCIe-switch-questions-tp24962145p24962145.html Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] MX31 SDRAM size
by alfred steele 14 Aug '09

14 Aug '09

Hi, We are thinking of migrating to a 256M chip on the MX31 3stack based board. WHich all config variables have to be changed apart from "SDRAM_SIZE" and no of banks(CSD0)? Thanks, Alfred.

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