August 2009 - U-Boot

[U-Boot] Porting to Broadcom BCM7038 (Hermes board)
by Peter Belm 20 Aug '09

20 Aug '09

I posted a message before about this, but I didn't really give it the most descriptive subject (I went off to find the chip model and then forgot to add it to the subject, doh!) Basically I'm trying to port uboot to the Broadcom BCM7038 chip, the current bootloader I have is specific to the board (Hermes), and loads the kernel from flash. I'd rather use uboot to start the SATA HDD and load the Linux kernel from there. I have the source code for the bootloader and all the Linux drivers, as well as documentation on the processor, but I'm not very good at low level code. As far as I can see I need to create a cpu/bcm7038 directory, add the start.S from the original bootloader, and modify it to work with uboot (this is the part I'm really not sure on!). Then add a board/hermes directory with the rest of the original bootloader init code, and modify that to include the SATA drivers, bring up the SATA interface, then load the kernel. But theory is far from practice, and I'm already having trouble. Would someone be able to assist me in porting to this cpu/board? -- Regards, Peter Belm

3 7

[U-Boot] u-boot fall-back application
by Florin Cotofan 20 Aug '09

20 Aug '09

Hi, Is it possible to have a standalone application started without the user intervention (auto-started at power-on)? I need to create a fall-back application which will boot a safe kernel if booting a user flashed kernel fails. We will store 2 kernel images in flash and if one of them is corrupted we need u-boot to try booting the second one. How can I test if a kernel image is corrupted? Regards, Florin

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[U-Boot] [PATCH] arm:kirkwood See to it that sent data is 8-byte aligned
by Simon Kagstrom 20 Aug '09

20 Aug '09

See to it that sent data is 8-byte aligned U-boot might use non-8-byte-aligned addresses for sending data, which the kwgbe_send doesn't accept (bootp does this for me). This patch copies the data to be sent to a malloced temporary buffer if it is non-aligned. v2: Malloc send buffer (comment from Stefan Roese) v3: No need to use jumbo frames, use 1518 bytes buffer instead (comment from Ben Warren) Signed-off-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> --- drivers/net/kirkwood_egiga.c | 26 ++++++++++++++++++++++---- 1 files changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index f31fefc..6627412 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -481,24 +481,42 @@ static int kwgbe_halt(struct eth_device *dev) return 0; } +#define KWGBE_SEND_BUF_SIZE 1518 static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, int datasize) { struct kwgbe_device *dkwgbe = to_dkwgbe(dev); struct kwgbe_registers *regs = dkwgbe->regs; struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc; + void *p = (void *)dataptr; u32 cmd_sts; + /* Copy buffer if it's misaligned */ if ((u32) dataptr & 0x07) { - printf("Err..(%s) xmit dataptr not 64bit aligned\n", - __FUNCTION__); - return -1; + static void *aligned_buf; + + if (!aligned_buf) + aligned_buf = memalign(sizeof(u32), + KWGBE_SEND_BUF_SIZE); + if (!aligned_buf) { + printf("Err...(%s): Cannot allocate aligned buffer\n", + __FUNCTION__); + return -1; + } + if (datasize > KWGBE_SEND_BUF_SIZE) { + printf("Err..(%s) Non-aligned data too large (%d)\n", + __FUNCTION__, datasize); + return -1; + } + memcpy(aligned_buf, p, datasize); + p = aligned_buf; } + p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC; p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC; p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA; p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT; - p_txdesc->buf_ptr = (u8 *) dataptr; + p_txdesc->buf_ptr = (u8 *) p; p_txdesc->byte_cnt = datasize; /* Apply send command using zeroth RXUQ */ -- 1.6.0.4

3 5

[U-Boot] [PATCH] arm:kirkwood Wait for the link to come up on kirkwood network init
by Simon Kagstrom 20 Aug '09

20 Aug '09

Wait for the link to come up on kirkwood network init This patch makes the device wait for up to 5 seconds for the link to come up, similar to what many of the other network drivers do. This avoids confusing situations where, e.g., a tftp fails when initiated early after U-boot has started (before the link has come up). Signed-off-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> --- drivers/net/kirkwood_egiga.c | 17 ++++++++++++----- 1 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index f31fefc..9ac9c1f 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -396,6 +396,7 @@ static int kwgbe_init(struct eth_device *dev) { struct kwgbe_device *dkwgbe = to_dkwgbe(dev); struct kwgbe_registers *regs = dkwgbe->regs; + int i; /* setup RX rings */ kwgbe_init_rx_desc_ring(dkwgbe); @@ -443,12 +444,18 @@ static int kwgbe_init(struct eth_device *dev) #if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) - u16 phyadr; - miiphy_read(dev->name, 0xEE, 0xEE, &phyadr); - if (!miiphy_link(dev->name, phyadr)) { - printf("%s: No link on %s\n", __FUNCTION__, dev->name); - return -1; + /* Wait up to 5s for the link status */ + for (i = 0; i < 5; i++) { + u16 phyadr; + miiphy_read(dev->name, 0xEE, 0xEE, &phyadr); + /* Return if we get link up */ + if (miiphy_link(dev->name, phyadr)) + return 0; + udelay(1000000); } + + printf("%s: No link on %s\n", __FUNCTION__, dev->name); + return -1; #endif return 0; } -- 1.6.0.4

3 5

[U-Boot] [PATCH v4] arm: kirkwood: See to it that sent data is 8-byte aligned
by Simon Kagstrom 20 Aug '09

20 Aug '09

U-boot might use non-8-byte-aligned addresses for sending data, which the kwgbe_send doesn't accept (bootp does this for me). This patch copies the data to be sent to a malloced temporary buffer if it is non-aligned. v2: Malloc send buffer v3: No need to use jumbo frames, use 1518 bytes buffer instead v4: Correct alignment passed to memalign (should be 8!), allocate buffer at initialization(), use PKTSIZE_ALIGN Signed-off-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> --- drivers/net/kirkwood_egiga.c | 21 +++++++++++++++++---- drivers/net/kirkwood_egiga.h | 1 + 2 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 9ac9c1f..008c5dd 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -494,18 +494,26 @@ static int kwgbe_send(struct eth_device *dev, volatile void *dataptr, struct kwgbe_device *dkwgbe = to_dkwgbe(dev); struct kwgbe_registers *regs = dkwgbe->regs; struct kwgbe_txdesc *p_txdesc = dkwgbe->p_txdesc; + void *p = (void *)dataptr; u32 cmd_sts; + /* Copy buffer if it's misaligned */ if ((u32) dataptr & 0x07) { - printf("Err..(%s) xmit dataptr not 64bit aligned\n", - __FUNCTION__); - return -1; + if (datasize > PKTSIZE_ALIGN) { + printf("Non-aligned data too large (%d)\n", + datasize); + return -1; + } + + memcpy(dkwgbe->p_aligned_txbuf, p, datasize); + p = dkwgbe->p_aligned_txbuf; } + p_txdesc->cmd_sts = KWGBE_ZERO_PADDING | KWGBE_GEN_CRC; p_txdesc->cmd_sts |= KWGBE_TX_FIRST_DESC | KWGBE_TX_LAST_DESC; p_txdesc->cmd_sts |= KWGBE_BUFFER_OWNED_BY_DMA; p_txdesc->cmd_sts |= KWGBE_TX_EN_INTERRUPT; - p_txdesc->buf_ptr = (u8 *) dataptr; + p_txdesc->buf_ptr = (u8 *) p; p_txdesc->byte_cnt = datasize; /* Apply send command using zeroth RXUQ */ @@ -622,8 +630,13 @@ int kirkwood_egiga_initialize(bd_t * bis) * PKTSIZE_ALIGN + 1))) goto error3; + if (!(dkwgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN))) + goto error4; + if (!(dkwgbe->p_txdesc = (struct kwgbe_txdesc *) memalign(PKTALIGN, sizeof(struct kwgbe_txdesc) + 1))) { + free(dkwgbe->p_aligned_txbuf); + error4: free(dkwgbe->p_rxbuf); error3: free(dkwgbe->p_rxdesc); diff --git a/drivers/net/kirkwood_egiga.h b/drivers/net/kirkwood_egiga.h index 9c893d1..16d5214 100644 --- a/drivers/net/kirkwood_egiga.h +++ b/drivers/net/kirkwood_egiga.h @@ -499,6 +499,7 @@ struct kwgbe_device { struct kwgbe_rxdesc *p_rxdesc; struct kwgbe_rxdesc *p_rxdesc_curr; u8 *p_rxbuf; + u8 *p_aligned_txbuf; }; #endif /* __EGIGA_H__ */ -- 1.6.0.4

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[U-Boot] [PATCH] net: See to it that sent data is aligned to the ethernet controllers wishes
by Simon Kagstrom 20 Aug '09

20 Aug '09

See to it that sent data is aligned to the ethernet controllers wishes This patch adds a send_alignment member to the eth_device structure which specifies what the alignment requirements are for the particular device. eth_send checks this alignment on sends, and if it doesn't match the device requirement, allocates an aligned buffer and copies the data there. Currently kirkwood_egiga.c has an 8-byte requirement. This patch is an alternative and replacement for "[PATCH] arm:kirkwood See to it that sent data is 8-byte aligned" sent here http://lists.denx.de/pipermail/u-boot/2009-August/058829.html For other devices, I've setup send_alignment to 1. Signed-off-by: Simon Kagstrom <simon.kagstrom(a)netinsight.net> --- board/MAI/AmigaOneG3SE/enet.c | 1 + board/Marvell/db64360/mv_eth.c | 1 + board/Marvell/db64460/mv_eth.c | 1 + board/esd/cpci750/mv_eth.c | 1 + board/evb64260/eth.c | 1 + board/prodrive/p3mx/mv_eth.c | 1 + cpu/ixp/npe/npe.c | 1 + cpu/mips/au1x00_eth.c | 1 + cpu/mpc8260/ether_scc.c | 1 + drivers/net/4xx_enet.c | 1 + drivers/net/ax88180.c | 1 + drivers/net/bfin_mac.c | 1 + drivers/net/davinci_emac.c | 1 + drivers/net/dc2114x.c | 1 + drivers/net/dm9000x.c | 1 + drivers/net/dnet.c | 1 + drivers/net/e1000.c | 1 + drivers/net/eepro100.c | 1 + drivers/net/fec_mxc.c | 1 + drivers/net/fsl_mcdmafec.c | 1 + drivers/net/ftmac100.c | 1 + drivers/net/greth.c | 1 + drivers/net/inca-ip_sw.c | 1 + drivers/net/kirkwood_egiga.c | 1 + drivers/net/macb.c | 1 + drivers/net/mcffec.c | 1 + drivers/net/mpc5xxx_fec.c | 1 + drivers/net/natsemi.c | 1 + drivers/net/ns8382x.c | 1 + drivers/net/pcnet.c | 1 + drivers/net/plb2800_eth.c | 1 + drivers/net/rtl8139.c | 1 + drivers/net/rtl8169.c | 1 + drivers/net/sh_eth.c | 1 + drivers/net/sk98lin/uboot_drv.c | 1 + drivers/net/smc911x.c | 1 + drivers/net/tsec.c | 1 + drivers/net/tsi108_eth.c | 1 + drivers/net/uli526x.c | 1 + drivers/qe/uec.c | 1 + include/net.h | 1 + net/eth.c | 31 ++++++++++++++++++++++++++++++- 42 files changed, 71 insertions(+), 1 deletions(-) diff --git a/board/MAI/AmigaOneG3SE/enet.c b/board/MAI/AmigaOneG3SE/enet.c index b9df55c..fb63de4 100644 --- a/board/MAI/AmigaOneG3SE/enet.c +++ b/board/MAI/AmigaOneG3SE/enet.c @@ -481,6 +481,7 @@ int eth_3com_initialize (bd_t * bis) sprintf (dev->name, "3Com 3c920c#%d", card_number); dev->iobase = eth_iobase; + dev->send_alignment = 1; dev->priv = (void *) devno; dev->init = eth_3com_init; dev->halt = eth_3com_halt; diff --git a/board/Marvell/db64360/mv_eth.c b/board/Marvell/db64360/mv_eth.c index dfc0bf7..a083af1 100644 --- a/board/Marvell/db64360/mv_eth.c +++ b/board/Marvell/db64360/mv_eth.c @@ -262,6 +262,7 @@ void mv6436x_eth_initialize (bd_t * bis) /* ronen - set the MAC addr in the HW */ eth_port_uc_addr_set (devnum, dev->enetaddr, 0); + dev->send_alignment = 1; dev->init = (void *) db64360_eth_probe; dev->halt = (void *) ethernet_phy_reset; dev->send = (void *) db64360_eth_transmit; diff --git a/board/Marvell/db64460/mv_eth.c b/board/Marvell/db64460/mv_eth.c index 0458164..9eaa547 100644 --- a/board/Marvell/db64460/mv_eth.c +++ b/board/Marvell/db64460/mv_eth.c @@ -262,6 +262,7 @@ void mv6446x_eth_initialize (bd_t * bis) /* ronen - set the MAC addr in the HW */ eth_port_uc_addr_set (devnum, dev->enetaddr, 0); + dev->send_alignment = 1; dev->init = (void *) db64460_eth_probe; dev->halt = (void *) ethernet_phy_reset; dev->send = (void *) db64460_eth_transmit; diff --git a/board/esd/cpci750/mv_eth.c b/board/esd/cpci750/mv_eth.c index 1c21527..45dab40 100644 --- a/board/esd/cpci750/mv_eth.c +++ b/board/esd/cpci750/mv_eth.c @@ -262,6 +262,7 @@ void mv6436x_eth_initialize (bd_t * bis) /* ronen - set the MAC addr in the HW */ eth_port_uc_addr_set (devnum, dev->enetaddr, 0); + dev->send_alignment = 1; dev->init = (void *) db64360_eth_probe; dev->halt = (void *) ethernet_phy_reset; dev->send = (void *) db64360_eth_transmit; diff --git a/board/evb64260/eth.c b/board/evb64260/eth.c index ca8bab5..91d5bf4 100644 --- a/board/evb64260/eth.c +++ b/board/evb64260/eth.c @@ -720,6 +720,7 @@ gt6426x_eth_initialize(bd_t *bis) s = (*e) ? e+1 : e; } + dev->send_alignment = 1; dev->init = (void*)gt6426x_eth_probe; dev->halt = (void*)gt6426x_eth_reset; dev->send = (void*)gt6426x_eth_transmit; diff --git a/board/prodrive/p3mx/mv_eth.c b/board/prodrive/p3mx/mv_eth.c index 8203b3c..2b0b1fa 100644 --- a/board/prodrive/p3mx/mv_eth.c +++ b/board/prodrive/p3mx/mv_eth.c @@ -312,6 +312,7 @@ void mv6446x_eth_initialize (bd_t * bis) /* ronen - set the MAC addr in the HW */ eth_port_uc_addr_set (devnum, dev->enetaddr, 0); + dev->send_alignment = 1; dev->init = (void *) db64460_eth_probe; dev->halt = (void *) ethernet_phy_reset; dev->send = (void *) db64460_eth_transmit; diff --git a/cpu/ixp/npe/npe.c b/cpu/ixp/npe/npe.c index 2e68689..42ba735 100644 --- a/cpu/ixp/npe/npe.c +++ b/cpu/ixp/npe/npe.c @@ -607,6 +607,7 @@ int npe_initialize(bd_t * bis) p_npe->phy_no = CONFIG_PHY_ADDR; sprintf(dev->name, "NPE%d", eth_num); + dev->send_alignment = 1; dev->priv = (void *)p_npe; dev->init = npe_init; dev->halt = npe_halt; diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index 5074997..569745d 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -294,6 +294,7 @@ int au1x00_enet_initialize(bd_t *bis){ sprintf(dev->name, "Au1X00 ethernet"); dev->iobase = 0; + dev->send_alignment = 1; dev->priv = 0; dev->init = au1x00_init; dev->halt = au1x00_halt; diff --git a/cpu/mpc8260/ether_scc.c b/cpu/mpc8260/ether_scc.c index 432111d..9fdf992 100644 --- a/cpu/mpc8260/ether_scc.c +++ b/cpu/mpc8260/ether_scc.c @@ -376,6 +376,7 @@ int mpc82xx_scc_enet_initialize(bd_t *bis) memset(dev, 0, sizeof *dev); sprintf(dev->name, "SCC ETHERNET"); + dev->send_alignment = 1; dev->init = sec_init; dev->halt = sec_halt; dev->send = sec_send; diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index 329eef0..3d68a80 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -2016,6 +2016,7 @@ int ppc_4xx_eth_initialize (bd_t * bis) hw->print_speed = 1; sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); + dev->send_alignment = 1; dev->priv = (void *) hw; dev->init = ppc_4xx_eth_init; dev->halt = ppc_4xx_eth_halt; diff --git a/drivers/net/ax88180.c b/drivers/net/ax88180.c index d843397..6c77865 100644 --- a/drivers/net/ax88180.c +++ b/drivers/net/ax88180.c @@ -694,6 +694,7 @@ int ax88180_initialize (bd_t * bis) sprintf (dev->name, "ax88180"); dev->iobase = AX88180_BASE; + dev->send_alignment = 1; dev->priv = priv; dev->init = ax88180_init; dev->halt = ax88180_halt; diff --git a/drivers/net/bfin_mac.c b/drivers/net/bfin_mac.c index 12d98c2..02f6e8b 100644 --- a/drivers/net/bfin_mac.c +++ b/drivers/net/bfin_mac.c @@ -101,6 +101,7 @@ int bfin_EMAC_initialize(bd_t *bis) sprintf(dev->name, "Blackfin EMAC"); dev->iobase = 0; + dev->send_alignment = 1; dev->priv = 0; dev->init = bfin_EMAC_init; dev->halt = bfin_EMAC_halt; diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c index fa8cee4..e9e930e 100644 --- a/drivers/net/davinci_emac.c +++ b/drivers/net/davinci_emac.c @@ -556,6 +556,7 @@ int davinci_emac_initialize(void) memset(dev, 0, sizeof *dev); dev->iobase = 0; + dev->send_alignment = 1; dev->init = davinci_eth_open; dev->halt = davinci_eth_close; dev->send = davinci_eth_send_packet; diff --git a/drivers/net/dc2114x.c b/drivers/net/dc2114x.c index 5ae53e8..c927a0a 100644 --- a/drivers/net/dc2114x.c +++ b/drivers/net/dc2114x.c @@ -291,6 +291,7 @@ int dc21x4x_initialize(bd_t *bis) #else dev->iobase = pci_mem_to_phys(devbusfn, iobase); #endif + dev->send_alignment = 1; dev->priv = (void*) devbusfn; dev->init = dc21x4x_init; dev->halt = dc21x4x_halt; diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c index efe9135..c2f3a80 100644 --- a/drivers/net/dm9000x.c +++ b/drivers/net/dm9000x.c @@ -621,6 +621,7 @@ int dm9000_initialize(bd_t *bis) { struct eth_device *dev = &(dm9000_info.netdev); + dev->send_alignment = 1; dev->init = dm9000_init; dev->halt = dm9000_halt; dev->send = dm9000_send; diff --git a/drivers/net/dnet.c b/drivers/net/dnet.c index bfe87fa..7881ef5 100644 --- a/drivers/net/dnet.c +++ b/drivers/net/dnet.c @@ -377,6 +377,7 @@ int dnet_eth_initialize(int id, void *regs, unsigned int phy_addr) dnet->phy_addr = phy_addr; sprintf(netdev->name, "dnet%d", id); + netdev->send_alignment = 1; netdev->init = dnet_init; netdev->halt = dnet_halt; netdev->send = dnet_send; diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index 777783a..83cc03e 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -5215,6 +5215,7 @@ e1000_initialize(bd_t * bis) nic->enetaddr[0], nic->enetaddr[1], nic->enetaddr[2], nic->enetaddr[3], nic->enetaddr[4], nic->enetaddr[5]); + nic->send_alignment = 1; nic->init = e1000_init; nic->recv = e1000_poll; nic->send = e1000_transmit; diff --git a/drivers/net/eepro100.c b/drivers/net/eepro100.c index 9c06b25..a0ccad1 100644 --- a/drivers/net/eepro100.c +++ b/drivers/net/eepro100.c @@ -453,6 +453,7 @@ int eepro100_initialize (bd_t * bis) sprintf (dev->name, "i82559#%d", card_number); dev->priv = (void *) devno; /* this have to come before bus_to_phys() */ dev->iobase = bus_to_phys (iobase); + dev->send_alignment = 1; dev->init = eepro100_init; dev->halt = eepro100_halt; dev->send = eepro100_send; diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index bd83a24..2238d1c 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -665,6 +665,7 @@ static int fec_probe(bd_t *bd) return -ENOMEM; } edev->priv = fec; + edev->send_alignment = 1; edev->init = fec_init; edev->send = fec_send; edev->recv = fec_recv; diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c index 35a6dfb..3a59a22 100644 --- a/drivers/net/fsl_mcdmafec.c +++ b/drivers/net/fsl_mcdmafec.c @@ -533,6 +533,7 @@ int mcdmafec_initialize(bd_t * bis) sprintf(dev->name, "FEC%d", fec_info[i].index); + dev->send_alignment = 1; dev->priv = &fec_info[i]; dev->init = fec_init; dev->halt = fec_halt; diff --git a/drivers/net/ftmac100.c b/drivers/net/ftmac100.c index 2328cb5..0bee211 100644 --- a/drivers/net/ftmac100.c +++ b/drivers/net/ftmac100.c @@ -261,6 +261,7 @@ int ftmac100_initialize (bd_t *bd) sprintf (dev->name, "FTMAC100"); dev->iobase = CONFIG_FTMAC100_BASE; + dev->send_alignment = 1; dev->init = ftmac100_init; dev->halt = ftmac100_halt; dev->send = ftmac100_send; diff --git a/drivers/net/greth.c b/drivers/net/greth.c index 79bc4d9..dbfc737 100644 --- a/drivers/net/greth.c +++ b/drivers/net/greth.c @@ -601,6 +601,7 @@ int greth_initialize(bd_t * bis) #endif dev->priv = (void *)greth; dev->iobase = (unsigned int)greth->regs; + dev->send_alignment = 1; dev->init = greth_init; dev->halt = greth_halt; dev->send = greth_send; diff --git a/drivers/net/inca-ip_sw.c b/drivers/net/inca-ip_sw.c index 492f5ce..b900de5 100644 --- a/drivers/net/inca-ip_sw.c +++ b/drivers/net/inca-ip_sw.c @@ -189,6 +189,7 @@ int inca_switch_initialize(bd_t * bis) #endif sprintf(dev->name, "INCA-IP Switch"); + dev->send_alignment = 1; dev->init = inca_switch_init; dev->halt = inca_switch_halt; dev->send = inca_switch_send; diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index f31fefc..c460e4a 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -660,6 +660,7 @@ int kirkwood_egiga_initialize(bd_t * bis) eth_setenv_enetaddr(s, dev->enetaddr); } + dev->send_alignment = 8; dev->init = (void *)kwgbe_init; dev->halt = (void *)kwgbe_halt; dev->send = (void *)kwgbe_send; diff --git a/drivers/net/macb.c b/drivers/net/macb.c index c184353..5bdef70 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -519,6 +519,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) macb->phy_addr = phy_addr; sprintf(netdev->name, "macb%d", id); + netdev->send_alignment = 1; netdev->init = macb_init; netdev->halt = macb_halt; netdev->send = macb_send; diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index 64be5de..1413860 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -572,6 +572,7 @@ int mcffec_initialize(bd_t * bis) sprintf(dev->name, "FEC%d", fec_info[i].index); + dev->send_alignment = 1; dev->priv = &fec_info[i]; dev->init = fec_init; dev->halt = fec_halt; diff --git a/drivers/net/mpc5xxx_fec.c b/drivers/net/mpc5xxx_fec.c index 1876b76..46c001b 100644 --- a/drivers/net/mpc5xxx_fec.c +++ b/drivers/net/mpc5xxx_fec.c @@ -918,6 +918,7 @@ int mpc5xxx_fec_initialize(bd_t * bis) dev->priv = (void *)fec; dev->iobase = MPC5XXX_FEC; + dev->send_alignment = 1; dev->init = mpc5xxx_fec_init; dev->halt = mpc5xxx_fec_halt; dev->send = mpc5xxx_fec_send; diff --git a/drivers/net/natsemi.c b/drivers/net/natsemi.c index ce12c3b..4709ec7 100644 --- a/drivers/net/natsemi.c +++ b/drivers/net/natsemi.c @@ -327,6 +327,7 @@ natsemi_initialize(bd_t * bis) #ifdef NATSEMI_DEBUG printf("natsemi: NatSemi ns8381[56] @ %#x\n", dev->iobase); #endif + dev->send_alignment = 1; dev->priv = (void *) devno; dev->init = natsemi_init; dev->halt = natsemi_disable; diff --git a/drivers/net/ns8382x.c b/drivers/net/ns8382x.c index 198f73d..fac0395 100644 --- a/drivers/net/ns8382x.c +++ b/drivers/net/ns8382x.c @@ -343,6 +343,7 @@ ns8382x_initialize(bd_t * bis) sprintf(dev->name, "dp8382x#%d", card_number); dev->iobase = bus_to_phys(iobase); + dev->send_alignment = 1; dev->priv = (void *) devno; dev->init = ns8382x_init; dev->halt = ns8382x_disable; diff --git a/drivers/net/pcnet.c b/drivers/net/pcnet.c index 99b6942..ea02f6f 100644 --- a/drivers/net/pcnet.c +++ b/drivers/net/pcnet.c @@ -223,6 +223,7 @@ int pcnet_initialize (bd_t * bis) /* * Setup device structure and register the driver. */ + dev->send_alignment = 1; dev->init = pcnet_init; dev->halt = pcnet_halt; dev->send = pcnet_send; diff --git a/drivers/net/plb2800_eth.c b/drivers/net/plb2800_eth.c index d799c73..1de73ae 100644 --- a/drivers/net/plb2800_eth.c +++ b/drivers/net/plb2800_eth.c @@ -111,6 +111,7 @@ int plb2800_eth_initialize(bd_t * bis) memset(dev, 0, sizeof(*dev)); sprintf(dev->name, "PLB2800 Switch"); + dev->send_alignment = 1; dev->init = plb2800_eth_init; dev->halt = plb2800_eth_halt; dev->send = plb2800_eth_send; diff --git a/drivers/net/rtl8139.c b/drivers/net/rtl8139.c index db8a727..b9fe39e 100644 --- a/drivers/net/rtl8139.c +++ b/drivers/net/rtl8139.c @@ -225,6 +225,7 @@ int rtl8139_initialize(bd_t *bis) dev->priv = (void *) devno; dev->iobase = (int)bus_to_phys(iobase); + dev->send_alignment = 1; dev->init = rtl8139_probe; dev->halt = rtl_disable; dev->send = rtl_transmit; diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index e45d1a5..5919723 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -899,6 +899,7 @@ int rtl8169_initialize(bd_t *bis) dev->priv = (void *) devno; dev->iobase = (int)pci_mem_to_phys(devno, iobase); + dev->send_alignment = 1; dev->init = rtl_reset; dev->halt = rtl_halt; diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 86cc324..d977169 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -652,6 +652,7 @@ int sh_eth_initialize(bd_t *bd) dev->priv = (void *)eth; dev->iobase = 0; + dev->send_alignment = 1; dev->init = sh_eth_init; dev->halt = sh_eth_halt; dev->send = sh_eth_send; diff --git a/drivers/net/sk98lin/uboot_drv.c b/drivers/net/sk98lin/uboot_drv.c index 0199b33..c166057 100644 --- a/drivers/net/sk98lin/uboot_drv.c +++ b/drivers/net/sk98lin/uboot_drv.c @@ -63,6 +63,7 @@ int skge_initialize(bd_t * bis) { sprintf (dev[i]->name, "SK98#%d", i); + dev[i]->send_alignment = 1; dev[i]->init = skge_init; dev[i]->halt = skge_halt; dev[i]->send = skge_send; diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 18a729c..ca99fcd 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -262,6 +262,7 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->enetaddr[4] = addrh; dev->enetaddr[5] = addrh >> 8; + dev->send_alignment = 1; dev->init = smc911x_init; dev->halt = smc911x_halt; dev->send = smc911x_send; diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index a9ba683..30c0ee3 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -141,6 +141,7 @@ int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info) sprintf(dev->name, tsec_info->devname); dev->iobase = 0; + dev->send_alignment = 1; dev->priv = priv; dev->init = tsec_init; dev->halt = tsec_halt; diff --git a/drivers/net/tsi108_eth.c b/drivers/net/tsi108_eth.c index 079354a..cbab8f0 100644 --- a/drivers/net/tsi108_eth.c +++ b/drivers/net/tsi108_eth.c @@ -735,6 +735,7 @@ int tsi108_eth_initialize (bd_t * bis) sprintf (dev->name, "TSI108_eth%d", index); dev->iobase = ETH_BASE + (index * ETH_PORT_OFFSET); + dev->send_alignment = 1; dev->priv = (void *)(phy_address[index]); dev->init = tsi108_eth_probe; dev->halt = tsi108_eth_halt; diff --git a/drivers/net/uli526x.c b/drivers/net/uli526x.c index 9477851..e86c0a1 100644 --- a/drivers/net/uli526x.c +++ b/drivers/net/uli526x.c @@ -232,6 +232,7 @@ int uli526x_initialize(bd_t *bis) dev->priv = db; db->pdev = devno; dev->iobase = iobase; + dev->send_alignment = 1; dev->init = uli526x_init_one; dev->halt = uli526x_disable; diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index db95ada..aed7bf3 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -1354,6 +1354,7 @@ int uec_initialize(bd_t *bis, uec_info_t *uec_info) sprintf(dev->name, "FSL UEC%d", uec_info->uf_info.ucc_num); dev->iobase = 0; + dev->send_alignment = 1; dev->priv = (void *)uec; dev->init = uec_init; dev->halt = uec_halt; diff --git a/include/net.h b/include/net.h index 4873000..1f84981 100644 --- a/include/net.h +++ b/include/net.h @@ -97,6 +97,7 @@ struct eth_device { unsigned char enetaddr[6]; int iobase; int state; + int send_alignment; /* Power of two send buffer alignment requirement */ int (*init) (struct eth_device*, bd_t*); int (*send) (struct eth_device*, volatile void* packet, int length); diff --git a/net/eth.c b/net/eth.c index 9b50312..4508a7d 100644 --- a/net/eth.c +++ b/net/eth.c @@ -362,10 +362,39 @@ void eth_halt(void) int eth_send(volatile void *packet, int length) { + void *p = (void *)packet; + if (!eth_current) return -1; - return eth_current->send(eth_current, packet, length); + /* Copy buffer if it's misaligned */ + if ((u32) packet & (eth_current->send_alignment - 1)) { + static void *aligned_buf; + + /* eth_current might have changed, so possibly reallocate the buf + * if it doesn't match the requirements for eth_current */ + if (aligned_buf && + ((u32)aligned_buf & (eth_current->send_alignment - 1))) { + free(aligned_buf); + aligned_buf = NULL; + } + + if (!aligned_buf) + aligned_buf = memalign(eth_current->send_alignment, + PKTSIZE_ALIGN); + if (!aligned_buf) { + printf("eth_send: Cannot allocate aligned buffer\n"); + return -1; + } + if (length > PKTSIZE_ALIGN) { + printf("eth_send: Non-aligned data too large (%d)\n", length); + return -1; + } + memcpy(aligned_buf, p, length); + p = aligned_buf; + } + + return eth_current->send(eth_current, p, length); } int eth_rx(void) -- 1.6.0.4

3 6

[U-Boot] [PATCH v6 1/2] arm: A320: driver for FTRTC010 real time clock
by ratbert.chuang＠gmail.com 20 Aug '09

20 Aug '09

From: Po-Yu Chuang <ratbert(a)faraday-tech.com> This patch adds an FTRTC010 driver for Faraday A320 evaluation board. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- drivers/rtc/Makefile | 1 + drivers/rtc/ftrtc010.c | 124 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/ftrtc010.c diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 822dc1a..25252b5 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_RTC_DS1556) += ds1556.o COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o COBJS-$(CONFIG_RTC_DS3231) += ds3231.o +COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-$(CONFIG_RTC_M41T11) += m41t11.o COBJS-$(CONFIG_RTC_M41T60) += m41t60.o diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c new file mode 100644 index 0000000..c3c0bc2 --- /dev/null +++ b/drivers/rtc/ftrtc010.c @@ -0,0 +1,124 @@ +/* + * Faraday FTRTC010 Real Time Clock + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <rtc.h> +#include <asm/io.h> + +struct ftrtc010 { + unsigned int sec; /* 0x00 */ + unsigned int min; /* 0x04 */ + unsigned int hour; /* 0x08 */ + unsigned int day; /* 0x0c */ + unsigned int alarm_sec; /* 0x10 */ + unsigned int alarm_min; /* 0x14 */ + unsigned int alarm_hour; /* 0x18 */ + unsigned int record; /* 0x1c */ + unsigned int cr; /* 0x20 */ +}; + +/* + * RTC Control Register + */ +#define FTRTC010_CR_ENABLE (1 << 0) +#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ +#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ +#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ +#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ + +static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; + +static void ftrtc010_enable (void) +{ + writel (FTRTC010_CR_ENABLE, &rtc->cr); +} + +/* + * return current time in seconds + */ +static unsigned long ftrtc010_time (void) +{ + unsigned long day; + unsigned long hour; + unsigned long minute; + unsigned long second; + unsigned long second2; + + do { + second = readl (&rtc->sec); + day = readl (&rtc->day); + hour = readl (&rtc->hour); + minute = readl (&rtc->min); + second2 = readl (&rtc->sec); + } while (second != second2); + + return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; +} + +/* + * Get the current time from the RTC + */ + +int rtc_get (struct rtc_time *tmp) +{ + unsigned long now; + + debug ("%s(): record register: %x\n", + __func__, readl (&rtc->record)); + + now = ftrtc010_time () + readl (&rtc->record); + + to_tm (now, tmp); + + return 0; +} + +/* + * Set the RTC + */ +int rtc_set (struct rtc_time *tmp) +{ + unsigned long new; + unsigned long now; + + debug ("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + __func__, + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + new = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, + tmp->tm_min, tmp->tm_sec); + + now = ftrtc010_time (); + + debug ("%s(): write %lx to record register\n", __func__, new - now); + + writel (new - now, &rtc->record); + + return 0; +} + +void rtc_reset (void) +{ + debug ("%s()\n", __func__); + ftrtc010_enable (); +} -- 1.6.3.3

1 0

Re: [U-Boot] [PATCH 3/3 v4] arm: A320: Add support for Faraday A320 evaluation board
by Po-Yu Chuang 20 Aug '09

20 Aug '09

This patch adds support for A320 development board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 7 + board/faraday/a320/Makefile | 51 +++++++ board/faraday/a320/a320.c | 64 ++++++++ board/faraday/a320/config.mk | 35 +++++ board/faraday/a320/lowlevel_init.S | 191 ++++++++++++++++++++++++ cpu/arm920t/faraday/Makefile | 46 ++++++ cpu/arm920t/faraday/ftsmc020.c | 51 +++++++ cpu/arm920t/faraday/timer.c | 195 +++++++++++++++++++++++++ include/asm-arm/arch-faraday/ftahbc020.h | 71 +++++++++ include/asm-arm/arch-faraday/ftpmu010.h | 190 ++++++++++++++++++++++++ include/asm-arm/arch-faraday/ftsdmc020.h | 103 +++++++++++++ include/asm-arm/arch-faraday/ftsmc020.h | 79 ++++++++++ include/asm-arm/arch-faraday/fttmr010.h | 73 +++++++++ include/configs/a320.h | 235 ++++++++++++++++++++++++++++++ 16 files changed, 1396 insertions(+), 0 deletions(-) create mode 100644 board/faraday/a320/Makefile create mode 100644 board/faraday/a320/a320.c create mode 100644 board/faraday/a320/config.mk create mode 100644 board/faraday/a320/lowlevel_init.S create mode 100644 cpu/arm920t/faraday/Makefile create mode 100644 cpu/arm920t/faraday/ftsmc020.c create mode 100644 cpu/arm920t/faraday/timer.c create mode 100644 include/asm-arm/arch-faraday/ftahbc020.h create mode 100644 include/asm-arm/arch-faraday/ftpmu010.h create mode 100644 include/asm-arm/arch-faraday/ftsdmc020.h create mode 100644 include/asm-arm/arch-faraday/ftsmc020.h create mode 100644 include/asm-arm/arch-faraday/fttmr010.h create mode 100644 include/configs/a320.h diff --git a/MAINTAINERS b/MAINTAINERS index b0e370f..ed41b3a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -680,6 +680,10 @@ Sergey Lapin <slapin(a)ossfans.org> afeb9260 ARM926EJS (AT91SAM9260 SoC) +Po-Yu Chuang <ratbert(a)faraday-tech.com> + + a320 FA526 (ARMv4/reuse arm920t source) faraday SoC + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index 027207d..530a253 100755 --- a/MAKEALL +++ b/MAKEALL @@ -498,6 +498,7 @@ LIST_ARM7=" \ ######################################################################### LIST_ARM9=" \ + a320 \ ap920t \ ap922_XA10 \ ap926ejs \ diff --git a/Makefile b/Makefile index 0ae1d36..f99e9d4 100644 --- a/Makefile +++ b/Makefile @@ -2991,6 +2991,13 @@ B2_config : unconfig @$(MKCONFIG) $(@:_config=) arm s3c44b0 B2 dave ######################################################################### +## Faraday A320 Systems +######################################################################### + +a320_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t a320 faraday faraday + +######################################################################### ## ARM720T Systems ######################################################################### diff --git a/board/faraday/a320/Makefile b/board/faraday/a320/Makefile new file mode 100644 index 0000000..ef053c2 --- /dev/null +++ b/board/faraday/a320/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := a320.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/faraday/a320/a320.c b/board/faraday/a320/a320.c new file mode 100644 index 0000000..94517c9 --- /dev/null +++ b/board/faraday/a320/a320.c @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <rtc.h> +#include <asm/io.h> + +#include <asm/arch/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_FARADAY; + + ftsmc020_init (); /* initialize Flash */ + rtc_reset (); /* enable RTC */ + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_eth_init (bd_t *bd) +{ + return ftmac100_initialize (bd); +} + +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/faraday/a320/config.mk b/board/faraday/a320/config.mk new file mode 100644 index 0000000..7573bbd --- /dev/null +++ b/board/faraday/a320/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2009 Faraday Technology +# Po-Yu Chuang <ratbert(a)faraday-tech.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus +# +# see http://www.faraday-tech.com/ for more information + +# A320 has 1 bank of 64 MB DRAM (after remapped) +# +# 0000'0000 to 0400'0000 +# +# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000 +# +# we load ourself to 03f8'0000 +# +# download area is 0200'0000 + +TEXT_BASE = 0x03f80000 diff --git a/board/faraday/a320/lowlevel_init.S b/board/faraday/a320/lowlevel_init.S new file mode 100644 index 0000000..4337740 --- /dev/null +++ b/board/faraday/a320/lowlevel_init.S @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <version.h> + +#include <asm/macro.h> +#include <asm/arch/ftahbc020.h> +#include <asm/arch/ftsdmc020.h> + +/* + * Memory Mapping + */ +#define ROM_DEFAULT_BASE 0x00000000 +#define SDRAM_DEFAULT_BASE 0x10000000 +#define SDRAM_REMAPPED_BASE PHYS_SDRAM_1 /* remap location */ + +/* + * parameters for the SDRAM controller + */ +#define TP0_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_TP0) +#define TP1_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_TP1) +#define CR_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_CR) +#define B0_BSR_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_BANK0_BSR) +#define ACR_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_ACR) + +#define TP0_D CONFIG_SYS_FTSDMC020_TP0 +#define TP1_D CONFIG_SYS_FTSDMC020_TP1 +#define CR_D1 FTSDMC020_CR_IPREC +#define CR_D2 FTSDMC020_CR_ISMR +#define CR_D3 FTSDMC020_CR_IREF + +#define B0_BSR_D1 (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ + FTSDMC020_BANK_BASE(SDRAM_DEFAULT_BASE)) +#define B0_BSR_D2 (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ + FTSDMC020_BANK_BASE(SDRAM_REMAPPED_BASE)) +#define ACR_D FTSDMC020_ACR_TOC(0x18) + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_SYS_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +.macro wait_sdram + ldr r0, =CONFIG_SYS_SDMC_BASE +1: + ldr r1, [r0, #FTSDMC020_OFFSET_CR] + cmp r1, #0 + bne 1b +.endm + +.global reset_cpu +reset_cpu: + b reset_cpu + +.globl lowlevel_init +lowlevel_init: + mov r11, lr + + led 0x0 + + /* if REMAP bit is set -> memory had been initialzed */ + + ldr r0, =CONFIG_SYS_AHBC_BASE + ldr r1, [r0, #FTAHBC020_OFFSET_ICR] + tst r1, #FTAHBC020_ICR_REMAP @ test REMAP bit + bne skip_remap + + led 0x1 + + bl init_sdmc + + led 0x2 + + /* + * copy U-Boot to RAM + */ +copy_code: + ldr r0, =ROM_DEFAULT_BASE /* r0 <- source address */ + ldr r1, =SDRAM_DEFAULT_BASE /* r1 <- target address */ + + ldr r2, .LC5 + ldr r3, .LC6 + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + + led 0x3 + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + led 0x4 + + bl remap + +skip_remap: + led 0x5 + + /* everything is fine now */ + mov lr, r11 + mov pc, lr + +.LC5: + .word _start +.LC6: + .word __bss_start + +/* + * memory initialization + */ +init_sdmc: + led 0x10 + + /* set SDRAM register */ + + write32 TP0_A, TP0_D + led 0x11 + + write32 TP1_A, TP1_D + led 0x12 + + /* set to precharge */ + write32 CR_A, CR_D1 + led 0x13 + + wait_sdram + led 0x14 + + /* set mode register */ + write32 CR_A, CR_D2 + led 0x15 + + wait_sdram + led 0x16 + + /* set to refresh */ + write32 CR_A, CR_D3 + led 0x17 + + wait_sdram + led 0x18 + + write32 B0_BSR_A, B0_BSR_D1 + led 0x19 + + write32 ACR_A, ACR_D + led 0x1a + + mov pc, lr + +/* + * This code will remap the memory ROM and SDRAM + * ROM will be placed on 0x80000000 SDRAM will jump to 0x0 + */ +remap: + ldr r0, =CONFIG_SYS_SDMC_BASE + + /* first adjust sdram */ + write32 B0_BSR_A, B0_BSR_D2 + + /* then remap */ + ldr r3, =CONFIG_SYS_AHBC_BASE + ldr r4, [r3, #FTAHBC020_OFFSET_ICR] + orr r4, r4, #FTAHBC020_ICR_REMAP @ Set REMAP bit + str r4, [r3, #FTAHBC020_OFFSET_ICR] + + mov pc, lr diff --git a/cpu/arm920t/faraday/Makefile b/cpu/arm920t/faraday/Makefile new file mode 100644 index 0000000..b879d87 --- /dev/null +++ b/cpu/arm920t/faraday/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS += timer.o +COBJS += ftsmc020.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm920t/faraday/ftsmc020.c b/cpu/arm920t/faraday/ftsmc020.c new file mode 100644 index 0000000..b1b00e1 --- /dev/null +++ b/cpu/arm920t/faraday/ftsmc020.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftsmc020.h> + +struct ftsmc020_config { + unsigned int config; + unsigned int timing; +}; + +static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; + +static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_SYS_SMC_BASE; + +static void ftsmc020_setup_bank (unsigned int bank, struct ftsmc020_config *cfg) +{ + if (bank > 3) { + printf ("bank # %u invalid\n", bank); + return; + } + + writel (cfg->config, &smc->bank[bank].cr); + writel (cfg->timing, &smc->bank[bank].tpr); +} + +void ftsmc020_init (void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE (config); i++) + ftsmc020_setup_bank (i, &config[i]); +} diff --git a/cpu/arm920t/faraday/timer.c b/cpu/arm920t/faraday/timer.c new file mode 100644 index 0000000..5a49b24 --- /dev/null +++ b/cpu/arm920t/faraday/timer.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#undef DEBUG + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftpmu010.h> +#include <asm/arch/fttmr010.h> + +static ulong timestamp; +static ulong lastdec; + +static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_SYS_TIMERBASE; +static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_SYS_FTPMU_BASE; + +#define TIMER_CLOCK 32768 +#define TIMER_LOAD_VAL 0xffffffff + +int timer_init (void) +{ + unsigned int oscc; + unsigned int cr; + + debug ("%s()\n", __func__); + + /* disable timers */ + writel (0, &tmr->cr); + + /* + * use 32768Hz oscillator for RTC, WDT, TIMER + */ + + /* enable the 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); + writel (oscc, &pmu->OSCC); + + /* wait until ready */ + while (!(readl (&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) + ; + + /* select 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc |= FTPMU010_RTCLSEL; + writel (oscc, &pmu->OSCC); + + /* setup timer */ + writel (TIMER_LOAD_VAL, &tmr->timer3_load); + writel (TIMER_LOAD_VAL, &tmr->timer3_counter); + writel (0, &tmr->timer3_match1); + writel (0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel (FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl (&tmr->cr); + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ + cr |= FTTMR010_TM3_ENABLE; + writel (cr, &tmr->cr); + + /* init the timestamp and lastdec value */ + reset_timer_masked (); + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * reset time + */ +void reset_timer_masked (void) +{ + /* capure current decrementer value time */ + lastdec = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ + + debug ("%s(): lastdec = %lx\n", __func__, lastdec); +} + +void reset_timer (void) +{ + debug ("%s()\n", __func__); + reset_timer_masked (); +} + +/* + * return timer ticks + */ +ulong get_timer_masked (void) +{ + /* current tick value */ + ulong now = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + debug ("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp fordward with absoulte diff ticks + */ + timestamp += lastdec - now; + } else { + /* + * we have overflow of the count down timer + * + * nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and + * cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + debug ("%s() returns %lx\n", __func__, timestamp); + + return timestamp; +} + +/* + * return difference between timer ticks and base + */ +ulong get_timer (ulong base) +{ + debug ("%s(%lx)\n", __func__, base); + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + debug ("%s(%lx)\n", __func__, t); + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + unsigned long now, last = readl(&tmr->timer3_counter); + + debug ("%s(%lu)\n", __func__, usec); + while (tmo > 0) { + now = readl(&tmr->timer3_counter); + if (now > last) /* count down timer overflow */ + tmo -= TIMER_LOAD_VAL + last - now; + else + tmo -= last - now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks (void) +{ + debug ("%s()\n", __func__); + return get_timer (0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + debug ("%s()\n", __func__); + return CONFIG_SYS_HZ; +} diff --git a/include/asm-arm/arch-faraday/ftahbc020.h b/include/asm-arm/arch-faraday/ftahbc020.h new file mode 100644 index 0000000..c2e039e --- /dev/null +++ b/include/asm-arm/arch-faraday/ftahbc020.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * AHB Controller + */ +#ifndef __FTAHBC020_H +#define __FTAHBC020_H + +#define FTAHBC020_OFFSET_SLAVE0_BSR 0x00 +#define FTAHBC020_OFFSET_SLAVE1_BSR 0x04 +#define FTAHBC020_OFFSET_SLAVE2_BSR 0x08 +#define FTAHBC020_OFFSET_SLAVE3_BSR 0x0C +#define FTAHBC020_OFFSET_SLAVE4_BSR 0x10 +#define FTAHBC020_OFFSET_SLAVE5_BSR 0x14 +#define FTAHBC020_OFFSET_SLAVE6_BSR 0x18 +#define FTAHBC020_OFFSET_SLAVE7_BSR 0x1C +#define FTAHBC020_OFFSET_SLAVE9_BSR 0x24 +#define FTAHBC020_OFFSET_SLAVE12_BSR 0x30 +#define FTAHBC020_OFFSET_SLAVE13_BSR 0x34 +#define FTAHBC020_OFFSET_SLAVE14_BSR 0x38 +#define FTAHBC020_OFFSET_SLAVE15_BSR 0x3C +#define FTAHBC020_OFFSET_SLAVE17_BSR 0x44 +#define FTAHBC020_OFFSET_SLAVE18_BSR 0x48 +#define FTAHBC020_OFFSET_SLAVE19_BSR 0x4C +#define FTAHBC020_OFFSET_SLAVE21_BSR 0x54 +#define FTAHBC020_OFFSET_SLAVE22_BSR 0x58 +#define FTAHBC020_OFFSET_PCR 0x80 +#define FTAHBC020_OFFSET_TCR 0x84 +#define FTAHBC020_OFFSET_ICR 0x88 + +/* + * AHB Slave n Base/Size Register + */ +#define FTAHBC020_BSR_BASE(x) ((x) & 0xfff00000) + +#define FTAHBC020_BSR_SIZE_1M (0x0 << 16) +#define FTAHBC020_BSR_SIZE_2M (0x1 << 16) +#define FTAHBC020_BSR_SIZE_4M (0x2 << 16) +#define FTAHBC020_BSR_SIZE_8M (0x3 << 16) +#define FTAHBC020_BSR_SIZE_16M (0x4 << 16) +#define FTAHBC020_BSR_SIZE_32M (0x5 << 16) +#define FTAHBC020_BSR_SIZE_64M (0x6 << 16) +#define FTAHBC020_BSR_SIZE_128M (0x7 << 16) +#define FTAHBC020_BSR_SIZE_256M (0x8 << 16) +#define FTAHBC020_BSR_SIZE_512M (0x9 << 16) +#define FTAHBC020_BSR_SIZE_1G (0xa << 16) +#define FTAHBC020_BSR_SIZE_2G (0xb << 16) + +/* + * AHB Interrupt Control Register + */ +#define FTAHBC020_ICR_REMAP (1 << 0) + +#endif /* __FTAHBC020_H */ diff --git a/include/asm-arm/arch-faraday/ftpmu010.h b/include/asm-arm/arch-faraday/ftpmu010.h new file mode 100644 index 0000000..e365af5 --- /dev/null +++ b/include/asm-arm/arch-faraday/ftpmu010.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +#define FTPMU010_OFFSET_IDNMBR0 0x00 +#define FTPMU010_OFFSET_OSCC 0x08 +#define FTPMU010_OFFSET_PMODE 0x0C +#define FTPMU010_OFFSET_PMCR 0x10 +#define FTPMU010_OFFSET_PED 0x14 +#define FTPMU010_OFFSET_PEDSR 0x18 +#define FTPMU010_OFFSET_PMSR 0x20 +#define FTPMU010_OFFSET_PGSR 0x24 +#define FTPMU010_OFFSET_MFPSR 0x28 +#define FTPMU010_OFFSET_MISC 0x2C +#define FTPMU010_OFFSET_PDLLCR0 0x30 +#define FTPMU010_OFFSET_PDLLCR1 0x34 +#define FTPMU010_OFFSET_AHBMCLKOFF 0x38 +#define FTPMU010_OFFSET_APBMCLKOFF 0x3C +#define FTPMU010_OFFSET_DCSRCR0 0x40 +#define FTPMU010_OFFSET_DCSRCR1 0x44 +#define FTPMU010_OFFSET_DCSRCR2 0x48 +#define FTPMU010_OFFSET_SDRAMHTC 0x4C +#define FTPMU010_OFFSET_PSPR0 0x50 +#define FTPMU010_OFFSET_PSPR1 0x54 +#define FTPMU010_OFFSET_PSPR2 0x58 +#define FTPMU010_OFFSET_PSPR3 0x5C +#define FTPMU010_OFFSET_PSPR4 0x60 +#define FTPMU010_OFFSET_PSPR5 0x64 +#define FTPMU010_OFFSET_PSPR6 0x68 +#define FTPMU010_OFFSET_PSPR7 0x6C +#define FTPMU010_OFFSET_PSPR8 0x70 +#define FTPMU010_OFFSET_PSPR9 0x74 +#define FTPMU010_OFFSET_PSPR10 0x78 +#define FTPMU010_OFFSET_PSPR11 0x7C +#define FTPMU010_OFFSET_PSPR12 0x80 +#define FTPMU010_OFFSET_PSPR13 0x84 +#define FTPMU010_OFFSET_PSPR14 0x88 +#define FTPMU010_OFFSET_PSPR15 0x8C +#define FTPMU010_OFFSET_AHBDMA_RACCS 0x90 +#define FTPMU010_OFFSET_JSS 0x9C +#define FTPMU010_OFFSET_CFC_RACC 0xA0 +#define FTPMU010_OFFSET_SSP1_RACC 0xA4 +#define FTPMU010_OFFSET_UART1TX_RACC 0xA8 +#define FTPMU010_OFFSET_UART1RX_RACC 0xAC +#define FTPMU010_OFFSET_UART2TX_RACC 0xB0 +#define FTPMU010_OFFSET_UART2RX_RACC 0xB4 +#define FTPMU010_OFFSET_SDC_RACC 0xB8 +#define FTPMU010_OFFSET_I2SAC97_RACC 0xBC +#define FTPMU010_OFFSET_IRDATX_RACC 0xC0 +#define FTPMU010_OFFSET_USBD_RACC 0xC8 +#define FTPMU010_OFFSET_IRDARX_RACC 0xCC +#define FTPMU010_OFFSET_IRDA_RACC 0xD0 +#define FTPMU010_OFFSET_ED0_RACC 0xD4 +#define FTPMU010_OFFSET_ED1_RACC 0xD8 + +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) + +/* + * PLL/DLL Control Register 0 + */ +#define FTPMU010_PDLLCR0_PLL1NS(x) (((x) & 0x1ff) << 3) +#define FTPMU010_PDLLCR0_PLL1NS_VALUEOF(reg) (((reg) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-faraday/ftsdmc020.h b/include/asm-arm/arch-faraday/ftsdmc020.h new file mode 100644 index 0000000..0699772 --- /dev/null +++ b/include/asm-arm/arch-faraday/ftsdmc020.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-faraday/ftsmc020.h b/include/asm-arm/arch-faraday/ftsmc020.h new file mode 100644 index 0000000..43dfa61 --- /dev/null +++ b/include/asm-arm/arch-faraday/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init (void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-faraday/fttmr010.h b/include/asm-arm/arch-faraday/fttmr010.h new file mode 100644 index 0000000..72abcb3 --- /dev/null +++ b/include/asm-arm/arch-faraday/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/include/configs/a320.h b/include/configs/a320.h new file mode 100644 index 0000000..daa17c4 --- /dev/null +++ b/include/configs/a320.h @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * Configuation settings for the Faraday A320 board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * CPU and Board Configuration Options + */ +#define CONFIG_A320 /* in a Faraday A320 SoC/Board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*----------------------------------------------------------------------- + * Timer + */ +#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ +#define CONFIG_SYS_TIMERBASE 0x98400000 + +/*----------------------------------------------------------------------- + * RTC + */ +#define CONFIG_RTC_FTRTC010 +#define CONFIG_SYS_RTC_BASE 0x98600000 + +/*----------------------------------------------------------------------- + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x98200000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 18432000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_FTMAC100 +#define CONFIG_SYS_MAC100_BASE 0x90900000 + +#define CONFIG_BOOTDELAY 3 + +/*----------------------------------------------------------------------- + * Hardware register bases + */ +#define CONFIG_SYS_AHBC_BASE 0x90100000 /* AHB Controller */ +#define CONFIG_SYS_SMC_BASE 0x90200000 /* Static Memory Controller */ +#define CONFIG_SYS_DEBUG_LED 0x902ffffc /* Debug LED */ +#define CONFIG_SYS_SDMC_BASE 0x90300000 /* SDRAM Controller */ + +#define CONFIG_SYS_FTPMU_BASE 0x98100000 /* Power Management Unit */ + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*----------------------------------------------------------------------- + * size in bytes reserved for initial data +*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/*----------------------------------------------------------------------- + * SDRAM controller configuration + */ +#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ + FTSDMC020_TP0_TRP(1) | \ + FTSDMC020_TP0_TRCD(1) | \ + FTSDMC020_TP0_TRF(3) | \ + FTSDMC020_TP0_TWR(1) | \ + FTSDMC020_TP0_TCL(2)) + +#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ + FTSDMC020_TP1_INI_REFT(8) | \ + FTSDMC020_TP1_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ + FTSDMC020_BANK_DDW_X16 | \ + FTSDMC020_BANK_DSZ_256M | \ + FTSDMC020_BANK_MBW_32 | \ + FTSDMC020_BANK_SIZE_64M) + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x02000000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x03F00000 + +/*----------------------------------------------------------------------- + * Static memory controller configuration + */ + +#include <asm/arch/ftsmc020.h> + +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_1M | \ + FTSMC020_BANK_MBW_8) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* no environments */ +#define CONFIG_ENV_IS_NOWHERE + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x20000 + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +/* support JEDEC */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + +#define PHYS_FLASH_1 0x80000000 +#define PHYS_FLASH_2 0x80400000 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } + +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_EMPTY_INFO + +#endif /* __CONFIG_H */ -- 1.6.3.3

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[U-Boot] [PATCH 3/3] mpc83xx: accommodate larger kernel sizes by default
by Kim Phillips 20 Aug '09

20 Aug '09

linux mpc83xx_defconfig kernels are getting bigger, accommodate for their growth by adjusting default load and fdt addresses. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- include/configs/MPC8313ERDB.h | 4 ++-- include/configs/MPC8315ERDB.h | 4 ++-- include/configs/MPC8323ERDB.h | 4 ++-- include/configs/MPC832XEMDS.h | 4 ++-- include/configs/MPC8349EMDS.h | 4 ++-- include/configs/MPC8360EMDS.h | 4 ++-- include/configs/MPC837XEMDS.h | 4 ++-- include/configs/MPC837XERDB.h | 4 ++-- include/configs/sbc8349.h | 4 ++-- include/configs/vme8349.h | 4 ++-- 10 files changed, 20 insertions(+), 20 deletions(-) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index d9aa60b..4bf05d2 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -594,7 +594,7 @@ #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_FDTFILE mpc8313erdb.dtb -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 @@ -611,7 +611,7 @@ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "console=ttyS0\0" \ "setbootargs=setenv bootargs " \ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index d5e62e3..84cc9fa 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -566,7 +566,7 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -576,7 +576,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=mpc8315erdb.dtb\0" \ "usb_phy_type=utmi\0" \ "" diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 907965d..c40d3d3 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -542,7 +542,7 @@ #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_FDTFILE mpc832x_rdb.dtb -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 @@ -558,7 +558,7 @@ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 4e23a11..f16616c 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -548,7 +548,7 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -558,7 +558,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=mpc832x_mds.dtb\0" \ "" diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 3cf59ef..09a1501 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -701,7 +701,7 @@ #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -732,7 +732,7 @@ "update=protect off fe000000 fe03ffff; " \ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ "upd=run load update\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=mpc8349emds.dtb\0" \ "" diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fe6ec48..b072e84 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -589,7 +589,7 @@ #define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -599,7 +599,7 @@ "consoledev=ttyS0\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=mpc836x_mds.dtb\0" \ "" diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index a2a2aad..a190a50 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -646,7 +646,7 @@ extern int board_pci_host_broken(void); #define CONFIG_BAUDRATE 115200 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -656,7 +656,7 @@ extern int board_pci_host_broken(void); "consoledev=ttyS0\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=ramfs.83xx\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=mpc8379_mds.dtb\0" \ "" diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index ca89b9b..89fafe7 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -668,7 +668,7 @@ #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_FDTFILE mpc8379_rdb.dtb -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200 @@ -684,7 +684,7 @@ "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \ "ramdiskaddr=1000000\0" \ "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 868bd54..70ede22 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -627,7 +627,7 @@ #define CONFIG_GATEWAYIP 192.168.1.1 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -654,7 +654,7 @@ "update=protect off ff800000 ff83ffff; " \ "era ff800000 ff83ffff; cp.b 100000 ff800000 ${filesize}\0" \ "upd=run load update\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=sbc8349.dtb\0" \ "" diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index 1477552..6b8cf38 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -555,7 +555,7 @@ #define CONFIG_ROOTPATH /tftpboot/rootfs #define CONFIG_BOOTFILE uImage -#define CONFIG_LOADADDR 500000 /* def location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* def location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* boot command will set bootargs */ @@ -582,7 +582,7 @@ "update=protect off fff00000 fff3ffff; " \ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ "upd=run load update\0" \ - "fdtaddr=400000\0" \ + "fdtaddr=780000\0" \ "fdtfile=vme8349.dtb\0" \ "" -- 1.6.4

1 0

[U-Boot] [RFC] cmd_ide: I/O functions cleanup
by Albin Tonnerre 20 Aug '09

20 Aug '09

Hi, This afternoon I spent some time trying to get a CompactFlash card to work on ARM (AT91). While looking at the code, I noticed several things in the I/O code that I think are wrong or could be improved, so I figured I'd ask here before writing a patch., as I might be overlooking some things. To access ide devices, we have a bunch of functions: ide_inb (overrideable) ide_outb (overrideable) input_data_shorts input_data output_data output_data_shorts input_data/_shorts and output_data/_shorts seem to be just the same functions, the only change is that _data reads twice as much data as _data_shorts (huh). What about getting rid of the _data version and just do this ? #define input_data(p,d,l) input_data_shorts(p,d,l*2) Also, input/output_data are doing their own read/writes playing with pointers, while we have ide_inb and ide_outb, which are arguably better at doing this job (especially since they can be overriden by board-specific code ...). Would it be a problem to make them use ide_inb and ide_outb ? The last issue is that when the following condition is not met: #if defined(__PPC__) || defined(CONFIG_PXA_PCMCIA) || defined(CONFIG_SH) then input_data resp. output_data are defined as follow: static void input_data(int dev, ulong *sect_buf, int words) { insw(ATA_CURR_BASE(dev)+ATA_DATA_REG, sect_buf, words << 1); } Now the issue with this is that some more code might be needed for that to work. For example on AT91, it seems that it is required to switch back and forth between 16-bit and 8-bit data bus width for CompactFlash cards to work correctly. This is not possible with the current code, as insw/outws ought to be more generic than that. Would it be possible to do just the same as with ide_inb and ide_outb, ie using ide_outsw and ide_insw as overrideable functions, while using the arch-specific insw and outsw as fallback ? Thanks in advance for your feedback, -- Albin Tonnerre, Free Electrons Kernel, drivers and embedded Linux development, consulting, training and support. http://free-electrons.com

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