August 2009 - U-Boot

[U-Boot] [PATCH] ppc/85xx: P1020RDB Support Added
by Poonam Aggrwal 20 Aug '09

20 Aug '09

Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- applies on http://git.denx.de/u-boot-mpc85xx.git branch->next Makefile | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index f92ef30..337bf89 100644 --- a/Makefile +++ b/Makefile @@ -2499,6 +2499,11 @@ P2020RDB_config: unconfig @echo "#define CONFIG_P2020" >>$(obj)include/config.h ; @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale +P1020RDB_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_P1020" >>$(obj)include/config.h ; + @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale + PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 -- 1.5.6.5

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[U-Boot] [PATCH] ppc/85xx: Added CONFIG_MAX_CPUS for P1020
by Poonam Aggrwal 20 Aug '09

20 Aug '09

Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- applies on http://git.denx.de/u-boot-mpc85xx.git branch->next include/asm-ppc/config.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index fd7961c..fb9c20e 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -38,8 +38,8 @@ #endif #endif -#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) \ - || defined(CONFIG_MPC8641) +#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020) || \ + defined(CONFIG_P1020) || defined(CONFIG_MPC8641) #define CONFIG_MAX_CPUS 2 #else #define CONFIG_MAX_CPUS 1 -- 1.5.6.5

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[U-Boot] [PATCH] ppc4xx: Rename compactcenter to intip
by Dirk Eibach 20 Aug '09

20 Aug '09

Signed-off-by: Dirk Eibach <eibach(a)gdsys.de> --- include/configs/compactcenter.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/compactcenter.h b/include/configs/compactcenter.h index f8a1bbb..9d33f56 100644 --- a/include/configs/compactcenter.h +++ b/include/configs/compactcenter.h @@ -39,8 +39,8 @@ #define CONFIG_HOSTNAME devconcenter #define CONFIG_IDENT_STRING " devconcenter 0.02" #else -#define CONFIG_HOSTNAME compactcenter -#define CONFIG_IDENT_STRING " compactcenter 0.02" +#define CONFIG_HOSTNAME intip +#define CONFIG_IDENT_STRING " intip 0.02" #endif #define CONFIG_440 1 #define CONFIG_4xx 1 /* ... PPC4xx family */ -- 1.5.6.5

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[U-Boot] [PATCH] ppc/85xx: Added support for P1011RDB and P2010RDB
by Poonam Aggrwal 20 Aug '09

20 Aug '09

P2010 and P1011 are single core variants of P2020 and P1010 respectively. The board(RDB) will be same. Signed-off-by: Poonam Aggrwal <poonam.aggrwal(a)freescale.com> Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- applies on http://git.denx.de/u-boot-mpc85xx.git branch->next Makefile | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index 337bf89..4c0e08d 100644 --- a/Makefile +++ b/Makefile @@ -2499,11 +2499,21 @@ P2020RDB_config: unconfig @echo "#define CONFIG_P2020" >>$(obj)include/config.h ; @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale +P2010RDB_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_P2010" >>$(obj)include/config.h ; + @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale + P1020RDB_config: unconfig @mkdir -p $(obj)include @echo "#define CONFIG_P1020" >>$(obj)include/config.h ; @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale +P1011RDB_config: unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_P1011" >>$(obj)include/config.h ; + @$(MKCONFIG) -a P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale + PM854_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc85xx pm854 -- 1.5.6.5

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[U-Boot] [PATCH] 85xx: Fix memory test range on MPC8536DS
by Felix Radensky 20 Aug '09

20 Aug '09

With current values of CONFIG_SYS_MEMTEST_START and CONFIG_SYS_MEMTEST_END memory test hangs if run without arguments. Set them to sane values, so that all available 512MB of RAM excluding exception vectors at the bottom and u-boot code and stack at the top can be tested. Signed-off-by: Felix Radensky <felix(a)embedded-sol.com> --- include/configs/MPC8536DS.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 9d2b860..93dd61e 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -77,8 +77,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ +#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* -- 1.5.4.3

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[U-Boot] [PATCH v2] ARM Cortex8 Rename and move v7_flush_dcache_all to flush_dcache
by Dirk Behme 20 Aug '09

20 Aug '09

Since there is only one version of flushing the dcache for arm_cortex8, rename v7_flush_dcache_all to the the generic name flush_dcache. Because the function is intended for only omap3 boards, move the function to the new file cache_flush.S. Signed-off-by: Tom Rix <Tom.Rix(a)windriver.com> Signed-off-by: Dirk Behme <dirk.behme(a)googlemail.com> --- Changes in v2: Rebase against recent git head 3b9043a7c03290c9bdbef03848307263f5f3472c "omap3: bug fix for NOR boot support" This patch updates http://lists.denx.de/pipermail/u-boot/2009-July/055543.html Second patch of this series http://lists.denx.de/pipermail/u-boot/2009-July/055544.html seems to be fixed already, so doesn't seem to be necessary any more. Compile tested with ./MAKEALL ARM_CORTEX_A8, boot tested on BeagleBoard. cpu/arm_cortexa8/cpu.c | 2 cpu/arm_cortexa8/omap3/Makefile | 1 cpu/arm_cortexa8/omap3/board.c | 2 cpu/arm_cortexa8/omap3/cache_flush.S | 118 +++++++++++++++++++++++++++++++++ cpu/arm_cortexa8/start.S | 86 ------------------------ include/asm-arm/arch-omap3/sys_proto.h | 2 6 files changed, 122 insertions(+), 89 deletions(-) create mode 100644 cpu/arm_cortexa8/omap3/cache_flush.S Index: u-boot-main/cpu/arm_cortexa8/cpu.c =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/cpu.c +++ u-boot-main/cpu/arm_cortexa8/cpu.c @@ -64,7 +64,7 @@ int cleanup_before_linux(void) /* turn off L2 cache */ l2_cache_disable(); /* invalidate L2 cache also */ - v7_flush_dcache_all(get_device_type()); + flush_dcache(get_device_type()); #endif i = 0; /* mem barrier to sync up things */ Index: u-boot-main/cpu/arm_cortexa8/omap3/board.c =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/omap3/board.c +++ u-boot-main/cpu/arm_cortexa8/omap3/board.c @@ -201,7 +201,7 @@ void s_init(void) * Right now flushing at low MPU speed. * Need to move after clock init */ - v7_flush_dcache_all(get_device_type()); + flush_dcache(get_device_type()); #ifndef CONFIG_ICACHE_OFF icache_enable(); #endif Index: u-boot-main/cpu/arm_cortexa8/omap3/cache_flush.S =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/omap3/cache_flush.S @@ -0,0 +1,118 @@ +/* + * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core + * + * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> + * + * Copyright (c) 2001 Marius GrÃ¶ger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex ZÃ¼pke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <garyj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * flush_dcache() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ + .align 5 +.global flush_dcache +flush_dcache: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + mov r7, r0 @ take a backup of device type + cmp r0, #0x3 @ check if the device type is + @ GP + moveq r12, #0x1 @ set up to invalide L2 +smi: .word 0x01600070 @ Call SMI monitor (smieq) + cmp r7, #0x3 @ compare again in case its + @ lost + beq finished_inval @ if GP device, inval done + @ above + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + + Index: u-boot-main/cpu/arm_cortexa8/start.S =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/start.S +++ u-boot-main/cpu/arm_cortexa8/start.S @@ -414,89 +414,3 @@ fiq: bl do_fiq #endif - -/* - * v7_flush_dcache_all() - * - * Flush the whole D-cache. - * - * Corrupted registers: r0-r5, r7, r9-r11 - * - * - mm - mm_struct describing address space - */ - .align 5 -.global v7_flush_dcache_all -v7_flush_dcache_all: - stmfd r13!, {r0 - r5, r7, r9 - r12, r14} - - mov r7, r0 @ take a backup of device type - cmp r0, #0x3 @ check if the device type is - @ GP - moveq r12, #0x1 @ set up to invalide L2 -smi: .word 0x01600070 @ Call SMI monitor (smieq) - cmp r7, #0x3 @ compare again in case its - @ lost - beq finished_inval @ if GP device, inval done - @ above - - mrc p15, 1, r0, c0, c0, 1 @ read clidr - ands r3, r0, #0x7000000 @ extract loc from clidr - mov r3, r3, lsr #23 @ left align loc bit field - beq finished_inval @ if loc is 0, then no need to - @ clean - mov r10, #0 @ start clean at cache level 0 -inval_loop1: - add r2, r10, r10, lsr #1 @ work out 3x current cache - @ level - mov r1, r0, lsr r2 @ extract cache type bits from - @ clidr - and r1, r1, #7 @ mask of the bits for current - @ cache only - cmp r1, #2 @ see what cache we have at - @ this level - blt skip_inval @ skip if no cache, or just - @ i-cache - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mov r2, #0 @ operand for mcr SBZ - mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to - @ sych the new cssr&csidr, - @ with armv7 this is 'isb', - @ but we compile with armv5 - mrc p15, 1, r1, c0, c0, 0 @ read the new csidr - and r2, r1, #7 @ extract the length of the - @ cache lines - add r2, r2, #4 @ add 4 (line length offset) - ldr r4, =0x3ff - ands r4, r4, r1, lsr #3 @ find maximum number on the - @ way size - clz r5, r4 @ find bit position of way - @ size increment - ldr r7, =0x7fff - ands r7, r7, r1, lsr #13 @ extract max number of the - @ index size -inval_loop2: - mov r9, r4 @ create working copy of max - @ way size -inval_loop3: - orr r11, r10, r9, lsl r5 @ factor way and cache number - @ into r11 - orr r11, r11, r7, lsl r2 @ factor index number into r11 - mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way - subs r9, r9, #1 @ decrement the way - bge inval_loop3 - subs r7, r7, #1 @ decrement the index - bge inval_loop2 -skip_inval: - add r10, r10, #2 @ increment cache number - cmp r3, r10 - bgt inval_loop1 -finished_inval: - mov r10, #0 @ swith back to cache level 0 - mcr p15, 2, r10, c0, c0, 0 @ select current cache level - @ in cssr - mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, - @ with armv7 this is 'isb', - @ but we compile with armv5 - - ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} Index: u-boot-main/cpu/arm_cortexa8/omap3/Makefile =================================================================== --- u-boot-main.orig/cpu/arm_cortexa8/omap3/Makefile +++ u-boot-main/cpu/arm_cortexa8/omap3/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).a SOBJS := lowlevel_init.o +SOBJS += cache_flush.o SOBJS += reset.o COBJS += board.o Index: u-boot-main/include/asm-arm/arch-omap3/sys_proto.h =================================================================== --- u-boot-main.orig/include/asm-arm/arch-omap3/sys_proto.h +++ u-boot-main/include/asm-arm/arch-omap3/sys_proto.h @@ -55,7 +55,7 @@ void secureworld_exit(void); void setup_auxcr(void); void try_unlock_memory(void); u32 get_boot_type(void); -void v7_flush_dcache_all(u32); +void flush_dcache(u32); void sr32(void *, u32, u32, u32); u32 wait_on_value(u32, u32, void *, u32); void sdelay(unsigned long);

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[U-Boot] [PATCH 2/3] mpc8377erdb: change DDR settings to those from latest bsp
by Kim Phillips 20 Aug '09

20 Aug '09

when using Linus' 83xx_defconfig, the mpc8377rdb would hanging at boot at either: NET: Registered protocol family 16 or the io scheduler cfq registered message. Fixing up these DDR settings appears to fix the problem. Signed-off-by: Kim Phillips <kim.phillips(a)freescale.com> --- include/configs/MPC837XERDB.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index b637f73..ca89b9b 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -190,8 +190,8 @@ /* 0x3937d322 */ #define CONFIG_SYS_DDR_TIMING_2 0x02984cc8 -#define CONFIG_SYS_DDR_INTERVAL ((1545 << SDRAM_INTERVAL_REFINT_SHIFT) \ - | (256 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) +#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ #if defined(CONFIG_DDR_2T_TIMING) @@ -205,7 +205,7 @@ /* 0x43000000 */ #endif #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ -#define CONFIG_SYS_DDR_MODE ((0x0440 << SDRAM_MODE_ESD_SHIFT) \ +#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) /* 0x04400442 */ /* DDR400 */ #define CONFIG_SYS_DDR_MODE2 0x00000000 -- 1.6.4

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[U-Boot] building u-boot using ELDK on 64-bit fedora 11
by Robert P. J. Day 20 Aug '09

20 Aug '09

i spent a few minutes earlier this morning building the latest u-boot for my beagleboard using the ELDK 4.2 arm toolchain on my 64-bit fedora 11 system and since google showed me there was some discussion as to how to do that on 64-bit debian, i figured i'd just verify that what i did seemed sane. i downloaded the ELDK 4.2 arm iso and installed, at which point i got numerous errors about a missing zlib library. since i already had glibc.i586 installed for other reasons, i just did: # yum install zlib.i586 at which point another attempt at installing ELDK worked fine. at that point, i just did the following for the latest "git pull" of u-boot (the "master" branch"): $ make omap3_beagle_config $ make and the build worked without a single diagnostic. haven't had a chance to flash and try it yet, but the end results: -rwxrwxr-x. 1 rpjday rpjday 702862 2009-08-19 10:45 u-boot -rwxrwxr-x. 1 rpjday rpjday 182500 2009-08-19 10:45 u-boot.bin -rw-rw-r--. 1 rpjday rpjday 174549 2009-08-19 10:45 u-boot.map -rwxrwxr-x. 1 rpjday rpjday 547628 2009-08-19 10:45 u-boot.srec $ file u-boot u-boot: ELF 32-bit LSB executable, ARM, version 1 (SYSV), statically linked, not stripped $ look reasonable. all in all, pretty simple unless someone wants to point out anything i did wrong. if i screwed up, it's just going on an SD card so there's little chance of me breaking anything. rday -- ======================================================================== Robert P. J. Day Waterloo, Ontario, CANADA Linux Consulting, Training and Annoying Kernel Pedantry. Web page: http://crashcourse.ca Twitter: http://twitter.com/rpjday ========================================================================

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[U-Boot] Regarding linux kernel booting.
by Thirumalai 20 Aug '09

20 Aug '09

Hi all, I am in bit of peculiar problem on booting linux kernel on my MPC7448-TSi108 based custom board. I am using u-boot 1.3.4 which was compiled on ELDK- 4.0. when i use bootp command to download the kernel image from the tftp server that was already working with other custom boards the kernel is not getting downloaded but if i am setting it to another environment variable i.e "> set ideboot bootp" and try to boot using "> run ideboot" this time the kernel image file is getting downloaded. kindly give me suggestion on this. i don't have any clue on what is happening ? The host system what ever i used for compilation is also same. Regards, T.

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[U-Boot] [PATCH/RFC] drivers/mmc/mmc.c: change the controller frequency before the card frequency
by Albin Tonnerre 20 Aug '09

20 Aug '09

While rewriting the atmel_mci driver to use the new MMC_GENERIC API (and allow the use of SD/MMC on AT91 in the process), it appeared that switching the card frequency before the controller frequency resulted in the answer from the card never being received. Changing the controller frequency before the controller frequency fixes that. Signed-off-by: Albin Tonnerre <albin.tonnerre(a)free-electrons.com> --- I'm sending this as an RFC, as I only own AT91-based boards. Therefore, I don't know whether doing so breaks the code for other cards or not. Andy, do you see any obvious problem with such a change ? Haavard: I did not find evidence of such a requirement in the AT91SAM9G20 datasheet, is it known behaviour, or do you think I'm doing something wrong that might cause this ? drivers/mmc/mmc.c | 16 ++++++++-------- 1 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index b69ce15..6ff3624 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -717,14 +717,6 @@ int mmc_startup(struct mmc *mmc) if (err) return err; - if (IS_SD(mmc)) - err = sd_change_freq(mmc); - else - err = mmc_change_freq(mmc); - - if (err) - return err; - /* Restrict card's capabilities by what the host can do */ mmc->card_caps &= mmc->host_caps; @@ -786,6 +778,14 @@ int mmc_startup(struct mmc *mmc) mmc_set_clock(mmc, 20000000); } + if (IS_SD(mmc)) + err = sd_change_freq(mmc); + else + err = mmc_change_freq(mmc); + + if (err) + return err; + /* fill in device description */ mmc->block_dev.lun = 0; mmc->block_dev.type = 0; -- 1.6.0.4

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