July 2009 - U-Boot

[U-Boot] [PATCH 1/7] eSPI: add the eSPI register support
by Mingkai Hu 27 Aug '09

27 Aug '09

Signed-off-by: Mingkai Hu <Mingkai.hu(a)freescale.com> --- include/asm-ppc/immap_85xx.h | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index 094fb9c..f3ab750 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -258,6 +258,21 @@ typedef struct ccsr_lbc { } ccsr_lbc_t; /* + * eSPI Registers(0x7000-0x8000) + */ +typedef struct ccsr_espi { + uint mode; /* 0x00 - eSPI mode register */ + uint event; /* 0x04 - eSPI event register */ + uint mask; /* 0x08 - eSPI mask register */ + uint com; /* 0x0c - eSPI command register */ + uint tx; /* 0x10 - eSPI transmit FIFO access register */ + uint rx; /* 0x14 - eSPI receive FIFO access register */ + char res1[8]; /* reserved */ + uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */ + char res2[4048]; /* fill up to 0x1000 */ +} ccsr_espi_t; + +/* * PCI Registers(0x8000-0x9000) */ typedef struct ccsr_pcix { @@ -1682,6 +1697,8 @@ typedef struct ccsr_gur { #define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) #define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) #define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) +#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) +#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) #define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) -- 1.5.4

7 35

[U-Boot] [PATCH] Add some second source legacy flash chips 256x8
by Niklaus Giger 27 Aug '09

27 Aug '09

Signed-off-by: Niklaus Giger <niklaus.giger(a)member.fsf.org> --- We tested some boot flashes as possible second source. As some had ids above 0x7f, we had to implement JEDEC JEP106Z in cfi_flash.c. I now that I just missed the merge window, but the patches are not urgent and I was away for a three week drivers/mtd/cfi_flash.c | 16 +++++++++-- drivers/mtd/jedec_flash.c | 67 +++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 10 ++++++- 3 files changed, 89 insertions(+), 4 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 81ac5d3..4cd0116 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -106,6 +106,8 @@ #define ATM_CMD_SOFTLOCK_START 0x80 #define ATM_CMD_LOCK_SECT 0x40 +#define FLASH_CONTINUATION_CODE 0x7F + #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 #define FLASH_OFFSET_DEVICE_ID2 0x0E @@ -1541,13 +1543,21 @@ static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) static void cmdset_amd_read_jedec_ids(flash_info_t *info) { - flash_write_cmd(info, 0, 0, AMD_CMD_RESET); + ushort bankId = 0; + uchar manuId; + + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); flash_unlock_seq(info, 0); flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); + manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); + /* JEDEC JEP106Z specifies ID codes up to bank 7 */ + while(manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { + bankId += 0x100; + manuId = flash_read_uchar (info, bankId | FLASH_OFFSET_MANUFACTURER_ID); + } + info->manufacturer_id = manuId; switch (info->chipwidth){ case FLASH_CFI_8BIT: diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index e48acec..488bbec 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -68,6 +68,17 @@ #define SST39SF010A 0x00B5 #define SST39SF020A 0x00B6 +/* MXIC */ +#define MX29LV040 0x004F + +/* WINBOND */ +#define W39L040A 0x00D6 + +/* AMIC */ +#define A29L040 0x0092 + +/* EON */ +#define EN29LV040A 0x004F /* * Unlock address sets for AMD command sets. @@ -225,6 +236,62 @@ static const struct amd_flash_info jedec_table[] = { ERASEINFO(0x10000,8), } }, + { + .mfr_id = (u16)MX_MANUFACT, + .dev_id = MX29LV040, + .name = "MXIC MX29LV040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, + { + .mfr_id = (u16)WINB_MANUFACT, + .dev_id = W39L040A, + .name = "WINBOND W39L040A", + .uaddr = { + [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, + { + .mfr_id = (u16)AMIC_MANUFACT, + .dev_id = A29L040, + .name = "AMIC A29L040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, + { + .mfr_id = (u16)EON_MANUFACT, + .dev_id = EN29LV040A, + .name = "EON EN29LV040A", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000,8), + } + }, #endif #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 { diff --git a/include/flash.h b/include/flash.h index b016162..8feca1b 100644 --- a/include/flash.h +++ b/include/flash.h @@ -46,7 +46,7 @@ typedef struct { ushort cmd_reset; /* vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ - uchar manufacturer_id; /* manufacturer id */ + ushort manufacturer_id; /* manufacturer id */ ushort device_id; /* device id */ ushort device_id2; /* extended device id */ ushort ext_addr; /* extended query table address */ @@ -154,6 +154,7 @@ extern flash_info_t *flash_get_info(ulong base); * Device IDs */ +/* Manufacturers inside bank 0 have ids like 0x00xx00xx */ #define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ #define ATM_MANUFACT 0x001F001F /* ATMEL */ @@ -166,6 +167,13 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ +#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ +#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 1 have ids like 0x01xx01xx */ +#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 2 have ids like 0x02xx02xx */ /* Micron Technologies (INTEL compat.) */ #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ -- 1.6.3.3

3 2

[U-Boot] [RESEND][PATCH 3/6]POSEIDON Board Support
by Vivek 26 Aug '09

26 Aug '09

Removed code referring Legacy NAND and did some code cleanup. Signed-off-by: Vivek Dalal <v.dalal(a)samsung.com> --- diff --git a/board/poseidon/Makefile b/board/poseidon/Makefile index e69de29..edbc696 100644 --- a/board/poseidon/Makefile +++ b/board/poseidon/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2009-2010 +# Samsung Electronics, <www.samsung.com> +# Vivek Dalal <v.dalal(a)samsung.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := poseidon.o mem.o sys_info.o +SOBJS := lowlevel_init.o load.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/poseidon/config.mk b/board/poseidon/config.mk index e69de29..f05593c 100644 --- a/board/poseidon/config.mk +++ b/board/poseidon/config.mk @@ -0,0 +1,20 @@ +# +# (C) Copyright 2009-2010 +# Samsung Electronics, <www.samsung.com> +# Vivek Dalal <v.dalal(a)samsung.com> +# +# Poseidon boad uses OMAP2430 (ARM1136) cpu +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) ES2 will be configurable +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x83e80000 + +# Handy to get symbols to debug ROM version. +#TEXT_BASE = 0x0 +#TEXT_BASE = 0x08000000 +#TEXT_BASE = 0x04000000 diff --git a/board/poseidon/load.S b/board/poseidon/load.S index e69de29..d38f66a 100644 --- a/board/poseidon/load.S +++ b/board/poseidon/load.S @@ -0,0 +1,14 @@ +.globl jumpto_addr +.globl jumpto_addr_forsave +jumpto_addr: + stmfd sp!, {r0 - r12, lr} + add lr, pc, #2 + mov pc, r0 + ldmfd sp!, {r0 - r12, pc} + +jumpto_addr_forsave: + stmfd sp!, {r0 - r12, lr} + mov r1, #0 + add lr, pc, #2 + mov pc, r0 + ldmfd sp!, {r0 - r12, pc} diff --git a/board/poseidon/lowlevel_init.S b/board/poseidon/lowlevel_init.S index e69de29..9052f71 100644 --- a/board/poseidon/lowlevel_init.S +++ b/board/poseidon/lowlevel_init.S @@ -0,0 +1,199 @@ +/* + * Board specific setup info + * + * (C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * Derived from OMAPZOOM source(board/omap2430sdp/lowlevel_init.S) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/omap24xx.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> + +_TEXT_BASE: + .word TEXT_BASE /* sdram load addr from config.mk */ + +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_NAND_BOOT) +/************************************************************************** + * cpy_clk_code: relocates clock code into SRAM where its safer to execute + * R1 = SRAM destination address. + *************************************************************************/ +.global cpy_clk_code + cpy_clk_code: + /* Copy DPLL code into SRAM */ + adr r0, go_to_speed /* get addr of clock setting code */ + mov r2, #384 /* r2 size to copy (div by 32 bytes) */ + mov r1, r1 /* r1 <- dest address (passed in) */ + add r2, r2, r0 /* r2 <- source end address */ +next2: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next2 + mov pc, lr /* back to caller */ + +/***************************************************************************** + * go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed + * -executed from SRAM. + * R0 = PRCM_CLKCFG_CTRL - addr of valid reg + * R1 = CM_CLKEN_PLL - addr dpll ctlr reg + * R2 = dpll value + * R3 = CM_IDLEST_CKGEN - addr dpll lock wait + ******************************************************************************/ +.global go_to_speed + go_to_speed: + sub sp, sp, #0x4 /* get some stack space */ + str r4, [sp] /* save r4's value */ + + /* move into fast relock bypass */ + ldr r8, pll_ctl_add + mov r4, #0x2 + str r4, [r8] + ldr r4, pll_stat +block: + ldr r8, [r4] /* wait for bypass to take effect */ + and r8, r8, #0x3 + cmp r8, #0x1 + bne block + + /* set new dpll dividers _after_ in bypass */ + ldr r4, pll_div_add + ldr r8, pll_div_val + str r8, [r4] + + /* now prepare GPMC (flash) for new dpll speed */ + /* flash needs to be stable when we jump back to it */ + ldr r4, flash_cfg3_addr + ldr r8, flash_cfg3_val + str r8, [r4] + ldr r4, flash_cfg4_addr + ldr r8, flash_cfg4_val + str r8, [r4] + ldr r4, flash_cfg5_addr + ldr r8, flash_cfg5_val + str r8, [r4] + ldr r4, flash_cfg1_addr + ldr r8, [r4] + orr r8, r8, #0x3 /* up gpmc divider */ + str r8, [r4] + + /* setup to 2x loop though code. The first loop pre-loads the + * icache, the 2nd commits the prcm config, and locks the dpll + */ + mov r4, #0x1000 /* spin spin spin */ + mov r8, #0x4 /* first pass condition & set registers */ + cmp r8, #0x4 +2: + ldrne r8, [r3] /* DPLL lock check */ + and r8, r8, #0x7 + cmp r8, #0x2 + beq 4f +3: + subeq r8, r8, #0x1 + streq r8, [r0] /* commit dividers (2nd time) */ + nop +lloop1: + sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop1 + mov r4, #0x40000 + cmp r8, #0x1 + nop + streq r2, [r1] /* lock dpll (2nd time) */ + nop +lloop2: + sub r4, r4, #0x1 /* loop currently necessary else bad jumps */ + nop + cmp r4, #0x0 + bne lloop2 + mov r4, #0x40000 + cmp r8, #0x1 + nop + ldreq r8, [r3] /* get lock condition for dpll */ + cmp r8, #0x4 /* first time though? */ + bne 2b + moveq r8, #0x2 /* set to dpll check condition. */ + beq 3b /* if condition not true branch */ +4: + ldr r4, [sp] + add sp, sp, #0x4 /* return stack space */ + mov pc, lr /* back to caller, locked */ + +_go_to_speed: .word go_to_speed + +/* these constants need to be close for PIC code */ +/* The Nor has to be in the Flash Base CS0 for this condition to happen */ +flash_cfg3_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG3) +flash_cfg3_val: + .word STNOR_GPMC_CONFIG3 +flash_cfg4_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG4) +flash_cfg5_val: + .word STNOR_GPMC_CONFIG5 +flash_cfg5_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG5) +flash_cfg4_val: + .word STNOR_GPMC_CONFIG4 +flash_cfg1_addr: + .word (GPMC_CONFIG_CS0 + GPMC_CONFIG1) +pll_ctl_add: + .word CM_CLKEN_PLL +pll_stat: + .word CM_IDLEST_CKGEN +pll_div_add: + .word CM_CLKSEL1_PLL +pll_div_val: + .word DPLL_VAL /* DPLL setting (300MHz default) */ + +#endif + +.globl lowlevel_init +lowlevel_init: + ldr sp, SRAM_STACK + str ip, [sp] /* stash old link register */ + mov ip, lr /* save link reg across call */ + bl s_init /* go setup pll,mux,memory */ + ldr ip, [sp] /* restore save ip */ + mov lr, ip /* restore link reg */ + + /* map interrupt controller */ + ldr r0, VAL_INTH_SETUP + mcr p15, 0, r0, c15, c2, 4 + + /* back to arch calling code */ + mov pc, lr + + /* the literal pools origin */ + .ltorg + +REG_CONTROL_STATUS: + .word CONTROL_STATUS +VAL_INTH_SETUP: + .word PERIFERAL_PORT_BASE +SRAM_STACK: + .word LOW_LEVEL_SRAM_STACK + diff --git a/board/poseidon/mem.c b/board/poseidon/mem.c index e69de29..8f7dc65 100644 --- a/board/poseidon/mem.c +++ b/board/poseidon/mem.c @@ -0,0 +1,226 @@ +/* + *(C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * Derived from OMAPZOOM source(board/omap2430sdp/mem.c) + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or(at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap24xx.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> +#include <asm/arch/clocks.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <environment.h> +#include <command.h> + +/****** DATA STRUCTURES ************/ + +/* Only One NAND allowed on board at a time. +* The GPMC CS Base for the same +*/ + +/* Board CS Organization - Poseidon */ +static const unsigned char chip_sel_sdp[][GPMC_MAX_CS] = { + /* GPMC CS Indices */ + /* S8- 1 2 3 IDX CS0, CS1, CS2 .. CS7 */ + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 0 OFF OFF OFF */ {0, 0, 0, 0, 0, 0, 0, 0}, + /* 7 ON ON ON */ + {PROC_ONENAND, PROC_NAND, PISMO_CS0, 0, 0, DBG_MPDB, 0, PISMO_CS1}, +}; + + +/* Values for each of the chips */ +static u32 gpmc_mpdb[GPMC_MAX_REG] = { + MPDB_GPMC_CONFIG1, + MPDB_GPMC_CONFIG2, + MPDB_GPMC_CONFIG3, + MPDB_GPMC_CONFIG4, + MPDB_GPMC_CONFIG5, + MPDB_GPMC_CONFIG6, 0 +}; +static u32 gpmc_onenand[GPMC_MAX_REG] = { + ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, 0 +}; + + + +/************************************************************ + * sdelay() - simple spin loop. Will be constant time as + * its generally used in 12MHz bypass conditions only. This + * is necessary until timers are accessible. + * + * not inline to increase chances its in cache when called + *************************************************************/ +void sdelay(unsigned long loops) +{ + __asm__ volatile("1 : \n" "subs %0, %1, #1\n" + "bne 1b" : "=r"(loops) : "0"(loops)); +} + +/********************************************************************** + * prcm_init() - inits clocks for PRCM. + * -- called from SRAM, or Flash(using temp SRAM stack). + **********************************************************************/ +void prcm_init(void) +{ + /* Will be Implemented later(Currently IPL code doing imp conf) */ +} + +/*********************************************************************** + * make_cs1_contiguous() - for es2 and above remap cs1 behind cs0 to allow + * command line mem=xyz use all memory with out discontigious support + * compiled in. Could do it at the ATAG, but there really is two banks... + * Called as part of 2nd phase DDR init. + ***********************************************************************/ +void make_cs1_contiguous(void) +{ + u32 size, a_add_low, a_add_high; + + size = get_sdr_cs_size(SDRC_CS0_OSET); + size /= SZ_32M; /* find size to offset CS1 */ + a_add_high = (size & 3) << 8; /* set up low field */ + a_add_low = (size & 0x3C) >> 2; /* set up high field */ + __raw_writel((a_add_high | a_add_low), SDRC_CS_CFG); + +} + +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in gussing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(void) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP24XX_SDRC_CS0; + + __raw_writel(0x0, addr + 0x400); /* clear pos A */ + __raw_writel(pattern, addr); /* pattern to pos B */ + __raw_writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = __raw_readl(addr + 0x400); /* get pos A value */ + val2 = __raw_readl(addr); /* get val2 */ + + if ((val1 != 0) || (val2 != pattern)) { /* see if pos A value changed */ + return 0; + } else + return 1; +} + +/******************************************************** + * sdrc_init() - init the sdrc chip selects CS0 and CS1 + * - early init routines, called from flash or + * SRAM. + *******************************************************/ +void sdrc_init(void) +{ + /* Done in ONENAND IPL */ +} + +/****************************************************************** + * do_sdrc_init(): initialize the SDRAM for use. + *****************************************************************/ +void do_sdrc_init(u32 offset, u32 early) +{ + /*Done in ONENAND IPL for Bank 0.Bank1 conf will be implemented later */ +} + +/***************************************************** + * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode(SDRAM in x32). + * This code can only be executed from SRAM or SDRAM. + *****************************************************/ +void gpmc_init(void) +{ + + u32 mux = 0, mtype, mwidth, gpmc_base = 0; + u32 size = 0x0; + u32 base = 0x0; + unsigned char *config_sel = NULL; + + /* global settings */ + __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */ + __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */ + __raw_writel(0, GPMC_TIMEOUT_CONTROL); /* timeout disable */ + + /* discover bus connection from sysboot */ + mux = BIT9; + mtype = 0x7; + + mwidth = WIDTH_16BIT; + + /* setup cs0 */ + __raw_writel(0, GPMC_CONFIG7_0); /* disable current map */ + sdelay(1000); + /* GPMC5 is always MPDB.. need to know the chip info */ + gpmc_base = GPMC_CONFIG_CS0 + (5 * GPMC_CONFIG_WIDTH); + gpmc_mpdb[0] |= mux; + base = DEBUG_BASE; + size = DBG_MPDB_SIZE; + + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_mpdb[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_mpdb[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_mpdb[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_mpdb[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_mpdb[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_mpdb[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + + sdelay(2000); + config_sel = (unsigned char *)(chip_sel_sdp[mtype]); + gpmc_base = GPMC_CONFIG_CS0 + (0 * GPMC_CONFIG_WIDTH); + base = 0x0; + size = PROC_ONENAND_SIZE; + __raw_writel(0, GPMC_CONFIG7 + gpmc_base); + sdelay(1000); + /* Delay for settling */ + __raw_writel(gpmc_onenand[0], GPMC_CONFIG1 + gpmc_base); + __raw_writel(gpmc_onenand[1], GPMC_CONFIG2 + gpmc_base); + __raw_writel(gpmc_onenand[2], GPMC_CONFIG3 + gpmc_base); + __raw_writel(gpmc_onenand[3], GPMC_CONFIG4 + gpmc_base); + __raw_writel(gpmc_onenand[4], GPMC_CONFIG5 + gpmc_base); + __raw_writel(gpmc_onenand[5], GPMC_CONFIG6 + gpmc_base); + /* Enable the config */ + + __raw_writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), GPMC_CONFIG7 + gpmc_base); + + sdelay(2000); + +} diff --git a/board/poseidon/poseidon.c b/board/poseidon/poseidon.c index e69de29..34fc203 100644 --- a/board/poseidon/poseidon.c +++ b/board/poseidon/poseidon.c @@ -0,0 +1,594 @@ +/* + *(C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * Derived from OMAPZOOM source(board/omap2430sdp/omap2430sdp.c) + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or(at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap24xx.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <asm/arch/mem.h> +#include <i2c.h> +#include <asm/mach-types.h> + +#define write_config_reg(reg, value) \ +do { \ + writeb(value, reg); \ +} while (0) + +#define mask_config_reg(reg, mask) \ +do { \ + char value = readb(reg) & ~(mask); \ + writeb(value, reg); \ +} while (0) + +void wait_for_command_complete(unsigned int wd_base); + +/******************************************************* + * Routine: delay + * Description: spinning delay to use before udelay works + ******************************************************/ +static inline void delay(unsigned long loops) +{ + __asm__ volatile("1 : \n" "subs %0, %1, #1\n" + "bne 1b" : "=r"(loops) : "0"(loops)); +} + +void muxSetupUART1(void) +{ + /* UART1_CTS pin configuration, PIN = D21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_CTS, 0); + /* UART1_RTS pin configuration, PIN = H21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_RTS, 0); + /* UART1_TX pin configuration, PIN = L20, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_TX, 0); + /* UART1_RX pin configuration, PIN = T21, Mode = 0, PUPD=Disabled */ + write_config_reg(CONTROL_PADCONF_UART1_RX, 0); + +} + + + +/***************************************** + * Routine: board_init + * Description: Early hardware init. + *****************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRM, finish GPMC */ + + (*(volatile unsigned int*)0x49002030) |= (0x18<<16); + *(volatile unsigned int*)0x49006200 |= (1<<17); + *(volatile unsigned int*)0x49006210 |= (1<<17); + *(volatile unsigned int*)0x490062A0 |= (1<<17); + __raw_writeb(0x1b, 0x4900211a); + + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_POSEIDON; + /*add of boot parameters*/ + gd->bd->bi_boot_params = (OMAP24XX_SDRC_CS0 + 0x100); + + return 0; + +} + +/***************************************** + * Routine: secure_unlock + * Description: Setup security registers for access + *(GP Device only) + *****************************************/ +void secure_unlock(void) +{ + /* Permission values for registers -Full fledged permissions to all */ +#define UNLOCK_1 0xFFFFFFFF +#define UNLOCK_2 0x00000000 +#define UNLOCK_3 0x0000FFFF + /* Protection Module Register Target APE(PM_RT)*/ + /* REQ_INFO_PERMISSION_1 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x68); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_1, PM_RT_APE_BASE_ADDR_ARM + 0x58); + /* ADDR_MATCH_1 L*/ + __raw_writel(UNLOCK_2, PM_RT_APE_BASE_ADDR_ARM + 0x60); + /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x48); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_GPMC_BASE_ADDR_ARM + 0x58); + /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x48); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_OCM_RAM_BASE_ADDR_ARM + 0x58); + /* ADDR_MATCH_2 L*/ + __raw_writel(UNLOCK_2, PM_OCM_RAM_BASE_ADDR_ARM + 0x80); + + /* IVA Changes */ + /* REQ_INFO_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x48); + /* READ_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x50); + /* WRITE_PERMISSION_0 L*/ + __raw_writel(UNLOCK_3, PM_IVA2_BASE_ADDR_ARM + 0x58); + +} + +/********************************************************** + * Routine: try_unlock_sram() + * Description: If chip is GP type, unlock the SRAM for + * general use. + ***********************************************************/ + +void try_unlock_sram(void) +{ + int mode; + + /* if GP device unlock device SRAM for general use */ + /* secure code breaks for Secure/Emulation device-HS/E/T*/ + mode = get_device_type(); + if (mode == GP_DEVICE) + secure_unlock(); + return; + +} + +/********************************************************** + * Routine: s_init + * Description: Does early system init of muxing and clocks. + * - Called path is with sram stack. + **********************************************************/ +void s_init(void) +{ + int in_sdram = running_in_sdram(); + /* u32 rev = get_cpu_rev(); unused as of now.. */ + + watchdog_init(); + try_unlock_sram();/* Do SRAM availability first*/ + + set_muxconf_regs(); + delay(100); + + if (!in_sdram) + prcm_init(); + + peripheral_enable(); + icache_enable(); + if (!in_sdram) + sdrc_init(); + +} + +/******************************************************* + * Routine: misc_init_r + * Description: Init ethernet(done here so udelay works) + ********************************************************/ +int misc_init_r(void) +{ + ether_init(); /* better done here so timers are init'ed */ + return 0; + +} + +/**************************************** + * Routine: watchdog_init + * Description: Shut down watch dogs + *****************************************/ +void watchdog_init(void) +{ + /* There are 4 watch dogs. 1 secure, and 3 general purpose. + * The ROM takes care of the secure one. Of the 3 GP ones, + * 1 can reset us directly, the other 2 only generate MPU interrupts + */ + __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR); + wait_for_command_complete(WD2_BASE); + __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR); + +} + +/****************************************************** + * Routine: wait_for_command_complete + * Description: Wait for posting to finish on watchdog + ******************************************************/ +void wait_for_command_complete(unsigned int wd_base) +{ + int pending = 1; + do { + pending = __raw_readl(wd_base + WWPS); + } while (pending); + +} + +/******************************************************************* + * Routine:ether_init + * Description: take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + ******************************************************************/ +void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + /* u32 rev = get_cpu_rev(); unused as of now */ + __raw_writew(0x0, LAN_RESET_REGISTER); + do { + __raw_writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + __raw_writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto h4reset_err_out; + --cnt; + } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + *((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01; + udelay(1000); + +h4reset_err_out: + return; +#endif + +} + +/********************************************** + * Routine: dram_init + * Description: sets uboots idea of sdram size + **********************************************/ +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + u32 mtype, btype; +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + u8 data; +#endif +#define NOT_EARLY 0 + +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + select_bus(1, CONFIG_SYS_I2C_SPEED); /* select bus with T2 on it */ +#endif + mtype = get_mem_type(); + display_board_info(btype); + + if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) + /* init other chip select and map CS1 right after CS0 */ + do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); + + size0 = get_sdr_cs_size(SDRC_CS0_OSET); + size1 = get_sdr_cs_size(SDRC_CS1_OSET); + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; + gd->bd->bi_dram[1].size = size1; + + return 0; + +} + +#define MUX_VAL(OFFSET,VALUE)\ + __raw_writeb((VALUE), OMAP24XX_CTRL_BASE + (OFFSET)); + +#ifdef CONFIG_2430 +#define MUX_DEFAULT()\ +/* SDRC */\ +MUX_VAL(0x0054, 0x1B) /* sdrc_a14 - EN, HI, 3, ->gpio_0 */\ +MUX_VAL(0x0055, 0x00) /* sdrc_a13 - EN, HI, 3, ->gpio_1 */\ +MUX_VAL(0x0056, 0x00) /* sdrc_a12 - Dis, 0 */\ +MUX_VAL(0x0046, 0x00) /* sdrc_ncs1 - Dis, 0 */\ +MUX_VAL(0x0048, 0x00) /* sdrc_cke1 - Dis, 0 */\ +/* GPMC */\ +MUX_VAL(0x0030, 0x00) /* gpmc_clk - Dis, 0 */\ +MUX_VAL(0x0032, 0x00) /* gpmc_ncs1- Dis, 0 */\ +MUX_VAL(0x0033, 0x00) /* gpmc_ncs2- Dis, 0 */\ +MUX_VAL(0x0034, 0x03) /* gpmc_ncs3- Dis, 3, ->gpio_24 */\ +MUX_VAL(0x0035, 0x03) /* gpmc_ncs4- Dis, 3, ->gpio_25 */\ +MUX_VAL(0x0036, 0x00) /* gpmc_ncs5- Dis, 0 */\ +MUX_VAL(0x0037, 0x03) /* gpmc_ncs6- Dis, 3, ->gpio_27 */\ +MUX_VAL(0x0038, 0x00) /* gpmc_ncs7- Dis, 0 */\ +MUX_VAL(0x0040, 0x18) /* gpmc_wait1- Dis, 0 */\ +MUX_VAL(0x0041, 0x18) /* gpmc_wait2- Dis, 0 */\ +MUX_VAL(0x0042, 0x1B) /* gpmc_wait3- EN, HI, 3, ->gpio_35 */\ +MUX_VAL(0x0085, 0x1B) /* gpmc_a10- EN, HI, 3, ->gpio_3 */\ +/* GPMC mux for NAND access */\ +MUX_VAL(0x0086, 0x18) /* gpmc_a9 - EN, HI, 0*/\ +MUX_VAL(0x0087, 0x18) /* gpmc_a8 - EN, HI, 0*/\ +MUX_VAL(0x0088, 0x18) /* gpmc_a7 - EN, HI, 0*/\ +MUX_VAL(0x0089, 0x18) /* gpmc_a6 - EN, HI, 0*/\ +MUX_VAL(0x008A, 0x18) /* gpmc_a5 - EN, HI, 0*/\ +MUX_VAL(0x008B, 0x18) /* gpmc_a4 - EN, HI, 0*/\ +MUX_VAL(0x008C, 0x18) /* gpmc_a3 - EN, HI, 0*/\ +MUX_VAL(0x008D, 0x18) /* gpmc_a2 - EN, HI, 0*/\ +MUX_VAL(0x008E, 0x18) /* gpmc_a1 - EN, HI, 0*/\ +MUX_VAL(0x008F, 0x18) /* gpmc_d15 - EN,HI, 0*/\ +MUX_VAL(0x0090, 0x18) /* gpmc_d14 - EN, HI, 0*/\ +MUX_VAL(0x0091, 0x18) /* gpmc_d13 - EN, HI, 0*/\ +MUX_VAL(0x0092, 0x18) /* gpmc_d12 - EN, HI, 0*/\ +MUX_VAL(0x0093, 0x18) /* gpmc_d11 - EN, HI, 0*/\ +MUX_VAL(0x0094, 0x18) /* gpmc_d10 - EN, HI, 0*/\ +MUX_VAL(0x0095, 0x18) /* gpmc_d9 - EN, HI, 0 */\ +MUX_VAL(0x0096, 0x18) /* gpmc_d8 - EN, HI, 0*/\ +/* DSS */\ +MUX_VAL(0x009F, 0x00) /* dss_data0- Dis, 0 */\ +MUX_VAL(0x00A0, 0x00) /* dss_data1- Dis, 0 */\ +MUX_VAL(0x00A1, 0x00) /* dss_data2- Dis, 0 */\ +MUX_VAL(0x00A2, 0x00) /* dss_data3- Dis, 0 */\ +MUX_VAL(0x00A3, 0x00) /* dss_data4- Dis, 0 */\ +MUX_VAL(0x00A4, 0x00) /* dss_data5- Dis, 0 */\ +MUX_VAL(0x00A5, 0x00) /* dss_data6- Dis, 0 */\ +MUX_VAL(0x00A6, 0x00) /* dss_data7- Dis, 0 */\ +MUX_VAL(0x00A7, 0x00) /* dss_data8- Dis, 0 */\ +MUX_VAL(0x00A8, 0x00) /* dss_data9- Dis, 0 */\ +MUX_VAL(0x00A9, 0x00) /* dss_data10- Dis, 0 */\ +MUX_VAL(0x00AA, 0x00) /* dss_data11- Dis, 0 */\ +MUX_VAL(0x00AB, 0x00) /* dss_data12- Dis, 0 */\ +MUX_VAL(0x00AC, 0x00) /* dss_data13- Dis, 0 */\ +MUX_VAL(0x00AD, 0x00) /* dss_data14- Dis, 0 */\ +MUX_VAL(0x00AE, 0x00) /* dss_data15- Dis, 0 */\ +MUX_VAL(0x00AF, 0x00) /* dss_data16- Dis, 0 */\ +MUX_VAL(0x00B0, 0x00) /* dss_data17- Dis, 0 */\ +MUX_VAL(0x00B9, 0x00) /* dss_hsync- Dis, 0 */\ +MUX_VAL(0x00BA, 0x00) /* dss_acbias- Dis, 0 */\ +MUX_VAL(0x00B1, 0x1B) /* uart1_cts- EN, HI, 3, ->gpio_32 */\ +MUX_VAL(0x00B2, 0x1B) /* uart1_rts- EN, HI, 3, ->gpio_8 */\ +MUX_VAL(0x00B3, 0x1B) /* uart1_tx- EN, HI, 3, ->gpio_9 */\ +MUX_VAL(0x00B4, 0x1B) /* uart1_rx- EN, HI, 3, ->gpio_10 */\ +MUX_VAL(0x00B5, 0x1B) /* mcbsp2_dr- EN, HI, 3, ->gpio_11 */\ +MUX_VAL(0x00B6, 0x1B) /* mcbsp2_clkx- EN, HI, 3, ->gpio_12 */\ +MUX_VAL(0x00B7, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +MUX_VAL(0x00B8, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +MUX_VAL(0x00B9, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +MUX_VAL(0x00BA, 0x0) /* CONTROL_PADCONF_DSS_PCLK*/\ +/* CONTROL */\ +MUX_VAL(0x00BB, 0x00) /* sys_nrespwron- Dis, 0 */\ +MUX_VAL(0x00BC, 0x00) /* sys_nreswarm- Dis, 0 */\ +MUX_VAL(0x00BD, 0x18) /* sys_nirq0- EN, HI, 0 */\ +/*MUX_VAL(0x00BD, 0x1B)*/ /* sys_nirq0- EN, HI, 3, ->gpio_56 */\ +MUX_VAL(0x00BE, 0x18) /* sys_nirq1- EN, HI, 0 */\ +MUX_VAL(0x00C7, 0x00) /* gpio_132- Dis, 0, ->gpio132 */\ +MUX_VAL(0x00CB, 0x00) /* gpio_133- Dis, 0, ->gpio133 */\ +MUX_VAL(0x00C9, 0x18) /* sys_clkout- Dis, 0 */\ +/*MUX_VAL(0x00C9, 0x1B)*/ /* sys_clkout- EN, HI, 3, ->gpio_111 */\ +MUX_VAL(0x00CC, 0x18) /* jtag_emu1- EN, HI, 0 */\ +MUX_VAL(0x00CD, 0x18) /* jtag_emu0- EN, HI, 0 */\ +/* CAMERA */\ +MUX_VAL(0x00DD, 0x02) /* cam_d0- Dis, 2, sti_dout */\ +MUX_VAL(0x00DC, 0x02) /* cam_d1- Dis, 2, sti_din */\ +MUX_VAL(0x00DB, 0x1B) /* cam_d2- EN, HI, 3, ->gpio_129 */\ +MUX_VAL(0x00DA, 0x1B) /* cam_d3- EN, HI, 3, ->gpio_128 */\ +MUX_VAL(0x00D9, 0x00) /* cam_d4- Dis, 0 */\ +MUX_VAL(0x00D8, 0x00) /* cam_d5- Dis, 0 */\ +MUX_VAL(0x00D7, 0x00) /* cam_d6- Dis, 0 */\ +MUX_VAL(0x00D6, 0x00) /* cam_d7- Dis, 0 */\ +MUX_VAL(0x00D5, 0x00) /* cam_d8- Dis, 0 */\ +MUX_VAL(0x00D4, 0x00) /* cam_d9- Dis, 0 */\ +MUX_VAL(0x00E3, 0x00) /* cam_d10- Dis, 0 */\ +MUX_VAL(0x00E2, 0x00) /* cam_d11- Dis, 0 */\ +MUX_VAL(0x00DE, 0x00) /* cam_hs- Dis, 0 */\ +MUX_VAL(0x00DF, 0x00) /* cam_vs- Dis, 0 */\ +MUX_VAL(0x00E0, 0x00) /* cam_lclk- Dis, 0 */\ +MUX_VAL(0x00E1, 0x00) /* cam_xclk- Dis, 0 */\ +MUX_VAL(0x00E4, 0x01) /* gpio_134- Dis, 1, ->ccp_datn */\ +MUX_VAL(0x00E5, 0x01) /* gpio_135- Dis, 1, ->ccp_datp */\ +MUX_VAL(0x00E6, 0x01) /* gpio_136- Dis, 1, ->ccp_clkn */\ +MUX_VAL(0x00E7, 0x01) /* gpio_137- Dis, 1, ->ccp_clkp */\ +MUX_VAL(0x00E8, 0x01) /* gpio_138- Dis, 1, ->spi3_clk */\ +MUX_VAL(0x00E9, 0x01) /* gpio_139- Dis, 1, ->spi3_cs0 */\ +MUX_VAL(0x00EA, 0x01) /* gpio_140- Dis, 1, ->spi3_simo */\ +MUX_VAL(0x00EB, 0x01) /* gpio_141- Dis, 1, ->spi3_somi */\ +MUX_VAL(0x00EC, 0x18) /* gpio_142- EN, HI, 0, ->gpio_142 */\ +MUX_VAL(0x00ED, 0x18) /* gpio_154- EN, HI, 0, ->gpio_154 */\ +MUX_VAL(0x00EE, 0x18) /* gpio_148- EN, HI, 0, ->gpio_148 */\ +MUX_VAL(0x00EF, 0x18) /* gpio_149- EN, HI, 0, ->gpio_149 */\ +MUX_VAL(0x00F0, 0x18) /* gpio_150- EN, HI, 0, ->gpio_150 */\ +MUX_VAL(0x00F1, 0x18) /* gpio_152- EN, HI, 0, ->gpio_152 */\ +MUX_VAL(0x00F2, 0x18) /* gpio_153- EN, HI, 0, ->gpio_153 */\ +/* MMC1 */\ +MUX_VAL(0x00F3, 0x00) /* mmc1_clko- Dis, 0 */\ +MUX_VAL(0x00F4, 0x18) /* mmc1_cmd- EN, HI, 0 */\ +MUX_VAL(0x00F5, 0x18) /* mmc1_dat0- EN, HI, 0 */\ +MUX_VAL(0x00F6, 0x18) /* mmc1_dat1- EN, HI, 0 */\ +MUX_VAL(0x00F7, 0x18) /* mmc1_dat2- EN, HI, 0 */\ +MUX_VAL(0x00F8, 0x18) /* mmc1_dat3- EN, HI, 0 */\ +/* MMC2 */\ +MUX_VAL(0x00F9, 0x00) /* mmc2_clko- Dis, 0 */\ +MUX_VAL(0x00FA, 0x18) /* mmc2_cmd- EN, HI, 0 */\ +MUX_VAL(0x00FB, 0x18) /* mmc2_dat0- EN, HI, 0 */\ +MUX_VAL(0x00FC, 0x18) /* mmc2_dat1- EN, HI, 0 */\ +MUX_VAL(0x00FD, 0x18) /* mmc2_dat2- EN, HI, 0 */\ +MUX_VAL(0x00FE, 0x18) /* mmc2_dat3- EN, HI, 0 */\ +/* UART2 */\ +MUX_VAL(0x00FF, 0x00) /* uart2_cts- Dis, 0 */\ +MUX_VAL(0x0100, 0x1B) /* uart2_rts- Dis, 0 gpio-68 by jhchoi*/\ +MUX_VAL(0x0101, 0x00) /* uart2_tx- Dis, 0 */\ +MUX_VAL(0x0102, 0x1B) /* uart2_rx- Dis, 0 */\ +/* MCBSP3 */\ +MUX_VAL(0x0103, 0x00) /* mcbsp3_clkx- Dis, 0 */\ +MUX_VAL(0x0104, 0x00) /* mcbsp3_fsx- Dis, 0 */\ +MUX_VAL(0x0105, 0x00) /* mcbsp3_dr- Dis, 0 */\ +MUX_VAL(0x0106, 0x00) /* mcbsp3_dx- Dis, 0 */\ +/* SSI1 */\ +MUX_VAL(0x0107, 0x01) /* ssi1_dat_tx- Dis, 1, ->uart1_tx */\ +MUX_VAL(0x0108, 0x01) /* ssi1_flag_tx- Dis, 1, ->uart1_rts */\ +MUX_VAL(0x0109, 0x01) /* ssi1_rdy_tx- Dis, 1, ->uart1_cts */\ +MUX_VAL(0x010A, 0x01) /* ssi1_dat_rx- Dis, 1, ->uart1_rx */\ +MUX_VAL(0x010B, 0x01) /* gpio_63- Dis, 1, ->mcbsp4_clkx */\ +MUX_VAL(0x010C, 0x01) /* ssi1_flag_rx- Dis, 1, ->mcbsp4_dr */\ +MUX_VAL(0x010D, 0x01) /* ssi1_rdy_rx- Dis, 1, ->mcbsp4_dx */\ +MUX_VAL(0x010E, 0x01) /* ssi1_wake- Dis, 1, ->mcbsp4_fsx */\ +/* SPI1 */\ +MUX_VAL(0x010F, 0x00) /* spi1_clk- Dis, 0 */\ +MUX_VAL(0x0110, 0x00) /* spi1_simo- Dis, 0 */\ +MUX_VAL(0x0111, 0x00) /* spi1_somi- Dis, 0 */\ +MUX_VAL(0x0112, 0x00) /* spi1_cs0- Dis, 0 */\ +MUX_VAL(0x0113, 0x00) /* spi1_cs1- Dis, 0 */\ +MUX_VAL(0x0114, 0x00) /* spi1_cs2- Dis, 0 */\ +MUX_VAL(0x0115, 0x00) /* spi1_cs3- Dis, 0 */\ +/* SPI2 */\ +MUX_VAL(0x0116, 0x1B) /* spi2_clk- EN, HI, 3, ->gpio_88 */\ +MUX_VAL(0x0117, 0x1B) /* spi2_simo- EN, HI, 3, ->gpio_89 */\ +MUX_VAL(0x0118, 0x1B) /* spi2_somi- EN, HI, 3, ->gpio_90 */\ +MUX_VAL(0x0119, 0x1B) /* spi2_cs0- EN, HI, 3, ->gpio_91 */\ +/* MCBSP1 */\ +MUX_VAL(0x011A, 0x00) /* mcbsp1_clkr- Dis, 0 */\ +MUX_VAL(0x011B, 0x00) /* mcbsp1_fsr- Dis, 0 */\ +MUX_VAL(0x011C, 0x00) /* mcbsp1_dx- Dis, 0 */\ +MUX_VAL(0x011D, 0x0B) /* mcbsp1_dr- Dis, 0 */\ +MUX_VAL(0x011E, 0x00) /* mcbsp1_clks- Dis, 0 */\ +MUX_VAL(0x011F, 0x00) /* mcbsp1_fsx- Dis, 0 */\ +MUX_VAL(0x0120, 0x00) /* mcbsp1_clkx- Dis, 0 */\ +/* HDQ */\ +MUX_VAL(0x0125, 0x00) /* hdq_sio- Dis, 0 */\ +/* UART3 */\ +MUX_VAL(0x0126, 0x00) /* uart3_cts_rctx- Dis, 0 */\ +MUX_VAL(0x0127, 0x00) /* uart3_rts_sd- Dis, 0 */\ +MUX_VAL(0x0128, 0x00) /* uart3_tx_irtx- Dis, 0 */\ +MUX_VAL(0x0129, 0x00) /* uart3_rx_irrx- Dis, 0 */\ +/* OTHERS */\ +MUX_VAL(0x012B, 0x1B) /* gpio_78- EN, HI, 3, ->gpio_78 */\ +MUX_VAL(0x012C, 0x01) /* gpio_79- Dis, 1, ->secure_indicator */\ +MUX_VAL(0x012D, 0x1B) /* gpio_80- EN, HI, 3, ->gpio_80 */\ +/* MCBSP2 */\ +MUX_VAL(0x012E, 0x01) /* gpio_113- Dis, 1, ->mcbsp2_clkx */\ +MUX_VAL(0x012F, 0x01) /* gpio_114- Dis, 1, ->mcbsp2_fsx */\ +MUX_VAL(0x0130, 0x01) /* gpio_115- Dis, 1, ->mcbsp2_dr */\ +MUX_VAL(0x0131, 0x01) /* gpio_116- Dis, 1, ->mcbsp2_dx */\ +/* GPIO7-AUDIOENVDD */\ +MUX_VAL(0x012A, 0x18) /* gpio_7- EN, HI, 3, ->gpio_7 */\ + +#else +/* For all other platforms */ +#define MUX_DEFAULT()\ + /* SDRC */\ +MUX_VAL(0x0054, 0x08) /* sdrc_a14 - EN, LO, 0 */\ +MUX_VAL(0x0055, 0x08) /* sdrc_a13 - EN, LO, 0 */\ +MUX_VAL(0x0056, 0x08) /* sdrc_a12 - EN, LO, 0 */\ +MUX_VAL(0x0045, 0x18) /* sdrc_ncs1 - EN, HI, 0 */\ +MUX_VAL(0x0046, 0x18) /* sdrc_ncs2 - EN, HI, 0 */\ +/* GPMC */\ +MUX_VAL(0x0030, 0x08) /* gpmc_clk - EN, LO, 0 */\ +MUX_VAL(0x0032, 0x18) /* gpmc_ncs1- EN, HI, 0 */\ +MUX_VAL(0x0033, 0x18) /* gpmc_ncs2- EN, HI, 0 */\ +MUX_VAL(0x0034, 0x18) /* gpmc_ncs3- EN, HI, 0 */\ +/* UART1 */\ +MUX_VAL(0x00B1, 0x18) /* uart1_cts- EN, HI, 0 */\ +MUX_VAL(0x00B2, 0x18) /* uart1_rts- EN, HI, 0 */\ +MUX_VAL(0x00B3, 0x18) /* uart1_tx- EN, HI, 0 */\ +MUX_VAL(0x00B4, 0x18) /* uart1_rx- EN, HI, 0 */\ +/* UART2 */\ +MUX_VAL(0x00FF, 0x18) /* uart2_cts- EN, HI, 0 */\ +MUX_VAL(0x0100, 0x18) /* uart2_rts- EN, HI, 0 */\ +MUX_VAL(0x0101, 0x18) /* uart2_tx- EN, HI, 0 */\ +MUX_VAL(0x0102, 0x18) /* uart2_rx- EN, HI, 0 */\ +/* UART3 */\ +MUX_VAL(0x0126, 0x18) /* uart3_cts_rctx- EN, HI, 0 */\ +MUX_VAL(0x0127, 0x18) /* uart3_rts_sd- EN, HI, 0 */\ +MUX_VAL(0x0127, 0x18) /* uart3_tx_irtx- EN, HI, 0 */\ +MUX_VAL(0x0127, 0x18) /* uart3_rx_irrx- EN, HI, 0 */\ +/* I2C1 */\ +MUX_VAL(0x0111, 0x00) /* i2c1_scl - DIS, NA, 0 */\ +MUX_VAL(0x0112, 0x00) /* i2c1_sda - DIS, NA, 0 */\ + +#endif /* End of Mux Mapping */ + +/********************************************************** + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers + * specific to the hardware. Many pins need + * to be moved from protect to primary mode. + *********************************************************/ +void set_muxconf_regs(void) +{ + u32 cpu; + cpu = get_cpu_type(); + /*Incase we have to handle multiple processors such as 2430 and 2430C */ + if (cpu == CPU_2430) { + MUX_DEFAULT(); + } else + return; + +} + +/***************************************************************** + * Routine: peripheral_enable + * Description: Enable the clks & power for perifs(GPT2, UART1,...) + ******************************************************************/ +void peripheral_enable(void) +{ + unsigned int v, if_clks1 = 0, func_clks1 = 0; + unsigned int if_clks2 = 0, func_clks2 = 0; + /* ALERT STATUS 10000 */ + /* Enable GP2 timer. */ + if_clks1 |= BIT4; + func_clks1 |= BIT4; + v = __raw_readl(CM_CLKSEL2_CORE) | 0x4;/* Sys_clk input OMAP24XX_GPT2 */ + __raw_writel(v, CM_CLKSEL2_CORE); + __raw_writel(0x1, CM_CLKSEL_WKUP); + +#ifdef CONFIG_SYS_NS16550 + /* Enable UART1 clock */ + func_clks1 |= BIT21; + if_clks1 |= BIT21; +#endif +#ifdef CONFIG_DRIVER_OMAP24XX_I2C + /* 2430 requires only the hs clock */ + func_clks2 |= BIT20|BIT19; /* i2c1 and 2 96 meg clock input */ + if_clks1 |= BIT20|BIT19; +#endif + + v = __raw_readl(CM_ICLKEN1_CORE) | if_clks1;/* Interface clocks on */ + __raw_writel(v, CM_ICLKEN1_CORE); + v = __raw_readl(CM_ICLKEN2_CORE) | if_clks2;/* Interface clocks on */ + __raw_writel(v, CM_ICLKEN2_CORE); + v = __raw_readl(CM_FCLKEN1_CORE) | func_clks1;/* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN1_CORE); + v = __raw_readl(CM_FCLKEN2_CORE) | func_clks2;/* Functional Clocks on */ + __raw_writel(v, CM_FCLKEN2_CORE); + delay(1000); +} + +/***************************************************************************** + * Routine: update_mux() + * Description: Update balls which are different beween boards. All should be + * updated to match functionaly. However, I'm only updating ones + * which I'll be using for now. When power comes into play they + * all need updating. + *****************************************************************************/ +void update_mux(u32 btype, u32 mtype) +{ + /* NOTHING as of now... */ +} diff --git a/board/poseidon/sys_info.c b/board/poseidon/sys_info.c index e69de29..c64f442 100644 --- a/board/poseidon/sys_info.c +++ b/board/poseidon/sys_info.c @@ -0,0 +1,380 @@ +/* + *(C) Copyright 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or(at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/omap24xx.h> +#include <asm/io.h> +#include <asm/arch/bits.h> +#include <asm/arch/mem.h> /* get mem tables */ +#include <asm/arch/sys_proto.h> +#include <asm/arch/sys_info.h> +#include <i2c.h> + +/**************************************************************************** + * check_fpga_revision number: the rev number should be a or b 0xA203/5 + * variant did not have it, but the B101 variant has EEPROM update facility + ***************************************************************************/ +static inline u16 check_fpga_rev(void) +{ + return __raw_readw(FPGA_REV_REGISTER); +} + +/**************************************************************************** + * check_eeprom_avail: Check FPGA Availability + * OnBoard DEBUG FPGA registers need to be ready for us to proceed + * Required to retrieve the bootmode also. + ***************************************************************************/ +int check_eeprom_avail(u32 offset) +{ + return 0; +} + +/************************************************************************** + * get_cpu_type() - Read the FPGA Debug registers and provide the DIP switch + * settings + * 1 is on + * 0 is off + * Will return Index of type of gpmc + ***************************************************************************/ +u32 get_gpmc0_type(void) +{ + u8 cs; + if (!check_fpga_rev()) + /* we dont have an DEBUG FPGA??? */ + /* Depend on #defines!! default to strata boot return param */ + return 0x0; + cs = (u8) __raw_readw(DIP_SWITCH_INPUT_REG2); + /* The bits are inverted- S8 0-2 define the CS0 select */ + return (~cs) & 0x07; +} + +/************************************************************************** + * get_cpu_type() - low level get cpu type + * - no C globals yet. + * - just looking to say if this is a 2422 or 2420 or ... + * - to start with we will look at switch settings.. + * - 2422 id's same as 2420 for ES1 will rely on H4 board characteristics + * (mux for 2420, non-mux for 2422). + ***************************************************************************/ +u32 get_cpu_type(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v &= CPU_24XX_ID_MASK; + + if (v == CPU_2430_CHIPID) { + return CPU_2430; + } else + return -1; /* don't know,return invalid val */ +} + +/****************************************** + * get_cpu_rev(void) - extract version info + ******************************************/ +u32 get_cpu_rev(void) +{ + u32 v; + v = __raw_readl(TAP_IDCODE_REG); + v = v >> 28; + return v + 1; +} + +/**************************************************** + * is_mem_sdr() - return 1 if mem type in use is SDR + ****************************************************/ +u32 is_mem_sdr(void) +{ + volatile u32 *burst = (volatile u32 *)(SDRC_MR_0 + SDRC_CS0_OSET); + if (*burst == H4_2420_SDRC_MR_0_SDR) + return 1; + return 0; +} + +/*********************************************************** + * get_mem_type() - identify type of mDDR part used. + * 2422 uses stacked DDR, 2 parts CS0/CS1. + * 2420 may have 1 or 2, no good way to know...only init 1... + * when eeprom data is up we can select 1 more. + *************************************************************/ +u32 get_mem_type(void) +{ + return DDR_DISCRETE; +} + +/*********************************************************************** + * get_cs0_size() - get size of chip select 0/1 + ************************************************************************/ +u32 get_sdr_cs_size(u32 offset) +{ + u32 size; + /* get ram size field */ + size = __raw_readl(SDRC_MCFG_0 + offset) >> 8; + size &= 0x3FF; /* remove unwanted bits */ + size *= SZ_2M; /* find size in MB */ + return size; +} + +/****************************************************************** + * get_sysboot_value() - get init word settings(dip switch on h4) + ******************************************************************/ +inline u32 get_sysboot_value(void) +{ + return 0x00000FFF & __raw_readl(CONTROL_STATUS); +} + +/*************************************************************************** + * get_gpmc0_base() - Return current address hardware will be + * fetching from. The below effectively gives what is correct, its a bit + * mis-leading compared to the TRM. For the most general case the mask + * needs to be also taken into account this does work in practice. + * - for u-boot we currently map: + * -- 0 to nothing, + * -- 4 to flash + * -- 8 to enent + * -- c to wifi + ****************************************************************************/ +u32 get_gpmc0_base(void) +{ + u32 b; + + b = __raw_readl(GPMC_CONFIG_CS0 + GPMC_CONFIG7); + b &= 0x1F; /* keep base [5:0] */ + b = b << 24; /* ret 0x0b000000 */ + return b; +} + +/******************************************************************* + * get_gpmc0_width() - See if bus is in x8 or x16(mainly for nand) + *******************************************************************/ +u32 get_gpmc0_width(void) +{ + u32 width; + width = get_sysboot_value(); + if ((width & 0xF) == (BIT3 | BIT2)) { + return WIDTH_8BIT; + } else + return WIDTH_16BIT; + +} + +/********************************************************************* + * wait_on_value() - common routine to allow waiting for changes in + * volatile regs. + *********************************************************************/ +u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound) +{ + u32 i = 0, val; + do { + ++i; + val = __raw_readl(read_addr) & read_bit_mask; + if (val == match_value) + return 1; + if (i == bound) + return 0; + } while (1); +} + +/***************************************************************** + * is_gpmc_muxed() - tells if address/data lines are multiplexed + *****************************************************************/ +u32 is_gpmc_muxed(void) +{ + u32 mux; + mux = get_sysboot_value(); + if ((mux & (BIT0 | BIT1 | BIT2 | BIT3)) == (BIT0 | BIT2 | BIT3)) + return GPMC_MUXED; /* NAND Boot mode */ + if (mux & BIT1) {/* if mux'ed */ + return GPMC_MUXED; + } else + return GPMC_NONMUXED; +} + +/************************************************************************* + * get_board_rev () - setup to pass board revision information + *************************************************************************/ +u32 get_board_rev(void) +{ + /* Default Value as per now Poseidon Board have only one Revision */ + return 0x01; +} + +/********************************************************************* + * display_board_info() - print banner with board info. + *********************************************************************/ +void display_board_info(u32 btype) +{ + char *bootmode[] = { + "ONND", + "SIB1", + "SIB0", + "NAND", + "SIB1", + "SIB0", + "NOR", + "OneNAND", + }; + u32 brev = get_board_rev(); + char cpu_2430s[] = "2430C"; + char db_ver[] = "0.0"; /* board type */ + char mem_sdr[] = "mSDR"; /* memory type */ + char mem_ddr[] = "mDDR"; + char t_tst[] = "TST"; /* security level */ + char t_emu[] = "EMU"; + char t_hs[] = "HS"; + char t_gp[] = "GP"; + char unk[] = "?"; + char t_poseidon[] = "POSEIDON"; +#ifdef CONFIG_LED_INFO + char led_string[CONFIG_LED_LEN] = { 0 }; +#endif + +#if defined(PRCM_CONFIG_I) + char prcm[] = "I"; +#elif defined(PRCM_CONFIG_II) + char prcm[] = "II"; +#endif + char *cpu_s, *db_s, *mem_s, *sec_s, *sdp; + u32 cpu, rev, sec; + + rev = get_cpu_rev(); + cpu = get_cpu_type(); + sec = get_device_type(); + + if (is_mem_sdr()) { + mem_s = mem_sdr; + } else + mem_s = mem_ddr; + + cpu_s = cpu_2430s; + + db_s = db_ver; + db_s[0] += (brev >> 4) & 0xF; + db_s[2] += brev & 0xF; + + switch (sec) { + case TST_DEVICE: + sec_s = t_tst; + break; + case EMU_DEVICE: + sec_s = t_emu; + break; + case HS_DEVICE: + sec_s = t_hs; + break; + case GP_DEVICE: + sec_s = t_gp; + break; + default: + sec_s = unk; + } + + sdp = t_poseidon; + + printf("OMAP%s-%s revision %d, PRCM %s\n", cpu_s, sec_s, rev, prcm); + printf("SAMSUNG %s %s Version + %s(Boot %s)\n", sdp, db_s, + mem_s, bootmode[get_gpmc0_type()]); +#ifdef CONFIG_LED_INFO + /* Format: 0123456789ABCDEF + * 2430C GP#5A NAND + */ + sprintf(led_string, "%5s%3s%3s %4s", cpu_s, sec_s, prcm, + bootmode[get_gpmc0_type()]); + /* reuse sec */ + for (sec = 0; sec < CONFIG_LED_LEN; sec += 2) { + /* invert byte loc */ + u16 val = led_string[sec] << 8; + val |= led_string[sec + 1]; + __raw_writew(val, LED_REGISTER + sec); + } +#endif + +} + +/******************************************************** + * get_base(); get upper addr of current execution + *******************************************************/ +u32 get_base(void) +{ + u32 val; + __asm__ __volatile__("mov %0, pc \n" : "=r"(val) : : "memory"); + val &= 0xF0000000; + val >>= 28; + return val; +} + +/******************************************************** + * running_in_flash() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_flash(void) +{ + if (get_base() < 4) + return 1; /* in flash */ + return 0; /* running in SRAM or SDRAM */ +} + +/******************************************************** + * running_in_sram() - tell if currently running in + * sram. + *******************************************************/ +u32 running_in_sram(void) +{ + if (get_base() == 4) + return 1; /* in SRAM */ + return 0; /* running in FLASH or SDRAM */ +} + +/******************************************************** + * running_in_sdram() - tell if currently running in + * flash. + *******************************************************/ +u32 running_in_sdram(void) +{ + if (get_base() > 4) + return 1; /* in sdram */ + return 0; /* running in SRAM or FLASH */ +} + +/************************************************************* + * running_from_internal_boot() - am I boot through mask rom. + *************************************************************/ +u32 running_from_internal_boot(void) +{ + u32 v; + + v = get_sysboot_value() & (BIT2 | BIT1 | BIT0); + /* external boot settings bit1 == bit2 */ + if (((v & BIT1) && (v & BIT2)) || (!(v & BIT1) && !(v & BIT2))) { + v = 0; + } else /* all other defined combos are internal */ + v = 1; + return v; +} + +/************************************************************* + * get_device_type(): tell if GP/HS/EMU/TST + *************************************************************/ +u32 get_device_type(void) +{ + int mode; + mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK); + return mode >>= 8; +} diff --git a/board/poseidon/u-boot.lds b/board/poseidon/u-boot.lds index e69de29..13f1971 100644 --- a/board/poseidon/u-boot.lds +++ b/board/poseidon/u-boot.lds @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2009-2010 + * Samsung Electronics, <www.samsung.com> + * Vivek Dalal <v.dalal(a)samsung.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +}

2 2

[U-Boot] [PATCH:v3] Support up to 7 banks for ids as specified in JEDEC JEP106Z
by Niklaus Giger 26 Aug '09

26 Aug '09

see http://www.jedec.org/download/search/jep106Z.pdf Add some second source legacy flash chips 256x8. Signed-off-by: Niklaus Giger <niklaus.giger(a)member.fsf.org> --- drivers/mtd/cfi_flash.c | 15 +++++++++- drivers/mtd/jedec_flash.c | 67 +++++++++++++++++++++++++++++++++++++++++++++ include/flash.h | 10 ++++++- 3 files changed, 89 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 81ac5d3..8f750cb 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -106,6 +106,8 @@ #define ATM_CMD_SOFTLOCK_START 0x80 #define ATM_CMD_LOCK_SECT 0x40 +#define FLASH_CONTINUATION_CODE 0x7F + #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 #define FLASH_OFFSET_DEVICE_ID2 0x0E @@ -1541,13 +1543,22 @@ static int cmdset_intel_init(flash_info_t *info, struct cfi_qry *qry) static void cmdset_amd_read_jedec_ids(flash_info_t *info) { + ushort bankId = 0; + uchar manuId; + flash_write_cmd(info, 0, 0, AMD_CMD_RESET); flash_unlock_seq(info, 0); flash_write_cmd(info, 0, info->addr_unlock1, FLASH_CMD_READ_ID); udelay(1000); /* some flash are slow to respond */ - info->manufacturer_id = flash_read_uchar (info, - FLASH_OFFSET_MANUFACTURER_ID); + manuId = flash_read_uchar (info, FLASH_OFFSET_MANUFACTURER_ID); + /* JEDEC JEP106Z specifies ID codes up to bank 7 */ + while (manuId == FLASH_CONTINUATION_CODE && bankId < 0x800) { + bankId += 0x100; + manuId = flash_read_uchar (info, + bankId | FLASH_OFFSET_MANUFACTURER_ID); + } + info->manufacturer_id = manuId; switch (info->chipwidth){ case FLASH_CFI_8BIT: diff --git a/drivers/mtd/jedec_flash.c b/drivers/mtd/jedec_flash.c index e48acec..223fb71 100644 --- a/drivers/mtd/jedec_flash.c +++ b/drivers/mtd/jedec_flash.c @@ -68,6 +68,17 @@ #define SST39SF010A 0x00B5 #define SST39SF020A 0x00B6 +/* MXIC */ +#define MX29LV040 0x004F + +/* WINBOND */ +#define W39L040A 0x00D6 + +/* AMIC */ +#define A29L040 0x0092 + +/* EON */ +#define EN29LV040A 0x004F /* * Unlock address sets for AMD command sets. @@ -225,6 +236,62 @@ static const struct amd_flash_info jedec_table[] = { ERASEINFO(0x10000,8), } }, + { + .mfr_id = (u16)MX_MANUFACT, + .dev_id = MX29LV040, + .name = "MXIC MX29LV040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)WINB_MANUFACT, + .dev_id = W39L040A, + .name = "WINBOND W39L040A", + .uaddr = { + [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)AMIC_MANUFACT, + .dev_id = A29L040, + .name = "AMIC A29L040", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, + { + .mfr_id = (u16)EON_MANUFACT, + .dev_id = EN29LV040A, + .name = "EON EN29LV040A", + .uaddr = { + [0] = MTD_UADDR_0x0555_0x02AA /* x8 */ + }, + .DevSize = SIZE_512KiB, + .CmdSet = P_ID_AMD_STD, + .NumEraseRegions= 1, + .regions = { + ERASEINFO(0x10000, 8), + } + }, #endif #ifdef CONFIG_SYS_FLASH_LEGACY_512Kx16 { diff --git a/include/flash.h b/include/flash.h index b016162..8feca1b 100644 --- a/include/flash.h +++ b/include/flash.h @@ -46,7 +46,7 @@ typedef struct { ushort cmd_reset; /* vendor specific reset command */ ushort interface; /* used for x8/x16 adjustments */ ushort legacy_unlock; /* support Intel legacy (un)locking */ - uchar manufacturer_id; /* manufacturer id */ + ushort manufacturer_id; /* manufacturer id */ ushort device_id; /* device id */ ushort device_id2; /* extended device id */ ushort ext_addr; /* extended query table address */ @@ -154,6 +154,7 @@ extern flash_info_t *flash_get_info(ulong base); * Device IDs */ +/* Manufacturers inside bank 0 have ids like 0x00xx00xx */ #define AMD_MANUFACT 0x00010001 /* AMD manuf. ID in D23..D16, D7..D0 */ #define FUJ_MANUFACT 0x00040004 /* FUJITSU manuf. ID in D23..D16, D7..D0 */ #define ATM_MANUFACT 0x001F001F /* ATMEL */ @@ -166,6 +167,13 @@ extern flash_info_t *flash_get_info(ulong base); #define TOSH_MANUFACT 0x00980098 /* TOSHIBA manuf. ID in D23..D16, D7..D0 */ #define MT2_MANUFACT 0x002C002C /* alternate MICRON manufacturer ID*/ #define EXCEL_MANUFACT 0x004A004A /* Excel Semiconductor */ +#define AMIC_MANUFACT 0x00370037 /* AMIC manuf. ID in D23..D16, D7..D0 */ +#define WINB_MANUFACT 0x00DA00DA /* Winbond manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 1 have ids like 0x01xx01xx */ +#define EON_MANUFACT 0x011C011C /* EON manuf. ID in D23..D16, D7..D0 */ + +/* Manufacturers inside bank 2 have ids like 0x02xx02xx */ /* Micron Technologies (INTEL compat.) */ #define MT_ID_28F400_T 0x44704470 /* 28F400B3 ID ( 4 M, top boot sector) */ -- 1.6.3.3

2 1

[U-Boot] ENV_IS_EMBEDDED vs CONFIG_ENV_IS_EMBEDDED
by Mike Frysinger 25 Aug '09

25 Aug '09

is there a reason to keep ENV_IS_EMBEDDED around ? i see a few places that use CONFIG_ENV_IS_EMBEDDED, but it seems to be largely useless at the moment as the define doesn't really do anything without ENV_IS_EMBEDDED. in other words, i'd like to just do a sed on the tree to convert all ENV_IS_EMBEDDED instances to CONFIG_ENV_IS_EMBEDDED. -mike

3 12

[U-Boot] [PATCH] jffs2: some fixes to summary support
by Ilya Yanok 24 Aug '09

24 Aug '09

This patch fixes some issues with JFFS2 summary support in U-Boot. 1/ Summary support made compilation configurable (as summary support considered expiremental even in Linux). 2/ Summary code can do unaligned 16-bit and 32-bit memory accesses. We need to get data byte by byte to exclude data aborts. 3/ Make summary scan in two passes so we can safely fall back to full scan if we found unsupported entry in the summary. Signed-off-by: Ilya Yanok <yanok(a)emcraft.com> --- fs/jffs2/jffs2_1pass.c | 122 ++++++++++++++++++++++++++++++++---------------- 1 files changed, 81 insertions(+), 41 deletions(-) diff --git a/fs/jffs2/jffs2_1pass.c b/fs/jffs2/jffs2_1pass.c index 11b66ab..ba8ac51 100644 --- a/fs/jffs2/jffs2_1pass.c +++ b/fs/jffs2/jffs2_1pass.c @@ -120,6 +120,7 @@ #include <jffs2/jffs2.h> #include <jffs2/jffs2_1pass.h> #include <linux/mtd/compat.h> +#include <asm/errno.h> #include "jffs2_private.h" @@ -1220,8 +1221,30 @@ jffs2_1pass_rescan_needed(struct part_info *part) return 0; } +#ifdef CONFIG_JFFS2_SUMMARY +static u32 sum_get_unaligned32(u32 *ptr) +{ + u32 val; + u8 *p = (u8 *)ptr; + + val = *p | (*(p + 1) << 8) | (*(p + 2) << 16) | (*(p + 3) << 24); + + return __le32_to_cpu(val); +} + +static u16 sum_get_unaligned16(u16 *ptr) +{ + u16 val; + u8 *p = (u8 *)ptr; + + val = *p | (*(p + 1) << 8); + + return __le16_to_cpu(val); +} + #define dbg_summary(...) do {} while (0); -/* Process the stored summary information - helper function for +/* + * Process the stored summary information - helper function for * jffs2_sum_scan_sumnode() */ @@ -1230,54 +1253,64 @@ static int jffs2_sum_process_sum_data(struct part_info *part, uint32_t offset, struct b_lists *pL) { void *sp; - int i; + int i, pass; + void *ret; - sp = summary->sum; + for (pass = 0; pass < 2; pass++) { + sp = summary->sum; - for (i = 0; i < summary->sum_num; i++) { - dbg_summary("processing summary index %d\n", i); + for (i = 0; i < summary->sum_num; i++) { + struct jffs2_sum_unknown_flash *spu = sp; + dbg_summary("processing summary index %d\n", i); - switch (((struct jffs2_sum_unknown_flash *)sp)->nodetype) { - case JFFS2_NODETYPE_INODE: { + switch (sum_get_unaligned16(&spu->nodetype)) { + case JFFS2_NODETYPE_INODE: { struct jffs2_sum_inode_flash *spi; - spi = sp; - - dbg_summary("Inode at 0x%08x-0x%08x\n", - offset + spi->offset, - offset + spi->offset + spi->totlen); + if (pass) { + spi = sp; - if (insert_node(&pL->frag, (u32) part->offset + - offset + spi->offset) == NULL) - return -1; + ret = insert_node(&pL->frag, + (u32)part->offset + + offset + + sum_get_unaligned32( + &spi->offset)); + if (ret == NULL) + return -1; + } - sp += JFFS2_SUMMARY_INODE_SIZE; + sp += JFFS2_SUMMARY_INODE_SIZE; - break; - } - - case JFFS2_NODETYPE_DIRENT: { - struct jffs2_sum_dirent_flash *spd; - spd = sp; - - dbg_summary("Dirent at 0x%08x-0x%08x\n", - offset + spd->offset, - offset + spd->offset + spd->totlen); - - if (insert_node(&pL->dir, (u32) part->offset + - offset + spd->offset) == NULL) - return -1; - - sp += JFFS2_SUMMARY_DIRENT_SIZE(spd->nsize); + break; + } + case JFFS2_NODETYPE_DIRENT: { + struct jffs2_sum_dirent_flash *spd; + spd = sp; + if (pass) { + ret = insert_node(&pL->dir, + (u32) part->offset + + offset + + sum_get_unaligned32( + &spd->offset)); + if (ret == NULL) + return -1; + } + + sp += JFFS2_SUMMARY_DIRENT_SIZE( + spd->nsize); - break; - } - default : { - uint16_t nodetype = - ((struct jffs2_sum_unknown_flash *) - sp)->nodetype; - printf("Unsupported node type %x found in " - "summary!\n", nodetype); - break; + break; + } + default : { + uint16_t nodetype = sum_get_unaligned16( + &spu->nodetype); + printf("Unsupported node type %x found" + " in summary!\n", + nodetype); + if ((nodetype & JFFS2_COMPAT_MASK) == + JFFS2_FEATURE_INCOMPAT) + return -EIO; + return -EBADMSG; + } } } } @@ -1335,6 +1368,8 @@ int jffs2_sum_scan_sumnode(struct part_info *part, uint32_t offset, dbg_summary("Summary : CLEANMARKER node \n"); ret = jffs2_sum_process_sum_data(part, offset, summary, pL); + if (ret == -EBADMSG) + return 0; if (ret) return ret; /* real error */ @@ -1345,6 +1380,7 @@ crc_err: return 0; } +#endif /* CONFIG_JFFS2_SUMMARY */ #ifdef DEBUG_FRAGMENTS static void @@ -1450,13 +1486,16 @@ jffs2_1pass_build_lists(struct part_info * part) uint32_t buf_ofs = sector_ofs; uint32_t buf_len; uint32_t ofs, prevofs; +#ifdef CONFIG_JFFS2_SUMMARY struct jffs2_sum_marker *sm; void *sumptr = NULL; uint32_t sumlen; int ret; +#endif WATCHDOG_RESET(); +#ifdef CONFIG_JFFS2_SUMMARY buf_len = sizeof(*sm); /* Read as much as we want into the _end_ of the preallocated @@ -1504,6 +1543,7 @@ jffs2_1pass_build_lists(struct part_info * part) continue; } +#endif /* CONFIG_JFFS2_SUMMARY */ buf_len = EMPTY_SCAN_SIZE(part->sector_size); -- 1.6.0.6

5 7

[U-Boot] [PATCH 1/6] include/config_cmd_default.h cleanup
by Prafulla Wadaskar 21 Aug '09

21 Aug '09

arranged configurations in alphabetical order CONFIG_CMD_FLASH moved under ifndef CONFIG_SYS_NO_FLASH Signed-off-by: Prafulla Wadaskar <prafulla(a)marvell.com> --- include/config_cmd_default.h | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/config_cmd_default.h b/include/config_cmd_default.h index 0376e44..a5d87a6 100644 --- a/include/config_cmd_default.h +++ b/include/config_cmd_default.h @@ -20,14 +20,13 @@ #define CONFIG_CMD_BOOTD /* bootd */ #define CONFIG_CMD_CONSOLE /* coninfo */ #define CONFIG_CMD_ECHO /* echo arguments */ -#define CONFIG_CMD_SAVEENV /* saveenv */ -#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_FPGA /* FPGA configuration Support */ #define CONFIG_CMD_IMI /* iminfo */ +#define CONFIG_CMD_ITEST /* Integer (and string) test */ #ifndef CONFIG_SYS_NO_FLASH +#define CONFIG_CMD_FLASH /* flinfo, erase, protect */ #define CONFIG_CMD_IMLS /* List all found images */ #endif -#define CONFIG_CMD_ITEST /* Integer (and string) test */ #define CONFIG_CMD_LOADB /* loadb */ #define CONFIG_CMD_LOADS /* loads */ #define CONFIG_CMD_MEMORY /* md mm nm mw cp cmp crc base loop mtest */ @@ -35,6 +34,7 @@ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_CMD_NFS /* NFS support */ #define CONFIG_CMD_RUN /* run command in env variable */ +#define CONFIG_CMD_SAVEENV /* saveenv */ #define CONFIG_CMD_SETGETDCR /* DCR support on 4xx */ #define CONFIG_CMD_SOURCE /* "source" command support */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ -- 1.5.3.3

6 34

[U-Boot] [PATCH] tsec: Wait for auto-negotiation to complete without link
by Peter Tyser 21 Aug '09

21 Aug '09

Previously, waiting for auto-negotiation would only occur if a valid link had been detected. Problems arose when attempting to use a tsec immediately after bootup but before link was achieved, eg: => dhcp Auto-neg error, defaulting to 10BT/HD eTSEC1: No link. Auto-neg error, defaulting to 10BT/HD eTSEC2: No link. => With this patch applied the same operation as above resulted in: => dhcp Waiting for PHY auto negotiation to complete. done Enet starting in 1000BT/FD Speed: 1000, full duplex Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- drivers/net/tsec.c | 19 +++++++++---------- 1 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index dc90f23..2e30fe9 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -352,8 +352,8 @@ uint mii_cr_init(uint mii_reg, struct tsec_private * priv) return MIIM_CR_INIT; } -/* Parse the status register for link, and then do - * auto-negotiation +/* + * Wait for auto-negotiation to complete, then determine link */ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) { @@ -362,8 +362,7 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) * (ie - we're capable and it's not done) */ mii_reg = read_phy_reg(priv, MIIM_STATUS); - if ((mii_reg & MIIM_STATUS_LINK) && (mii_reg & PHY_BMSR_AUTN_ABLE) - && !(mii_reg & PHY_BMSR_AUTN_COMP)) { + if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) { int i = 0; puts("Waiting for PHY auto negotiation to complete"); @@ -384,15 +383,15 @@ uint mii_parse_sr(uint mii_reg, struct tsec_private * priv) mii_reg = read_phy_reg(priv, MIIM_STATUS); } puts(" done\n"); - priv->link = 1; + + /* Link status bit is latched low, read it again */ + mii_reg = read_phy_reg(priv, MIIM_STATUS); + udelay(500000); /* another 500 ms (results in faster booting) */ - } else { - if (mii_reg & MIIM_STATUS_LINK) - priv->link = 1; - else - priv->link = 0; } + priv->link = mii_reg & MIIM_STATUS_LINK ? 1 : 0; + return 0; } -- 1.6.0.2.GIT

6 22

Re: [U-Boot] [PATCH 3/3 v4] arm: A320: Add support for Faraday A320 evaluation board
by Po-Yu Chuang 20 Aug '09

20 Aug '09

This patch adds support for A320 development board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 7 + board/faraday/a320/Makefile | 51 +++++++ board/faraday/a320/a320.c | 64 ++++++++ board/faraday/a320/config.mk | 35 +++++ board/faraday/a320/lowlevel_init.S | 191 ++++++++++++++++++++++++ cpu/arm920t/faraday/Makefile | 46 ++++++ cpu/arm920t/faraday/ftsmc020.c | 51 +++++++ cpu/arm920t/faraday/timer.c | 195 +++++++++++++++++++++++++ include/asm-arm/arch-faraday/ftahbc020.h | 71 +++++++++ include/asm-arm/arch-faraday/ftpmu010.h | 190 ++++++++++++++++++++++++ include/asm-arm/arch-faraday/ftsdmc020.h | 103 +++++++++++++ include/asm-arm/arch-faraday/ftsmc020.h | 79 ++++++++++ include/asm-arm/arch-faraday/fttmr010.h | 73 +++++++++ include/configs/a320.h | 235 ++++++++++++++++++++++++++++++ 16 files changed, 1396 insertions(+), 0 deletions(-) create mode 100644 board/faraday/a320/Makefile create mode 100644 board/faraday/a320/a320.c create mode 100644 board/faraday/a320/config.mk create mode 100644 board/faraday/a320/lowlevel_init.S create mode 100644 cpu/arm920t/faraday/Makefile create mode 100644 cpu/arm920t/faraday/ftsmc020.c create mode 100644 cpu/arm920t/faraday/timer.c create mode 100644 include/asm-arm/arch-faraday/ftahbc020.h create mode 100644 include/asm-arm/arch-faraday/ftpmu010.h create mode 100644 include/asm-arm/arch-faraday/ftsdmc020.h create mode 100644 include/asm-arm/arch-faraday/ftsmc020.h create mode 100644 include/asm-arm/arch-faraday/fttmr010.h create mode 100644 include/configs/a320.h diff --git a/MAINTAINERS b/MAINTAINERS index b0e370f..ed41b3a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -680,6 +680,10 @@ Sergey Lapin <slapin(a)ossfans.org> afeb9260 ARM926EJS (AT91SAM9260 SoC) +Po-Yu Chuang <ratbert(a)faraday-tech.com> + + a320 FA526 (ARMv4/reuse arm920t source) faraday SoC + ------------------------------------------------------------------------- Unknown / orphaned boards: diff --git a/MAKEALL b/MAKEALL index 027207d..530a253 100755 --- a/MAKEALL +++ b/MAKEALL @@ -498,6 +498,7 @@ LIST_ARM7=" \ ######################################################################### LIST_ARM9=" \ + a320 \ ap920t \ ap922_XA10 \ ap926ejs \ diff --git a/Makefile b/Makefile index 0ae1d36..f99e9d4 100644 --- a/Makefile +++ b/Makefile @@ -2991,6 +2991,13 @@ B2_config : unconfig @$(MKCONFIG) $(@:_config=) arm s3c44b0 B2 dave ######################################################################### +## Faraday A320 Systems +######################################################################### + +a320_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm920t a320 faraday faraday + +######################################################################### ## ARM720T Systems ######################################################################### diff --git a/board/faraday/a320/Makefile b/board/faraday/a320/Makefile new file mode 100644 index 0000000..ef053c2 --- /dev/null +++ b/board/faraday/a320/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := a320.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/faraday/a320/a320.c b/board/faraday/a320/a320.c new file mode 100644 index 0000000..94517c9 --- /dev/null +++ b/board/faraday/a320/a320.c @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <netdev.h> +#include <rtc.h> +#include <asm/io.h> + +#include <asm/arch/ftsmc020.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscellaneous platform dependent initialisations + */ + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_FARADAY; + + ftsmc020_init (); /* initialize Flash */ + rtc_reset (); /* enable RTC */ + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_eth_init (bd_t *bd) +{ + return ftmac100_initialize (bd); +} + +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t *info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = FLASH_CFI_8BIT; + info->chipwidth = FLASH_CFI_BY8; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/faraday/a320/config.mk b/board/faraday/a320/config.mk new file mode 100644 index 0000000..7573bbd --- /dev/null +++ b/board/faraday/a320/config.mk @@ -0,0 +1,35 @@ +# +# (C) Copyright 2009 Faraday Technology +# Po-Yu Chuang <ratbert(a)faraday-tech.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# Faraday A320 board with FA526/FA626TE/ARM926EJ-S cpus +# +# see http://www.faraday-tech.com/ for more information + +# A320 has 1 bank of 64 MB DRAM (after remapped) +# +# 0000'0000 to 0400'0000 +# +# Linux-Kernel is expected to be at 0000'8000, entry 0000'8000 +# +# we load ourself to 03f8'0000 +# +# download area is 0200'0000 + +TEXT_BASE = 0x03f80000 diff --git a/board/faraday/a320/lowlevel_init.S b/board/faraday/a320/lowlevel_init.S new file mode 100644 index 0000000..4337740 --- /dev/null +++ b/board/faraday/a320/lowlevel_init.S @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <version.h> + +#include <asm/macro.h> +#include <asm/arch/ftahbc020.h> +#include <asm/arch/ftsdmc020.h> + +/* + * Memory Mapping + */ +#define ROM_DEFAULT_BASE 0x00000000 +#define SDRAM_DEFAULT_BASE 0x10000000 +#define SDRAM_REMAPPED_BASE PHYS_SDRAM_1 /* remap location */ + +/* + * parameters for the SDRAM controller + */ +#define TP0_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_TP0) +#define TP1_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_TP1) +#define CR_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_CR) +#define B0_BSR_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_BANK0_BSR) +#define ACR_A (CONFIG_SYS_SDMC_BASE + FTSDMC020_OFFSET_ACR) + +#define TP0_D CONFIG_SYS_FTSDMC020_TP0 +#define TP1_D CONFIG_SYS_FTSDMC020_TP1 +#define CR_D1 FTSDMC020_CR_IPREC +#define CR_D2 FTSDMC020_CR_ISMR +#define CR_D3 FTSDMC020_CR_IREF + +#define B0_BSR_D1 (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ + FTSDMC020_BANK_BASE(SDRAM_DEFAULT_BASE)) +#define B0_BSR_D2 (CONFIG_SYS_FTSDMC020_BANK0_BSR | \ + FTSDMC020_BANK_BASE(SDRAM_REMAPPED_BASE)) +#define ACR_D FTSDMC020_ACR_TOC(0x18) + +/* + * numeric 7 segment display + */ +.macro led, num + write32 CONFIG_SYS_DEBUG_LED, \num +.endm + +/* + * Waiting for SDRAM to set up + */ +.macro wait_sdram + ldr r0, =CONFIG_SYS_SDMC_BASE +1: + ldr r1, [r0, #FTSDMC020_OFFSET_CR] + cmp r1, #0 + bne 1b +.endm + +.global reset_cpu +reset_cpu: + b reset_cpu + +.globl lowlevel_init +lowlevel_init: + mov r11, lr + + led 0x0 + + /* if REMAP bit is set -> memory had been initialzed */ + + ldr r0, =CONFIG_SYS_AHBC_BASE + ldr r1, [r0, #FTAHBC020_OFFSET_ICR] + tst r1, #FTAHBC020_ICR_REMAP @ test REMAP bit + bne skip_remap + + led 0x1 + + bl init_sdmc + + led 0x2 + + /* + * copy U-Boot to RAM + */ +copy_code: + ldr r0, =ROM_DEFAULT_BASE /* r0 <- source address */ + ldr r1, =SDRAM_DEFAULT_BASE /* r1 <- target address */ + + ldr r2, .LC5 + ldr r3, .LC6 + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + + led 0x3 + +copy_loop: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + + led 0x4 + + bl remap + +skip_remap: + led 0x5 + + /* everything is fine now */ + mov lr, r11 + mov pc, lr + +.LC5: + .word _start +.LC6: + .word __bss_start + +/* + * memory initialization + */ +init_sdmc: + led 0x10 + + /* set SDRAM register */ + + write32 TP0_A, TP0_D + led 0x11 + + write32 TP1_A, TP1_D + led 0x12 + + /* set to precharge */ + write32 CR_A, CR_D1 + led 0x13 + + wait_sdram + led 0x14 + + /* set mode register */ + write32 CR_A, CR_D2 + led 0x15 + + wait_sdram + led 0x16 + + /* set to refresh */ + write32 CR_A, CR_D3 + led 0x17 + + wait_sdram + led 0x18 + + write32 B0_BSR_A, B0_BSR_D1 + led 0x19 + + write32 ACR_A, ACR_D + led 0x1a + + mov pc, lr + +/* + * This code will remap the memory ROM and SDRAM + * ROM will be placed on 0x80000000 SDRAM will jump to 0x0 + */ +remap: + ldr r0, =CONFIG_SYS_SDMC_BASE + + /* first adjust sdram */ + write32 B0_BSR_A, B0_BSR_D2 + + /* then remap */ + ldr r3, =CONFIG_SYS_AHBC_BASE + ldr r4, [r3, #FTAHBC020_OFFSET_ICR] + orr r4, r4, #FTAHBC020_ICR_REMAP @ Set REMAP bit + str r4, [r3, #FTAHBC020_OFFSET_ICR] + + mov pc, lr diff --git a/cpu/arm920t/faraday/Makefile b/cpu/arm920t/faraday/Makefile new file mode 100644 index 0000000..b879d87 --- /dev/null +++ b/cpu/arm920t/faraday/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS += timer.o +COBJS += ftsmc020.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/cpu/arm920t/faraday/ftsmc020.c b/cpu/arm920t/faraday/ftsmc020.c new file mode 100644 index 0000000..b1b00e1 --- /dev/null +++ b/cpu/arm920t/faraday/ftsmc020.c @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftsmc020.h> + +struct ftsmc020_config { + unsigned int config; + unsigned int timing; +}; + +static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS; + +static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_SYS_SMC_BASE; + +static void ftsmc020_setup_bank (unsigned int bank, struct ftsmc020_config *cfg) +{ + if (bank > 3) { + printf ("bank # %u invalid\n", bank); + return; + } + + writel (cfg->config, &smc->bank[bank].cr); + writel (cfg->timing, &smc->bank[bank].tpr); +} + +void ftsmc020_init (void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE (config); i++) + ftsmc020_setup_bank (i, &config[i]); +} diff --git a/cpu/arm920t/faraday/timer.c b/cpu/arm920t/faraday/timer.c new file mode 100644 index 0000000..5a49b24 --- /dev/null +++ b/cpu/arm920t/faraday/timer.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#undef DEBUG + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/ftpmu010.h> +#include <asm/arch/fttmr010.h> + +static ulong timestamp; +static ulong lastdec; + +static struct fttmr010 *tmr = (struct fttmr010 *)CONFIG_SYS_TIMERBASE; +static struct ftpmu010 *pmu = (struct ftpmu010 *)CONFIG_SYS_FTPMU_BASE; + +#define TIMER_CLOCK 32768 +#define TIMER_LOAD_VAL 0xffffffff + +int timer_init (void) +{ + unsigned int oscc; + unsigned int cr; + + debug ("%s()\n", __func__); + + /* disable timers */ + writel (0, &tmr->cr); + + /* + * use 32768Hz oscillator for RTC, WDT, TIMER + */ + + /* enable the 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc &= ~(FTPMU010_OSCC_OSCL_OFF | FTPMU010_OSCC_OSCL_TRI); + writel (oscc, &pmu->OSCC); + + /* wait until ready */ + while (!(readl (&pmu->OSCC) & FTPMU010_OSCC_OSCL_STABLE)) + ; + + /* select 32768Hz oscillator */ + oscc = readl (&pmu->OSCC); + oscc |= FTPMU010_RTCLSEL; + writel (oscc, &pmu->OSCC); + + /* setup timer */ + writel (TIMER_LOAD_VAL, &tmr->timer3_load); + writel (TIMER_LOAD_VAL, &tmr->timer3_counter); + writel (0, &tmr->timer3_match1); + writel (0, &tmr->timer3_match2); + + /* we don't want timer to issue interrupts */ + writel (FTTMR010_TM3_MATCH1 | + FTTMR010_TM3_MATCH2 | + FTTMR010_TM3_OVERFLOW, + &tmr->interrupt_mask); + + cr = readl (&tmr->cr); + cr |= FTTMR010_TM3_CLOCK; /* use external clock */ + cr |= FTTMR010_TM3_ENABLE; + writel (cr, &tmr->cr); + + /* init the timestamp and lastdec value */ + reset_timer_masked (); + + return 0; +} + +/* + * timer without interrupts + */ + +/* + * reset time + */ +void reset_timer_masked (void) +{ + /* capure current decrementer value time */ + lastdec = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + timestamp = 0; /* start "advancing" time stamp from 0 */ + + debug ("%s(): lastdec = %lx\n", __func__, lastdec); +} + +void reset_timer (void) +{ + debug ("%s()\n", __func__); + reset_timer_masked (); +} + +/* + * return timer ticks + */ +ulong get_timer_masked (void) +{ + /* current tick value */ + ulong now = readl (&tmr->timer3_counter) / (TIMER_CLOCK / CONFIG_SYS_HZ); + + debug ("%s(): now = %lx, lastdec = %lx\n", __func__, now, lastdec); + + if (lastdec >= now) { + /* + * normal mode (non roll) + * move stamp fordward with absoulte diff ticks + */ + timestamp += lastdec - now; + } else { + /* + * we have overflow of the count down timer + * + * nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and + * cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + + lastdec = now; + + debug ("%s() returns %lx\n", __func__, timestamp); + + return timestamp; +} + +/* + * return difference between timer ticks and base + */ +ulong get_timer (ulong base) +{ + debug ("%s(%lx)\n", __func__, base); + return get_timer_masked () - base; +} + +void set_timer (ulong t) +{ + debug ("%s(%lx)\n", __func__, t); + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void udelay (unsigned long usec) +{ + long tmo = usec * (TIMER_CLOCK / 1000) / 1000; + unsigned long now, last = readl(&tmr->timer3_counter); + + debug ("%s(%lu)\n", __func__, usec); + while (tmo > 0) { + now = readl(&tmr->timer3_counter); + if (now > last) /* count down timer overflow */ + tmo -= TIMER_LOAD_VAL + last - now; + else + tmo -= last - now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks (void) +{ + debug ("%s()\n", __func__); + return get_timer (0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + debug ("%s()\n", __func__); + return CONFIG_SYS_HZ; +} diff --git a/include/asm-arm/arch-faraday/ftahbc020.h b/include/asm-arm/arch-faraday/ftahbc020.h new file mode 100644 index 0000000..c2e039e --- /dev/null +++ b/include/asm-arm/arch-faraday/ftahbc020.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * AHB Controller + */ +#ifndef __FTAHBC020_H +#define __FTAHBC020_H + +#define FTAHBC020_OFFSET_SLAVE0_BSR 0x00 +#define FTAHBC020_OFFSET_SLAVE1_BSR 0x04 +#define FTAHBC020_OFFSET_SLAVE2_BSR 0x08 +#define FTAHBC020_OFFSET_SLAVE3_BSR 0x0C +#define FTAHBC020_OFFSET_SLAVE4_BSR 0x10 +#define FTAHBC020_OFFSET_SLAVE5_BSR 0x14 +#define FTAHBC020_OFFSET_SLAVE6_BSR 0x18 +#define FTAHBC020_OFFSET_SLAVE7_BSR 0x1C +#define FTAHBC020_OFFSET_SLAVE9_BSR 0x24 +#define FTAHBC020_OFFSET_SLAVE12_BSR 0x30 +#define FTAHBC020_OFFSET_SLAVE13_BSR 0x34 +#define FTAHBC020_OFFSET_SLAVE14_BSR 0x38 +#define FTAHBC020_OFFSET_SLAVE15_BSR 0x3C +#define FTAHBC020_OFFSET_SLAVE17_BSR 0x44 +#define FTAHBC020_OFFSET_SLAVE18_BSR 0x48 +#define FTAHBC020_OFFSET_SLAVE19_BSR 0x4C +#define FTAHBC020_OFFSET_SLAVE21_BSR 0x54 +#define FTAHBC020_OFFSET_SLAVE22_BSR 0x58 +#define FTAHBC020_OFFSET_PCR 0x80 +#define FTAHBC020_OFFSET_TCR 0x84 +#define FTAHBC020_OFFSET_ICR 0x88 + +/* + * AHB Slave n Base/Size Register + */ +#define FTAHBC020_BSR_BASE(x) ((x) & 0xfff00000) + +#define FTAHBC020_BSR_SIZE_1M (0x0 << 16) +#define FTAHBC020_BSR_SIZE_2M (0x1 << 16) +#define FTAHBC020_BSR_SIZE_4M (0x2 << 16) +#define FTAHBC020_BSR_SIZE_8M (0x3 << 16) +#define FTAHBC020_BSR_SIZE_16M (0x4 << 16) +#define FTAHBC020_BSR_SIZE_32M (0x5 << 16) +#define FTAHBC020_BSR_SIZE_64M (0x6 << 16) +#define FTAHBC020_BSR_SIZE_128M (0x7 << 16) +#define FTAHBC020_BSR_SIZE_256M (0x8 << 16) +#define FTAHBC020_BSR_SIZE_512M (0x9 << 16) +#define FTAHBC020_BSR_SIZE_1G (0xa << 16) +#define FTAHBC020_BSR_SIZE_2G (0xb << 16) + +/* + * AHB Interrupt Control Register + */ +#define FTAHBC020_ICR_REMAP (1 << 0) + +#endif /* __FTAHBC020_H */ diff --git a/include/asm-arm/arch-faraday/ftpmu010.h b/include/asm-arm/arch-faraday/ftpmu010.h new file mode 100644 index 0000000..e365af5 --- /dev/null +++ b/include/asm-arm/arch-faraday/ftpmu010.h @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Power Management Unit + */ +#ifndef __FTPMU010_H +#define __FTPMU010_H + +#define FTPMU010_OFFSET_IDNMBR0 0x00 +#define FTPMU010_OFFSET_OSCC 0x08 +#define FTPMU010_OFFSET_PMODE 0x0C +#define FTPMU010_OFFSET_PMCR 0x10 +#define FTPMU010_OFFSET_PED 0x14 +#define FTPMU010_OFFSET_PEDSR 0x18 +#define FTPMU010_OFFSET_PMSR 0x20 +#define FTPMU010_OFFSET_PGSR 0x24 +#define FTPMU010_OFFSET_MFPSR 0x28 +#define FTPMU010_OFFSET_MISC 0x2C +#define FTPMU010_OFFSET_PDLLCR0 0x30 +#define FTPMU010_OFFSET_PDLLCR1 0x34 +#define FTPMU010_OFFSET_AHBMCLKOFF 0x38 +#define FTPMU010_OFFSET_APBMCLKOFF 0x3C +#define FTPMU010_OFFSET_DCSRCR0 0x40 +#define FTPMU010_OFFSET_DCSRCR1 0x44 +#define FTPMU010_OFFSET_DCSRCR2 0x48 +#define FTPMU010_OFFSET_SDRAMHTC 0x4C +#define FTPMU010_OFFSET_PSPR0 0x50 +#define FTPMU010_OFFSET_PSPR1 0x54 +#define FTPMU010_OFFSET_PSPR2 0x58 +#define FTPMU010_OFFSET_PSPR3 0x5C +#define FTPMU010_OFFSET_PSPR4 0x60 +#define FTPMU010_OFFSET_PSPR5 0x64 +#define FTPMU010_OFFSET_PSPR6 0x68 +#define FTPMU010_OFFSET_PSPR7 0x6C +#define FTPMU010_OFFSET_PSPR8 0x70 +#define FTPMU010_OFFSET_PSPR9 0x74 +#define FTPMU010_OFFSET_PSPR10 0x78 +#define FTPMU010_OFFSET_PSPR11 0x7C +#define FTPMU010_OFFSET_PSPR12 0x80 +#define FTPMU010_OFFSET_PSPR13 0x84 +#define FTPMU010_OFFSET_PSPR14 0x88 +#define FTPMU010_OFFSET_PSPR15 0x8C +#define FTPMU010_OFFSET_AHBDMA_RACCS 0x90 +#define FTPMU010_OFFSET_JSS 0x9C +#define FTPMU010_OFFSET_CFC_RACC 0xA0 +#define FTPMU010_OFFSET_SSP1_RACC 0xA4 +#define FTPMU010_OFFSET_UART1TX_RACC 0xA8 +#define FTPMU010_OFFSET_UART1RX_RACC 0xAC +#define FTPMU010_OFFSET_UART2TX_RACC 0xB0 +#define FTPMU010_OFFSET_UART2RX_RACC 0xB4 +#define FTPMU010_OFFSET_SDC_RACC 0xB8 +#define FTPMU010_OFFSET_I2SAC97_RACC 0xBC +#define FTPMU010_OFFSET_IRDATX_RACC 0xC0 +#define FTPMU010_OFFSET_USBD_RACC 0xC8 +#define FTPMU010_OFFSET_IRDARX_RACC 0xCC +#define FTPMU010_OFFSET_IRDA_RACC 0xD0 +#define FTPMU010_OFFSET_ED0_RACC 0xD4 +#define FTPMU010_OFFSET_ED1_RACC 0xD8 + +struct ftpmu010 { + unsigned int IDNMBR0; /* 0x00 */ + unsigned int reserved0; /* 0x04 */ + unsigned int OSCC; /* 0x08 */ + unsigned int PMODE; /* 0x0C */ + unsigned int PMCR; /* 0x10 */ + unsigned int PED; /* 0x14 */ + unsigned int PEDSR; /* 0x18 */ + unsigned int reserved1; /* 0x1C */ + unsigned int PMSR; /* 0x20 */ + unsigned int PGSR; /* 0x24 */ + unsigned int MFPSR; /* 0x28 */ + unsigned int MISC; /* 0x2C */ + unsigned int PDLLCR0; /* 0x30 */ + unsigned int PDLLCR1; /* 0x34 */ + unsigned int AHBMCLKOFF; /* 0x38 */ + unsigned int APBMCLKOFF; /* 0x3C */ + unsigned int DCSRCR0; /* 0x40 */ + unsigned int DCSRCR1; /* 0x44 */ + unsigned int DCSRCR2; /* 0x48 */ + unsigned int SDRAMHTC; /* 0x4C */ + unsigned int PSPR0; /* 0x50 */ + unsigned int PSPR1; /* 0x54 */ + unsigned int PSPR2; /* 0x58 */ + unsigned int PSPR3; /* 0x5C */ + unsigned int PSPR4; /* 0x60 */ + unsigned int PSPR5; /* 0x64 */ + unsigned int PSPR6; /* 0x68 */ + unsigned int PSPR7; /* 0x6C */ + unsigned int PSPR8; /* 0x70 */ + unsigned int PSPR9; /* 0x74 */ + unsigned int PSPR10; /* 0x78 */ + unsigned int PSPR11; /* 0x7C */ + unsigned int PSPR12; /* 0x80 */ + unsigned int PSPR13; /* 0x84 */ + unsigned int PSPR14; /* 0x88 */ + unsigned int PSPR15; /* 0x8C */ + unsigned int AHBDMA_RACCS; /* 0x90 */ + unsigned int reserved2; /* 0x94 */ + unsigned int reserved3; /* 0x98 */ + unsigned int JSS; /* 0x9C */ + unsigned int CFC_RACC; /* 0xA0 */ + unsigned int SSP1_RACC; /* 0xA4 */ + unsigned int UART1TX_RACC; /* 0xA8 */ + unsigned int UART1RX_RACC; /* 0xAC */ + unsigned int UART2TX_RACC; /* 0xB0 */ + unsigned int UART2RX_RACC; /* 0xB4 */ + unsigned int SDC_RACC; /* 0xB8 */ + unsigned int I2SAC97_RACC; /* 0xBC */ + unsigned int IRDATX_RACC; /* 0xC0 */ + unsigned int reserved4; /* 0xC4 */ + unsigned int USBD_RACC; /* 0xC8 */ + unsigned int IRDARX_RACC; /* 0xCC */ + unsigned int IRDA_RACC; /* 0xD0 */ + unsigned int ED0_RACC; /* 0xD4 */ + unsigned int ED1_RACC; /* 0xD8 */ +}; + +/* + * ID Number 0 Register + */ +#define FTPMU010_ID_A320A 0x03200000 +#define FTPMU010_ID_A320C 0x03200010 +#define FTPMU010_ID_A320D 0x03200030 + +/* + * OSC Control Register + */ +#define FTPMU010_OSCC_OSCH_TRI (1 << 11) +#define FTPMU010_OSCC_OSCH_STABLE (1 << 9) +#define FTPMU010_OSCC_OSCH_OFF (1 << 8) + +#define FTPMU010_OSCC_OSCL_TRI (1 << 3) +#define FTPMU010_RTCLSEL (1 << 2) +#define FTPMU010_OSCC_OSCL_STABLE (1 << 1) +#define FTPMU010_OSCC_OSCL_OFF (1 << 0) + +/* + * Power Mode Register + */ +#define FTPMU010_PMODE_DIVAHBCLK_MASK (0x7 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_2 (0x0 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_3 (0x1 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_4 (0x2 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_6 (0x3 << 4) +#define FTPMU010_PMODE_DIVAHBCLK_8 (0x4 << 4) +#define FTPMU010_PMODE_FCS (1 << 2) +#define FTPMU010_PMODE_TURBO (1 << 1) +#define FTPMU010_PMODE_SLEEP (1 << 0) + +/* + * Power Manager Status Register + */ +#define FTPMU010_PMSR_SMR (1 << 10) + +#define FTPMU010_PMSR_RDH (1 << 2) +#define FTPMU010_PMSR_PH (1 << 1) +#define FTPMU010_PMSR_CKEHLOW (1 << 0) + +/* + * Multi-Function Port Setting Register + */ +#define FTPMU010_MFPSR_MODEMPINSEL (1 << 14) +#define FTPMU010_MFPSR_AC97CLKOUTSEL (1 << 13) +#define FTPMU010_MFPSR_AC97PINSEL (1 << 3) + +/* + * PLL/DLL Control Register 0 + */ +#define FTPMU010_PDLLCR0_PLL1NS(x) (((x) & 0x1ff) << 3) +#define FTPMU010_PDLLCR0_PLL1NS_VALUEOF(reg) (((reg) >> 3) & 0x1ff) +#define FTPMU010_PDLLCR0_PLL1DIS (1 << 0) + +#endif /* __FTPMU010_H */ diff --git a/include/asm-arm/arch-faraday/ftsdmc020.h b/include/asm-arm/arch-faraday/ftsdmc020.h new file mode 100644 index 0000000..0699772 --- /dev/null +++ b/include/asm-arm/arch-faraday/ftsdmc020.h @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * SDRAM Controller + */ +#ifndef __FTSDMC020_H +#define __FTSDMC020_H + +#define FTSDMC020_OFFSET_TP0 0x00 +#define FTSDMC020_OFFSET_TP1 0x04 +#define FTSDMC020_OFFSET_CR 0x08 +#define FTSDMC020_OFFSET_BANK0_BSR 0x0C +#define FTSDMC020_OFFSET_BANK1_BSR 0x10 +#define FTSDMC020_OFFSET_BANK2_BSR 0x14 +#define FTSDMC020_OFFSET_BANK3_BSR 0x18 +#define FTSDMC020_OFFSET_BANK4_BSR 0x1C +#define FTSDMC020_OFFSET_BANK5_BSR 0x20 +#define FTSDMC020_OFFSET_BANK6_BSR 0x24 +#define FTSDMC020_OFFSET_BANK7_BSR 0x28 +#define FTSDMC020_OFFSET_ACR 0x34 + +/* + * Timing Parametet 0 Register + */ +#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) +#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) +#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) +#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) +#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) + +/* + * Timing Parametet 1 Register + */ +#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) +#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) +#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) + +/* + * Configuration Register + */ +#define FTSDMC020_CR_SREF (1 << 0) +#define FTSDMC020_CR_PWDN (1 << 1) +#define FTSDMC020_CR_ISMR (1 << 2) +#define FTSDMC020_CR_IREF (1 << 3) +#define FTSDMC020_CR_IPREC (1 << 4) +#define FTSDMC020_CR_REFTYPE (1 << 5) + +/* + * SDRAM External Bank Base/Size Register + */ +#define FTSDMC020_BANK_ENABLE (1 << 28) + +#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) + +#define FTSDMC020_BANK_DDW_X4 (0 << 12) +#define FTSDMC020_BANK_DDW_X8 (1 << 12) +#define FTSDMC020_BANK_DDW_X16 (2 << 12) +#define FTSDMC020_BANK_DDW_X32 (3 << 12) + +#define FTSDMC020_BANK_DSZ_16M (0 << 8) +#define FTSDMC020_BANK_DSZ_64M (1 << 8) +#define FTSDMC020_BANK_DSZ_128M (2 << 8) +#define FTSDMC020_BANK_DSZ_256M (3 << 8) + +#define FTSDMC020_BANK_MBW_8 (0 << 4) +#define FTSDMC020_BANK_MBW_16 (1 << 4) +#define FTSDMC020_BANK_MBW_32 (2 << 4) + +#define FTSDMC020_BANK_SIZE_1M 0x0 +#define FTSDMC020_BANK_SIZE_2M 0x1 +#define FTSDMC020_BANK_SIZE_4M 0x2 +#define FTSDMC020_BANK_SIZE_8M 0x3 +#define FTSDMC020_BANK_SIZE_16M 0x4 +#define FTSDMC020_BANK_SIZE_32M 0x5 +#define FTSDMC020_BANK_SIZE_64M 0x6 +#define FTSDMC020_BANK_SIZE_128M 0x7 +#define FTSDMC020_BANK_SIZE_256M 0x8 + +/* + * Arbiter Control Register + */ +#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) +#define FTSDMC020_ACR_TOE (1 << 8) + +#endif /* __FTSDMC020_H */ diff --git a/include/asm-arm/arch-faraday/ftsmc020.h b/include/asm-arm/arch-faraday/ftsmc020.h new file mode 100644 index 0000000..43dfa61 --- /dev/null +++ b/include/asm-arm/arch-faraday/ftsmc020.h @@ -0,0 +1,79 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Static Memory Controller + */ +#ifndef __FTSMC020_H +#define __FTSMC020_H + +#ifndef __ASSEMBLY__ + +struct ftsmc020 { + struct { + unsigned int cr; /* 0x00, 0x08, 0x10, 0x18 */ + unsigned int tpr; /* 0x04, 0x0c, 0x14, 0x1c */ + } bank[4]; + unsigned int pad[8]; /* 0x20 - 0x3c */ + unsigned int ssr; /* 0x40 */ +}; + +void ftsmc020_init (void); + +#endif /* __ASSEMBLY__ */ + +/* + * Memory Bank Configuration Register + */ +#define FTSMC020_BANK_ENABLE (1 << 28) +#define FTSMC020_BANK_BASE(x) ((x) & 0x0fff1000) + +#define FTSMC020_BANK_WPROT (1 << 11) + +#define FTSMC020_BANK_SIZE_32K (0xb << 4) +#define FTSMC020_BANK_SIZE_64K (0xc << 4) +#define FTSMC020_BANK_SIZE_128K (0xd << 4) +#define FTSMC020_BANK_SIZE_256K (0xe << 4) +#define FTSMC020_BANK_SIZE_512K (0xf << 4) +#define FTSMC020_BANK_SIZE_1M (0x0 << 4) +#define FTSMC020_BANK_SIZE_2M (0x1 << 4) +#define FTSMC020_BANK_SIZE_4M (0x2 << 4) +#define FTSMC020_BANK_SIZE_8M (0x3 << 4) +#define FTSMC020_BANK_SIZE_16M (0x4 << 4) +#define FTSMC020_BANK_SIZE_32M (0x5 << 4) + +#define FTSMC020_BANK_MBW_8 (0x0 << 0) +#define FTSMC020_BANK_MBW_16 (0x1 << 0) +#define FTSMC020_BANK_MBW_32 (0x2 << 0) + +/* + * Memory Bank Timing Parameter Register + */ +#define FTSMC020_TPR_ETRNA(x) (((x) & 0xf) << 28) +#define FTSMC020_TPR_EATI(x) (((x) & 0xf) << 24) +#define FTSMC020_TPR_RBE (1 << 20) +#define FTSMC020_TPR_AST(x) (((x) & 0x3) << 18) +#define FTSMC020_TPR_CTW(x) (((x) & 0x3) << 16) +#define FTSMC020_TPR_ATI(x) (((x) & 0xf) << 12) +#define FTSMC020_TPR_AT2(x) (((x) & 0x3) << 8) +#define FTSMC020_TPR_WTC(x) (((x) & 0x3) << 6) +#define FTSMC020_TPR_AHT(x) (((x) & 0x3) << 4) +#define FTSMC020_TPR_TRNA(x) (((x) & 0xf) << 0) + +#endif /* __FTSMC020_H */ diff --git a/include/asm-arm/arch-faraday/fttmr010.h b/include/asm-arm/arch-faraday/fttmr010.h new file mode 100644 index 0000000..72abcb3 --- /dev/null +++ b/include/asm-arm/arch-faraday/fttmr010.h @@ -0,0 +1,73 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* + * Timer + */ +#ifndef __FTTMR010_H +#define __FTTMR010_H + +struct fttmr010 { + unsigned int timer1_counter; /* 0x00 */ + unsigned int timer1_load; /* 0x04 */ + unsigned int timer1_match1; /* 0x08 */ + unsigned int timer1_match2; /* 0x0c */ + unsigned int timer2_counter; /* 0x10 */ + unsigned int timer2_load; /* 0x14 */ + unsigned int timer2_match1; /* 0x18 */ + unsigned int timer2_match2; /* 0x1c */ + unsigned int timer3_counter; /* 0x20 */ + unsigned int timer3_load; /* 0x24 */ + unsigned int timer3_match1; /* 0x28 */ + unsigned int timer3_match2; /* 0x2c */ + unsigned int cr; /* 0x30 */ + unsigned int interrupt_state; /* 0x34 */ + unsigned int interrupt_mask; /* 0x38 */ +}; + +/* + * Timer Control Register + */ +#define FTTMR010_TM3_UPDOWN (1 << 11) +#define FTTMR010_TM2_UPDOWN (1 << 10) +#define FTTMR010_TM1_UPDOWN (1 << 9) +#define FTTMR010_TM3_OFENABLE (1 << 8) +#define FTTMR010_TM3_CLOCK (1 << 7) +#define FTTMR010_TM3_ENABLE (1 << 6) +#define FTTMR010_TM2_OFENABLE (1 << 5) +#define FTTMR010_TM2_CLOCK (1 << 4) +#define FTTMR010_TM2_ENABLE (1 << 3) +#define FTTMR010_TM1_OFENABLE (1 << 2) +#define FTTMR010_TM1_CLOCK (1 << 1) +#define FTTMR010_TM1_ENABLE (1 << 0) + +/* + * Timer Interrupt State & Mask Registers + */ +#define FTTMR010_TM3_OVERFLOW (1 << 8) +#define FTTMR010_TM3_MATCH2 (1 << 7) +#define FTTMR010_TM3_MATCH1 (1 << 6) +#define FTTMR010_TM2_OVERFLOW (1 << 5) +#define FTTMR010_TM2_MATCH2 (1 << 4) +#define FTTMR010_TM2_MATCH1 (1 << 3) +#define FTTMR010_TM1_OVERFLOW (1 << 2) +#define FTTMR010_TM1_MATCH2 (1 << 1) +#define FTTMR010_TM1_MATCH1 (1 << 0) + +#endif /* __FTTMR010_H */ diff --git a/include/configs/a320.h b/include/configs/a320.h new file mode 100644 index 0000000..daa17c4 --- /dev/null +++ b/include/configs/a320.h @@ -0,0 +1,235 @@ +/* + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * Configuation settings for the Faraday A320 board. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * CPU and Board Configuration Options + */ +#define CONFIG_A320 /* in a Faraday A320 SoC/Board */ + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#undef CONFIG_SKIP_LOWLEVEL_INIT + +/*----------------------------------------------------------------------- + * Timer + */ +#define CONFIG_SYS_HZ 1000 /* timer ticks per second */ +#define CONFIG_SYS_TIMERBASE 0x98400000 + +/*----------------------------------------------------------------------- + * RTC + */ +#define CONFIG_RTC_FTRTC010 +#define CONFIG_SYS_RTC_BASE 0x98600000 + +/*----------------------------------------------------------------------- + * Serial console configuration + */ + +/* FTUART is a high speed NS 16C550A compatible UART */ +#define CONFIG_BAUDRATE 38400 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_COM1 0x98200000 +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_CLK 18432000 + +/* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/*----------------------------------------------------------------------- + * Ethernet + */ +#define CONFIG_NET_MULTI +#define CONFIG_DRIVER_FTMAC100 +#define CONFIG_SYS_MAC100_BASE 0x90900000 + +#define CONFIG_BOOTDELAY 3 + +/*----------------------------------------------------------------------- + * Hardware register bases + */ +#define CONFIG_SYS_AHBC_BASE 0x90100000 /* AHB Controller */ +#define CONFIG_SYS_SMC_BASE 0x90200000 /* Static Memory Controller */ +#define CONFIG_SYS_DEBUG_LED 0x902ffffc /* Debug LED */ +#define CONFIG_SYS_SDMC_BASE 0x90300000 /* SDRAM Controller */ + +#define CONFIG_SYS_FTPMU_BASE 0x98100000 /* Power Management Unit */ + +/*----------------------------------------------------------------------- + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_PING + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "A320 # " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) + +/* max number of command args */ +#define CONFIG_SYS_MAXARGS 16 + +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ +#endif + +/*----------------------------------------------------------------------- + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) + +/*----------------------------------------------------------------------- + * size in bytes reserved for initial data +*/ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/*----------------------------------------------------------------------- + * SDRAM controller configuration + */ +#define CONFIG_SYS_FTSDMC020_TP0 (FTSDMC020_TP0_TRAS(2) | \ + FTSDMC020_TP0_TRP(1) | \ + FTSDMC020_TP0_TRCD(1) | \ + FTSDMC020_TP0_TRF(3) | \ + FTSDMC020_TP0_TWR(1) | \ + FTSDMC020_TP0_TCL(2)) + +#define CONFIG_SYS_FTSDMC020_TP1 (FTSDMC020_TP1_INI_PREC(4) | \ + FTSDMC020_TP1_INI_REFT(8) | \ + FTSDMC020_TP1_REF_INTV(0x180)) + +#define CONFIG_SYS_FTSDMC020_BANK0_BSR (FTSDMC020_BANK_ENABLE | \ + FTSDMC020_BANK_DDW_X16 | \ + FTSDMC020_BANK_DSZ_256M | \ + FTSDMC020_BANK_MBW_32 | \ + FTSDMC020_BANK_SIZE_64M) + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ + +/* + * Load address and memory test area should agree with + * board/faraday/a320/config.mk. Be careful not to overwrite U-boot itself. + */ +#define CONFIG_SYS_LOAD_ADDR 0x02000000 + +/* memtest works on 63 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x00000000 +#define CONFIG_SYS_MEMTEST_END 0x03F00000 + +/*----------------------------------------------------------------------- + * Static memory controller configuration + */ + +#include <asm/arch/ftsmc020.h> + +#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ + FTSMC020_BANK_SIZE_1M | \ + FTSMC020_BANK_MBW_8) + +#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_RBE | \ + FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define FTSMC020_BANK1_CONFIG (FTSMC020_BANK_ENABLE | \ + FTSMC020_BANK_BASE(PHYS_FLASH_2) | \ + FTSMC020_BANK_SIZE_32M | \ + FTSMC020_BANK_MBW_32) + +#define FTSMC020_BANK1_TIMING (FTSMC020_TPR_AST(3) | \ + FTSMC020_TPR_CTW(3) | \ + FTSMC020_TPR_ATI(0xf) | \ + FTSMC020_TPR_AT2(3) | \ + FTSMC020_TPR_WTC(3) | \ + FTSMC020_TPR_AHT(3) | \ + FTSMC020_TPR_TRNA(0xf)) + +#define CONFIG_SYS_FTSMC020_CONFIGS { \ + { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ + { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ +} + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ + +/* no environments */ +#define CONFIG_ENV_IS_NOWHERE + +/* Total Size of Environment Sector */ +#define CONFIG_ENV_SIZE 0x20000 + +/* use CFI framework */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER + +/* support JEDEC */ +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx8 + +#define PHYS_FLASH_1 0x80000000 +#define PHYS_FLASH_2 0x80400000 +#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2, } + +#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 + +/* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +/* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +#undef CONFIG_SYS_FLASH_EMPTY_INFO + +#endif /* __CONFIG_H */ -- 1.6.3.3

3 13

[U-Boot] [PATCH v3] create and use common code for Matrix Vision boards
by André Schwarz 19 Aug '09

19 Aug '09

This patch adds and uses common code for all Matrix Vision boards. Signed-off-by: André Schwarz <andre.schwarz(a)matrix-vision.de> --- Heiko's comments have been addressed and common/mv_common.h has been included where needed. board/matrix_vision/common/Makefile | 54 ++++++++++++++ board/matrix_vision/common/mv_common.c | 125 ++++++++++++++++++++++++++++++++ board/matrix_vision/common/mv_common.h | 25 +++++++ board/matrix_vision/mvbc_p/mvbc_p.c | 76 +------------------- board/matrix_vision/mvblm7/mvblm7.c | 38 +++------- board/matrix_vision/mvblm7/pci.c | 35 ++-------- include/configs/MVBC_P.h | 14 +++- include/configs/MVBLM7.h | 49 +++++-------- 8 files changed, 254 insertions(+), 162 deletions(-) diff --git a/board/matrix_vision/common/Makefile b/board/matrix_vision/common/Makefile new file mode 100644 index 0000000..b496258 --- /dev/null +++ b/board/matrix_vision/common/Makefile @@ -0,0 +1,54 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).a + +COBJS-y = mv_common.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c new file mode 100644 index 0000000..284de16 --- /dev/null +++ b/board/matrix_vision/common/mv_common.c @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2008 + * Andre Schwarz, Matrix Vision GmbH, andre.schwarz(a)matrix-vision.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <environment.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +static char* entries_to_keep[] = { + "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt", + "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr", + "static_ipaddr", "static_netmask", "static_gateway", + "syslog", "watchdog", "netboot", "evo8serialnumber" }; + +#define MV_MAX_ENV_ENTRY_LENGTH 64 +#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep) + +void mv_reset_environment(void) +{ + int i; + char *s[MV_KEEP_ENTRIES]; + char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH]; + + printf("\n*** RESET ENVIRONMENT ***\n"); + + memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH); + for (i = 0; i < MV_KEEP_ENTRIES; i++) { + s[i] = getenv(entries_to_keep[i]); + if (s[i]) { + printf("save '%s' : %s\n", entries_to_keep[i], s[i]); + strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH); + } + } + + gd->env_valid = 0; + env_relocate(); + + for (i = 0; i < MV_KEEP_ENTRIES; i++) { + if (s[i]) { + printf("restore '%s' : %s\n", entries_to_keep[i], s[i]); + setenv(entries_to_keep[i], s[i]); + } + } + + saveenv(); +} + +int mv_load_fpga(void) +{ + int result; + size_t data_size = 0; + void *fpga_data = NULL; + char *datastr = getenv("fpgadata"); + char *sizestr = getenv("fpgadatasize"); + + if (getenv("skip_fpga")) { + printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); + return -1; + } + printf("loading FPGA\n"); + + if (datastr) + fpga_data = (void *)simple_strtoul(datastr, NULL, 16); + if (sizestr) + data_size = (size_t)simple_strtoul(sizestr, NULL, 16); + if (!data_size) { + printf("fpgadatasize invalid -> FPGA _not_ loaded !\n"); + return -1; + } + + result = fpga_load(0, fpga_data, data_size); + if (!result) + show_boot_progress(0); + + return result; +} + +u8 *dhcp_vendorex_prep(u8 *e) +{ + char *ptr; + + /* DHCP vendor-class-identifier = 60 */ + if ((ptr = getenv("dhcp_vendor-class-identifier"))) { + *e++ = 60; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + /* DHCP_CLIENT_IDENTIFIER = 61 */ + if ((ptr = getenv("dhcp_client_id"))) { + *e++ = 61; + *e++ = strlen(ptr); + while (*ptr) + *e++ = *ptr++; + } + + return e; +} + +u8 *dhcp_vendorex_proc(u8 *popt) +{ + return NULL; +} diff --git a/board/matrix_vision/common/mv_common.h b/board/matrix_vision/common/mv_common.h new file mode 100644 index 0000000..046c038 --- /dev/null +++ b/board/matrix_vision/common/mv_common.h @@ -0,0 +1,25 @@ +/* + * Copyright 2008 Matrix Vision GmbH + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +extern int mv_load_fpga(void); +extern void mv_reset_environment(void); diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c index a300342..4ebe185 100644 --- a/board/matrix_vision/mvbc_p/mvbc_p.c +++ b/board/matrix_vision/mvbc_p/mvbc_p.c @@ -39,6 +39,7 @@ #include <asm/io.h> #include "fpga.h" #include "mvbc_p.h" +#include "../common/mv_common.h" #define SDRAM_MODE 0x00CD0000 #define SDRAM_CONTROL 0x504F0000 @@ -134,23 +135,6 @@ void mvbc_init_gpio(void) printf("sint_gpioe : 0x%08x\n", gpio->sint_gpioe); } -void reset_environment(void) -{ - char *s, sernr[64]; - - printf("\n*** RESET ENVIRONMENT ***\n"); - memset(sernr, 0, sizeof(sernr)); - s = getenv("serial#"); - if (s) { - printf("found serial# : %s\n", s); - strncpy(sernr, s, 64); - } - gd->env_valid = 0; - env_relocate(); - if (s) - setenv("serial#", sernr); -} - int misc_init_r(void) { char *s = getenv("reset_env"); @@ -166,7 +150,7 @@ int misc_init_r(void) return 0; } printf(" === FACTORY RESET ===\n"); - reset_environment(); + mv_reset_environment(); saveenv(); return -1; @@ -234,69 +218,15 @@ struct pci_controller hose = { fixup_irq:pci_mvbc_fixup_irq }; -int mvbc_p_load_fpga(void) -{ - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - - return fpga_load(0, fpga_data, data_size); -} - extern void pci_mpc5xxx_init(struct pci_controller *); void pci_init_board(void) { - char *s; - int load_fpga = 1; - mvbc_p_init_fpga(); - s = getenv("skip_fpga"); - if (s) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - load_fpga = 0; - } - if (load_fpga) { - printf("loading FPGA ... "); - mvbc_p_load_fpga(); - printf("done\n"); - } + mv_load_fpga(); pci_mpc5xxx_init(&hose); } -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - - return e; -} - -u8 *dhcp_vendorex_proc (u8 *popt) -{ - return NULL; -} - void show_boot_progress(int val) { struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio*)MPC5XXX_GPIO; diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c index 6984af9..2cecd1f 100644 --- a/board/matrix_vision/mvblm7/mvblm7.c +++ b/board/matrix_vision/mvblm7/mvblm7.c @@ -64,7 +64,7 @@ int fixed_sdram(void) im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2; im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE; im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL; - im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL; + im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL; udelay(300); @@ -88,40 +88,22 @@ phys_size_t initdram(int board_type) return msize * 1024 * 1024; } -int checkboard(void) +int misc_init_r(void) { - puts("Board: Matrix Vision mvBlueLYNX-M7\n"); - - return 0; -} + char *s = getenv("reset_env"); -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - ptr = getenv("dhcp_vendor-class-identifier"); - if (ptr) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - ptr = getenv("dhcp_client_id"); - if (ptr) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; + if (s) { + mv_reset_environment(); } - return e; + return 0; } -u8 *dhcp_vendorex_proc(u8 *popt) +int checkboard(void) { - return NULL; + puts("Board: Matrix Vision mvBlueLYNX-M7\n"); + + return 0; } #ifdef CONFIG_HARD_SPI diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c index 9f31719..2db51f1 100644 --- a/board/matrix_vision/mvblm7/pci.c +++ b/board/matrix_vision/mvblm7/pci.c @@ -32,24 +32,10 @@ #include <fpga.h> #include "mvblm7.h" #include "fpga.h" +#include "../common/mv_common.h" DECLARE_GLOBAL_DATA_PTR; -int mvblm7_load_fpga(void) -{ - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - - return fpga_load(0, fpga_data, data_size); -} - static struct pci_region pci_regions[] = { { bus_start: CONFIG_SYS_PCI1_MEM_BASE, @@ -73,10 +59,8 @@ static struct pci_region pci_regions[] = { void pci_init_board(void) { - char *s; int i; int warmboot; - int load_fpga; volatile immap_t *immr; volatile pcictrl83xx_t *pci_ctrl; volatile gpio83xx_t *gpio; @@ -84,32 +68,23 @@ void pci_init_board(void) volatile law83xx_t *pci_law; struct pci_region *reg[] = { pci_regions }; - load_fpga = 1; immr = (immap_t *) CONFIG_SYS_IMMR; clk = (clk83xx_t *) &immr->clk; pci_ctrl = immr->pci_ctrl; pci_law = immr->sysconf.pcilaw; gpio = (volatile gpio83xx_t *)&immr->gpio[0]; - s = getenv("skip_fpga"); - if (s) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - load_fpga = 0; - } - gpio->dat = MV_GPIO_DAT; gpio->odr = MV_GPIO_ODE; - if (load_fpga) - gpio->dir = MV_GPIO_OUT; - else - gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); + gpio->dir = MV_GPIO_OUT; printf("SICRH / SICRL : 0x%08x / 0x%08x\n", immr->sysconf.sicrh, immr->sysconf.sicrl); mvblm7_init_fpga(); - if (load_fpga) - mvblm7_load_fpga(); + mv_load_fpga(); + + gpio->dir = MV_GPIO_OUT & ~(FPGA_DIN|FPGA_CCLK); /* Enable PCI_CLK_OUTPUTs 0 and 1 with 1:1 clocking */ clk->occr = 0xc0000000; diff --git a/include/configs/MVBC_P.h b/include/configs/MVBC_P.h index edbc701..867e8e0 100644 --- a/include/configs/MVBC_P.h +++ b/include/configs/MVBC_P.h @@ -68,9 +68,9 @@ #define MV_VCI mvBlueCOUGAR-P #define MV_FPGA_DATA 0xff860000 #define MV_FPGA_SIZE 0x0003c886 -#define MV_KERNEL_ADDR 0xffc00000 +#define MV_KERNEL_ADDR 0xffd00000 #define MV_INITRD_ADDR 0xff900000 -#define MV_INITRD_LENGTH 0x00300000 +#define MV_INITRD_LENGTH 0x00400000 #define MV_SCRATCH_ADDR 0x00000000 #define MV_SCRATCH_LENGTH MV_INITRD_LENGTH #define MV_SOURCE_ADDR 0xff840000 @@ -105,6 +105,7 @@ #define CONFIG_CMD_SDRAM #define CONFIG_CMD_PCI #define CONFIG_CMD_FPGA +#define CONFIG_CMD_I2C #undef CONFIG_WATCHDOG @@ -182,6 +183,7 @@ "propdev_debug=0\0" \ "gevss_debug=0\0" \ "watchdog=1\0" \ + "sensor_cnt=1\0" \ "" #undef XMK_STR @@ -249,6 +251,14 @@ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* + * I2C configuration + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_MODULE 1 +#define CONFIG_SYS_I2C_SPEED 86000 +#define CONFIG_SYS_I2C_SLAVE 0x7F + +/* * Ethernet configuration */ #define CONFIG_NET_MULTI diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index ac8cb57..3e3a2c0 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -47,10 +47,9 @@ #define CONFIG_MPC8XXX_SPI #define CONFIG_HARD_SPI #define MVBLM7_MMC_CS 0x04000000 +#define CONFIG_MISC_INIT_R /* I2C */ -#undef CONFIG_SOFT_I2C - #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_OFFSET 0x3000 @@ -62,44 +61,36 @@ /* * DDR Setup */ +#undef CONFIG_SPD_EEPROM + #define CONFIG_SYS_DDR_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE #define CONFIG_SYS_83XX_DDR_USES_CS0 1 #define CONFIG_SYS_MEMTEST_START (60<<20) #define CONFIG_SYS_MEMTEST_END (70<<20) +#define CONFIG_VERY_BIG_RAM -#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ - DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 - -#define CONFIG_SYS_DDR_SIZE 256 +#define CONFIG_SYS_DDRCDR 0x22000001 +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 -/* HC, 75Ohm, DDR-II, DRQ */ -#define CONFIG_SYS_DDRCDR 0x80000001 -/* EN, ODT_WR, 3BA, 14row, 10col */ -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014102 -#define CONFIG_SYS_DDR_CS1_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS2_CONFIG 0x0 -#define CONFIG_SYS_DDR_CS3_CONFIG 0x0 +#define CONFIG_SYS_DDR_SIZE 512 -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f -#define CONFIG_SYS_DDR_CS1_BNDS 0x0 -#define CONFIG_SYS_DDR_CS2_BNDS 0x0 -#define CONFIG_SYS_DDR_CS3_BNDS 0x0 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 -#define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_TIMING_0 0x00260802 -#define CONFIG_SYS_DDR_TIMING_1 0x2625b221 -#define CONFIG_SYS_DDR_TIMING_2 0x1f9820c7 -#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 0x00260802 +#define CONFIG_SYS_DDR_TIMING_1 0x3837c322 +#define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 -/* ~MEM_EN, SREN, DDR-II, 32_BE */ -#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080000 +#define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 -#define CONFIG_SYS_DDR_INTERVAL 0x04060100 +#define CONFIG_SYS_DDR_INTERVAL 0x02000100 -#define CONFIG_SYS_DDR_MODE 0x078e0232 +#define CONFIG_SYS_DDR_MODE 0x04040242 +#define CONFIG_SYS_DDR_MODE2 0x00800000 /* Flash */ #define CONFIG_SYS_FLASH_CFI @@ -405,8 +396,8 @@ #define MV_CI mvBL-M7 #define MV_VCI mvBL-M7 -#define MV_FPGA_DATA 0xfff80000 -#define MV_FPGA_SIZE 0x00076ca2 +#define MV_FPGA_DATA 0xfff40000 +#define MV_FPGA_SIZE 0 #define MV_KERNEL_ADDR 0xff810000 #define MV_INITRD_ADDR 0xffb00000 #define MV_SOURCE_ADDR 0xff804000 @@ -453,7 +444,7 @@ "static_ipaddr=192.168.90.10\0" \ "static_netmask=255.255.255.0\0" \ "static_gateway=0.0.0.0\0" \ - "initrd_name=uInitrd.mvblm7-xenorfs\0" \ + "initrd_name=uInitrd.mvBL-M7-rfs\0" \ "zcip=no\0" \ "netboot=yes\0" \ "mvtest=Ff\0" \ MATRIX VISION GmbH, Talstrasse 16, DE-71570 Oppenweiler Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschiaeftsf�hrer: Gerhard Thullner, Werner Armingeon, Uwe Furtner, Hans-Joachim Reich

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