June 2009 - U-Boot

[U-Boot] [PATCH] Add AVR32 LCD support
by Mark Jackson 13 Jun '09

13 Jun '09

This patch adds support for the AVR32 LCD controller. This patch is based off the latest Denx master (not the current AVR32 git). A quick summary of what's going on:- Enable LCDC pixel clock Enable LCDC port pins Correctly specify LCDC guard time Add framebuffer pointer to global_data struct Allocate framebuffer To use the new code, update your board config to include something like this:- #define CONFIG_LCD 1 #if defined(CONFIG_LCD) #define CONFIG_CMD_BMP #define CONFIG_ATMEL_LCD 1 #define LCD_BPP LCD_COLOR16 #define CONFIG_BMP_16BPP 1 #define CONFIG_FB_ADDR 0x10600000 #define CONFIG_WHITE_ON_BLACK 1 #define CONFIG_VIDEO_BMP_GZIP 1 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE 262144 #define CONFIG_ATMEL_LCD_BGR555 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 #define CONFIG_SPLASH_SCREEN 1 #endif The standard U-Boot BMP and Splash-screen features should just work. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- cpu/at32ap/at32ap700x/clk.c | 5 + cpu/at32ap/at32ap700x/portmux.c | 90 +++++++++++++++++++++ drivers/video/atmel_lcdfb.c | 5 +- include/asm-avr32/arch-at32ap700x/chip-features.h | 5 + include/asm-avr32/arch-at32ap700x/clk.h | 6 ++ include/asm-avr32/arch-at32ap700x/portmux.h | 5 +- include/asm-avr32/global_data.h | 3 + include/lcd.h | 2 +- lib_avr32/board.c | 11 +++ 9 files changed, 128 insertions(+), 4 deletions(-) diff --git a/cpu/at32ap/at32ap700x/clk.c b/cpu/at32ap/at32ap700x/clk.c index 2c2e19c..742bc6b 100644 --- a/cpu/at32ap/at32ap700x/clk.c +++ b/cpu/at32ap/at32ap700x/clk.c @@ -65,6 +65,11 @@ void clk_init(void) #ifdef CONFIG_PLL /* Use PLL0 as main clock */ sm_writel(PM_MCCTRL, SM_BIT(PLLSEL)); + +#ifdef CONFIG_LCD + /* Set up pixel clock for the LCDC */ + sm_writel(PM_GCCTRL(7), SM_BIT(PLLSEL) | SM_BIT(CEN)); +#endif #endif } diff --git a/cpu/at32ap/at32ap700x/portmux.c b/cpu/at32ap/at32ap700x/portmux.c index 2a3b004..e71b2bf 100644 --- a/cpu/at32ap/at32ap700x/portmux.c +++ b/cpu/at32ap/at32ap700x/portmux.c @@ -202,3 +202,93 @@ void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength) PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH); } #endif + +#ifdef AT32AP700x_CHIP_HAS_LCDC +void portmux_enable_lcdc(int pin_config) +{ + unsigned long portc_mask = 0; + unsigned long portd_mask = 0; + unsigned long porte_mask = 0; + + switch(pin_config) { + case 0: + portc_mask = (1 << 19) /* CC */ + | (1 << 20) /* HSYNC */ + | (1 << 21) /* PCLK */ + | (1 << 22) /* VSYNC */ + | (1 << 23) /* DVAL */ + | (1 << 24) /* MODE */ + | (1 << 25) /* PWR */ + | (1 << 26) /* DATA0 */ + | (1 << 27) /* DATA1 */ + | (1 << 28) /* DATA2 */ + | (1 << 29) /* DATA3 */ + | (1 << 30) /* DATA4 */ + | (1 << 31); /* DATA5 */ + + portd_mask = (1 << 0) /* DATA6 */ + | (1 << 1) /* DATA7 */ + | (1 << 2) /* DATA8 */ + | (1 << 3) /* DATA9 */ + | (1 << 4) /* DATA10 */ + | (1 << 5) /* DATA11 */ + | (1 << 6) /* DATA12 */ + | (1 << 7) /* DATA13 */ + | (1 << 8) /* DATA14 */ + | (1 << 9) /* DATA15 */ + | (1 << 10) /* DATA16 */ + | (1 << 11) /* DATA17 */ + | (1 << 12) /* DATA18 */ + | (1 << 13) /* DATA19 */ + | (1 << 14) /* DATA20 */ + | (1 << 15) /* DATA21 */ + | (1 << 16) /* DATA22 */ + | (1 << 17); /* DATA23 */ + break; + + case 1: + portc_mask = (1 << 20) /* HSYNC */ + | (1 << 21) /* PCLK */ + | (1 << 22) /* VSYNC */ + | (1 << 25) /* PWR */ + | (1 << 31); /* DATA5 */ + + portd_mask = (1 << 0) /* DATA6 */ + | (1 << 1) /* DATA7 */ + | (1 << 7) /* DATA13 */ + | (1 << 8) /* DATA14 */ + | (1 << 9) /* DATA15 */ + | (1 << 16) /* DATA22 */ + | (1 << 17); /* DATA23 */ + + porte_mask = (1 << 0) /* CC */ + | (1 << 1) /* DVAL */ + | (1 << 2) /* MODE */ + | (1 << 3) /* DATA0 */ + | (1 << 4) /* DATA1 */ + | (1 << 5) /* DATA2 */ + | (1 << 6) /* DATA3 */ + | (1 << 7) /* DATA4 */ + | (1 << 8) /* DATA8 */ + | (1 << 9) /* DATA9 */ + | (1 << 10) /* DATA10 */ + | (1 << 11) /* DATA11 */ + | (1 << 12) /* DATA12 */ + | (1 << 13) /* DATA16 */ + | (1 << 14) /* DATA17 */ + | (1 << 15) /* DATA18 */ + | (1 << 16) /* DATA19 */ + | (1 << 17) /* DATA20 */ + | (1 << 18); /* DATA21 */ + break; + } + + /* REVISIT: Some pins are probably pure outputs */ + portmux_select_peripheral(PORTMUX_PORT_C, portc_mask, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); + portmux_select_peripheral(PORTMUX_PORT_D, portd_mask, + PORTMUX_FUNC_A, PORTMUX_BUSKEEPER); + portmux_select_peripheral(PORTMUX_PORT_E, porte_mask, + PORTMUX_FUNC_B, PORTMUX_BUSKEEPER); +} +#endif diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 3a51cc7..14f578e 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -42,6 +42,7 @@ short console_row; /* configurable parameters */ #define ATMEL_LCDC_CVAL_DEFAULT 0xc8 #define ATMEL_LCDC_DMA_BURST_LEN 8 +#define ATMEL_LCDC_GUARD_TIME 2 #if defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91CAP9) #define ATMEL_LCDC_FIFO_SIZE 2048 @@ -69,7 +70,7 @@ void lcd_ctrl_init(void *lcdbase) /* Turn off the LCD controller and the DMA controller */ lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, - 1 << ATMEL_LCDC_GUARDT_OFFSET); + ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET); /* Wait for the LCDC core to become idle */ while (lcdc_readl(panel_info.mmio, ATMEL_LCDC_PWRCON) & ATMEL_LCDC_BUSY) @@ -150,7 +151,7 @@ void lcd_ctrl_init(void *lcdbase) lcdc_writel(panel_info.mmio, ATMEL_LCDC_DMACON, ATMEL_LCDC_DMAEN); lcdc_writel(panel_info.mmio, ATMEL_LCDC_PWRCON, - (1 << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); + (ATMEL_LCDC_GUARD_TIME << ATMEL_LCDC_GUARDT_OFFSET) | ATMEL_LCDC_PWR); } ulong calc_fbsize(void) diff --git a/include/asm-avr32/arch-at32ap700x/chip-features.h b/include/asm-avr32/arch-at32ap700x/chip-features.h index c47107e..40a2476 100644 --- a/include/asm-avr32/arch-at32ap700x/chip-features.h +++ b/include/asm-avr32/arch-at32ap700x/chip-features.h @@ -32,4 +32,9 @@ #define AT32AP700x_CHIP_HAS_MACB #endif +/* AP7000 and AP7002 have LCD controller, but AP7001 does not */ +#if defined(CONFIG_AT32AP7000) || defined(CONFIG_AT32AP7002) +#define AT32AP700x_CHIP_HAS_LCDC +#endif + #endif /* __ASM_AVR32_ARCH_CHIP_FEATURES_H__ */ diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index d83e93b..7a0b655 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -83,6 +83,12 @@ static inline unsigned long get_spi_clk_rate(unsigned int dev_id) return get_pba_clk_rate(); } #endif +#ifdef AT32AP700x_CHIP_HAS_LCDC +static inline unsigned long get_lcdc_clk_rate(unsigned int dev_id) +{ + return get_hsb_clk_rate(); +} +#endif extern void clk_init(void); diff --git a/include/asm-avr32/arch-at32ap700x/portmux.h b/include/asm-avr32/arch-at32ap700x/portmux.h index 96fe70d..8574aec 100644 --- a/include/asm-avr32/arch-at32ap700x/portmux.h +++ b/include/asm-avr32/arch-at32ap700x/portmux.h @@ -85,5 +85,8 @@ void portmux_enable_mmci(unsigned int slot, unsigned long flags, void portmux_enable_spi0(unsigned long cs_mask, unsigned long drive_strength); void portmux_enable_spi1(unsigned long cs_mask, unsigned long drive_strength); #endif - +#ifdef AT32AP700x_CHIP_HAS_LCDC +void portmux_enable_lcdc(int pin_config); +#endif + #endif /* __ASM_AVR32_ARCH_PORTMUX_H__ */ diff --git a/include/asm-avr32/global_data.h b/include/asm-avr32/global_data.h index 97a6c61..efbdda9 100644 --- a/include/asm-avr32/global_data.h +++ b/include/asm-avr32/global_data.h @@ -42,6 +42,9 @@ typedef struct global_data { unsigned long env_addr; /* Address of env struct */ unsigned long env_valid; /* Checksum of env valid? */ unsigned long cpu_hz; /* cpu core clock frequency */ +#if defined(CONFIG_LCD) + void *fb_base; /* framebuffer address */ +#endif void **jt; /* jump table */ } gd_t; diff --git a/include/lcd.h b/include/lcd.h index f054cac..0d6549c 100644 --- a/include/lcd.h +++ b/include/lcd.h @@ -314,7 +314,7 @@ void lcd_show_board_info(void); #if LCD_BPP == LCD_MONOCHROME # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) -#elif LCD_BPP == LCD_COLOR8 +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) # define COLOR_MASK(c) (c) #else # error Unsupported LCD BPP. diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 57115df..1389ada 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -239,6 +239,17 @@ void board_init_f(ulong board_type) addr -= CONFIG_SYS_DMA_ALLOC_LEN; #endif +#ifdef CONFIG_LCD +#ifdef CONFIG_FB_ADDR + printf("LCD: Frame buffer allocated at preset 0x%08x\n", CONFIG_FB_ADDR); + gd->fb_base = (void*)CONFIG_FB_ADDR; +#else + addr = lcd_setmem(addr); + printf("LCD: Frame buffer allocated at 0x%08lx\n", addr); + gd->fb_base = (void*)addr; +#endif /* CONFIG_FB_ADDR */ +#endif /* CONFIG_LCD */ + /* Allocate a Board Info struct on a word boundary */ addr -= sizeof(bd_t); addr &= ~3UL;

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[U-Boot] [PATCH 1/5] pm9263: lowlevel init update
by Jean-Christophe PLAGNIOL-VILLARD 13 Jun '09

13 Jun '09

move PSRAM init to pm9263.c this will allow us after to make the nor lowlevel_init generic Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- board/ronetix/pm9263/lowlevel_init.S | 17 +---------------- board/ronetix/pm9263/pm9263.c | 21 +++++++++++++++++++++ include/configs/pm9263.h | 10 +--------- 3 files changed, 23 insertions(+), 25 deletions(-) diff --git a/board/ronetix/pm9263/lowlevel_init.S b/board/ronetix/pm9263/lowlevel_init.S index c048c91..561722c 100644 --- a/board/ronetix/pm9263/lowlevel_init.S +++ b/board/ronetix/pm9263/lowlevel_init.S @@ -194,12 +194,10 @@ SMRDATA: .word (AT91_BASE_SYS + AT91_MATRIX_EBI0CSA) .word CONFIG_SYS_MATRIX_EBI0CSA_VAL - .word (AT91_BASE_SYS + AT91_MATRIX_EBI1CSA) - .word CONFIG_SYS_MATRIX_EBI1CSA_VAL /* flash */ .word (AT91_BASE_SYS + AT91_SMC_MODE(0)) - .word CONFIG_SYS_SMC0_CTRL0_VAL + .word CONFIG_SYS_SMC0_MODE0_VAL .word (AT91_BASE_SYS + AT91_SMC_CYCLE(0)) .word CONFIG_SYS_SMC0_CYCLE0_VAL @@ -210,19 +208,6 @@ SMRDATA: .word (AT91_BASE_SYS + AT91_SMC_SETUP(0)) .word CONFIG_SYS_SMC0_SETUP0_VAL - /* PSRAM */ - .word (AT91_BASE_SYS + AT91_SMC1_MODE(0)) - .word CONFIG_SYS_SMC1_CTRL0_VAL - - .word (AT91_BASE_SYS + AT91_SMC1_CYCLE(0)) - .word CONFIG_SYS_SMC1_CYCLE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC1_PULSE(0)) - .word CONFIG_SYS_SMC1_PULSE0_VAL - - .word (AT91_BASE_SYS + AT91_SMC1_SETUP(0)) - .word CONFIG_SYS_SMC1_SETUP0_VAL - SMRDATA1: .word (AT91_BASE_SYS + AT91_SDRAMC_MR) .word CONFIG_SYS_SDRC_MR_VAL1 diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c index d2598a0..8ca71da 100644 --- a/board/ronetix/pm9263/pm9263.c +++ b/board/ronetix/pm9263/pm9263.c @@ -165,6 +165,27 @@ void lcd_disable(void) static int pm9263_lcd_hw_psram_init(void) { volatile uint16_t x; + unsigned long csa; + + /* Enable CS3 3.3v, no pull-ups */ + csa = at91_sys_read(AT91_MATRIX_EBI1CSA); + at91_sys_write(AT91_MATRIX_EBI1CSA, + csa | AT91_MATRIX_EBI1_DBPUC | + AT91_MATRIX_EBI1_VDDIOMSEL_3_3V); + + /* Configure SMC1 CS0 for PSRAM - 16-bit */ + at91_sys_write(AT91_SMC1_SETUP(0), + AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | + AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); + at91_sys_write(AT91_SMC1_PULSE(0), + AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) | + AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7)); + at91_sys_write(AT91_SMC1_CYCLE(0), + AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8)); + at91_sys_write(AT91_SMC1_MODE(0), + AT91_SMC_DBW_16 | + AT91_SMC_PMEN | + AT91_SMC_PS_32); /* setup PB29 as output */ at91_set_gpio_output(PSRAM_CRE_PIN, 1); diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index f0dbe81..5ebf286 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -67,8 +67,6 @@ #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ #define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A -/* EBI1_CSA, 3.3v, no pull-ups */ -#define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100 /* SDRAM */ /* SDRAMC_MR Mode register */ @@ -100,13 +98,7 @@ #define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ #define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ #define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ -#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */ - -/* setup SMC1, CS0 (PSRAM) - 16-bit */ -#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */ -#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */ -#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */ -#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */ +#define CONFIG_SYS_SMC0_MODE0_VAL 0x00161003 /* SMC_MODE */ #define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */ -- 1.6.3.1

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[U-Boot] Add support for AT91 WDT
by Giulio Benetti 13 Jun '09

13 Jun '09

-- Giulio Benetti R&D Micronova srl

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[U-Boot] Boot ELF image using tftpboot
by Vered Zvi 13 Jun '09

13 Jun '09

Hello, I want to boot vxworks with uboot 1.3.4 using tftp. After I got the prompt I wrote: tftpboot. The vxworks ELF image was downloaded to the target but then I had to write bootelf. Should tftpboot load and run the ELF image upon download completion ? I also tried: tftp; bootelf. After download completion I got the prompt. bootelf was not executed. Thanks. The information contained in this communication is proprietary to Israel Aerospace Industries Ltd., ELTA Systems Ltd. and/or third parties, may contain classified or privileged information, and is intended only for the use of the intended addressee thereof. If you are not the intended addressee, please be aware that any use, disclosure, distribution and/or copying of this communication is strictly prohibited. If you receive this communication in error, please notify the sender immediately and delete it from your computer. Thank you. This message is processed by the PrivaWall Email Security Server.

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[U-Boot] [PATCH] DaVinci Network Driver Updates
by s-paulraj＠ti.com 12 Jun '09

12 Jun '09

Different flavours of DaVinci SOC's have differences in their EMAC IP This patch does the following 1) Updates base addresses for DM365 2) Updates MDIO frequencies for DM365 and DM646x 3) Update EMAC wrapper registers for DM365 and DM646x Patch applies to u-boot-net git. the EMAC driver itself will be updated shortly to add support for DM365 and DM646x Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- include/asm-arm/arch-davinci/emac_defs.h | 32 +++++++++++++++++++++++++++++- 1 files changed, 31 insertions(+), 1 deletions(-) diff --git a/include/asm-arm/arch-davinci/emac_defs.h b/include/asm-arm/arch-davinci/emac_defs.h index c11161f..ae75f84 100644 --- a/include/asm-arm/arch-davinci/emac_defs.h +++ b/include/asm-arm/arch-davinci/emac_defs.h @@ -38,15 +38,38 @@ #include <asm/arch/hardware.h> +#ifdef CONFIG_SOC_DM365 +#define EMAC_BASE_ADDR (0x01d07000) +#define EMAC_WRAPPER_BASE_ADDR (0x01d0a000) +#define EMAC_WRAPPER_RAM_ADDR (0x01d08000) +#define EMAC_MDIO_BASE_ADDR (0x01d0b000) +#else #define EMAC_BASE_ADDR (0x01c80000) #define EMAC_WRAPPER_BASE_ADDR (0x01c81000) #define EMAC_WRAPPER_RAM_ADDR (0x01c82000) #define EMAC_MDIO_BASE_ADDR (0x01c84000) +#endif +#ifdef CONFIG_SOC_DM646x +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ 76500000 +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2500000 /* 2.5 MHz */ +#elif defined(CONFIG_SOC_DM365) +/* MDIO module input frequency */ +#define EMAC_MDIO_BUS_FREQ 121500000 +/* MDIO clock output frequency */ +#define EMAC_MDIO_CLOCK_FREQ 2200000 /* 2.2 MHz */ +#else /* MDIO module input frequency */ #define EMAC_MDIO_BUS_FREQ 99000000 /* PLL/6 - 99 MHz */ /* MDIO clock output frequency */ #define EMAC_MDIO_CLOCK_FREQ 2000000 /* 2.0 MHz */ +#endif + +/* PHY mask - set only those phy number bits where phy is/can be connected */ +#define EMAC_MDIO_PHY_NUM 1 +#define EMAC_MDIO_PHY_MASK (1 << EMAC_MDIO_PHY_NUM) /* Ethernet Min/Max packet size */ #define EMAC_MIN_ETHERNET_PKT_SIZE 60 @@ -103,6 +126,8 @@ typedef volatile struct _emac_desc #define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) #define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) +#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) +#define EMAC_MACCONTROL_GIGFORCE (1 << 17) #define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) #define EMAC_RXMBPENABLE_RXBROADEN (0x2000) @@ -258,12 +283,17 @@ typedef struct { /* EMAC Wrapper Registers Structure */ typedef struct { +#if defined(CONFIG_SOC_DM646x) || defined(CONFIG_SOC_DM365) + dv_reg IDVER; + dv_reg SOFTRST; + dv_reg EMCTRL; +#else u_int8_t RSVD0[4100]; dv_reg EWCTL; dv_reg EWINTTCNT; +#endif } ewrap_regs; - /* EMAC MDIO Registers Structure */ typedef struct { dv_reg VERSION; -- 1.6.0.4

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[U-Boot] [STATUS] "next" branch rebased
by Wolfgang Denk 12 Jun '09

12 Jun '09

Hi everybody, sorry for the inconvenience, but I had to rebase the "next" branch. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Those who do not understand Unix are condemned to reinvent it, poorly. - Henry Spencer, University of Toronto Unix hack

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[U-Boot] Please pull u-boot-mpc85xx - master branch
by Kumar Gala 12 Jun '09

12 Jun '09

(some fixes for v2009.06) The following changes since commit c3ab4243b5c44a5551204c324510175f444f6fd5: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx are available in the git repository at: git://git.denx.de/u-boot-mpc85xx.git master Haiying Wang (5): 85xx: Fix MURAM size for MPC8569 85xx: Fix some settings for MPC8569MDS board 85xx: Add PIB support at CS4/CS5 for MPC8569MDS 85xx: Add UART1 support for MPC8569MDS 85xx: Add README for MPC8569MDS Kumar Gala (2): 85xx: Use print_size to report amount of memory not mapped by TLBs fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT board/freescale/mpc8569mds/mpc8569mds.c | 6 ++ cpu/mpc85xx/tlb.c | 2 +- cpu/mpc8xxx/ddr/ctrl_regs.c | 3 +- cpu/mpc8xxx/ddr/ddr.h | 2 +- cpu/mpc8xxx/ddr/ddr1_dimm_params.c | 4 +- cpu/mpc8xxx/ddr/ddr2_dimm_params.c | 4 +- cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 4 +- cpu/mpc8xxx/ddr/main.c | 45 ++++++++--------- cpu/mpc8xxx/ddr/util.c | 18 +++++-- doc/README.mpc8569mds | 78 +++++++++++++++++++++++++++++++ include/asm-ppc/immap_qe.h | 9 +++- include/configs/MPC8569MDS.h | 16 +++++-- 12 files changed, 145 insertions(+), 46 deletions(-) create mode 100644 doc/README.mpc8569mds

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[U-Boot] MPC5xxx Pull Request (for "next" branch)
by Wolfgang Denk 12 Jun '09

12 Jun '09

The following changes since commit 48716e55b684927f5b33b2f9ac890e35309a1de4: Stefan Roese (1): mpc512x: Use serial_setbrg() in serial_init() to not duplicate the code are available in the git repository at: git://git.denx.de/u-boot-mpc5xxx.git next Stefan Roese (5): mpc512x: Fix problem with I2C access before relocation mcp512x: Add macros for SCFR LPC divisor access mpc512x: Add esd gmbh mecp5123 board support nand/mpc512x: Add MPC512x NAND support (NFC) mpc512x: MPC5121ADS: Add NAND support MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + board/esd/mecp5123/Makefile | 50 +++ board/esd/mecp5123/config.mk | 23 + board/esd/mecp5123/mecp5123.c | 381 +++++++++++++++++ board/freescale/mpc5121ads/mpc5121ads.c | 41 ++- cpu/mpc512x/i2c.c | 2 +- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/mpc5121_nfc.c | 692 +++++++++++++++++++++++++++++++ include/asm-ppc/immap_512x.h | 3 + include/configs/mecp5123.h | 458 ++++++++++++++++++++ include/configs/mpc5121ads.h | 22 +- 13 files changed, 1669 insertions(+), 9 deletions(-) create mode 100644 board/esd/mecp5123/Makefile create mode 100644 board/esd/mecp5123/config.mk create mode 100644 board/esd/mecp5123/mecp5123.c create mode 100644 drivers/mtd/nand/mpc5121_nfc.c create mode 100644 include/configs/mecp5123.h Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de There's a way out of any cage. -- Captain Christopher Pike, "The Menagerie" ("The Cage"), stardate unknown.

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[U-Boot] [PATCH] mpc512x: MPC5121ADS: Add NAND support
by Stefan Roese 12 Jun '09

12 Jun '09

This patch adds NAND support to the MPC5121ADS board. Please note that the image size increased since NAND support didn't fit in the current image size (256k). Signed-off-by: Stefan Roese <sr(a)denx.de> Cc: Wolfgang Denk <wd(a)denx.de> --- board/freescale/mpc5121ads/mpc5121ads.c | 27 +++++++++++++++++++++++++++ include/configs/mpc5121ads.h | 22 +++++++++++++++++++++- 2 files changed, 48 insertions(+), 1 deletions(-) diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 9d94c23..6c80cda 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -31,6 +31,9 @@ #include <i2c.h> #endif +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> + DECLARE_GLOBAL_DATA_PTR; extern void ide_set_reset(int idereset); @@ -43,6 +46,7 @@ extern void ide_set_reset(int idereset); CLOCK_SCCR1_DDR_EN | \ CLOCK_SCCR1_FEC_EN | \ CLOCK_SCCR1_PATA_EN | \ + CLOCK_SCCR1_NFC_EN | \ CLOCK_SCCR1_PCI_EN | \ CLOCK_SCCR1_TPR_EN) @@ -55,6 +59,29 @@ extern void ide_set_reset(int idereset); #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) long int fixed_sdram(void); +void __mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip); + +/* Active chip number set in board_nand_select_device() (mpc5121_nfc.c) */ +extern int mpc5121_nfc_chip; + +/* Control chips select signal on MPC5121ADS board */ +void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip) +{ + unsigned char *csreg = (u8 *)CONFIG_SYS_CPLD_BASE + 0x09; + u8 v; + + v = in_8(csreg); + v |= 0x0F; + + if (chip >= 0) { + __mpc5121_nfc_select_chip(mtd, 0); + v &= ~(1 << mpc5121_nfc_chip); + } else { + __mpc5121_nfc_select_chip(mtd, -1); + } + + out_8(csreg, v); +} int board_early_init_f (void) { diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index dff7f1a..45a004e 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -200,6 +200,26 @@ #undef CONFIG_SYS_FLASH_CHECKSUM /* + * NAND FLASH + * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon only) + */ +#define CONFIG_CMD_NAND +#define CONFIG_NAND_MPC5121_NFC +#define CONFIG_SYS_NAND_BASE 0x40000000 + +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE /* driver supports mutipl. chips */ + +/* + * Configuration parameters for MPC5121 NAND driver + */ +#define CONFIG_FSL_NFC_WIDTH 1 +#define CONFIG_FSL_NFC_WRITE_SIZE 2048 +#define CONFIG_FSL_NFC_SPARE_SIZE 64 +#define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE + +/* * CPLD registers area is really only 32 bytes in size, but the smallest possible LP * window is 64KB */ @@ -222,7 +242,7 @@ #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* Start of monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ #ifdef CONFIG_FSL_DIU_FB #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ #else -- 1.6.3.2

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[U-Boot] [PATCH] mcp512x: Add macros for SCFR LPC divisor access
by Stefan Roese 12 Jun '09

12 Jun '09

Thos macros will be used by the esd mecp5123 board. Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/asm-ppc/immap_512x.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 4f4b284..cdbbfea 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -238,6 +238,9 @@ typedef struct clk512x { #define SCFR1_PCI_DIV_MASK 0x00700000 #define SCFR1_PCI_DIV_SHIFT 20 +#define SCFR1_LPC_DIV_MASK 0x00003800 +#define SCFR1_LPC_DIV_SHIFT 11 + /* SCFR2 System Clock Frequency Register 2 */ #define SCFR2_SYS_DIV 0xFC000000 #define SCFR2_SYS_DIV_SHIFT 26 -- 1.6.3.2

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