April 2009 - U-Boot

[U-Boot] PPC + NatSemi dp83640 phy?
by Nathan French 05 May '09

05 May '09

Hi all, I've been tasked with bringing up a new board next week for my company that is essentially a Kilauea with a National Semiconductor DP83640 ethernet phy. We have U-Boot working on our previous board rev which used the Marvell 88E1111 ethernet phy which U-Boot supports. I'm new to ethernet devices. I see that both the 88E1111 and the DP83xxx devices use MII. Does this mean the DP83640 may just work as is? Thanks, Nathan French

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[U-Boot] [PATCH] include/ns16550.h: Unify structure declaration for registers
by Detlev Zundel 05 May '09

05 May '09

Instead of special casing the different access patterns, use common code with light macros sprinkled in to accomodate for the different layouts of the register structure. Note that this also changes the types of the registers for the "positively packed (>1)" cases. As the registers truly are unsigned chars, this is surely the Right Thing, but it is a semantic change. Note that for this case depending on the endianness on the bus, we may see a change of behaviour. Signed-off-by: Detlev Zundel <dzu(a)denx.de> --- include/ns16550.h | 130 +++++++++++++++-------------------------------------- 1 files changed, 37 insertions(+), 93 deletions(-) Note, that I checked that the offsets are ok in the used cases switching from the old to the new code. They *do* shift however in the positive packed cases, because the old code uses data types different than unsigned char. Note that doing this, I also noticed that using "unsigned long" for 4 byte registers is also no longer true on 64-bit architectures. One more reason to change the code. Apart from that the code was also compile tested on several configurations using different REG_SIZES and compiles without warnings. The special interesting case of +4 was successfully tested on CU824. diff --git a/include/ns16550.h b/include/ns16550.h index 87624bf..ce606b5 100644 --- a/include/ns16550.h +++ b/include/ns16550.h @@ -16,102 +16,46 @@ * by Richard Danter (richard.danter(a)windriver.com), (C) 2005 Wind River Systems */ -#if (CONFIG_SYS_NS16550_REG_SIZE == 1) -struct NS16550 { - unsigned char rbr; /* 0 */ - unsigned char ier; /* 1 */ - unsigned char fcr; /* 2 */ - unsigned char lcr; /* 3 */ - unsigned char mcr; /* 4 */ - unsigned char lsr; /* 5 */ - unsigned char msr; /* 6 */ - unsigned char scr; /* 7 */ -#if defined(CONFIG_OMAP730) - unsigned char mdr1; /* 8 */ - unsigned char reg9; /* 9 */ - unsigned char regA; /* A */ - unsigned char regB; /* B */ - unsigned char regC; /* C */ - unsigned char regD; /* D */ - unsigned char regE; /* E */ - unsigned char regF; /* F */ - unsigned char reg10; /* 10 */ - unsigned char ssr; /* 11*/ -#endif -} __attribute__ ((packed)); -#elif (CONFIG_SYS_NS16550_REG_SIZE == 2) -struct NS16550 { - unsigned short rbr; /* 0 */ - unsigned short ier; /* 1 */ - unsigned short fcr; /* 2 */ - unsigned short lcr; /* 3 */ - unsigned short mcr; /* 4 */ - unsigned short lsr; /* 5 */ - unsigned short msr; /* 6 */ - unsigned short scr; /* 7 */ -} __attribute__ ((packed)); -#elif (CONFIG_SYS_NS16550_REG_SIZE == 4) -struct NS16550 { - unsigned long rbr; /* 0 r */ - unsigned long ier; /* 1 rw */ - unsigned long fcr; /* 2 w */ - unsigned long lcr; /* 3 rw */ - unsigned long mcr; /* 4 rw */ - unsigned long lsr; /* 5 r */ - unsigned long msr; /* 6 r */ - unsigned long scr; /* 7 rw */ -}; /* No need to pack an already aligned struct */ -#elif (CONFIG_SYS_NS16550_REG_SIZE == -4) -struct NS16550 { - unsigned char rbr; /* 0 */ - int pad1:24; - unsigned char ier; /* 1 */ - int pad2:24; - unsigned char fcr; /* 2 */ - int pad3:24; - unsigned char lcr; /* 3 */ - int pad4:24; - unsigned char mcr; /* 4 */ - int pad5:24; - unsigned char lsr; /* 5 */ - int pad6:24; - unsigned char msr; /* 6 */ - int pad7:24; - unsigned char scr; /* 7 */ - int pad8:24; -#if defined(CONFIG_OMAP) - unsigned char mdr1; /* mode select reset TL16C750*/ -#endif -#ifdef CONFIG_OMAP1510 - int pad9:24; - unsigned long pad[10]; - unsigned char osc_12m_sel; - int pad10:24; -#endif -} __attribute__ ((packed)); -#elif (CONFIG_SYS_NS16550_REG_SIZE == -8) -struct NS16550 { - unsigned char rbr; /* 0 */ - unsigned char pad0[7]; - unsigned char ier; /* 1 */ - unsigned char pad1[7]; - unsigned char fcr; /* 2 */ - unsigned char pad2[7]; - unsigned char lcr; /* 3 */ - unsigned char pad3[7]; - unsigned char mcr; /* 4 */ - unsigned char pad4[7]; - unsigned char lsr; /* 5 */ - unsigned char pad5[7]; - unsigned char msr; /* 6 */ - unsigned char pad6[7]; - unsigned char scr; /* 7 */ - unsigned char pad7[7]; -} __attribute__ ((packed)); -#else +/* + * Note that the following macro magic uses the fact that the compiler + * will not allocate storage for arrays of size 0 + */ + +#if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0) #error "Please define NS16550 registers size." +#elif (CONFIG_SYS_NS16550_REG_SIZE > 0) +#define UART_REG(x) \ + unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \ + unsigned char x; +#elif (CONFIG_SYS_NS16550_REG_SIZE < 0) +#define UART_REG(x) \ + unsigned char x; \ + unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1]; #endif +struct NS16550 { + UART_REG(rbr); /* 0 */ + UART_REG(ier); /* 1 */ + UART_REG(fcr); /* 2 */ + UART_REG(lcr); /* 3 */ + UART_REG(mcr); /* 4 */ + UART_REG(lsr); /* 5 */ + UART_REG(msr); /* 6 */ + UART_REG(spr); /* 7 */ + UART_REG(mdr1); /* 8 */ + UART_REG(reg9); /* 9 */ + UART_REG(regA); /* A */ + UART_REG(regB); /* B */ + UART_REG(regC); /* C */ + UART_REG(regD); /* D */ + UART_REG(regE); /* E */ + UART_REG(uasr); /* F */ + UART_REG(scr); /* 10*/ + UART_REG(ssr); /* 11*/ + UART_REG(reg12); /* 12*/ + UART_REG(osc_12m_sel); /* 13*/ +}; + #define thr rbr #define iir fcr #define dll rbr -- 1.6.0.6

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Re: [U-Boot] Ping on Coldfire patch status
by Richard Retanubun 04 May '09

04 May '09

Liew Tsi Chung-R5AAHP wrote: > Richard, > > Sorry for the late reply. I was time off last week .. mandatory. I'm ok Hi TC, Thanks for the reply, sorry If I made you reply from vacation :( > with three out of four patches (Activate timer, watchdog and compiler > warning patches). I can place these patches before the next merging > window. > > As for the I2C, re-order the value may not be the best solution. I had > this calculation a while back, try it and let me know what you think. Which calculation do you want me to try? > The drawback is ... It is slower than fix value. - Richard

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[U-Boot] Current status of UBI?
by Matthew L. Creech 04 May '09

04 May '09

Hi, I'm using the latest U-Boot GIT snapshot (4/28), and trying to get UBI/UBIFS working. I'm wondering what the current status of UBI support in U-Boot is, and whether what I'm doing will work. The goal is to get a single R/W filesystem on a large NAND partition. If I understand correctly, I should be able to: 1. [In U-Boot]: Use "mtdparts" to partition my NAND device 2. [In U-Boot]: Use "ubi part" to setup UBI on a partition 3. [In U-Boot]: Use "ubi create" to create a volume which fills the whole partition 4. [On my PC]: Use "mkfs.ubifs" & "ubinize" to create a UBIFS image 5. [In U-Boot]: Use "ubi write" to write the UBIFS image to the volume 6. [In Linux]: Boot using the UBIFS image as my rootfs Is this more or less correct? The problem I'm currently running into is step 2, which throws an error in ubi_io_write() (see below). Googling around turned up a few hits that suggested turning off sub-page writes, so I tried adding NAND_NO_SUBPAGE_WRITE to NAND_SAMSUNG_LP_OPTIONS, but that causes a crash. Actually, it gets to volume table copy #2 in that case, so the crash may be unrelated to subpage writes. Anyway, I'm mainly wondering whether this is a good approach before I go chasing down this crash, and also whether others are using UBIFS on large-page flash devices successfully in U-Boot. Any feedback is appreciated, thanks! ==== => mtdparts device nand0 <flash>, # parts = 2 #: name size offset mask_flags 0: uboot 0x00500000 0x00000000 0 1: root 0x3fb00000 0x00500000 0 active partition: nand0,0 - (uboot) 0x00500000 @ 0x00000000 defaults: mtdids : nand0=flash mtdparts: mtdparts=flash:5M(uboot),-(root) => ubi part root Creating 1 MTD partitions on "nand0": 0x00500000-0x40000000 : "mtd=1" Bad block table found at page 524224, version 0x01 Bad block table found at page 524160, version 0x01 nand_read_bbt: Bad block at 0x01fc0000 nand_read_bbt: Bad block at 0x03440000 nand_read_bbt: Bad block at 0x03460000 nand_read_bbt: Bad block at 0x21fc0000 nand_read_bbt: Bad block at 0x21fe0000 nand_read_bbt: Bad block at 0x3a000000 UBI: attaching mtd1 to ubi0 UBI: physical eraseblock size: 131072 bytes (128 KiB) UBI: logical eraseblock size: 129024 bytes UBI: smallest flash I/O unit: 2048 UBI: sub-page size: 512 UBI: VID header offset: 512 (aligned 512) UBI: data offset: 2048 UBI: empty MTD device detected UBI: create volume table (copy #1) UBI error: ubi_io_write: error -5 while writing 512 bytes to PEB 0:512, written 0 bytes UBI error: ubi_io_write: error -5 while writing 512 bytes to PEB 1:512, written 0 bytes UBI error: ubi_io_write: error -5 while writing 512 bytes to PEB 2:512, written 0 bytes UBI error: ubi_io_write: error -5 while writing 512 bytes to PEB 3:512, written 0 bytes UBI error: ubi_io_write: error -5 while writing 512 bytes to PEB 4:512, written 0 bytes UBI error: ubi_io_write: error -5 while writing 512 bytes to PEB 5:512, written 0 bytes UBI error: ubi_init: cannot attach mtd1 UBI error: ubi_init: UBI error: cannot initialize UBI, error -5 UBI init error -5 exit not allowed from main input shell. => -- Matthew L. Creech

3 6

[U-Boot] AMCC 405EX Trap
by Jonathan Haws 04 May '09

04 May '09

All, I am experiencing a machine check on a custom AMCC 405EX PPC board. Our board is based on the AMCC Kilauea evaluation board. We have a few of these boards that are up and running, but I am trying to track down a machine check error on a couple of them. My question for you is this: when the registers are printed to the console, there is one called TRAP. I want to know how/where/when and with what data that gets populated. I have read through the AMCC manuals a couple of times trying to find it and have searched through the U-Boot code to no avail. All I know is that there is a data type "struct pt_regs*" that contains all that data, but nowhere can I find where it is populated. Below is the console output. The line "!!!! PAUSE !!!!" was inserted by me after I copied the text from the console to remind me of the ~20 second pause that occurs at that point. I am hoping that someone can point me to the bit definitions for whatever register is being displayed in TRAP. From there, I think I can trace the problem back to the specific piece of hardware and get it fixed. Thanks! Jonathan U-Boot 1.3.4 (Apr 28 2009 - 16:10:06) CPU: AMCC PowerPC 405EX Rev. C at 400 MHz (PLB=200, OPB=100, EBC=100 MHz) Security support Bootstrap Option C - Boot ROM Location EBC (16 bits) 16 kB I-Cache 16 kB D-Cache Board: SDLPPC - RT PPC405EX Board I2C: ready DRAM: 256 MB Reserving 16384k for kernel logbuffer at 0fffb000 Top of RAM usable for U-Boot at: 0fffb000 Reserving 306k for U-Boot at: 0ffae000 Reserving 1040k for malloc() at: 0feaa000 Reserving 124 Bytes for Board Info at: 0fea9f84 Reserving 64 Bytes for Global Data at: 0fea9f44 Stack Pointer at: 0fea9f28 New Stack Pointer is: 0fea9f28 !!!! PAUSE !!!! Now running in RAM - U-Boot at: 0ffae000 -> Initializing logBuff pointers... -> Calling post_output_backlog()... -> Calling post_reloc()... -> Sync'ing CPU... -> Setting up trap handlers... Bus Fault @ 0x00000000, fixup 0x00000000 Machine Check Exception. Caused by (from msr): regs 0fea9de8 Instruction Synchronous Machine Check exception NIP: 00000000 XER: 20000000 LR: 0FFB071C REGS: 0fea9de8 TRAP: 0200 DEAR: 00000000 MSR: 00000000 EE: 0 PR: 0 FP: 0 ME: 0 IR/DR: 00 GPR00: 0FFB039C 0FEA9ED8 0FEA9F44 0FFAE000 0FFB3D6C 00000001 00000001 00021000 GPR08: 00000600 00002098 17D78400 00000002 2BA7DEF3 FFFFFFFF 0FFF1D00 1000E000 GPR16: 775DF377 FFFFF6FF FFFFFFFF FF5FF7FF FFFFFFFF FFFFFFFF FFDFFFFF FF7FFFFF GPR24: 0000A000 0FEA9F44 0FFAE000 0FEA9F84 0FEAE000 0FEA9F84 0FFF1ED8 00000000 Call backtrace: 0FFB3D64 0FFB06A4 machine check -- Jonathan R. Haws Electrical Engineering Space Dynamics Laboratory Jonathan.Haws(a)sdl.usu.edu (435)797-4629

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[U-Boot] U-boot -printk kernel crash dump using md on PDK
by alfred steele 04 May '09

04 May '09

Hi All, I am using mx31 pdk and uImage generated by LTIB. Basically, my problem is my kernel gets stuck after printing the "Done...Booting the kernel". Please the responses below. Upon inspecting the printk log by doing a memory dump of the _buf_log symbol in System.map(i translated it to the physical address before dumping it ). It seems before the console got initialized, the bootup was successful to a certain extent, but i am unable to interpret anything conclusive from the logs. ANy hints as to what might be happening? I am guessing that unexpected RAM regions are getting overwritten after uncompression happens or the sdram hasn't been initialized fully by U-boot. I have attached the printk circular buffer log. smc911x: initializing smc911x: detected <NULL> controller smc911x: phy initialized smc911x: MAC 92:92:92:bb:bb:bb TFTP from server 206.44.18.25; our IP address is 206.44.18.31 Filename 'zImage_spin2_23march'. Load address: 0x81000000 Loading: * ################################################################# ################################################# done Bytes transferred = 1665000 (1967e8 hex) => go 0x81000000 ## Starting application at 0x81000000 ... Uncompressing Linux............................................................. ............................................... done, booting the kernel. PRINTK log ========== md 80350f68 5000 50 80350f68: 4c3e353c 78756e69 72657620 6e6f6973 <5>Linux version 80350f78: 362e3220 2d34322e 2d303431 65383667 2.6.24-140-g68e 80350f88: 34623462 79742820 406f7561 656c7954 b4b4 (tyauo@Tyle 80350f98: 4c575372 694c6261 3278756e 2e4d412e rSWLabLinux2.AM. 80350fa8: 50524f43 4952502e 28202956 20636367 CORP.PRIV) (gcc 80350fb8: 73726576 206e6f69 2e312e34 23202932 version 4.1.2) # 80350fc8: 52502033 504d4545 68542054 70412075 3 PREEMPT Thu Ap 80350fd8: 33322072 3a353120 323a3131 44432039 r 23 15:11:29 CD 80350fe8: 30322054 3c0a3930 50433e34 41203a55 T 2009.<4>CPU: A 80350ff8: 36764d52 6d6f632d 69746170 20656c62 RMv6-compatible 80351008: 636f7270 6f737365 345b2072 62373031 processor [4107b 80351018: 5d343633 76657220 6f697369 2034206e 364] revision 4 80351028: 4d524128 45543676 202c294a 303d7263 (ARMv6TEJ), cr=0 80351038: 33356530 0a663738 4d3e343c 69686361 0e5387f.<4>Machi 80351048: 203a656e 65657246 6c616373 584d2065 ne: Freescale MX 80351058: 4d2f3133 20323358 74532d33 206b6361 31/MX32 3-Stack 80351068: 72616f42 343c0a64 6d654d3e 2079726f Board.<4>Memory 80351078: 696c6f70 203a7963 20434345 61736964 policy: ECC disa 80351088: 64656c62 6144202c 63206174 65686361 bled, Data cache 80351098: 69727720 61626574 3c0a6b63 6e4f3e37 writeback.<7>On 803510a8: 646f6e20 20302065 61746f74 6761706c node 0 totalpag 803510b8: 203a7365 36373233 373c0a38 4420203e es: 32768.<7> D 803510c8: 7a20414d 3a656e6f 20383420 65676170 MA zone: 48 page 803510d8: 73752073 66206465 6d20726f 616d6d65 s used for memma 803510e8: 373c0a70 4420203e 7a20414d 3a656e6f p.<7> DMA zone: 803510f8: 70203020 73656761 73657220 65767265 0 pages reserve 80351108: 373c0a64 4420203e 7a20414d 3a656e6f d.<7> DMA zone: 80351118: 39303620 61702036 2c736567 46494c20 6096 pages, LIF 80351128: 6162204f 3a686374 373c0a30 4e20203e O batch:0.<7> N 80351138: 616d726f 6f7a206c 203a656e 20383032 ormal zone: 208 80351148: 65676170 73752073 66206465 6d20726f pages used for m 80351158: 616d6d65 373c0a70 4e20203e 616d726f emmap.<7> Norma 80351168: 6f7a206c 203a656e 31343632 61702036 l zone: 26416 pa 80351178: 2c736567 46494c20 6162204f 3a686374 ges, LIFO batch: 80351188: 373c0a37 4d20203e 6261766f 7a20656c 7.<7> Movable z 80351198: 3a656e6f 70203020 73656761 65737520 one: 0 pages use 803511a8: 6f662064 656d2072 70616d6d 3e343c0a d for memmap.<4> 803511b8: 30555043 2044203a 54504956 69727720 CPU0: D VIPT wri 803511c8: 622d6574 206b6361 68636163 343c0a65 te-back cache.<4 803511d8: 5550433e 49203a30 63616320 203a6568 >CPU0: I cache: 803511e8: 38333631 79622034 2c736574 73736120 16384 bytes, ass 803511f8: 6169636f 69766974 34207974 3233202c ociativity 4, 32 80351208: 74796220 696c2065 2c73656e 38323120 byte lines, 128 80351218: 74657320 343c0a73 5550433e 44203a30 sets.<4>CPU0: D 80351228: 63616320 203a6568 38333631 79622034 cache: 16384 by 80351238: 2c736574 73736120 6169636f 69766974 tes, associativi 80351248: 34207974 3233202c 74796220 696c2065 ty 4, 32 byte li 80351258: 2c73656e 38323120 74657320 343c0a73 nes, 128 sets.<4 80351268: 6975423e 3120746c 6e6f7a20 73696c65 >Built 1 zonelis 80351278: 69207374 6f5a206e 6f20656e 72656472 ts in Zone order 80351288: 6f6d202c 696c6962 67207974 70756f72 , mobility group 80351298: 20676e69 202e6e6f 746f5420 70206c61 ing on. Total p 803512a8: 73656761 3233203a 0a323135 4b3e353c ages: 32512.<5>K 803512b8: 656e7265 6f63206c 6e616d6d 696c2064 ernel command li 803512c8: 203a656e 6e696f6e 64727469 6e6f6320 ne: noinitrd con 803512d8: 656c6f73 7974743d 3063786d 3531312c sole=ttymxc0,115 803512e8: 20303032 74696e69 696c2f3d 7278756e 200 init=/linuxr 803512f8: 6f722063 2f3d746f 2f766564 2073666e c root=/dev/nfs 80351308: 7273666e 3d746f6f 2e363032 312e3434 nfsroot=206.44.1 80351318: 35322e38 66742f3a 6f627074 6c2f746f 8.25:/tftpboot/l 80351328: 2f626974 746f6f72 69207366 68643d70 tib/rootfs ip=dh 80351338: 3c0a7063 584d3e36 52492043 6e692051 cp.<6>MXC IRQ in 80351348: 61697469 657a696c 343c0a64 4449503e itialized.<4>PID 80351358: 73616820 61742068 20656c62 72746e65 hash table entr 80351368: 3a736569 32313520 726f2820 3a726564 ies: 512 (order: 80351378: 202c3920 38343032 74796220 0a297365 9, 2048 bytes). 80351388: 4d3e363c 47204358 74205450 72656d69 <6>MXC GPT timer 80351398: 696e6920 6c616974 64657a69 6172202c initialized, ra 803513a8: 3d206574 36363120 30303532 343c0a30 te = 16625000.<4 803513b8: 6e6f433e 656c6f73 6f63203a 72756f6c >Console: colour 803513c8: 6d756420 6420796d 63697665 30382065 dummy device 80 803513d8: 0a303378 443e363c 72746e65 61632079 x30.<6>Dentry ca 803513e8: 20656863 68736168 62617420 6520656c che hash table e 803513f8: 6972746e 203a7365 38333631 6f282034 ntries: 16384 (o 80351408: 72656472 2c34203a 35353620 62203633 rder: 4, 65536 b 80351418: 73657479 363c0a29 6f6e493e 632d6564 ytes).<6>Inode-c 80351428: 65686361 73616820 61742068 20656c62 ache hash table 80351438: 72746e65 3a736569 39313820 6f282032 entries: 8192 (o 80351448: 72656472 2c33203a 37323320 62203836 rder: 3, 32768 b 80351458: 73657479 363c0a29 6d654d3e 3a79726f ytes).<6>Memory: 80351468: 38323120 3d20424d 38323120 7420424d 128MB = 128MB t 80351478: 6c61746f 3e353c0a 6f6d654d 203a7972 otal.<5>Memory: 80351488: 34363231 424b3631 61766120 62616c69 126416KB availab 80351498: 2820656c 30303133 6f63204b 202c6564 le (3100K code, 803514a8: 4b303832 74616420 31202c61 204b3830 280K data, 108K 803514b8: 74696e69 373c0a29 6c61433e 61726269 init).<7>Calibra 803514c8: 676e6974 6c656420 6c207961 2e706f6f ting delay loop. 803514d8: 35202e2e 382e3033 6f422034 494d6f67 .. 530.84 BogoMI 803514e8: 28205350 3d6a706c 34353632 29383032 PS (lpj=2654208) 803514f8: 3e343c0a 6e756f4d 61632d74 20656863 .<4>Mount-cache 80351508: 68736168 62617420 6520656c 6972746e hash table entri 80351518: 203a7365 0a323135 433e363c 203a5550 es: 512.<6>CPU: 80351528: 74736554 20676e69 74697277 75622065 Testing write bu 80351538: 72656666 686f6320 6e657265 203a7963 ffer coherency: 80351548: 3c0a6b6f 656e3e36 616e5f74 7073656d ok.<6>net_namesp 80351558: 3a656361 20343620 65747962 363c0a73 ace: 64 bytes.<6 80351568: 54454e3e 6552203a 74736967 64657265 >NET: Registered 80351578: 6f727020 6f636f74 6166206c 796c696d protocol family 80351588: 0a363120 4c3e363c 20305832 68636163 16.<6>L2X0 cach 80351598: 6f632065 6f72746e 72656c6c 616e6520 e controller ena 803515a8: 64656c62 3e363c0a 20555043 69207369 bled.<6>CPU is i 803515b8: 33584d2e 65522031 69736976 32206e6f .MX31 Revision 2 803515c8: 3c0a302e 6c433e36 206b636f 75706e69 .0.<6>Clock inpu 803515d8: 6f732074 65637275 20736920 30303632 t source is 2600 803515e8: 30303030 3e363c0a 2043584d 4f495047 0000.<6>MXC GPIO 803515f8: 72616820 72617764 363c0a65 6973553e hardware.<6>Usi 80351608: 5320676e 20414d44 50412e49 363c0a49 ng SDMA I.API.<6 80351618: 43584d3e 414d4420 49504120 696e6920 >MXC DMA API ini 80351628: 6c616974 64657a69 3e373c0a 69676552 tialized.<7>Regi 80351638: 72657473 20676e69 20656874 20495053 stering the SPI 80351648: 746e6f43 6c6c6f72 44207265 65766972 Controller Drive 80351658: 373c0a72 63786d3e 6970735f 63786d20 r.<7>mxc_spi mxc 80351668: 6970735f 203a302e 5f495053 20564552 _spi.0: SPI_REV 80351678: 0a342e30 633e363c 69666e6f 4c435f67 0.4.<6>config_CL 80351688: 635f4949 6b636f6c 7465533a 676e6974 II_clock:Setting 80351698: 20707520 49494c43 6f6c6320 0a2e6b63 up CLII clock.. 803516a8: 633e363c 69666e6f 4c435f67 635f4949 <6>config_CLII_c 803516b8: 6b636f6c 7465533a 676e6974 20707520 lock:Setting up 803516c8: 5f43584d 5f4d5750 434d5750 78302852 MXC_PWM_PWMCR(0x 803516d8: 65326366 30303030 6f742029 30783020 fc2e0000) to 0x0 803516e8: 30326333 2e303030 3e363c0a 666e6f63 3c20000..<6>conf 803516f8: 435f6769 5f49494c 636f6c63 65533a6b ig_CLII_clock:Se 80351708: 6e697474 70752067 43584d20 4d57505f tting up MXC_PWM 80351718: 4d57505f 30285249 32636678 30303065 _PWMIR(0xfc2e000 80351728: 74202938 7830206f 30303030 30303030 8) to 0x00000000 80351738: 363c0a2e 6e6f633e 5f676966 49494c43 ..<6>config_CLII 80351748: 6f6c635f 533a6b63 69747465 7520676e _clock:Setting u 80351758: 584d2070 57505f43 57505f4d 2852434d p MXC_PWM_PWMCR( 80351768: 63667830 30306532 20296330 30206f74 0xfc2e000c) to 0 80351778: 30303078 31303030 3c0a2e30 6f633e36 x00000010..<6>co 80351788: 6769666e 494c435f 6c635f49 3a6b636f nfig_CLII_clock: 80351798: 74746553 20676e69 4d207075 505f4358 Setting up MXC_P 803517a8: 505f4d57 52434d57 66783028 30653263 WM_PWMCR(0xfc2e0 803517b8: 29303130 206f7420 30307830 30303030 010) to 0x000000 803517c8: 0a2e3032 633e363c 69666e6f 4c435f67 20..<6>config_CL 803517d8: 635f4949 6b636f6c 7465533a 676e6974 II_clock:Setting 803517e8: 20707520 5f43584d 5f4d5750 434d5750 up MXC_PWM_PWMC 803517f8: 78302852 65326366 30303030 6f742029 R(0xfc2e0000) to 80351808: 30783020 30326333 2e313030 3e363c0a 0x03c20001..<6> 80351818: 666e6f63 435f6769 5f49494c 636f6c63 config_CLII_cloc 80351828: 65533a6b 6e697474 70752067 4d575020 k:Setting up PWM 80351838: 6170204f 65722064 74736967 0a2e7265 O pad register.. 80351848: 6d3e373c 735f6378 6d206970 735f6378 <7>mxc_spi mxc_s 80351858: 302e6970 6572203a 74736967 64657265 pi.0: registered 80351868: 73616d20 20726574 31697073 3e373c0a master spi1.<7> 80351878: 5f63786d 5f697073 75746573 6d203a70 mxc_spi_setup: m 80351888: 2065646f 38202c30 77706220 3035202c ode 0, 8 bpw, 50 80351898: 30303030 7a682030 3e373c0a 5f63786d 00000 hz.<7>mxc_ 803518a8: 20697073 5f63786d 2e697073 72203a30 spi mxc_spi.0: r 803518b8: 73696765 65726574 68632064 20646c69 egistered child 803518c8: 31697073 3c0a322e 786d3e37 70735f63 spi1.2.<7>mxc_sp 803518d8: 65735f69 3a707574 646f6d20 2c302065 i_setup: mode 0, 803518e8: 62203820 202c7770 30303035 68203030 8 bpw, 500000 h 803518f8: 373c0a7a 63786d3e 6970735f 63786d20 z.<7>mxc_spi mxc 80351908: 6970735f 203a302e 69676572 72657473 _spi.0: register 80351918: 63206465 646c6968 69707320 0a302e31 ed child spi1.0. 80351928: 433e363c 3a495053 63786d20 6970735f <6>CSPI: mxc_spi 80351938: 7020302d 65626f72 373c0a64 63786d3e -0 probed.<7>mxc 80351948: 6970735f 63786d20 6970735f 203a312e _spi mxc_spi.1: 80351958: 5f495053 20564552 0a342e30 6d3e373c SPI_REV 0.4.<7>m 80351968: 735f6378 6d206970 735f6378 312e6970 xc_spi mxc_spi.1 80351978: 6572203a 74736967 64657265 73616d20 : registered mas 80351988: 20726574 32697073 3e373c0a 5f63786d ter spi2.<7>mxc_ 80351998: 5f697073 75746573 6d203a70 2065646f spi_setup: mode 803519a8: 38202c30 77706220 3034202c 30303030 0, 8 bpw, 400000 803519b8: 7a682030 3e373c0a 5f63786d 20697073 0 hz.<7>mxc_spi 803519c8: 5f63786d 2e697073 72203a31 73696765 mxc_spi.1: regis 803519d8: 65726574 68632064 20646c69 32697073 tered child spi2 803519e8: 3c0a322e 53433e36 203a4950 5f63786d .2.<6>CSPI: mxc_ 803519f8: 2d697073 72702031 6465626f 3e363c0a spi-1 probed.<6> 80351a08: 2043584d 20433249 76697264 3c0a7265 MXC I2C driver.< 80351a18: 6c633e34 55203a6b 6c62616e 6f742065 4>clk: Unable to 80351a28: 74656720 71657220 74736575 63206465 get requested c 80351a38: 6b636f6c 6664203a 6c635f6d 373c0a6b lock: dfm_clk.<7 80351a48: 63786d3e 6970735f 7465735f 203a7075 >mxc_spi_setup: 80351a58: 65646f6d 202c3620 62203233 202c7770 mode 6, 32 bpw, 80351a68: 30303034 20303030 3c0a7a68 636d3e36 4000000 hz.<6>mc 80351a78: 38373331 65522033 2e332076 69462035 13783 Rev 3.5 Fi 80351a88: 7265566e 64203420 63657465 0a646574 nVer 4 detected. 80351a98: 503e363c 2043494d 20435452 63637573 <6>PMIC RTC succ 80351aa8: 66737365 796c6c75 6f727020 0a646562 essfully probed. 80351ab8: 503e363c 2043494d 6867694c 75732074 <6>PMIC Light su 80351ac8: 73656363 6c756673 6c20796c 6564616f ccessfully loade 80351ad8: 363c0a64 31434d3e 33383733 67657220 d.<6>MC13783 reg 80351ae8: 74616c75 7320726f 65636375 75667373 ulator successfu 80351af8: 20796c6c 626f7270 000a6465 00000000 lly probed...... 80351b08: 00000000 00000000 00000000 00000000 ................ 80351b18: 00000000 00000000 494d503e 6f502043 ........>PMIC Po 80351b28: 20726577 63637573 66737365 796c6c75 wer successfully 80351b38: 6f727020 0a646562 4e3e363c 203a5445 probed.<6>NET: 80351b48: 69676552 72657473 70206465 6f746f72 Registered proto 80351b58: 206c6f63 696d6166 3220796c 0000000a col family 2.... 80351b68: 00000000 00000000 00000000 00000000 ................ 80351b78: 00000000 00000000 61682065 65622073 ........e has be 80351b88: 69206e65 6174736e 64656c6c 373c0a2e en installed..<7 80351b98: 6977533e 65686374 6f742064 67696820 >Switched to hig 80351ba8: 65722068 756c6f73 6e6f6974 646f6d20 h resolution mod 80351bb8: 6e6f2065 55504320 3c0a3020 50493e36 e on CPU 0.<6>IP 80351bc8: 756f7220 63206574 65686361 73616820 route cache has 80351bd8: 61742068 20656c62 72746e65 3a736569 h table entries: 80351be8: 32303120 6f282034 72656472 2c30203a 1024 (order: 0, 80351bf8: 39303420 79622036 29736574 0000000a 4096 bytes).... 80351c08: 00000000 00000000 00000000 00000000 ................ 80351c18: 00000000 00000000 6520656c 6972746e ........le entri 80351c28: 203a7365 36393034 726f2820 3a726564 es: 4096 (order: 80351c38: 202c3320 36373233 79622038 29736574 3, 32768 bytes) 80351c48: 3e363c0a 20504354 646e6962 73616820 .<6>TCP bind has 80351c58: 61742068 20656c62 72746e65 3a736569 h table entries: 80351c68: 39303420 6f282036 72656472 2c32203a 4096 (order: 2, 80351c78: 33363120 62203438 73657479 363c0a29 16384 bytes).<6 80351c88: 5043543e 6148203a 74206873 656c6261 >TCP: Hash table 80351c98: 6f632073 6769666e 64657275 73652820 s configured (es 80351ca8: 6c626174 65687369 30342064 62203639 tablished 4096 b 80351cb8: 20646e69 36393034 363c0a29 5043543e ind 4096).<6>TCP 80351cc8: 6e657220 6572206f 74736967 64657265 reno registered 80351cd8: 3e363c0a 2d776f4c 6576654c 4d50206c .<6>Low-Level PM 80351ce8: 69724420 20726576 75646f6d 6c20656c Driver module l 80351cf8: 6564616f 00000a64 696c633e 71726969 oaded...>cliiirq 80351d08: 6970203a 31313d6e 37373038 2c353632 : pin=118077265, 80351d18: 3d717269 672c3137 3d6f6970 6f702c37 irq=71,gpio=7,po 80351d28: 303d7472 6769732c 3d6f6e5f 00000a37 rt=0,sig_no=7... 80351d38: 00000000 00000000 00002043 00000000 ........C ...... 80351d48: 00000000 00000000 00000000 00000000 ................ 80351d58: 00000000 00000000 49494c43 43414d20 ........CLII MAC 80351d68: 6f6d3a3a 656c7564 74696e49 696c6169 ::moduleInitiali 80351d78: 6320657a 4d69696c 6f496361 6f6d654d ze cliiMacIoMemo 80351d88: 203a7972 38637830 30343038 64203030 ry: 0xc8804000 d 80351d98: 0a656e6f 00000000 6e61686e 64656c64 one.....nhandled 80351da8: 75616620 203a746c 65747865 6c616e72 fault: external 80351db8: 6f626120 6f207472 6f6e206e 696c2d6e abort on non-li 80351dc8: 6566656e 20686374 30783028 20293830 nefetch (0x008) 80351dd8: 30207461 38386378 30303430 00000a30 at 0xc8804000... 80351de8: 00000000 00000000 00000000 00000000 ................ 80351df8: 00000000 00000000 5250205d 504d4545 ........] PREEMP 80351e08: 00000a54 00000000 00000000 00000000 T............... 80351e18: 00000000 00000000 433e343c 203a5550 ........<4>CPU: 80351e28: 20202030 746f4e20 69617420 6465746e 0 Not tainted 80351e38: 32282020 322e362e 34312d34 36672d30 (2.6.24-140-g6 80351e48: 34626538 23203462 000a2933 00000000 8eb4b4 #3)...... 80351e58: 00000000 00000000 6c75646f 696e4965 ........oduleIni 80351e68: 6c616974 2b657a69 34377830 3178302f tialize+0x74/0x1 80351e78: 000a3035 00000000 20736920 76207461 50...... is at v 80351e88: 6e697270 302b6b74 63373378 3478302f printk+0x37c/0x4 80351e98: 000a3832 00000000 5b203a20 3030633c 28...... : [<c00 80351ea8: 35366330 205d3e30 6c202020 203a2072 0c650>] lr : 80351eb8: 30633c5b 64353430 5d3e3835 20202020 [<c0045d58>] 80351ec8: 3a727370 30303420 31303030 343c0a33 psr: 40000013.<4 80351ed8: 2070733e 3763203a 66393163 20203037 >sp : c7c19f70 80351ee8: 3a207069 63376320 64653931 66202030 ip : c7c19ed0 f 80351ef8: 203a2070 31633763 63386639 0000000a p : c7c19f8c.... 80351f08: 00000000 00000000 00000000 00000000 ................ 80351f18: 00000000 00000000 30303030 38722020 ........0000 r8 80351f28: 63203a20 38316337 0a303030 00000000 : c7c18000..... 80351f38: 00000000 00000000 30303030 36722020 ........0000 r6 80351f48: 63203a20 64313030 20386639 20357220 : c001d9f8 r5 80351f58: 3863203a 30343038 20203030 3a203472 : c8804000 r4 : 80351f68: 30303020 30303030 00000a30 00000000 00000000....... 80351f78: 00000000 00000000 20203030 3a203272 ........00 r2 : 80351f88: 63376320 30303831 72202030 203a2031 c7c18000 r1 : 80351f98: 30303030 31303030 30722020 30203a20 00000001 r0 : 0 80351fa8: 30303030 0a663330 00000000 00000000 000003f......... 80351fb8: 00000000 00000000 73515249 206e6f20 ........IRQs on 80351fc8: 51494620 6e6f2073 6f4d2020 53206564 FIQs on Mode S 80351fd8: 335f4356 49202032 41204153 20204d52 VC_32 ISA ARM 80351fe8: 6d676553 20746e65 6e72656b 3c0a6c65 Segment kernel.< 80351ff8: 6f433e34 6f72746e 30203a6c 33356530 4>Control: 00e53 80352008: 20663738 62615420 203a656c 30303038 87f Table: 8000 80352018: 30303034 41442020 30203a43 30303030 4000 DAC: 00000 80352028: 0a373130 00000000 00000000 00000000 017............. 80352038: 00000000 00000000 3a646970 202c3120 ........pid: 1, 80352048: 63617473 696c206b 2074696d 7830203d stack limit = 0x 80352058: 31633763 30363238 00000a29 00000000 c7c18260)....... 80352068: 00000000 00000000 00000000 00000000 ................ 80352078: 00000000 00000000 30306131 000a2930 ........1a000).. 80352088: 00000000 00000000 00000000 00000000 ................ 80352098: 00000000 00000000 00002020 00000000 ........ ...... 803520a8: 00000000 00000000 00000000 00000000 ................ 803520b8: 00000000 00000000 30303030 00002030 ........00000 .. 803520c8: 00000000 00000000 00000000 00000000 ................ 803520d8: 00000000 00000000 0000203a 00000000 ........: ...... 803520e8: 00000000 00000000 00000000 00000000 ................ 803520f8: 00000000 00000000 65356330 00002038 ........0c5e8 .. 80352108: 00000000 00000000 00000000 00000000 ................ 80352118: 00000000 00000000 00000020 00000000 ........ ....... 80352128: 00000000 00000000 00000000 00000000 ................ 80352138: 00000000 00000000 62663931 00002030 ........19fb0 .. 80352148: 00000000 00000000 00000000 00000000 ................ 80352158: 00000000 00000000 00000020 00000000 ........ ....... 80352168: 00000000 00000000 00000000 00000000 ................ 80352178: 00000000 00000000 30636639 0000203a ........9fc0: .. 80352188: 00000000 00000000 00000000 00000000 ................ 80352198: 00000000 00000000 00000020 00000000 ........ ....... 803521a8: 00000000 00000000 00000000 00000000 ................ 803521b8: 00000000 00000000 30303030 30303020 ........0000 000 803521c8: 30303030 3c0a2030 66393e34 203a3065 00000 .<4>9fe0: 803521d8: 30303030 30303030 00000020 00000000 00000000 ....... 803521e8: 00000000 00000000 00000000 00000000 ................ 803521f8: 00000000 00000000 63373738 00000020 ........877c ... 80352208: 00000000 00000000 00000000 00000000 ................ 80352218: 00000000 00000000 0000000a 00000000 ................ 80352228: 00000000 00000000 00000000 00000000 ................ 80352238: 00000000 00000000 646f6d28 49656c75 ........(moduleI 80352248: 6974696e 7a696c61 78302b65 78302f30 nitialize+0x0/0x 80352258: 29303531 00000020 3c5b206d 30303063 150) ...m [<c000 80352268: 38643738 00205d3e 00000000 00000000 87d8>] ......... 80352278: 00000000 00000000 3278302f 0a296338 ......../0x28c). 80352288: 00000000 00000000 00000000 00000000 ................ 80352298: 00000000 00000000 00386639 00000000 ........9f8..... 803522a8: 00000000 00000000 00000000 00000000 ................ 803522b8: 00000000 00000000 3030633c 31373830 ........<c000871 803522c8: 205d3e30 00000000 00000000 00000000 0>] ............ 803522d8: 00000000 00000000 20296338 00000000 ........8c) .... 803522e8: 00000000 00000000 00000000 00000000 ................ 803522f8: 00000000 00000000 302f3078 30353778 ........x0/0x750 80352308: 00000a29 00000000 00000000 00000000 )............... 80352318: 00000000 00000000 65653565 00000020 ........e5ee ... 80352328: 00000000 00000000 00000000 00000000 ................ 80352338: 00000000 00000000 00002029 00000000 ........) ...... 80352348: 00000000 00000000 00000000 00000000 ................ 80352358: 00000000 00000000 65316233 2d5d2033 ........3b1e3 ]- 80352368: 000a2d2d 00000000 00000000 00000000 --.............. 80352378: 00000000 00000000 6e797320 676e6963 ........ syncing 80352388: 7441203a 706d6574 20646574 6b206f74 : Attempted to k 80352398: 206c6c69 74696e69 00000a21 00000000 ill init!....... 803523a8: 00000000 00000000 00000000 00000000 ................ 803523b8: 00000000 00000000 00000000 00000000 ................ 803523c8: 00000000 00000000 00000000 00000000 ................ 803523d8: 00000000 00000000 00000000 00000000 ................ 803523e8: 00000000 00000000 00000000 00000000 ................ 803523f8: 00000000 00000000 00000000 00000000 ................ 80352408: 00000000 00000000 00000000 00000000 ................ 80352418: 00000000 00000000 00000000 00000000 ................ 80352428: 00000000 00000000 00000000 00000000 ................ 80352438: 00000000 00000000 00000000 00000000 ................ 80352448: 00000000 00000000 00000000 00000000 ................ 80352458: 00000000 00000000 00000000 00000000 ................ 80352468: 00000000 00000000 00000000 00000000 ................ 80352478: 00000000 00000000 00000000 00000000 ................ 80352488: 00000000 00000000 00000000 00000000 ................ 80352498: 00000000 00000000 00000000 00000000 ................

4 42

[U-Boot] PPC4xx without CONFIG_NET_MULTI
by Ben Warren 04 May '09

04 May '09

Hi Stefan (and anybody else that can answer), I'm trying to understand why some 4xx boards use CONFIG_NET_MULTI and a few don't. Is there a technical reason why these few can't (limited storage or something else) or are they just older? There are 47 boards in-tree that use CONFIG_PPC4xx_EMAC and the following 18 use the older net API. --- bwarren@bwarren-bldsrv:~/src/u-boot-net/include/configs$ grep -l PPC4xx_EMAC * | xargs grep -L CONFIG_NET_MULTI AR405.h CPCIISER4.h CRAYL1.h csb272.h csb472.h DP405.h ERIC.h EXBITGEN.h HUB405.h JSE.h MIP405.h OCRTC.h ORSG.h PIP405.h sbc405.h W7OLMC.h W7OLMG.h WUH405.h --- I'd like to move all over to CONFIG_NET_MULTI, which in itself is trivial since the EMAC driver supports both APIs, but am wary of breaking something. regards, Ben

4 7

[U-Boot] [PATCH 1/6] esd/common: extend cpld command with address parameter
by matthias.fuchs＠esd.eu 04 May '09

04 May '09

From: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> This patch adds support for an address parameter to esd's cpld command. This is in preparation to remove compiled-in binary cpld (xsvf) bitstreams. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- board/esd/common/xilinx_jtag/micro.c | 24 ++++++++++++++++-------- board/esd/common/xilinx_jtag/ports.c | 10 ++++------ 2 files changed, 20 insertions(+), 14 deletions(-) diff --git a/board/esd/common/xilinx_jtag/micro.c b/board/esd/common/xilinx_jtag/micro.c index 9b2cf90..37ac0cc 100644 --- a/board/esd/common/xilinx_jtag/micro.c +++ b/board/esd/common/xilinx_jtag/micro.c @@ -66,10 +66,7 @@ #include "lenval.h" #include "ports.h" - -extern const unsigned char fpgadata[]; -extern int filesize; - +const unsigned char *xsvfdata; /*============================================================================ * XSVF #define @@ -1838,12 +1835,23 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned long duration; unsigned long long startClock, endClock; + if (argc == 2) + xsvfdata = (unsigned char *)simple_strtoul(argv[1], NULL, 16); + else { +#ifdef CONFIG_SYS_XSVF_DEFAULT_ADDR + xsvfdata = (unsigned char *)CONFIG_SYS_XSVF_DEFAULT_ADDR; +#else + printf("Usage:\ncpld %s\n", cmdtp->help); + return -1; +#endif + } + iErrorCode = XSVF_ERRORCODE( XSVF_ERROR_NONE ); pzXsvfFileName = 0; xsvf_iDebugLevel = 0; printf("XSVF Player v%s, Xilinx, Inc.\n", XSVF_VERSION); - printf("XSVF Filesize = %d bytes\n", filesize); + printf("Reading XSVF data @ %p\n", xsvfdata); /* Initialize the I/O. SetPort initializes I/O on first call */ setPort( TMS, 1 ); @@ -1858,7 +1866,7 @@ int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return( iErrorCode ); } U_BOOT_CMD( - cpld, 1, 1, do_cpld, - "Program onboard CPLD", - NULL + cpld, 2, 1, do_cpld, + "program onboard CPLD", + "<xsvf-addr>" ); diff --git a/board/esd/common/xilinx_jtag/ports.c b/board/esd/common/xilinx_jtag/ports.c index ac0d7ac..f039d04 100644 --- a/board/esd/common/xilinx_jtag/ports.c +++ b/board/esd/common/xilinx_jtag/ports.c @@ -42,9 +42,7 @@ static int oldstate = 0; static int newstate = 0; static int readptr = 0; -extern long filesize; -extern const unsigned char fpgadata[]; - +extern const unsigned char *xsvfdata; /* if in debugging mode, then just set the variables */ void setPort(short p,short val) @@ -86,10 +84,10 @@ void pulseClock(void) void readByte(unsigned char *data) { /* pretend reading using a file */ - *data = fpgadata[readptr++]; - newstate = (100 * filepos++) / filesize; + *data = xsvfdata[readptr++]; + newstate = filepos++ >> 10; if (newstate != oldstate) { - printf("%4d\r\r\r\r", newstate); + printf("%4d kB\r\r\r\r", newstate); oldstate = newstate; } } -- 1.5.3

2 6

[U-Boot] [PATCH] ARM DaVinci:Adding DM365 Support
by s-paulraj＠ti.com 04 May '09

04 May '09

Patch adds support for DaVinci DM365. It does not have the DM9000 like the DM355 but has capability for 4 BIT ECC correction just like DM355. This patch lacks 2 features 1) No 4 BIT ECC correction. We will add support for 4 BIT ECC correction to the NAND driver(davinci_nand.c) soon so that other device like the DM355 can also use this feature. Other TI SOCs like DA830(Primus) not yet part of the U-Boot GIT can also use this once support is added. Some core NAND driver APIs were changed and are being used by TI in our internal releases but those patches were not accepted when posted to the MTD list. So this support will have to wait for some time. 2) I have managed to get EMAC working in my branch but i see that there are patches where the location of the EMAC driver has changed along with a few other changes. The EMAC on all TI SOCs like DM644x, DM6467, DM365 and DA830 is simlar but not the same. So i need to come up with a patch which will enable EMAC to work on all TI SOCs. Patches for the above features mentioned will be added soon. Patch for 4 BIT ECC correction and EMAC should not take much time to submit but the feature where we change the NAND read APIs to work along with the EMIF 2.3 IP present in latest DaVinci SOCs will take some time. Signed-off-by: Sandeep Paulraj <s-paulraj(a)ti.com> --- MAKEALL | 1 + Makefile | 3 + board/davinci/dm365_evm/Makefile | 52 ++++++++++ board/davinci/dm365_evm/board_init.S | 29 ++++++ board/davinci/dm365_evm/config.mk | 39 ++++++++ board/davinci/dm365_evm/dm365_evm.c | 97 +++++++++++++++++++ board/davinci/dm365_evm/u-boot.lds | 52 ++++++++++ cpu/arm926ejs/davinci/Makefile | 1 + cpu/arm926ejs/davinci/dm365.c | 39 ++++++++ include/asm-arm/arch-davinci/hardware.h | 3 + include/configs/davinci_dm365_evm.h | 155 +++++++++++++++++++++++++++++++ 11 files changed, 471 insertions(+), 0 deletions(-) create mode 100644 board/davinci/dm365_evm/Makefile create mode 100644 board/davinci/dm365_evm/board_init.S create mode 100644 board/davinci/dm365_evm/config.mk create mode 100755 board/davinci/dm365_evm/dm365_evm.c create mode 100644 board/davinci/dm365_evm/u-boot.lds create mode 100644 cpu/arm926ejs/davinci/dm365.c create mode 100644 include/configs/davinci_dm365_evm.h diff --git a/MAKEALL b/MAKEALL index c65f418..31cbaef 100755 --- a/MAKEALL +++ b/MAKEALL @@ -529,6 +529,7 @@ LIST_ARM9=" \ davinci_sonata \ davinci_dm355evm \ davinci_dm357_evm \ + davinci_dm365_evm \ " ######################################################################### diff --git a/Makefile b/Makefile index fb0ce64..6a8ffa0 100644 --- a/Makefile +++ b/Makefile @@ -2796,6 +2796,9 @@ davinci_dm355evm_config : unconfig davinci_dm357_evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm357_evm davinci davinci +davinci_dm365_evm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dm365_evm davinci davinci + lpd7a400_config \ lpd7a404_config: unconfig @$(MKCONFIG) $(@:_config=) arm lh7a40x lpd7a40x diff --git a/board/davinci/dm365_evm/Makefile b/board/davinci/dm365_evm/Makefile new file mode 100644 index 0000000..a0ed353 --- /dev/null +++ b/board/davinci/dm365_evm/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dm365_evm.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dm365_evm/board_init.S b/board/davinci/dm365_evm/board_init.S new file mode 100644 index 0000000..22d8adc --- /dev/null +++ b/board/davinci/dm365_evm/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/dm365_evm/config.mk b/board/davinci/dm365_evm/config.mk new file mode 100644 index 0000000..aa89d0e --- /dev/null +++ b/board/davinci/dm365_evm/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# (C) Copyright 2003 +# Texas Instruments, <www.ti.com> +# Swaminathan <swami.iyer(a)ti.com> +# +# Davinci EVM board (ARM925EJS) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# Davinci EVM has 1 bank of 256 MB DDR RAM +# Physical Address: +# 8000'0000 to 9000'0000 +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# Visioneering Corp. Sonata board (ARM926EJS) cpu +# +# Sonata board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu +# +# Schmoogie board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 8800'0000 +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# we load ourself to 8108 '0000 +# +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm365_evm/dm365_evm.c b/board/davinci/dm365_evm/dm365_evm.c new file mode 100755 index 0000000..24b40d0 --- /dev/null +++ b/board/davinci/dm365_evm/dm365_evm.c @@ -0,0 +1,97 @@ +/* + * + * Copyright (C) 2009 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + * + */ +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/i2c_defs.h> + +/******************************************* + Routine: board_init + Description: Board Initialization routine +*******************************************/ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + /* arch number of DaVinci DM365 */ + gd->bd->bi_arch_number = 1939; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return 0; +} + + +/****************************** + Routine: misc_init_r + Description: Misc. init +******************************/ +int misc_init_r(void) +{ + int i; + u_int8_t tmp[20], buf[10]; + + /* Set Ethernet MAC address from EEPROM */ + if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7f00, + CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, 6)) { + printf("\nEEPROM @ 0x%02x read FAILED!!!\n", + CONFIG_SYS_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], + "%02x:%02x:%02x:%02x:%02x:%02x", buf[0], + buf[1], buf[2], buf[3], buf[4], buf[5]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) + printf("ethernet init failed!\n"); + + return 0; +} + +/****************************** + Routine: dram_init + Description: Memory Info +******************************/ +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + diff --git a/board/davinci/dm365_evm/u-boot.lds b/board/davinci/dm365_evm/u-boot.lds new file mode 100644 index 0000000..4d50f2c --- /dev/null +++ b/board/davinci/dm365_evm/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/cpu/arm926ejs/davinci/Makefile b/cpu/arm926ejs/davinci/Makefile index dee5be4..96e495a 100644 --- a/cpu/arm926ejs/davinci/Makefile +++ b/cpu/arm926ejs/davinci/Makefile @@ -30,6 +30,7 @@ LIB = $(obj)lib$(SOC).a COBJS-y += timer.o psc.o COBJS-$(CONFIG_SOC_DM355) += dm355.o COBJS-$(CONFIG_SOC_DM644X) += dm644x.o +COBJS-$(CONFIG_SOC_DM365) += dm365.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += ether.o lxt972.o dp83848.o SOBJS = reset.o diff --git a/cpu/arm926ejs/davinci/dm365.c b/cpu/arm926ejs/davinci/dm365.c new file mode 100644 index 0000000..01efb34 --- /dev/null +++ b/cpu/arm926ejs/davinci/dm365.c @@ -0,0 +1,39 @@ +/* + * TI DM365 SOC specific code + * + * Copyright (C) 2009 Texas Instruments + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <common.h> +#include <asm/arch/hardware.h> + + +void davinci_enable_uart0(void) +{ + lpsc_on(DAVINCI_LPSC_UART0); +} + + +#ifdef CONFIG_DRIVER_DAVINCI_I2C +void davinci_enable_i2c(void) +{ + lpsc_on(DAVINCI_LPSC_I2C); +} +#endif diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index a28cfb4..d38ab72 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -99,6 +99,9 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000 #define DAVINCI_MMC_SD0_BASE 0x01e11000 +#elif defined(CONFIG_SOC_DM365) +#define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000 + #endif /* Power and Sleep Controller (PSC) Domains */ diff --git a/include/configs/davinci_dm365_evm.h b/include/configs/davinci_dm365_evm.h new file mode 100644 index 0000000..a3a5016 --- /dev/null +++ b/include/configs/davinci_dm365_evm.h @@ -0,0 +1,155 @@ +/* + * (C) Copyright 2009 + * Texas Instruments Inc. + * Configuation settings for the TI Davinci DM365 EVM board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/*=======*/ +/* Board */ +/*=======*/ +#define CFG_DM365_EVM +#define CONFIG_SYS_USE_NAND +#define CONFIG_SOC_DM365 +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK 24000000 +#define CONFIG_SYS_HZ 1000 +/*====================================================*/ +/* EEPROM definitions for the DM365 EVM */ +/*====================================================*/ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CONFIG_SYS_MALLOC_LEN (0x40000 + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_SYS_MEMTEST_START 0x82000000 +#define CONFIG_SYS_MEMTEST_END 0x90000000 +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x8000000 /* DDR size 128MB */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CONFIG_SYS_NS16550_CLK 24000000 +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 10 +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#define CONFIG_NAND_DAVINCI +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* Env sector Size */ +#define CONFIG_ENV_SIZE SZ_256K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CONFIG_SYS_NAND_BASE 0x02000000 +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define CONFIG_ENV_OFFSET 0x3C0000 +#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ + CONFIG_SYS_NAND_BASE + 0x4000} +#define DEF_BOOTM "" +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#define CONFIG_BOOTDELAY 4 +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DM365 EVM > " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_LOAD_ADDR 0x80700000 +#define CONFIG_VERSION_VARIABLE +#define CONFIG_CMDLINE_EDITING +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */ -- 1.6.0.4

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Re: [U-Boot] Help!Some memory doesn't work on PPC405Ex based board!
by SunNeo 04 May '09

04 May '09

Feng Kan, Stefan and Grant, Thanks for all your suggestion. I tried to add auto-calibration related configuration to my configuation file, but Linux still hangs at the same location. It seems error happened when threads of Linux Kernel tried to access the high 512m memory. Just like the Kilauea evb, there is no ECC on my board, and I use the same regisger setting for DDR Controller as Kilauea. Maybe you know, Kilauea uses the "MT47H64M16HR" DDRII SDRAM and only one rank. My board uses the "MT47H256M8THN" and two ranks. So, I changed setting of MB0CF & MB1CF. I think I can confirm all 1024M memory can work well at U-Boot. And if I add the parameter "mem=512M" to bootargs, and set "initrd_high" to "20000000", Linux can boot normally. Best Regards, Sun > Date: Tue, 14 Apr 2009 09:30:46 -0700 > From: fkan(a)amcc.com > To: sunwx2001(a)hotmail.com > CC: support(a)amcc.com; linuxppc-dev(a)ozlabs.org > Subject: Re: Help!Some memory doesn't work on PPC405Ex based board! > > Hi SunNeo: > > The fact that it is hanging at the same place in kernel seems strange. > Usually when dram initialization is incorrect, > the kernel would not run at all. Uboot just hangs at relocate code. I > suggest you turn on early kernel printf to see > if you get some other outputs. > > P.S when you have discrete memory on board. you have to be sure that > your calibration values are correct. The RDCC > RQDC value should be best possible. You can run the fix initialization > and then lift the autocalibration routine > to the end of the fix dram init to determine the best RFDC RQDC windows. > After that recode the fix values for those > registers. > > Feng Kan > AMCC Software > > SunNeo wrote: > > Hi, Stefan, > > > > Thanks for your help. > > > > My platform uses the MICRON MT47H256M8THN DDRII SDRAM and the DDRII SDRAM is soldered on the board. > > > > As I said, my board was similar with "Kilauea" evb, so I created my configuration header file from Kilauea's at U-Boot. In the configuration file, register value for the DDR SDRAM controller is defined. But I have removed DDR autocalibraton related configuration from the configuration file, do you think this will cause any issues? > > > > I'm not sure what you mean about "intensive memory test". I use "mm" cmd under U-Boot command prompt to modify value of high 512M memory, and this command works well. > > > > About booting Linux, the kernel hangs at the same location. Always after this print info "<4>Mount-cache hash table entries: 512". > > > > Best Regards, > > Sun > > > > > >> From: sr(a)denx.de > >> To: linuxppc-dev(a)ozlabs.org > >> Subject: Re: Help!Some memory doesn't work on PPC405Ex based board! > >> Date: Tue, 14 Apr 2009 11:23:02 +0200 > >> CC: sunwx2001(a)hotmail.com > >> > >> On Monday 13 April 2009, SunNeo wrote: > >> > >>> I'm porting Linux-2.6.29 on PPC405Ex based board, it's very similar to AMCC > >>> "Kilauea" evb. > >>> > >>> In my board, two 512MB DDRII memory is connected to 2 ranks of the 405Ex > >>> CPU. This 1GB memory works well at U-Boot-2009.01, but when I boot > >>> Linux-2.6.29, the kernel hangs somewhere. > >>> > >> Does it just hang "somewhere", or always at the same location? A random hangup > >> could mean that you are having a memory problem (hardware, or wrong > >> initialization). > >> > >> > >>> What interesting is, if I > >>> configured the system to use only 512MB memory at U-Boot, the Linux can > >>> boot normally . > >>> > >> Are you using DIMM's on your platform? Or soldered chips? Which memory > >> initialization code are you using in U-Boot? And which autocalibration code? > >> > >> Did you do some intensive memory test? > >> > >> Best regards, > >> Stefan > >> > > > > > > _____ > > > > 把MSN装进手机，更多聊天乐趣等你挖掘！立刻下载！ <http://mobile.msn.com.cn/> > > > > > _________________________________________________________________ 打工，挣钱，买房子，快来MClub一起”金屋藏娇”！ http://club.msn.cn/?from=10

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