April 2009 - U-Boot

[U-Boot] Pull request: u-boot-usb
by Remy Bohmer 07 Apr '09

07 Apr '09

The following changes since commit 712ac6a1a6909a58d6549fb220cc921a7e9f9979: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-arm are available in the git repository at: git://git.denx.de/u-boot-usb.git master Jean-Christophe PLAGNIOL-VILLARD (1): drivers/usb: regorganisation Remy Bohmer (1): Support for PXA27X UDC. Makefile | 4 +- drivers/serial/usbtty.c | 2 +- drivers/serial/usbtty.h | 10 +- drivers/usb/{ => gadget}/Makefile | 31 +- drivers/usb/{usbdcore.c => gadget/core.c} | 2 +- drivers/usb/{usbdcore_ep0.c => gadget/ep0.c} | 2 +- include/usbdcore_ep0.h => drivers/usb/gadget/ep0.h | 0 .../usb/{usbdcore_mpc8xx.c => gadget/mpc8xx_udc.c} | 9 +- .../{usbdcore_omap1510.c => gadget/omap1510_udc.c} | 6 +- drivers/usb/gadget/pxa27x_udc.c | 702 ++++++++++++++++++++ drivers/usb/{ => host}/Makefile | 37 +- drivers/usb/{usb_ehci_core.h => host/ehci-core.h} | 0 drivers/usb/{usb_ehci_fsl.c => host/ehci-fsl.c} | 6 +- drivers/usb/{usb_ehci_fsl.h => host/ehci-fsl.h} | 0 drivers/usb/{usb_ehci_core.c => host/ehci-hcd.c} | 3 +- drivers/usb/{usb_ehci_ixp.c => host/ehci-ixp4xx.c} | 5 +- drivers/usb/{usb_ehci_pci.c => host/ehci-pci.c} | 5 +- drivers/usb/{usb_ehci_vct.c => host/ehci-vct.c} | 4 +- drivers/usb/{usb_ehci.h => host/ehci.h} | 0 drivers/usb/{ => host}/isp116x-hcd.c | 0 drivers/usb/{ => host}/isp116x.h | 0 drivers/usb/{atmel_usb.c => host/ohci-at91.c} | 0 drivers/usb/{usb_ohci.c => host/ohci-hcd.c} | 3 +- drivers/usb/{usb_ohci.h => host/ohci.h} | 0 drivers/usb/{ => host}/r8a66597-hcd.c | 0 drivers/usb/{ => host}/r8a66597.h | 0 drivers/usb/{s3c64xx_usb.c => host/s3c64xx-hcd.c} | 0 drivers/usb/{sl811_usb.c => host/sl811-hcd.c} | 2 +- drivers/usb/{ => host}/sl811.h | 0 drivers/usb/musb/Makefile | 47 ++ drivers/usb/{davinci_usb.c => musb/davinci.c} | 2 +- drivers/usb/{davinci_usb.h => musb/davinci.h} | 0 drivers/usb/{ => musb}/musb_core.c | 0 drivers/usb/{ => musb}/musb_core.h | 0 drivers/usb/{ => musb}/musb_hcd.c | 0 drivers/usb/{ => musb}/musb_hcd.h | 0 include/asm-arm/arch-pxa/pxa-regs.h | 296 +++++++-- include/{usbdcore_mpc8xx.h => usb/mpc8xx_udc.h} | 0 .../{usbdcore_omap1510.h => usb/omap1510_udc.h} | 0 include/usb/pxa27x_udc.h | 69 ++ include/{usbdcore.h => usbdevice.h} | 0 41 files changed, 1118 insertions(+), 129 deletions(-) copy drivers/usb/{ => gadget}/Makefile (60%) rename drivers/usb/{usbdcore.c => gadget/core.c} (99%) rename drivers/usb/{usbdcore_ep0.c => gadget/ep0.c} (99%) rename include/usbdcore_ep0.h => drivers/usb/gadget/ep0.h (100%) rename drivers/usb/{usbdcore_mpc8xx.c => gadget/mpc8xx_udc.c} (99%) rename drivers/usb/{usbdcore_omap1510.c => gadget/omap1510_udc.c} (99%) create mode 100644 drivers/usb/gadget/pxa27x_udc.c rename drivers/usb/{ => host}/Makefile (64%) rename drivers/usb/{usb_ehci_core.h => host/ehci-core.h} (100%) rename drivers/usb/{usb_ehci_fsl.c => host/ehci-fsl.c} (97%) rename drivers/usb/{usb_ehci_fsl.h => host/ehci-fsl.h} (100%) rename drivers/usb/{usb_ehci_core.c => host/ehci-hcd.c} (99%) rename drivers/usb/{usb_ehci_ixp.c => host/ehci-ixp4xx.c} (96%) rename drivers/usb/{usb_ehci_pci.c => host/ehci-pci.c} (97%) rename drivers/usb/{usb_ehci_vct.c => host/ehci-vct.c} (96%) rename drivers/usb/{usb_ehci.h => host/ehci.h} (100%) rename drivers/usb/{ => host}/isp116x-hcd.c (100%) rename drivers/usb/{ => host}/isp116x.h (100%) rename drivers/usb/{atmel_usb.c => host/ohci-at91.c} (100%) rename drivers/usb/{usb_ohci.c => host/ohci-hcd.c} (99%) rename drivers/usb/{usb_ohci.h => host/ohci.h} (100%) rename drivers/usb/{ => host}/r8a66597-hcd.c (100%) rename drivers/usb/{ => host}/r8a66597.h (100%) rename drivers/usb/{s3c64xx_usb.c => host/s3c64xx-hcd.c} (100%) rename drivers/usb/{sl811_usb.c => host/sl811-hcd.c} (99%) rename drivers/usb/{ => host}/sl811.h (100%) create mode 100644 drivers/usb/musb/Makefile rename drivers/usb/{davinci_usb.c => musb/davinci.c} (99%) rename drivers/usb/{davinci_usb.h => musb/davinci.h} (100%) rename drivers/usb/{ => musb}/musb_core.c (100%) rename drivers/usb/{ => musb}/musb_core.h (100%) rename drivers/usb/{ => musb}/musb_hcd.c (100%) rename drivers/usb/{ => musb}/musb_hcd.h (100%) rename include/{usbdcore_mpc8xx.h => usb/mpc8xx_udc.h} (100%) rename include/{usbdcore_omap1510.h => usb/omap1510_udc.h} (100%) create mode 100644 include/usb/pxa27x_udc.h rename include/{usbdcore.h => usbdevice.h} (100%)

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[U-Boot] ARM Pull Request
by Jean-Christophe PLAGNIOL-VILLARD 07 Apr '09

07 Apr '09

Hi Wolfgang, Please pull The following changes since commit 23e4af49e066a53cd3e3659b68ef90572d88de84: Guennadi Liakhovetski (1): ARM: add the imx31_phycore_eet target to MAINTAINERS are available in the git repository at: git://git.denx.de/u-boot-arm.git master Dirk Behme (1): OMAP3: Update Overo pin mux for new expansion board Jean-Christophe PLAGNIOL-VILLARD (4): arm: update co-processor 15 access arm: clean cache management arm: unify reset command integratorap: fix PCI support Kyungmin Park (1): Move machine specific code to board at s3c64xx (v2) Minkyu Kang (1): s3c64xx: fix the wrong gpio offset Sanjeev Premi (1): OMAP: Fix compile issue Tom Rix (2): OMAP3 Fix multiline formatting in board init files. ZOOM1 Remove legacy NAND defines board/armltd/integratorap/split_by_variant.sh | 18 +++- board/omap3/beagle/beagle.c | 20 ++-- board/omap3/evm/evm.c | 16 ++-- board/omap3/overo/overo.c | 12 +- board/omap3/overo/overo.h | 9 +- board/omap3/pandora/pandora.c | 12 +- board/omap3/zoom1/zoom1.c | 12 +- board/samsung/smdk6400/lowlevel_init.S | 7 ++ cpu/arm1136/cpu.c | 90 ++---------------- cpu/arm1176/cpu.c | 103 +-------------------- cpu/arm1176/s3c64xx/cpu_init.S | 7 -- cpu/arm720t/cpu.c | 120 +++--------------------- cpu/arm920t/cpu.c | 124 ++---------------------- cpu/arm925t/cpu.c | 96 ++----------------- cpu/arm926ejs/cpu.c | 125 ++---------------------- cpu/arm946es/cpu.c | 101 ++------------------ cpu/arm_cortexa8/cpu.c | 82 +---------------- cpu/arm_cortexa8/omap3/board.c | 2 +- cpu/arm_intcm/cpu.c | 25 ----- cpu/ixp/cpu.c | 83 ++-------------- cpu/lh7a40x/cpu.c | 121 ++---------------------- cpu/pxa/cpu.c | 81 ++-------------- cpu/s3c44b0/cpu.c | 9 -- cpu/sa1100/cpu.c | 81 ++-------------- include/asm-arm/system.h | 84 +++++++++++++++++ include/configs/B2.h | 1 + include/configs/assabet.h | 2 + include/configs/cerf250.h | 3 + include/configs/cradle.h | 3 + include/configs/csb226.h | 4 + include/configs/delta.h | 3 + include/configs/dnp1110.h | 2 + include/configs/evb4510.h | 1 + include/configs/gcplus.h | 2 + include/configs/innokom.h | 4 + include/configs/integratorap.h | 4 +- include/configs/lart.h | 2 + include/configs/logodl.h | 4 + include/configs/lubbock.h | 3 + include/configs/omap3_zoom1.h | 17 ---- include/configs/pleb2.h | 3 + include/configs/pxa255_idp.h | 3 + include/configs/shannon.h | 2 + include/configs/trizepsiv.h | 3 + include/configs/wepep250.h | 2 + include/configs/xaeniax.h | 3 + include/configs/xm250.h | 3 + include/configs/xsengine.h | 3 + include/configs/zylonite.h | 3 + include/s3c6400.h | 11 ++- lib_arm/Makefile | 4 + lib_arm/cache-cp15.c | 120 ++++++++++++++++++++++++ lib_arm/reset.c | 53 +++++++++++ 53 files changed, 501 insertions(+), 1207 deletions(-) create mode 100644 include/asm-arm/system.h create mode 100644 lib_arm/cache-cp15.c create mode 100644 lib_arm/reset.c Best Regards, J.

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Re: [U-Boot] Auto-response for your message to the "U-Boot-Users" mailing list
by justin_q 07 Apr '09

07 Apr '09

在2009-04-08，u-boot-users-bounces(a)lists.sourceforge.net 写道： >This mailing list is dead. Please subscribe to the >u-boot(a)lists.denx.de mailing list instead. For details please see >http://lists.denx.de/mailman/listinfo/u-boot

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[U-Boot] [PATCH] Add support to Colibri PXA-270 board
by Alon Bar-Lev 07 Apr '09

07 Apr '09

This configuration is based on the trizepsiv board, and the work Daniel Mack did in the past [1]. The following files were taken as-is from trizepsiv board: - lowlevel_init.S - pxavoltage.S - u-boot.lds The main module is the same except it does not use multi serial and does not have usb support. The configuration is based on Daniel Mack work, with zeros when trizepsiv required configuration while Daniel did not provide any. After modification, u-boot is running, can access the on-board flash, can access network using Ethernet and can boot Linux kernel. Although there are few colibri boards, the name "colibri" for the board is the same as the name the linux kernel has for the Colibri PXA-270 board. Signed-off-by: Alon Bar-Lev <alon.barlev(a)gmail.com> [1] http://www.mail-archive.com/u-boot-users%40lists.sourceforge.net/msg01498.h… --- diff --git a/Makefile b/Makefile index 49b83c0..4e5e290 100644 --- a/Makefile +++ b/Makefile @@ -3039,6 +3039,9 @@ pxa255_idp_config: unconfig trizepsiv_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa trizepsiv +colibri_config : unconfig + @$(MKCONFIG) $(@:_config=) arm pxa colibri + wepep250_config : unconfig @$(MKCONFIG) $(@:_config=) arm pxa wepep250 diff --git a/board/colibri/Makefile b/board/colibri/Makefile new file mode 100644 index 0000000..efd67e1 --- /dev/null +++ b/board/colibri/Makefile @@ -0,0 +1,51 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := lowlevel_init.o pxavoltage.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/colibri/colibri.c b/board/colibri/colibri.c new file mode 100644 index 0000000..fd91836 --- /dev/null +++ b/board/colibri/colibri.c @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley(a)applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* ------------------------------------------------------------------------- */ + +int board_init (void) +{ + /* memory and cpu-speed are setup before relocation */ + /* so we do _nothing_ here */ + + /* arch number of Board */ + gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0xa0000100; + + return 0; +} + +int board_late_init(void) +{ + setenv("stdout", "serial"); + setenv("stdin", "serial"); + setenv("stderr", "serial"); + return 0; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; + + return 0; +} diff --git a/board/colibri/config.mk b/board/colibri/config.mk new file mode 100644 index 0000000..4486f6b --- /dev/null +++ b/board/colibri/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE =0xa1f00000 +# 0xa1700000 +#TEXT_BASE = 0 diff --git a/board/colibri/lowlevel_init.S b/board/colibri/lowlevel_init.S new file mode 100644 index 0000000..128d554 --- /dev/null +++ b/board/colibri/lowlevel_init.S @@ -0,0 +1,503 @@ +/* + * This was originally from the Lubbock u-boot port. + * + * Most of this taken from Redboot hal_platform_setup.h with cleanup + * + * NOTE: I haven't clean this up considerably, just enough to get it + * running. See hal_platform_setup.h for the source. See + * board/cradle/lowlevel_init.S for another PXA250 setup that is + * much cleaner. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/arch/pxa-regs.h> + +/* wait for coprocessor write complete */ + .macro CPWAIT reg + mrc p15,0,\reg,c2,c0,0 + mov \reg,\reg + sub pc,pc,#4 + .endm + + +/* + * Memory setup + */ + +.globl lowlevel_init +lowlevel_init: + + /* Set up GPIO pins first ----------------------------------------- */ + + ldr r0, =GPSR0 + ldr r1, =CONFIG_SYS_GPSR0_VAL + str r1, [r0] + + ldr r0, =GPSR1 + ldr r1, =CONFIG_SYS_GPSR1_VAL + str r1, [r0] + + ldr r0, =GPSR2 + ldr r1, =CONFIG_SYS_GPSR2_VAL + str r1, [r0] + + ldr r0, =GPSR3 + ldr r1, =CONFIG_SYS_GPSR3_VAL + str r1, [r0] + + ldr r0, =GPCR0 + ldr r1, =CONFIG_SYS_GPCR0_VAL + str r1, [r0] + + ldr r0, =GPCR1 + ldr r1, =CONFIG_SYS_GPCR1_VAL + str r1, [r0] + + ldr r0, =GPCR2 + ldr r1, =CONFIG_SYS_GPCR2_VAL + str r1, [r0] + + ldr r0, =GPCR3 + ldr r1, =CONFIG_SYS_GPCR3_VAL + str r1, [r0] + + ldr r0, =GRER0 + ldr r1, =CONFIG_SYS_GRER0_VAL + str r1, [r0] + + ldr r0, =GRER1 + ldr r1, =CONFIG_SYS_GRER1_VAL + str r1, [r0] + + ldr r0, =GRER2 + ldr r1, =CONFIG_SYS_GRER2_VAL + str r1, [r0] + + ldr r0, =GRER3 + ldr r1, =CONFIG_SYS_GRER3_VAL + str r1, [r0] + + ldr r0, =GFER0 + ldr r1, =CONFIG_SYS_GFER0_VAL + str r1, [r0] + + ldr r0, =GFER1 + ldr r1, =CONFIG_SYS_GFER1_VAL + str r1, [r0] + + ldr r0, =GFER2 + ldr r1, =CONFIG_SYS_GFER2_VAL + str r1, [r0] + + ldr r0, =GFER3 + ldr r1, =CONFIG_SYS_GFER3_VAL + str r1, [r0] + + ldr r0, =GPDR0 + ldr r1, =CONFIG_SYS_GPDR0_VAL + str r1, [r0] + + ldr r0, =GPDR1 + ldr r1, =CONFIG_SYS_GPDR1_VAL + str r1, [r0] + + ldr r0, =GPDR2 + ldr r1, =CONFIG_SYS_GPDR2_VAL + str r1, [r0] + + ldr r0, =GPDR3 + ldr r1, =CONFIG_SYS_GPDR3_VAL + str r1, [r0] + + ldr r0, =GAFR0_L + ldr r1, =CONFIG_SYS_GAFR0_L_VAL + str r1, [r0] + + ldr r0, =GAFR0_U + ldr r1, =CONFIG_SYS_GAFR0_U_VAL + str r1, [r0] + + ldr r0, =GAFR1_L + ldr r1, =CONFIG_SYS_GAFR1_L_VAL + str r1, [r0] + + ldr r0, =GAFR1_U + ldr r1, =CONFIG_SYS_GAFR1_U_VAL + str r1, [r0] + + ldr r0, =GAFR2_L + ldr r1, =CONFIG_SYS_GAFR2_L_VAL + str r1, [r0] + + ldr r0, =GAFR2_U + ldr r1, =CONFIG_SYS_GAFR2_U_VAL + str r1, [r0] + + ldr r0, =GAFR3_L + ldr r1, =CONFIG_SYS_GAFR3_L_VAL + str r1, [r0] + + ldr r0, =GAFR3_U + ldr r1, =CONFIG_SYS_GAFR3_U_VAL + str r1, [r0] + + ldr r0, =PSSR /* enable GPIO pins */ + ldr r1, =CONFIG_SYS_PSSR_VAL + str r1, [r0] + + /* ---------------------------------------------------------------- */ + /* Enable memory interface */ + /* */ + /* The sequence below is based on the recommended init steps */ + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ + /* Chapter 10. */ + /* ---------------------------------------------------------------- */ + + /* ---------------------------------------------------------------- */ + /* Step 1: Wait for at least 200 microsedonds to allow internal */ + /* clocks to settle. Only necessary after hard reset... */ + /* FIXME: can be optimized later */ + /* ---------------------------------------------------------------- */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + +mem_init: + + ldr r1, =MEMC_BASE /* get memory controller base addr. */ + + /* ---------------------------------------------------------------- */ + /* Step 2a: Initialize Asynchronous static memory controller */ + /* ---------------------------------------------------------------- */ + + /* MSC registers: timing, bus width, mem type */ + + /* MSC0: nCS(0,1) */ + ldr r2, =CONFIG_SYS_MSC0_VAL + str r2, [r1, #MSC0_OFFSET] + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ + /* that data latches */ + /* MSC1: nCS(2,3) */ + ldr r2, =CONFIG_SYS_MSC1_VAL + str r2, [r1, #MSC1_OFFSET] + ldr r2, [r1, #MSC1_OFFSET] + + /* MSC2: nCS(4,5) */ + ldr r2, =CONFIG_SYS_MSC2_VAL + str r2, [r1, #MSC2_OFFSET] + ldr r2, [r1, #MSC2_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2b: Initialize Card Interface */ + /* ---------------------------------------------------------------- */ + + /* MECR: Memory Expansion Card Register */ + ldr r2, =CONFIG_SYS_MECR_VAL + str r2, [r1, #MECR_OFFSET] + ldr r2, [r1, #MECR_OFFSET] + + /* MCMEM0: Card Interface slot 0 timing */ + ldr r2, =CONFIG_SYS_MCMEM0_VAL + str r2, [r1, #MCMEM0_OFFSET] + ldr r2, [r1, #MCMEM0_OFFSET] + + /* MCMEM1: Card Interface slot 1 timing */ + ldr r2, =CONFIG_SYS_MCMEM1_VAL + str r2, [r1, #MCMEM1_OFFSET] + ldr r2, [r1, #MCMEM1_OFFSET] + + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ + ldr r2, =CONFIG_SYS_MCATT0_VAL + str r2, [r1, #MCATT0_OFFSET] + ldr r2, [r1, #MCATT0_OFFSET] + + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ + ldr r2, =CONFIG_SYS_MCATT1_VAL + str r2, [r1, #MCATT1_OFFSET] + ldr r2, [r1, #MCATT1_OFFSET] + + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ + ldr r2, =CONFIG_SYS_MCIO0_VAL + str r2, [r1, #MCIO0_OFFSET] + ldr r2, [r1, #MCIO0_OFFSET] + + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ + ldr r2, =CONFIG_SYS_MCIO1_VAL + str r2, [r1, #MCIO1_OFFSET] + ldr r2, [r1, #MCIO1_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ + /* ---------------------------------------------------------------- */ + ldr r2, =CONFIG_SYS_FLYCNFG_VAL + str r2, [r1, #FLYCNFG_OFFSET] + str r2, [r1, #FLYCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ + /* ---------------------------------------------------------------- */ + + /* Before accessing MDREFR we need a valid DRI field, so we set */ + /* this to power on defaults + DRI field. */ + + ldr r4, [r1, #MDREFR_OFFSET] + ldr r2, =0xFFF + bic r4, r4, r2 + + ldr r3, =CONFIG_SYS_MDREFR_VAL + and r3, r3, r2 + + orr r4, r4, r3 + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + + orr r4, r4, #MDREFR_K0RUN + orr r4, r4, #MDREFR_K0DB4 + orr r4, r4, #MDREFR_K0FREE + orr r4, r4, #MDREFR_K0DB2 + orr r4, r4, #MDREFR_K1DB2 + bic r4, r4, #MDREFR_K1FREE + bic r4, r4, #MDREFR_K2FREE + + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ + ldr r4, [r1, #MDREFR_OFFSET] + + /* Note: preserve the mdrefr value in r4 */ + + + /* ---------------------------------------------------------------- */ + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ + /* ---------------------------------------------------------------- */ + + /* Initialize SXCNFG register. Assert the enable bits */ + + /* Write SXMRS to cause an MRS command to all enabled banks of */ + /* synchronous static memory. Note that SXLCR need not be written */ + /* at this time. */ + + ldr r2, =CONFIG_SYS_SXCNFG_VAL + str r2, [r1, #SXCNFG_OFFSET] + + /* ---------------------------------------------------------------- */ + /* Step 4: Initialize SDRAM */ + /* ---------------------------------------------------------------- */ + + bic r4, r4, #(MDREFR_K2FREE |MDREFR_K1FREE | MDREFR_K0FREE) + + orr r4, r4, #MDREFR_K1RUN + bic r4, r4, #MDREFR_K2DB2 + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + bic r4, r4, #MDREFR_SLFRSH + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + orr r4, r4, #MDREFR_E1PIN + str r4, [r1, #MDREFR_OFFSET] + ldr r4, [r1, #MDREFR_OFFSET] + + nop + nop + + + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ + /* configure but not enable each SDRAM partition pair. */ + + ldr r4, =CONFIG_SYS_MDCNFG_VAL + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) + bic r4, r4, #(MDCNFG_DE2|MDCNFG_DE3) + + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ + ldr r4, [r1, #MDCNFG_OFFSET] + + + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ + /* 100..200 �sec. */ + + ldr r3, =OSCR /* reset the OS Timer Count to zero */ + mov r2, #0 + str r2, [r3] + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ + /* so 0x300 should be plenty */ +1: + ldr r2, [r3] + cmp r4, r2 + bgt 1b + + + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ + /* attempting non-burst read or write accesses to disabled */ + /* SDRAM, as commonly specified in the power up sequence */ + /* documented in SDRAM data sheets. The address(es) used */ + /* for this purpose must not be cacheable. */ + + ldr r3, =CONFIG_SYS_DRAM_BASE + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + str r2, [r3] + + + /* Step 4g: Write MDCNFG with enable bits asserted */ + /* (MDCNFG:DEx set to 1). */ + + ldr r3, [r1, #MDCNFG_OFFSET] + mov r4, r3 + orr r3, r3, #MDCNFG_DE0 + str r3, [r1, #MDCNFG_OFFSET] + mov r0, r3 + + /* Step 4h: Write MDMRS. */ + + ldr r2, =CONFIG_SYS_MDMRS_VAL + str r2, [r1, #MDMRS_OFFSET] + + /* enable APD */ + ldr r3, [r1, #MDREFR_OFFSET] + orr r3, r3, #MDREFR_APD + str r3, [r1, #MDREFR_OFFSET] + + /* We are finished with Intel's memory controller initialisation */ + + +setvoltage: + + mov r10, lr + bl initPXAvoltage /* In case the board is rebooting with a */ + mov lr, r10 /* low voltage raise it up to a good one. */ + +#if 1 + b initirqs +#endif + +wakeup: + /* Are we waking from sleep? */ + ldr r0, =RCSR + ldr r1, [r0] + and r1, r1, #(RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR) + str r1, [r0] + teq r1, #RCSR_SMR + + bne initirqs + + ldr r0, =PSSR + mov r1, #PSSR_PH + str r1, [r0] + + /* if so, resume at PSPR */ + ldr r0, =PSPR + ldr r1, [r0] + mov pc, r1 + + /* ---------------------------------------------------------------- */ + /* Disable (mask) all interrupts at interrupt controller */ + /* ---------------------------------------------------------------- */ + +initirqs: + + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ + ldr r2, =ICLR + str r1, [r2] + + ldr r2, =ICMR /* mask all interrupts at the controller */ + str r1, [r2] + + /* ---------------------------------------------------------------- */ + /* Clock initialisation */ + /* ---------------------------------------------------------------- */ + +initclks: + + /* Disable the peripheral clocks, and set the core clock frequency */ + + /* Turn Off on-chip peripheral clocks (except for memory) */ + /* for re-configuration. */ + ldr r1, =CKEN + ldr r2, =CONFIG_SYS_CKEN + str r2, [r1] + + /* ... and write the core clock config register */ + ldr r2, =CONFIG_SYS_CCCR + ldr r1, =CCCR + str r2, [r1] + + /* Turn on turbo mode */ + mrc p14, 0, r2, c6, c0, 0 + orr r2, r2, #0xB /* Turbo, Fast-Bus, Freq change**/ + mcr p14, 0, r2, c6, c0, 0 + + /* Re-write MDREFR */ + ldr r1, =MEMC_BASE + ldr r2, [r1, #MDREFR_OFFSET] + str r2, [r1, #MDREFR_OFFSET] +#ifdef RTC + /* enable the 32Khz oscillator for RTC and PowerManager */ + ldr r1, =OSCC + mov r2, #OSCC_OON + str r2, [r1] + + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ + /* has settled. */ +60: + ldr r2, [r1] + ands r2, r2, #1 + beq 60b +#else +#error "RTC not defined" +#endif + + /* Interrupt init: Mask all interrupts */ + ldr r0, =ICMR /* enable no sources */ + mov r1, #0 + str r1, [r0] + /* FIXME */ + +#ifdef NODEBUG + /*Disable software and data breakpoints */ + mov r0,#0 + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ + mcr p15,0,r0,c14,c4,0 /* dbcon */ + + /*Enable all debug functionality */ + mov r0,#0x80000000 + mcr p14,0,r0,c10,c0,0 /* dcsr */ +#endif + + /* ---------------------------------------------------------------- */ + /* End lowlevel_init */ + /* ---------------------------------------------------------------- */ + +endlowlevel_init: + + mov pc, lr diff --git a/board/colibri/pxavoltage.S b/board/colibri/pxavoltage.S new file mode 100644 index 0000000..9659c2b --- /dev/null +++ b/board/colibri/pxavoltage.S @@ -0,0 +1,29 @@ +/* + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/pxa-regs.h> + + .global initPXAvoltage + +initPXAvoltage: + mov pc, lr diff --git a/board/colibri/u-boot.lds b/board/colibri/u-boot.lds new file mode 100644 index 0000000..a077bc5 --- /dev/null +++ b/board/colibri/u-boot.lds @@ -0,0 +1,56 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/pxa/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) . = ALIGN(4); } + _end = .; +} diff --git a/include/configs/colibri.h b/include/configs/colibri.h new file mode 100644 index 0000000..ad23caf --- /dev/null +++ b/include/configs/colibri.h @@ -0,0 +1,280 @@ +/* + * (C) Copyright 2007 + * Daniel Mack, caiaq + * + * (C) Copyright 2007 + * Stefano Babic, DENX Gmbh, sbabic(a)denx.de + * + * (C) Copyright 2004 + * Robert Whaley, Applied Data Systems, Inc. rwhaley(a)applieddata.net + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * Configuation settings for the LUBBOCK board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_PXA27X 1 /* This is an PXA27x CPU */ +#define CONFIG_COLIBRI 1 /* on a Colibri Board */ +#define CONFIG_MMC 1 +#define BOARD_LATE_INIT 1 + +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_NO_DCACHE + +#define RTC + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +/* + * select serial console configuration + */ +#define CONFIG_FFUART 1 /* we use FFUART */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_PING + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ + +#undef CONFIG_SHOW_BOOT_PROGRESS + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ETHADDR 80:81:82:83:84:85 +#define CONFIG_SERVERIP 192.168.0.1 +#define CONFIG_BOOTCOMMAND "run bootdhcp" +#define CONFIG_BOOTARGS "" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autoload=no\0" \ + "bootdhcp=dhcp;tftp a0100000 uImage; bootm a0100000\0" + +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +/* #define CONFIG_INITRD_TAG 1 */ + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_HUSH_PARSER 1 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ +#else +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#endif +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 + +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ + +#define CONFIG_SYS_LOAD_ADDR 0xa1000000 /* default load address */ + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CPUSPEED 0x190 /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */ + + /* valid baudrates */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 +#endif + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ +#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ +#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ +#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ +#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ + +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ + +#define CONFIG_SYS_DRAM_BASE 0xa0000000 +#define CONFIG_SYS_DRAM_SIZE 0x04000000 + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 + +/* + * GPIO settings + */ +#define CONFIG_SYS_GPSR0_VAL 0x00000000 +#define CONFIG_SYS_GPSR1_VAL 0x00020000 /*GPIO49 set --> 49-nPWE-Ethernet*/ +#define CONFIG_SYS_GPSR2_VAL 0x0000c000 /*GPIO78, GPIO79 set --> 78-nCS<2>, 79-nEXT_CS[1]*/ +#define CONFIG_SYS_GPSR3_VAL 0x00000000 +#define CONFIG_SYS_GPCR0_VAL 0x00000000 +#define CONFIG_SYS_GPCR1_VAL 0x00000000 +#define CONFIG_SYS_GPCR2_VAL 0x00000000 +#define CONFIG_SYS_GPCR3_VAL 0x00000000 +#define CONFIG_SYS_GPDR0_VAL 0x08000000 /*GPIO27 output --> 27-FF_RTS*/ +#define CONFIG_SYS_GPDR1_VAL 0x00020180 /*GPIO39, GPIO40, GPIO49 output -->39-FF_TXD, 40-FF_DTR*/ +#define CONFIG_SYS_GPDR2_VAL 0x0000c000 /*GPIO78, GPIO79 output*/ +#define CONFIG_SYS_GPDR3_VAL 0x00000000 +#define CONFIG_SYS_GAFR0_L_VAL 0x00100000 /*GPIO10_AF1 --> FFDCD*/ +#define CONFIG_SYS_GAFR0_U_VAL 0x00c00010 /*GPIO18_AF1, GPIO27_AF3 --> 18-RDY, 27-FF_RTS*/ +#define CONFIG_SYS_GAFR1_L_VAL 0x00029018 /*GPIO33_AF2, GPIO34_AF1,GPIO38_AF1, GPIO39_AF2, GPIO40_AF2 --> 33-FF_DSR, 34-FF_RXD, 38-FF_RI, 39-FF_TXD, 40-FF_DTR*/ +#define CONFIG_SYS_GAFR1_U_VAL 0x00000008 /*GPIO49_AF2 --> 49- nPWE*/ +#define CONFIG_SYS_GAFR2_L_VAL 0xa0000000 /*GPIO78_AF2, GPIO79_AF2 --> 78-nCS<2>, 79-nCS<3>*/ +#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 +#define CONFIG_SYS_GAFR3_L_VAL 0x00000300 +#define CONFIG_SYS_GAFR3_U_VAL 0x00000000 +#define CONFIG_SYS_GRER0_VAL 0x00000000 +#define CONFIG_SYS_GRER1_VAL 0x00000000 +#define CONFIG_SYS_GRER2_VAL 0x00000000 +#define CONFIG_SYS_GRER3_VAL 0x00000000 +#define CONFIG_SYS_GFER0_VAL 0x00000000 +#define CONFIG_SYS_GFER1_VAL 0x00000000 +#define CONFIG_SYS_GFER2_VAL 0x00000000 +#define CONFIG_SYS_GFER3_VAL 0x00000020 + + +#define CONFIG_SYS_PSSR_VAL 0x20 /* CHECK */ + +/* + * Clock settings + */ +#define CONFIG_SYS_CKEN 0x00400240 /* CHECK */ +#define CONFIG_SYS_CCCR 0x00000190 /* 312Mhz */ + +/* + * Memory settings + */ + +#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 +#define CONFIG_SYS_MSC1_VAL 0x9ee1f974 +#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 +#define CONFIG_SYS_MDCNFG_VAL 0x090009c9 +#define CONFIG_SYS_MDREFR_VAL 0x00000031 +#define CONFIG_SYS_MDMRS_VAL 0x00000000 + +#define CONFIG_SYS_FLYCNFG_VAL 0x00010001 +#define CONFIG_SYS_SXCNFG_VAL 0x40044004 + +/* + * PCMCIA and CF Interfaces + */ +#define CONFIG_SYS_MECR_VAL 0x00000002 +#define CONFIG_SYS_MCMEM0_VAL 0x00004204 +#define CONFIG_SYS_MCMEM1_VAL 0x00000000 +#define CONFIG_SYS_MCATT0_VAL 0x00010504 +#define CONFIG_SYS_MCATT1_VAL 0x00000000 +#define CONFIG_SYS_MCIO0_VAL 0x00008407 +#define CONFIG_SYS_MCIO1_VAL 0x00000000 + +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x08000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE+0x8004) + +/* + * FLASH and environment organization + */ + +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER 1 + +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_MONITOR_LEN 0x40000 + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 4 + 255 /* max number of sectors on one chip */ + +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ + +/* write flash less slowly */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 + +/* Flash environment locations */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector */ +#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment */ +#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) + +#endif /* __CONFIG_H */

2 5

[U-Boot] Den Tists Database in the US
by Augustus Mcdonough 07 Apr '09

07 Apr '09

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1 0

[U-Boot] U-Boot & x86 with IDE Flash Drive
by Dallas Clement 07 Apr '09

07 Apr '09

Hello All, I'm trying to determine if U-Boot is a suitable choice for my particular motherboard which is a Jetway / Via C7 (i686) mini-ITX board with a IDE flash drive, and a Realtek 8169 PHY. I am running an embedded Linux app on this board. I have been using Grub2 for the past year and have reached the point where I need either TFTP or NFS boot capability to 1) ease development 2) provide a firmware recovery mechanism. Grub2 lacks network boot capability other than PXE boot which my board does not suppport. It seems like U-Boot has everything I need but is quite a bit more complicated to configure. Can someone please confirm whether or not I should proceed down this path? If U-Boot is a suitable choice, could you also please help me figure out how to install it on 1) an IDE flash drive and 2) a USB thumb drive Thanks very much, Dallas Clement

2 1

[U-Boot] [PATCH 1/1] Fix for NFS boot for OMAP3 EVM
by Manikandan Pillai 07 Apr '09

07 Apr '09

The eth_halt() function has been modified to remove the chip reset and instead stop the transmit/receive from the device. Signed-off-by: Manikandan Pillai <mani.pillai(a)ti.com> --- drivers/net/smc911x.c | 23 ++++++++++++++++++++++- 1 files changed, 22 insertions(+), 1 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 1ded8f0..2f0852e 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -116,6 +116,27 @@ static int smc911x_phy_reset(void) return 0; } +static void smc911x_shutdown(void) +{ + unsigned cr; + + /* Turn of Rx and TX */ + cr = smc911x_get_mac_csr(MAC_CR); + cr &= ~(MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); + smc911x_set_mac_csr(MAC_CR, cr); + + /* Stop Transmission */ + cr = smc911x_get_mac_csr(TX_CFG); + cr &= ~(TX_CFG_STOP_TX); + smc911x_set_mac_csr(TX_CFG, cr); + /* Stop receiving packets */ + cr = smc911x_get_mac_csr(RX_CFG); + cr &= ~(RX_CFG_RXDOFF); + smc911x_set_mac_csr(RX_CFG, cr); + +} + + static void smc911x_phy_configure(void) { int timeout; @@ -224,7 +245,7 @@ int eth_send(volatile void *packet, int length) void eth_halt(void) { - smc911x_reset(); + smc911x_shutdown(); } int eth_rx(void) -- 1.5.6

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Re: [U-Boot] iPAQ 21x support (+PXA3xx NAND flash and MMC)
by Oliver Ford 07 Apr '09

07 Apr '09

Daniel Mack wrote: > Hi Oliver, > > getting back to this ancient thread now as I just got back to this > project. > ... > > Very cool - this helped me a lot and works well on a PXA303 board. > Thanks again. Did you try any further to bring this upstream? > > > Good to hear it helped and no, I've not even looked at getting the ipaq stuff into either the mainline kernel or u-boot. I don't really have the time to even read the u-boot mailing list posts let alone commit to merging it. > And would you share the relevant parts of your config, especially those > which define the environment storage? > Iirc, I have it set with no environment but just set a big boot command to set it all up. The ipaq214 config is here: http://www.oliford.co.uk/hpipaq214/public/u-boot/ipaq214.h (ignore the other files in that dir) and my u-boot git tree is here if you want anything else: http://www.oliford.co.uk/hpipaq214/u-boot.git/ It also now has in there MMC/SD and basic keypad and LCD support for the PXA310. Let me know if there's anything else you want. Oliver

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[U-Boot] Uboot booting RTOS
by rahanesh＠tataelxsi.co.in 07 Apr '09

07 Apr '09

Hi All, I am trying to boot a RTOS from uboot. I have the uboot flashed in NAND Flash. When i power on the board(OMAP3530 based from Mistral) uboot prompt comes up. Now how do i boot an RTOS which is also residing in NAND Flash at different offset.? Can i acheive this without changing the source code of current Uboot. ? ie Can i acheive this by setting certain environment variables? The format of RTOS which i am trying to port is not similar to Linux. It is Just an executable(OS and application compiled and built together to form an executable). I am newbie to uboot. Please help me on this Thanks, Rahanesh The information contained in this electronic message and any attachments to this message are intended for the exclusive use of the addressee(s) and may contain proprietary, confidential or privileged information. If you are not the intended recipient, you should not disseminate, distribute or copy this e-mail. Please notify the sender immediately and destroy all copies of this message and any attachments contained in it.

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[U-Boot] inline ppc assembly on standalone applications
by eija_flight 07 Apr '09

07 Apr '09

Hello, I need to access board cpu registers using ppc assembly language. It is possible to add inline assembly codes in standalone applications? Thanks, -- View this message in context: http://www.nabble.com/inline-ppc-assembly-on-standalone-applications-tp2292… Sent from the Uboot - Users mailing list archive at Nabble.com.

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