April 2009 - U-Boot

[U-Boot] Uboot MMC port
by alfred steele 15 Apr '09

15 Apr '09

Hi Magnus, The uboot pacth you had supplied earlier for the MX31 PDK does not include the mmc driver. I have asked for a candidate port for me to give a headstart for the sdhc/mmc infrastructure on the MX31 PDK board. In fact, it seems that none of the MX31 based boards support MMC/SDHC. I even tried sending an email to the mmc-git owner but got no reply. I am not sure who to approach on this. Is there a candidate existing in the uboot-git for the mx31 mmc driver. Apologize for using the same thread. Thanks.

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[U-Boot] [PATCH] Add I2C speed and divider formula for ColdFire
by Tsi-Chung Liew 15 Apr '09

15 Apr '09

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Implement formula to obtain I2C speed and internal bus divider. This will provide accurate divider than fix table divider value. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- drivers/i2c/fsl_i2c.c | 76 +++++++++++++++++++++++++++++++++---------------- 1 files changed, 51 insertions(+), 25 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 6ab7d3d..7f6d864 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -84,14 +84,12 @@ static const struct fsl_i2c *i2c_dev[2] = { * A different table is defined and are based on MCF5xxx user manual. * */ +#ifdef __PPC__ static const struct { unsigned short divider; -#ifdef __PPC__ u8 dfsr; -#endif u8 fdr; } fsl_i2c_speed_map[] = { -#ifdef __PPC__ {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, @@ -108,26 +106,22 @@ static const struct { {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, {61440, 1, 31}, {-1, 1, 31} +}; #elif defined(__M68K__) - {20, 32}, {22, 33}, {24, 34}, {26, 35}, - {28, 0}, {28, 36}, {30, 1}, {32, 37}, - {34, 2}, {36, 38}, {40, 3}, {40, 39}, - {44, 4}, {48, 5}, {48, 40}, {56, 6}, - {56, 41}, {64, 42}, {68, 7}, {72, 43}, - {80, 8}, {80, 44}, {88, 9}, {96, 41}, - {104, 10}, {112, 42}, {128, 11}, {128, 43}, - {144, 12}, {160, 13}, {160, 48}, {192, 14}, - {192, 49}, {224, 50}, {240, 15}, {256, 51}, - {288, 16}, {320, 17}, {320, 52}, {384, 18}, - {384, 53}, {448, 54}, {480, 19}, {512, 55}, - {576, 20}, {640, 21}, {640, 56}, {768, 22}, - {768, 57}, {960, 23}, {896, 58}, {1024, 59}, - {1152, 24}, {1280, 25}, {1280, 60}, {1536, 26}, - {1536, 61}, {1792, 62}, {1920, 27}, {2048, 63}, - {2304, 28}, {2560, 29}, {3072, 30}, {3840, 31}, - {-1, 31} -#endif +struct coldfire_i2c_tap { + int scl2tap; + int tap2tap; +} scltap[] = { + {4, 1}, + {4, 2}, + {6, 4}, + {6, 8}, + {14, 16}, + {30, 32}, + {62, 64}, + {126, 128} }; +#endif /** * Set the I2C bus speed for a given I2C device @@ -143,6 +137,7 @@ static const struct { static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, unsigned int i2c_clk, unsigned int speed) { +#ifdef __PPC__ unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); unsigned int i; @@ -156,20 +151,51 @@ static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) if (fsl_i2c_speed_map[i].divider >= divider) { u8 fdr; -#ifdef __PPC__ u8 dfsr; dfsr = fsl_i2c_speed_map[i].dfsr; -#endif fdr = fsl_i2c_speed_map[i].fdr; speed = i2c_clk / fsl_i2c_speed_map[i].divider; writeb(fdr, &dev->fdr); /* set bus speed */ -#ifdef __PPC__ writeb(dfsr, &dev->dfsrr); /* set default filter */ -#endif break; } return speed; +#elif defined(__M68K__) + int fdr = -1; + ulong best_speed = 0; + ulong divider; + ulong ipb, scl; + ulong bestmatch = 0xffffffffUL; + int best_i = 0, best_j = 0, i, j; + int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8 }; + + ipb = gd->bus_clk; + for (i = 7; i >= 0; i--) { + for (j = 7; j >= 0; j--) { + scl = 2 * (scltap[j].scl2tap + + (SCL_Tap[i] - 1) * scltap[j].tap2tap + 2); + if (ipb <= speed * scl) { + if ((speed * scl - ipb) < bestmatch) { + bestmatch = speed * scl - ipb; + best_i = i; + best_j = j; + best_speed = ipb / scl; + } + } + } + } + + divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2); + if (gd->flags & GD_FLG_RELOC) + fdr = divider; + else + printf("%ld kHz, ", best_speed / 1000); + + speed = best_speed; + + return speed; +#endif } void -- 1.5.6.4

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[U-Boot] Disabling PCI on PPC460EX
by Felix Radensky 15 Apr '09

15 Apr '09

Hi, Is there a way to disable PCI on 460EX (via some config option) while leaving PCI-E enabled ? I'm asking because on custom board I have PCI is unused, but both PCI-E slots should be enabled. I had problems with this in u-boot-1.3.4, and had to modify pci_init_board() to not invoke pci_440_init(). Thanks. Felix.

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[U-Boot] [PATCH] ppc4xx: Disable POST memory test on NAND-booting Kilauea
by Stefan Roese 15 Apr '09

15 Apr '09

Don't run the memory POST on the NAND-booting version. It will overwrite part of the U-Boot image which is already loaded from NAND to SDRAM. We were just lucky that it booted at all with this SDRAM test enabled. Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/kilauea.h | 13 ++++++++++++- 1 files changed, 12 insertions(+), 1 deletions(-) diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 26cb854..97bac99 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -430,12 +430,23 @@ #define CONFIG_CMD_PCI #define CONFIG_CMD_SNTP +/* + * Don't run the memory POST on the NAND-booting version. It will + * overwrite part of the U-Boot image which is already loaded from NAND + * to SDRAM. + */ +#if defined(CONFIG_NAND_U_BOOT) +#define CONFIG_SYS_POST_MEMORY_ON 0 +#else +#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY +#endif + /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ CONFIG_SYS_POST_CPU | \ CONFIG_SYS_POST_ETHER | \ CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_MEMORY_ON | \ CONFIG_SYS_POST_UART) /* Define here the base-addresses of the UARTs to test in POST */ -- 1.6.2.3

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[U-Boot] [PATCH] ppc4xx: Disable POST memory test on NAND-booting Sequoia
by Stefan Roese 15 Apr '09

15 Apr '09

Don't run the memory POST on the NAND-booting version. It will overwrite part of the U-Boot image which is already loaded from NAND to SDRAM. We were just lucky that it booted at all with this SDRAM test enabled. Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/sequoia.h | 15 +++++++++++++-- 1 files changed, 13 insertions(+), 2 deletions(-) diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index a3e2fce..fa226b2 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -301,13 +301,24 @@ #define CONFIG_SYS_POST_FPU_ON 0 #endif +/* + * Don't run the memory POST on the NAND-booting version. It will + * overwrite part of the U-Boot image which is already loaded from NAND + * to SDRAM. + */ +#if defined(CONFIG_NAND_U_BOOT) +#define CONFIG_SYS_POST_MEMORY_ON 0 +#else +#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY +#endif + /* POST support */ #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \ CONFIG_SYS_POST_CPU | \ CONFIG_SYS_POST_ETHER | \ - CONFIG_SYS_POST_FPU_ON | \ + CONFIG_SYS_POST_FPU_ON | \ CONFIG_SYS_POST_I2C | \ - CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_MEMORY_ON | \ CONFIG_SYS_POST_SPR | \ CONFIG_SYS_POST_UART) -- 1.6.2.3

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[U-Boot] Ethernet receive issue in PPC440
by prathika 15 Apr '09

15 Apr '09

hi all, i am porting uboot in PowerPC 440. i tried using the ping command.i have connected my board to PC via cross cable. When i monitor on the PC side using Network Monitor, the PC receives the ARP request packet and the PC is replying with acknowledgement. I verified reading the receive status register in PPC, it shows there was FCS error and the EMAC rejects the received packet. Actually i enabled external loop back in PowerPC and made appropriate configuration in PPC and in the PHY chip.I have no issues in receiving the packet.things work absolutely fine. but when it comes to peer to peer communication, i have problem.. should i doubt on my hardware??what can be the possibilities?? has anyone faced such an issue? Someone please help me in this regard. Thanks & Regards, Prathika R

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[U-Boot] [PATCH] Add feature-removal-schedule.txt
by Peter Tyser 15 Apr '09

15 Apr '09

Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- See the following threads for background: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/48429 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/47755 http://article.gmane.org/gmane.comp.boot-loaders.u-boot/53340 doc/feature-removal-schedule.txt | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 doc/feature-removal-schedule.txt diff --git a/doc/feature-removal-schedule.txt b/doc/feature-removal-schedule.txt new file mode 100644 index 0000000..901dc46 --- /dev/null +++ b/doc/feature-removal-schedule.txt @@ -0,0 +1,37 @@ +The following is a list of files and features that are going to be +removed from the U-Boot source tree. Every entry should contain what +exactly is going away, when it will be gone, why it is being removed, +and who is going to be doing the work. When the feature is removed +from U-Boot, its corresponding entry should also be removed from this +file. + +--------------------------- + +What: "autoscr" command +When: August 2009 +Why: "autosrc" is an ugly and completely non-standard name. The "autoscr" + command is deprecated and will be replaced the "source" command as + used by other shells such as bash. Both commands will be supported + for a transition period of 6 months after which "autoscr" will be + removed. +Who: Peter Tyser <ptyser(a)xes-inc.com> + +--------------------------- + +What: Individual I2C commands +When: April 2009 +Why: Per the U-Boot README, individual I2C commands such as "imd", "imm", + "imw", etc are deprecated. The single "i2c" command which is + currently enabled via CONFIG_I2C_CMD_TREE contains the same + functionality as the individual I2C commands. The individual + I2C commands should be removed as well as any references to + CONFIG_I2C_CMD_TREE. +Who: Peter Tyser <ptyser(a)xes-inc.com> + +--------------------------- + +What: Legacy NAND code +When: April 2009 +Why: Legacy NAND code is deprecated. Similar functionality exists in + more recent NAND code ported from the Linux kernel. +Who: Scott Wood <scottwood(a)freescale.com> -- 1.6.0.2.GIT

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[U-Boot] [PATCH] ppc4xx: Add "booting from NAND" to 4xx NAND-booting targets
by Stefan Roese 15 Apr '09

15 Apr '09

This additional text in the bootup log helps to see if the board is configured for NAND-booting. Especially helpful for boards that can boot from NOR and NAND (e.g. most of the AMCC eval boards). Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/cpu.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index d09c4c2..9a6a8d7 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -586,7 +586,11 @@ int checkcpu (void) #endif /* I2C_BOOTROM */ #if defined(SDR0_PINSTP_SHIFT) printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]); - printf ("Boot ROM Location %s\n", bootstrap_str[bootstrap_option()]); + printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]); +#ifdef CONFIG_NAND_U_BOOT + puts(", booting from NAND"); +#endif /* CONFIG_NAND_U_BOOT */ + putc('\n'); #endif /* SDR0_PINSTP_SHIFT */ #if defined(CONFIG_PCI) && !defined(CONFIG_405EX) -- 1.6.2.3

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[U-Boot] [HELP]PCIX problem on MPC8547 in uboot
by hank peng 15 Apr '09

15 Apr '09

I have a self-designed board which is based on MPC8548PC demo board, but CPU is MPC8547E. I configured PCI to PCI-X 64bits asynchrous mode, 100MHz, and there were two SATA controllers connected directly to BUS #0. U-boot version is 1.1.4 which is previouly for MPC8548PC demo board, I have modified some code for my board. After power on, uboot can print some information, when it comes to PCI bus scan, CPU died. The messages is like this: U-Boot 1.1.4 (Apr 13 2009 - 19:42:42) CPU: 8547_E, Version: 2.0, (0x80390120) Core: e500v2, Version: 2.0, (0x80210020) Clock Configuration: CPU: 999 MHz, CCB: 399 MHz, DDR: 199 MHz, LBC: 24 MHz L1: D-cache 32 kB enabled I-cache 32 kB enabled Board: MPC85xx Processor Card Rev. A. -- Boot Flash is U30 SerDes Interface is enabled PEX : X8 2.5Gbps, Root Complex PCI1: 64 bit, async, Host PCI2: disabled I2C: ready DRAM: Initializing ..init ECC from 10000000 to 10000100 SDRAM test phase 1: SDRAM test phase 2: SDRAM test passed. DDR: 512 MB Top of RAM usable for U-Boot at: 20000000 Reserving 180k for U-Boot at: 1ffd0000 Reserving 136k for malloc() at: 1ffae000 Reserving 80 Bytes for Board Info at: 1ffadfb0 Reserving 48 Bytes for Global Data at: 1ffadf80 Stack Pointer at: 1ffadf68 New Stack Pointer is: 1ffadf68 Now running in RAM - U-Boot at: 1ffd0000 FLASH: flash_get_size: man id = 0100 flash_get_size: device id1 = 7e22 flash_get_size: device id2 = 2122 flash_get_size: device id3 = 0122 flash_get_size: flash id = 00700000 flash_get_size: man id = 0100 flash_get_size: device id1 = 7e22 flash_get_size: device id2 = 2122 flash_get_size: device id3 = 0122 flash_get_size: flash id = 00700000 flash_protect ON: from 0xFFF80000 to 0xFFFA85FF protect on 124 protect on 125 flash_protect ON: from 0xFFF60000 to 0xFFF7FFFF protect on 123 32 MB L2 cache 512KB: enabled PORPLLSR = 0x00c54018 PORBMSR = 0x86370000 PORIMPSCR = 0x0003007f PORDEVSR = 0x023aea61 DEVDISR = 0x500c0000 Do you want to skip PCI initialization?(y/n, 5 seconds left): Init PCI1 in pci_mpc85xx_init ... after pci_set_region after pci_setup_indirect Outbound register1 has been initilized Outbound register2 has been initilized Inbound register has been initilized Register hose 1: reg16 = 0x00000004 2: reg16 = 0x00000106 In pci_mpc85xx_init: vendor = 0x00001057 In pci_mpc85xx_init: device = 0x00000018 Clear non-reserved bits in status register bridge = 0x00000000 PCIX init...: PCIX_COMMAND = 0x00000030 PCIX_STATUS = 0x1fff98b8 Done! To get last bus number: pciauto_config_init: ENTER Middle PCI Autoconfig: Memory region: [80000000-8fffffff] PCI Autoconfig: I/O region: [e2000000-e27fffff] pciauto_config_init: EXIT pci_hose_scan_bus: ENTER <cpu died> Interestingly, when I confiured PCI to PCI 32bits mode, uboot can run normally. I have doubt whether this version of uboot code support PCIX mode, if so where should I do to support PCIX mode? -- The simplest is not all best but the best is surely the simplest!

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[U-Boot] Compiler error with BUILD_DIR
by Günter Leonhardt 15 Apr '09

15 Apr '09

Hello, I'am getting an compiler error if I use a seperate BUILD_DIR: /home/gl/swserver/work/LINUX/ELINOS_PROJECTS/ELINOS_50/demoF302P/src/u-boot/build/tools/fdt.c:81: error: conflicting types for âfdt_offset_ptrâ /usr/include/../include/libfdt.h:125: error: previous declaration of âfdt_offset_ptrâ was here because I have installed a different version of the dtc. If I build u-boot without a seperate BUILD_DIR, I get no error. I'am using u-boot-2009.03. Thanks for any help Günter

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