March 2009 - U-Boot

[U-Boot] Out-of-tree build for imx31_phycore_eet fails
by Wolfgang Denk 31 Mar '09

31 Mar '09

Dear Guennadi, out-of-tree building for the imx31_phycore_eet target fails: -> make O=/work/wd/tmp-arm imx31_phycore_eet_config /bin/sh: line 1: /work/wd/tmp-arm/include/config.h: No such file or directory make: *** [imx31_phycore_eet_config] Error 1 Please fix. BTW: you also forgot to add your name to the MAINTAINERS file. Please fix this, too. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de When a program is being tested, it is too late to make design changes. -- Geoffrey James, "The Tao of Programming"

3 3

[U-Boot] sf patches
by Mike Frysinger 31 Mar '09

31 Mar '09

since there doesnt seem to be a "proper" location for spi flash patches to accumulate, do you mind if i start up a branch to accumulate the current set ? i dont know how active you want to be with the sf subsystem ... or maybe you're like me; you dont care so long as it continues to work properly :). -mike

2 1

[U-Boot] [Patch] soft_i2c.c compiler/linker error
by Jens Scharsig 31 Mar '09

31 Mar '09

This patch fix the compiler/linker errors common/cmd_i2c.c:1252: undefined reference to `i2c_get_bus_speed' common/cmd_i2c.c:1256: undefined reference to `i2c_set_bus_speed' if board use CONFIG_I2C_CMD_TREE and CONFIG_I2C_MULTI_BUS is not uesd/undef Signed-off-by: Jens Scharsig <esw(a)bus-elektronik.de> --- diff --git a/drivers/i2c/soft_i2c.c b/drivers/i2c/soft_i2c.c index ed5f5b2..68b267f 100644 --- a/drivers/i2c/soft_i2c.c +++ b/drivers/i2c/soft_i2c.c @@ -246,6 +246,7 @@ int i2c_set_bus_num(unsigned int bus) #endif return 0; } +#endif /* TODO: add 100/400k switching */ unsigned int i2c_get_bus_speed(void) @@ -260,7 +261,7 @@ int i2c_set_bus_speed(unsigned int speed) return 0; } -#endif + /*----------------------------------------------------------------------- * if ack == I2C_ACK, ACK the byte so can continue reading, else

3 9

[U-Boot] [PATCH] 8313erdb: Set guarded bit on BAT that covers the end of the address space.
by Scott Wood 31 Mar '09

31 Mar '09

This board currently sets DBAT6 to cover all of the final 256MiB of address space; however, not all of this space is covered by a device. In particular, flash sits at 0xfe000000-0xfe7fffff, and nothing is mapped at the far end of the address space. In zlib, there is a loop that references p[-1] if p is non-NULL. Under some circumstances, this leads to the CPU speculatively loading from 0xfffffff8 if p is NULL. This leads to a machine check. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- Note that there are likely other board with the same issue. include/configs/MPC8313ERDB.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 0ef4eba..21aedee 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -544,7 +544,7 @@ #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT7L (0) -- 1.5.3

8 15

[U-Boot] Please pull u-boot-mpc85xx.git
by Kumar Gala 30 Mar '09

30 Mar '09

The following changes since commit 2344bb8de2354101a8264c2123303c9d8d2aed3c: Detlev Zundel (1): inka4x0: Use proper accessor macros for memory mapped registers. are available in the git repository at: git://www.denx.de/git/u-boot-mpc85xx.git master Dave Liu (2): fsl-ddr: Fix two bugs in the ddr infrastructure fsl-ddr: add the DDR3 SPD infrastructure Haiying Wang (3): MPC85xx: Load and enable QE microcode patch in IRAM MPC85xx: Add MPC8569 CPU support MPC85xx: Add MPC8569MDS board support Kumar Gala (4): Add LSDMR (SDRAM Mode Register) definition on localbus 85xx: Use common LSDMR defines from asm/fsl_lbc.h 83xx: Use common LSDMR defines from asm/fsl_lbc.h 85xx: Add support for additional e500mc features MAKEALL | 1 + Makefile | 3 + board/freescale/mpc8541cds/mpc8541cds.c | 14 +- board/freescale/mpc8548cds/mpc8548cds.c | 10 +- board/freescale/mpc8555cds/mpc8555cds.c | 14 +- board/freescale/mpc8560ads/mpc8560ads.c | 1 + board/freescale/mpc8568mds/mpc8568mds.c | 10 +- board/freescale/mpc8569mds/Makefile | 55 ++++ board/freescale/mpc8569mds/bcsr.c | 49 ++++ board/freescale/mpc8569mds/bcsr.h | 82 ++++++ board/freescale/mpc8569mds/config.mk | 30 ++ board/freescale/mpc8569mds/ddr.c | 84 ++++++ board/freescale/mpc8569mds/law.c | 59 ++++ board/freescale/mpc8569mds/mpc8569mds.c | 329 ++++++++++++++++++++++ board/freescale/mpc8569mds/tlb.c | 103 +++++++ board/freescale/mpc8569mds/u-boot.lds | 143 ++++++++++ board/sbc8548/sbc8548.c | 10 +- common/ddr_spd.c | 53 ++++ cpu/mpc85xx/Makefile | 1 + cpu/mpc85xx/cpu.c | 2 + cpu/mpc85xx/cpu_init.c | 13 + cpu/mpc85xx/ddr-gen3.c | 6 +- cpu/mpc85xx/fdt.c | 64 +++++- cpu/mpc85xx/release.S | 16 + cpu/mpc85xx/start.S | 51 ++++ cpu/mpc8xxx/ddr/Makefile | 4 + cpu/mpc8xxx/ddr/ctrl_regs.c | 383 +++++++++++++++++++++++--- cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 314 +++++++++++++++++++++ cpu/mpc8xxx/ddr/lc_common_dimm_params.c | 74 +++++- cpu/mpc8xxx/ddr/options.c | 28 ++- drivers/misc/fsl_law.c | 2 +- drivers/qe/qe.c | 9 + drivers/qe/qe.h | 1 + include/asm-ppc/fsl_ddr_dimm_params.h | 7 + include/asm-ppc/fsl_ddr_sdram.h | 31 ++- include/asm-ppc/fsl_lbc.h | 27 ++ include/asm-ppc/immap_85xx.h | 13 +- include/asm-ppc/immap_qe.h | 8 +- include/asm-ppc/processor.h | 2 + include/configs/MPC8323ERDB.h | 26 -- include/configs/MPC832XEMDS.h | 26 -- include/configs/MPC8349EMDS.h | 62 +---- include/configs/MPC8360EMDS.h | 27 +-- include/configs/MPC8540ADS.h | 59 +--- include/configs/MPC8541CDS.h | 37 +-- include/configs/MPC8548CDS.h | 37 +-- include/configs/MPC8555CDS.h | 37 +-- include/configs/MPC8560ADS.h | 59 +--- include/configs/MPC8568MDS.h | 37 +-- include/configs/MPC8569MDS.h | 454 +++++++++++++++++++++++++++++++ include/configs/sbc8349.h | 62 +---- include/configs/sbc8548.h | 37 +-- include/ddr_spd.h | 13 +- 53 files changed, 2580 insertions(+), 499 deletions(-) create mode 100644 board/freescale/mpc8569mds/Makefile create mode 100644 board/freescale/mpc8569mds/bcsr.c create mode 100644 board/freescale/mpc8569mds/bcsr.h create mode 100644 board/freescale/mpc8569mds/config.mk create mode 100644 board/freescale/mpc8569mds/ddr.c create mode 100644 board/freescale/mpc8569mds/law.c create mode 100644 board/freescale/mpc8569mds/mpc8569mds.c create mode 100644 board/freescale/mpc8569mds/tlb.c create mode 100644 board/freescale/mpc8569mds/u-boot.lds create mode 100644 cpu/mpc8xxx/ddr/ddr3_dimm_params.c create mode 100644 include/configs/MPC8569MDS.h

1 0

[U-Boot] [PATCH] OMAP3: Update Overo pin mux for new expansion board
by Dirk Behme 30 Mar '09

30 Mar '09

A new Overo expansion board uses GPIO 14, 21, 22 and 23 for LED's and switches. This patch changes the pinmux configuration for those pins. They were previously set up for unused MMC3_DAT4-7. Signed-off-by: Steve Sakoman <steve(a)sakoman.com> --- Patch is against recent mainline commit 'b3dd629e78870ba2dc9f8032978721c0fa02a856' "Prepare 2009.03-rc2" --- board/omap3/overo/overo.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) Index: u-boot-main/board/omap3/overo/overo.h =================================================================== --- u-boot-main.orig/board/omap3/overo/overo.h +++ u-boot-main/board/omap3/overo/overo.h @@ -185,6 +185,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) /*CSI2_DX0*/\ MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) /*CSI2_DY0*/\ MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) /*GPIO_114*/\ + /* - PEN_DOWN*/\ MUX_VAL(CP(CSI2_DY1), (IEN | PTU | EN | M4)) /*GPIO_115*/\ /*Audio Interface */\ MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) /*McBSP2_FSX*/\ @@ -295,7 +296,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M2)) /*MMC3_CLK*/\ MUX_VAL(CP(ETK_CTL_ES2), (IEN | PTU | EN | M2)) /*MMC3_CMD*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT4*/\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | EN | M4)) /*GPIO_14*/\ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M4)) /*GPIO_15 - X_GATE*/\ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | EN | M4)) /*GPIO_16*/\ /* - W2W_NRESET*/\ @@ -303,9 +304,9 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT0*/\ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT1*/\ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT2*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT7*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT6*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M2)) /*MMC3_DAT5*/\ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | EN | M4)) /*GPIO_21*/\ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | EN | M4)) /*GPIO_22*/\ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | EN | M4)) /*GPIO_23*/\ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_CLK*/\ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTD | DIS | M3)) /*HSUSB2_STP*/\ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M3)) /*HSUSB2_DIR*/\

3 4

[U-Boot] [PATCH] Add imls utility command
by Marco 30 Mar '09

30 Mar '09

This patch adds, under tools folder, a new command called imls. Its goal is the same of UBoot imls but it can be used as Linux shell command. It reads from raw mtd partition and prints the list of the stored images. I'd like to receive comments about the usefulness of this command. Signed-off-by: Marco Stornelli <marco.stornelli(a)gmail.com> --- diff -uprN u-boot-2009.03-orig/tools/imls.c u-boot-2009.03/tools/imls.c --- u-boot-2009.03-orig/tools/imls.c 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2009.03/tools/imls.c 2009-03-30 19:06:56.000000000 +0200 @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2009 Marco Stornelli + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include "imls.h" + +extern unsigned long crc32(unsigned long crc, const char *buf, unsigned int len); +static void usage(void); +static int image_verify_header(char *ptr, int fd); + +char *cmdname; +char *devicefile; + +unsigned int sectorcount = 0; +int sflag = 0; +unsigned int sectoroffset = 0; +unsigned int sectorsize = 0; +int cflag = 0; + +int main (int argc, char **argv) +{ + int fd = -1, err = 0, readbyte = 0, j, len; + uint32_t mtdsize, dim; + struct mtd_info_user mtdinfo; + char *buf; + int found = 0; + + cmdname = *argv; + + while (--argc > 0 && **++argv == '-') { + while (*++*argv) { + switch (**argv) { + case 's': + if (--argc <= 0) + usage (); + sectorcount = (unsigned int)atoi(*++argv); + sflag = 1; + goto NXTARG; + case 'o': + if (--argc <= 0) + usage (); + sectoroffset = (unsigned int)atoi(*++argv); + goto NXTARG; + + case 'c': + if (--argc <= 0) + usage (); + sectorsize = (unsigned int)atoi(*++argv); + cflag = 1; + goto NXTARG; + default: + usage (); + } + } +NXTARG: ; + } + + if (argc != 1 || cflag == 0 || sflag == 0) + usage(); + + devicefile = *argv; + + fd = open(devicefile, O_RDONLY); + if (fd < 0) { + fprintf (stderr, "%s: Can't open %s: %s\n", + cmdname, devicefile, strerror(errno)); + exit(EXIT_FAILURE); + } + + err = ioctl(fd, MEMGETINFO, &mtdinfo); + if (err < 0) { + fprintf(stderr, "%s: Cannot get MTD information: %s\n",cmdname,strerror(errno)); + exit(EXIT_FAILURE); + } + + mtdsize = mtdinfo.size; + + if (sectorsize * sectorcount != mtdsize) { + fprintf(stderr, "%s: Partition size (%d) incompatible with sector size and count\n", cmdname, mtdsize); + exit(EXIT_FAILURE); + } + + if (sectorsize * sectoroffset >= mtdsize) { + fprintf(stderr, "%s: Partition size (%d) incompatible with sector offset given\n", cmdname, mtdsize); + exit(EXIT_FAILURE); + } + + if (sectoroffset > sectorcount - 1) { + fprintf(stderr, "%s: Sector offset cannot be grater than sector count minus one\n", cmdname); + exit(EXIT_FAILURE); + } + + dim = image_get_header_size(); + + buf = malloc(sizeof(char)*dim); + if (!buf) { + fprintf (stderr, "%s: Can't allocate memory: %s\n", + cmdname, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (sectoroffset != 0) + lseek(fd, sectoroffset*sectorsize, SEEK_SET); + + printf("Searching....\n"); + + for (j = sectoroffset; j < sectorcount; ++j) { + + readbyte = read(fd, buf, dim); + if (readbyte != dim) { + fprintf(stderr, "%s: Can't read from device: %s\n", + cmdname, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (fdt_check_header(buf)) { + /* old-style image */ + if (image_verify_header(buf, fd)) { + found = 1; + image_print_contents((image_header_t *)buf); + } + } else { + /* FIT image */ + fit_print_contents(buf); + } + + } + + free(buf); + + close(fd); + + if(!found) + printf("No images found\n"); + + exit(EXIT_SUCCESS); +} + +void usage() +{ + fprintf (stderr, "Usage:\n" + " %s [-o offset] -s count -c size \n" + " -o ==> number of sectors to use as offset\n" + " -s ==> number of sectors\n" + " -c ==> size of sectors\n", + cmdname); + + exit (EXIT_FAILURE); +} + +static int image_verify_header(char *ptr, int fd) +{ + int len, n; + char *data; + uint32_t checksum; + image_header_t *hdr = (image_header_t *)ptr; + + if (ntohl(hdr->ih_magic) != IH_MAGIC) { + return 0; + } + + data = (char *)hdr; + len = sizeof(image_header_t); + + checksum = ntohl(hdr->ih_hcrc); + hdr->ih_hcrc = htonl(0); /* clear for re-calculation */ + + if (crc32(0, data, len) != checksum) { + fprintf (stderr, + "%s: Maybe image found but it has bad header checksum!\n", + cmdname); + return 0; + } + + len = ntohl(hdr->ih_size); + data = malloc(len * sizeof(char)); + if (!data) { + fprintf (stderr, "%s: Can't allocate memory: %s\n", + cmdname, strerror(errno)); + exit(EXIT_FAILURE); + } + + n = read(fd, data, len); + if (n != len) { + fprintf (stderr, + "%s: Error while reading: %s\n", + cmdname, strerror(errno)); + exit(EXIT_FAILURE); + } + + if (crc32(0, data, len) != ntohl(hdr->ih_dcrc)) { + fprintf (stderr, + "%s: Maybe image found but it has corrupted data!\n", + cmdname); + free(data); + return 0; + } + + free(data); + + return 1; +} + diff -uprN u-boot-2009.03-orig/tools/imls.h u-boot-2009.03/tools/imls.h --- u-boot-2009.03-orig/tools/imls.h 1970-01-01 01:00:00.000000000 +0100 +++ u-boot-2009.03/tools/imls.h 2009-03-29 11:43:31.000000000 +0200 @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2009 Marco Stornelli + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <errno.h> +#include <fcntl.h> +#include <stdio.h> +#include <stdlib.h> +#include <stddef.h> +#include <string.h> +#include <sys/types.h> +#include <sys/ioctl.h> +#include <sys/stat.h> +#include <unistd.h> + +#ifdef MTD_OLD +# include <stdint.h> +# include <linux/mtd/mtd.h> +#else +# define __user /* nothing */ +# include <mtd/mtd-user.h> +#endif + +#include <sha1.h> +#include "fdt_host.h" +#include <image.h> diff -uprN u-boot-2009.03-orig/tools/Makefile u-boot-2009.03/tools/Makefile --- u-boot-2009.03-orig/tools/Makefile 2009-03-21 22:04:41.000000000 +0100 +++ u-boot-2009.03/tools/Makefile 2009-03-28 18:47:38.000000000 +0100 @@ -21,10 +21,10 @@ # MA 02111-1307 USA # -BIN_FILES = img2srec$(SFX) mkimage$(SFX) envcrc$(SFX) ubsha1$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) +BIN_FILES = img2srec$(SFX) mkimage$(SFX) imls$(SFX) envcrc$(SFX) ubsha1$(SFX) gen_eth_addr$(SFX) bmp_logo$(SFX) OBJ_LINKS = env_embedded.o crc32.o md5.o sha1.o image.o -OBJ_FILES = img2srec.o mkimage.o envcrc.o ubsha1.o gen_eth_addr.o bmp_logo.o +OBJ_FILES = img2srec.o mkimage.o imls.o envcrc.o ubsha1.o gen_eth_addr.o bmp_logo.o ifeq ($(ARCH),mips) BIN_FILES += inca-swap-bytes$(SFX) @@ -151,6 +151,10 @@ $(obj)mkimage$(SFX): $(obj)mkimage.o $(o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ +$(obj)imls$(SFX): $(obj)imls.o $(obj)crc32.o $(obj)image.o $(obj)md5.o $(obj)sha1.o $(LIBFDT_OBJ_FILES) + $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ + $(STRIP) $@ + $(obj)ncb$(SFX): $(obj)ncb.o $(CC) $(CFLAGS) $(HOST_LDFLAGS) -o $@ $^ $(STRIP) $@ @@ -196,6 +200,9 @@ $(obj)image.o: $(obj)image.c $(obj)mkimage.o: $(src)mkimage.c $(CC) -g $(FIT_CFLAGS) -c -o $@ $< +$(obj)imls.o: $(src)imls.c + $(CC) -g $(FIT_CFLAGS) -c -o $@ $< + $(obj)ncb.o: $(src)ncb.c $(CC) -g $(CFLAGS) -c -o $@ $<

1 0

[U-Boot] What to do for a working BIOSEMU and ATI_RADEON_FB environment?
by Markus Rathgeb 30 Mar '09

30 Mar '09

Hi! I own a phytec's pcm-030 with the shipped baseboard pcm-973. I would like to use a radeon 9200 pci card in the slot on the baseboard. I have done a git checkout of the u-boot and I am using the 'board support patch for phyCORE-MPC5200B-tiny‎' from the mailing list. To provide the necessary informations here some outputs the u-boot command line: ================= uboot> pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.18.00 0x1002 0x5c63 Display controller 0x00 00.18.01 0x1002 0x5c43 Display controller 0x80 00.1a.00 0x1057 0x5809 Bridge device 0x80 uboot> pci header 00.1a.00 vendor ID = 0x1057 device ID = 0x5809 command register = 0x0006 status register = 0x22a0 revision ID = 0x00 class code = 0x06 (Bridge device) sub class code = 0x80 programming interface = 0x00 cache line = 0x08 latency time = 0xf8 header type = 0x00 BIST = 0x00 base address 0 = 0xf0000000 base address 1 = 0x00000008 base address 2 = 0x00000000 base address 3 = 0x00000000 base address 4 = 0x00000000 base address 5 = 0x00000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x0000 sub system ID = 0x0000 expansion ROM base address = 0x00000000 interrupt line = 0x00 interrupt pin = 0x00 min Grant = 0x00 max Latency = 0x00 uboot> pci display 00.1a.00 0 40 00000000: 58091057 22a00006 06800000 0000f808 00000010: f0000000 00000008 00000000 00000000 00000020: 00000000 00000000 00000000 00000000 00000030: 00000000 00000000 00000000 00000000 00000040: 00000000 00000000 00000000 00000000 00000050: 00000000 00000000 00000000 00000000 00000060: 00000000 00000000 00000000 00000000 00000070: 00000000 00000000 00000000 00000000 00000080: 00000000 00000000 00000000 00000000 00000090: 00000000 00000000 00000000 00000000 000000a0: 00000000 00000000 00000000 00000000 000000b0: 00000000 00000000 00000000 00000000 000000c0: 00000000 00000000 00000000 00000000 000000d0: 00000000 00000000 00000000 00000000 000000e0: 00000000 00000000 00000000 00000000 000000f0: 00000000 00000000 00000000 00000000 uboot> pci header 00.18.00 vendor ID = 0x1002 device ID = 0x5c63 command register = 0x0007 status register = 0x0290 revision ID = 0x01 class code = 0x03 (Display controller) sub class code = 0x00 programming interface = 0x00 cache line = 0x08 latency time = 0x80 header type = 0x80 BIST = 0x00 base address 0 = 0x40000008 base address 1 = 0x50000001 base address 2 = 0x44000000 base address 3 = 0x00000000 base address 4 = 0x00000000 base address 5 = 0x00000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x0001 sub system ID = 0x0001 expansion ROM base address = 0x00000000 interrupt line = 0xff interrupt pin = 0x01 min Grant = 0x08 max Latency = 0x00 uboot> pci display 00.18.00 0 40 00000000: 5c631002 02900007 03000001 00808008 00000010: 40000008 50000001 44000000 00000000 00000020: 00000000 00000000 00000000 00010001 00000030: 00000000 00000050 00000000 000801ff 00000040: 00000000 00000000 00000000 00010001 00000050: 06020001 00000000 00205002 4f000210 00000060: 00000200 00000000 00000000 00000000 00000070: 00000000 00000000 00000000 00000000 00000080: 00000005 00000000 00000000 00000000 00000090: 00000000 00000000 00000000 00000000 000000a0: 00000000 00000000 00000000 00000000 000000b0: 00000000 00000000 00000000 00000000 000000c0: 00000000 00000000 00000000 00000000 000000d0: 00000000 00000000 00000000 00000000 000000e0: 00000000 00000000 00000000 00000000 000000f0: 00000000 00000000 00000000 00000000 uboot> pci header 00.18.01 vendor ID = 0x1002 device ID = 0x5c43 command register = 0x0006 status register = 0x0290 revision ID = 0x01 class code = 0x03 (Display controller) sub class code = 0x80 programming interface = 0x00 cache line = 0x08 latency time = 0x80 header type = 0x00 BIST = 0x00 base address 0 = 0x48000008 base address 1 = 0x4c000000 base address 2 = 0x00000000 base address 3 = 0x00000000 base address 4 = 0x00000000 base address 5 = 0x00000000 cardBus CIS pointer = 0x00000000 sub system vendor ID = 0x0001 sub system ID = 0x0000 expansion ROM base address = 0x00000000 interrupt line = 0xff interrupt pin = 0x00 min Grant = 0x08 max Latency = 0x00 uboot> pci display 00.18.01 0 40 00000000: 5c431002 02900006 03800001 00008008 00000010: 48000008 4c000000 00000000 00000000 00000020: 00000000 00000000 00000000 00000001 00000030: 00000000 00000050 00000000 000800ff 00000040: 00000000 00000000 00000000 00000000 00000050: 06020001 00000000 00205002 4f000210 00000060: 00000200 00000000 00000000 00000000 00000070: 00000000 00000000 00000000 00000000 00000080: 00000000 00000000 00000000 00000000 00000090: 00000000 00000000 00000000 00000000 000000a0: 00000000 00000000 00000000 00000000 000000b0: 00000000 00000000 00000000 00000000 000000c0: 00000000 00000000 00000000 00000000 000000d0: 00000000 00000000 00000000 00000000 000000e0: 00000000 00000000 00000000 00000000 000000f0: 00000000 00000000 00000000 00000000 ================= Then I prepared to access the following memory addresses: 00.1a.00: BAR0, BAR1, BAR2 uboot> md 0xf0000000 1 f0000000: 0000f000 .... uboot> md 0x00000008 1 00000008: 00c43004 ..0. uboot> md 0x00000000 1 00000000: 12c40044 ...D 00.18.00: BAR0, BAR1, BAR2 uboot> md 0x40000008 1 40000008: --> hang uboot> md 0x50000001 1 50000001: 00000000 .... uboot> md 0x44000000 1 44000000: 00000000 .... 00.18.00: BAR0, BAR1, BAR2 uboot> md 0x48000008 1 48000008: --> hang uboot> md 0x4c000000 1 4c000000: 00000000 .... uboot> md 0x00000000 1 00000000: 12c40044 ...D But this should be okay, because the card requieres some "BIOS" initialization code to be run (i believe). See: http://lists.denx.de/pipermail/u-boot/2004-November/007754.html Then I added the following lines to u-boot configuration file for phyCORE-MPC5200B-tiny‎: #define CONFIG_VIDEO #ifdef CONFIG_VIDEO #define CONFIG_BIOSEMU /* x86 bios emulator for vga bios */ #define CONFIG_ATI_RADEON_FB /* use radeon framebuffer driver */ #define VIDEO_IO_OFFSET CONFIG_PCI_IO_BUS #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #define CONFIG_VIDEO_SW_CURSOR #define CONFIG_VIDEO_LOGO #define CONFIG_CFB_CONSOLE #define CONFIG_SPLASH_SCREEN #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_CMD_BMP #endif (Is VIDEO_IO_OFFSET okay? Is CONFIG_SYS_ISA_IO_BASE_ADDRESS needed?) When I start the board with that u-boot configuration (I define DEBUG in ./video/ati_radeon_fb.c) I get the following messages: CPU: MPC5200B v2.2, Core v1.4 at 400 MHz Bus 133.333 MHz, IPB 133.333 MHz, PCI 33.333 MHz Board: phyCORE-MPC5200B-tiny I2C: ready DRAM: 64 MB SP: 0x03e45758 FLASH: 16 MB PCI: Bus Dev VenId DevId Class Int 00 18 1002 5c63 0300 ff 00 18 1002 5c43 0380 ff 00 1a 1057 5809 0680 00 ATI Radeon video card (1002, 5c63) found @(0:24:0) videoboot: Booting PCI video card bus 0, function 0, device 24 radeonfb: Found 0k of SDRAM 64 bits wide videoram Radeon: framebuffer base phy address 0x40000000,MMIO base phy address 0x44000000,framebuffer local base 0xfb400000. 640x480x8 31kHz 59Hz Cursor Start 4004b000 Pattern Start 4004c000 Then the system hangs again. I prepare to find the line that is responsible and believe it is in the file './video/ati_radeon_fb.c' in the function 'void *video_hw_init(void)' When the video memory will be accessed. /* Clear video memory (only visible screen area) */ i = pGD->winSizeX * pGD->winSizeY * pGD->gdfBytesPP / 4; vm = (unsigned int *) pGD->pciBase; while (i--) *vm++ = 0; <-- HERE !! So, what can I do? Can somebody help me. Something to say about the baseboard from the patch set of the current BSP. There is the device tree changed (pcm030.dts) with this comment: =========== The regular shipped PCM-973 baseboard has only processor's IRQ0 routed as INT A to the single slot. This means, the interrupt routing map must be much smaller to get a correct behaviour. The current DTS also contains a second slot definition, that was never present on this type of baseboard. ----------------------------------------------------------------------------- Attention: The restriction in available interrupt channels prevent the usage of multi function PCI devices! Its impossible to use other functions than the first one, if the other functions are using INT B...INT D for their interrupt. ----------------------------------------------------------------------------- It seems the PCM-973 supports three additional (not soldered) resistors, to route the missed INT B... INT D signals to processor's IRQ1...IRQ3. This need some help from the manufacturer to find resistor's right locations. --> Unresolved yet. =========== But the device tree is not the problem at this step, or am I missing something?

3 6

[U-Boot] [PATCH 01/19] s3c4510b: move specific code to soc directory
by Jean-Christophe PLAGNIOL-VILLARD 30 Mar '09

30 Mar '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- Makefile | 2 +- cpu/arm720t/cpu.c | 62 -------------- cpu/arm720t/s3c4510b/Makefile | 46 +++++++++++ cpu/arm720t/s3c4510b/cache.c | 86 ++++++++++++++++++++ include/asm-arm/arch-arm720t/hardware.h | 4 +- .../s3c4510b.h => arch-s3c4510b/hardware.h} | 0 6 files changed, 134 insertions(+), 66 deletions(-) create mode 100644 cpu/arm720t/s3c4510b/Makefile create mode 100644 cpu/arm720t/s3c4510b/cache.c rename include/asm-arm/{arch-arm720t/s3c4510b.h => arch-s3c4510b/hardware.h} (100%) diff --git a/Makefile b/Makefile index 1cce381..a6dadf6 100644 --- a/Makefile +++ b/Makefile @@ -2943,7 +2943,7 @@ modnet50_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm720t modnet50 evb4510_config : unconfig - @$(MKCONFIG) $(@:_config=) arm arm720t evb4510 + @$(MKCONFIG) $(@:_config=) arm arm720t evb4510 NULL s3c4510b lpc2292sodimm_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm720t lpc2292sodimm NULL lpc2292 diff --git a/cpu/arm720t/cpu.c b/cpu/arm720t/cpu.c index 5ac8f59..8166982 100644 --- a/cpu/arm720t/cpu.c +++ b/cpu/arm720t/cpu.c @@ -188,71 +188,9 @@ int dcache_status (void) { return (read_p15_c1 () & C1_IDC) != 0; } - -#elif defined(CONFIG_S3C4510B) - -void icache_enable (void) -{ - s32 i; - - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); - - /* 8KB cache, write enable */ - SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); - - /* clear TAG RAM bits */ - for ( i = 0; i < 256; i++) - PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); - - /* clear SET0 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); - - /* clear SET1 RAM */ - for(i=0; i < 1024; i++) - PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); - - /* enable cache */ - SET_REG( REG_SYSCFG, CACHE_ENABLE); - -} - -void icache_disable (void) -{ - /* disable all cache bits */ - CLR_REG( REG_SYSCFG, 0x3F); -} - -int icache_status (void) -{ - return GET_REG( REG_SYSCFG) & CACHE_ENABLE; -} - -void dcache_enable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_enable(); -} - -void dcache_disable (void) -{ - /* we don't have seperate instruction/data caches */ - icache_disable(); -} - -int dcache_status (void) -{ - /* we don't have seperate instruction/data caches */ - return icache_status(); -} - #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No specific cache setup for IntegratorAP/CM720T as yet */ void icache_enable (void) { } -#elif defined(CONFIG_LPC2292) /* just to satisfy the compiler */ -#else -#error No icache/dcache enable/disable functions defined for this CPU type #endif diff --git a/cpu/arm720t/s3c4510b/Makefile b/cpu/arm720t/s3c4510b/Makefile new file mode 100644 index 0000000..c9520b6 --- /dev/null +++ b/cpu/arm720t/s3c4510b/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2000-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS-y += cache.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### + diff --git a/cpu/arm720t/s3c4510b/cache.c b/cpu/arm720t/s3c4510b/cache.c new file mode 100644 index 0000000..104d287 --- /dev/null +++ b/cpu/arm720t/s3c4510b/cache.c @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke <azu(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/hardware.h> + +void icache_enable (void) +{ + s32 i; + + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); + + /* 8KB cache, write enable */ + SET_REG( REG_SYSCFG, CACHE_WRITE_BUFF | CACHE_MODE_01); + + /* clear TAG RAM bits */ + for ( i = 0; i < 256; i++) + PUT_REG( CACHE_TAG_RAM + 4*i, 0x00000000); + + /* clear SET0 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET0_RAM + 4*i, 0x00000000); + + /* clear SET1 RAM */ + for(i=0; i < 1024; i++) + PUT_REG( CACHE_SET1_RAM + 4*i, 0x00000000); + + /* enable cache */ + SET_REG( REG_SYSCFG, CACHE_ENABLE); + +} + +void icache_disable (void) +{ + /* disable all cache bits */ + CLR_REG( REG_SYSCFG, 0x3F); +} + +int icache_status (void) +{ + return GET_REG( REG_SYSCFG) & CACHE_ENABLE; +} + +void dcache_enable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_enable(); +} + +void dcache_disable (void) +{ + /* we don't have seperate instruction/data caches */ + icache_disable(); +} + +int dcache_status (void) +{ + /* we don't have seperate instruction/data caches */ + return icache_status(); +} diff --git a/include/asm-arm/arch-arm720t/hardware.h b/include/asm-arm/arch-arm720t/hardware.h index 3056ca7..ec053c9 100644 --- a/include/asm-arm/arch-arm720t/hardware.h +++ b/include/asm-arm/arch-arm720t/hardware.h @@ -24,9 +24,7 @@ * MA 02111-1307 USA */ -#if defined(CONFIG_S3C4510B) -#include <asm-arm/arch-arm720t/s3c4510b.h> -#elif defined(CONFIG_NETARM) +#if defined(CONFIG_NETARM) #include <asm-arm/arch-arm720t/netarm_registers.h> #elif defined(CONFIG_IMPA7) /* include IMPA7 specific hardware file if there was one */ diff --git a/include/asm-arm/arch-arm720t/s3c4510b.h b/include/asm-arm/arch-s3c4510b/hardware.h similarity index 100% rename from include/asm-arm/arch-arm720t/s3c4510b.h rename to include/asm-arm/arch-s3c4510b/hardware.h -- 1.6.2.1

2 19

[U-Boot] [PATCH v3 0/5] Update for inka4x0 plus some new features
by Detlev Zundel 30 Mar '09

30 Mar '09

This patchset contains updates for the ink4x0 platform. Namely it adds hardware diagnostic funtions and an RTC driver. For a nice integration by using private command tables, do_help is extended to support this scenario also. To successfully convert all the pointer access to accessor macros, a bunch of new defines is also needed for the 5200 cpu. Changes from v2: Addresses comments from ML. Specifically: - Fixing the odd empty line here and there - Removed some cruft uncovered in the review process - Rebased against master becaus some patches were already applied by Wolfgang. Detlev Zundel (5): drivers/twserial: Add protocol driver for "three wire serial" interface. rtc: add support for 4543 RTC (manufactured by e.g. EPSON) inka4x0: Add hardware diagnosis functions for inka4x0 inka4x0: Add hardware diagnosis and RTC in configuration. inka4x0: Use proper accessor macros for memory mapped registers. Makefile | 3 +- board/inka4x0/Makefile | 4 +- board/inka4x0/inka4x0.c | 171 +++++++++----- board/inka4x0/inkadiag.c | 514 +++++++++++++++++++++++++++++++++++++++++++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc4543.c | 118 ++++++++++ drivers/twserial/Makefile | 46 ++++ drivers/twserial/soft_tws.c | 111 ++++++++++ include/configs/inka4x0.h | 91 +++++++- include/ns16550.h | 11 + include/rtc.h | 4 + include/tws.h | 38 ++++ 12 files changed, 1042 insertions(+), 70 deletions(-) create mode 100644 board/inka4x0/inkadiag.c create mode 100644 drivers/rtc/rtc4543.c create mode 100644 drivers/twserial/Makefile create mode 100644 drivers/twserial/soft_tws.c create mode 100644 include/tws.h

2 10