February 2009 - U-Boot

[U-Boot] [PATCH 00/30] standardize mac address handling in u-boot (v2)
by Mike Frysinger 16 Jul '09

16 Jul '09

this set of patches aims to standardize the mac address handling in all of u-boot by doing the following: - add helper funcs for working with mac addresses (binary & string) - add format strings from Linux for printf-ing mac addresses - convert all duplicated code to use aforementioned helper funcs - convert all places to get the mac address from the environment - drop the global data instances of bi_enet*addr - document the whole damned thing ive taken pains to make sure the patchset doesnt break along the way (in terms of doing bisection and such). but in general, the interdependency looks something like: - add util funcs - convert net/boards/drivers/cpu/commands from global data to env - convert arch/board.c init to not touch global data - remove global data from all arch headers the ppc steps with load_sernum_ethaddr() are a little hairy due to the spread of code and trying to make sure things don't break bisection. but the other option is to squash all these commits (the common ppc board code as well as each individual board) into one change. doesn't matter to me either way. v2 of the patchset brings these changes: - import updated printf modifiers from the kernel - convert str_enetaddr() to %pM - convert print_IPaddr() to %pI4 - convert board_get_enetaddr() to board specific code - misc fixes/changes based on feedback from people while the new printf code is bigger by about 900bytes, i think we make up most of that by converting str_enetaddr/print_IPaddr users over to it. currently this patch series is maintained in my tree: git://www.denx.de/git/u-boot-blackfin.git macaddr Mike Frysinger (30): vsprintf: pull updates from Linux kernel convert print_IPaddr() to %pI4 net: new utility functions for working with enetaddr's doc/README.enetaddr: document proper MAC usage Blackfin: bfin_mac: force boards to setup the MAC themselves net: get mac address from environment and use eth util funcs bdinfo: get mac address from environment bootvx: get mac address from environment lynxkdi: get mac address from environment nvedit: do not update global bi_enetaddr and do not call eth_set_enetaddr() AmigaOneG3SE/enet: get mac address from environment boards: get mac address from environment drivers/net/: get mac address from environment bcm570x: get mac address from environment cs8900: get mac address from environment sh_eth: get mac address from environment lan91c96/smc91111/smc911x: get mac address from environment cpu/: get mac address from environment npe: get mac address from environment lib_*/board.c: do not initialize bi_enet*addr in global data nx823: get mac address from environment arm: get mac address from environment boards: move board_get_enetaddr() into board-specific init cmc_pu2: get mac address from environment pcs440ep: get mac address from environment and move load_sernum_ethaddr() to board init kup4k/kup4x: rename load_sernum_ethaddr() to kup_load_sernum_ethaddr() tqm8xx: rename load_sernum_ethaddr() to tqc_load_sernum_ethaddr() ppc: mark global bi_enet*addr as legacy drop now unused load_sernum_ethaddr() function remove bi_enet*addr from global data for all arches board/MAI/AmigaOneG3SE/enet.c | 42 +--- board/RPXClassic/RPXClassic.c | 16 +- board/cmc_pu2/load_sernum_ethaddr.c | 18 +- board/etin/debris/debris.c | 10 +- board/keymile/mgcoge/mgcoge.c | 4 +- board/keymile/mgsuvd/mgsuvd.c | 4 +- board/kup/common/load_sernum_ethaddr.c | 2 +- board/kup/kup4k/kup4k.c | 3 + board/kup/kup4x/kup4x.c | 4 +- board/m501sk/m501sk.c | 5 - board/mbx8xx/mbx8xx.c | 14 +- board/mpl/vcma9/cmd_vcma9.c | 11 +- board/muas3001/muas3001.c | 4 +- board/netstal/common/nm_bsp.c | 40 +-- board/nx823/flash.c | 5 +- board/nx823/nx823.c | 41 +-- board/pcs440ep/pcs440ep.c | 31 +-- board/pn62/pn62.c | 24 +- board/sandburst/common/sb_common.c | 4 +- board/sandburst/common/sb_common.h | 1 + board/sandburst/karef/karef.c | 29 ++ board/sandburst/metrobox/metrobox.c | 29 ++ board/siemens/IAD210/IAD210.c | 14 +- board/sixnet/sixnet.c | 11 +- board/tqc/tqm8xx/load_sernum_ethaddr.c | 2 +- board/tqc/tqm8xx/tqm8xx.c | 3 + board/v38b/v38b.c | 12 + board/xilinx/xilinx_enet/emac_adapter.c | 8 +- board/xpedite1k/xpedite1k.c | 51 +++- common/cmd_bdinfo.c | 166 ++++-------- common/cmd_elf.c | 6 +- common/cmd_ide.c | 10 +- common/cmd_nvedit.c | 24 +-- common/lynxkdi.c | 2 +- cpu/arm920t/at91rm9200/ether.c | 8 +- cpu/ixp/npe/npe.c | 36 +-- cpu/mpc512x/cpu.c | 6 +- cpu/mpc5xxx/cpu.c | 6 +- cpu/mpc8260/ether_fcc.c | 4 +- cpu/mpc8260/ether_scc.c | 4 +- cpu/ppc4xx/cpu_init.c | 14 +- disk/part.c | 2 +- doc/README.enetaddr | 97 +++++++ drivers/net/3c589.c | 7 +- drivers/net/4xx_enet.c | 13 +- drivers/net/bcm570x.c | 4 +- drivers/net/bcm570x_lm.h | 2 +- drivers/net/bfin_mac.c | 16 +- drivers/net/bfin_mac.h | 2 +- drivers/net/cs8900.c | 56 +--- drivers/net/dc2114x.c | 9 +- drivers/net/dm9000x.c | 26 +-- drivers/net/enc28j60.c | 4 +- drivers/net/fsl_mcdmafec.c | 11 +- drivers/net/ks8695eth.c | 8 +- drivers/net/lan91c96.c | 75 +---- drivers/net/mcffec.c | 10 +- drivers/net/rtl8019.c | 14 +- drivers/net/rtl8169.c | 2 +- drivers/net/s3c4510b_eth.c | 2 +- drivers/net/s3c4510b_eth.h | 2 +- drivers/net/sh_eth.c | 28 +-- drivers/net/smc91111.c | 72 +---- drivers/net/smc911x.c | 14 +- drivers/net/tigon3.c | 7 +- drivers/net/xilinx_emac.c | 12 +- drivers/net/xilinx_emaclite.c | 11 +- include/asm-arm/u-boot.h | 5 - include/asm-avr32/u-boot.h | 1 - include/asm-blackfin/u-boot.h | 1 - include/asm-i386/u-boot.h | 1 - include/asm-m68k/u-boot.h | 13 - include/asm-microblaze/u-boot.h | 1 - include/asm-mips/u-boot.h | 1 - include/asm-nios/u-boot.h | 1 - include/asm-nios2/u-boot.h | 1 - include/asm-ppc/u-boot.h | 14 +- include/asm-sh/u-boot.h | 1 - include/asm-sparc/u-boot.h | 12 - include/common.h | 9 - include/configs/IAD210.h | 1 + include/configs/MBX860T.h | 2 + include/configs/RPXClassic.h | 1 + include/configs/XPEDITE1K.h | 1 + include/configs/cmc_pu2.h | 1 + include/configs/v38b.h | 1 + include/net.h | 6 +- lib_arm/board.c | 47 +--- lib_blackfin/board.c | 48 +--- lib_generic/vsprintf.c | 479 ++++++++++++++++++++++++------- lib_i386/board.c | 17 -- lib_m68k/board.c | 38 --- lib_microblaze/board.c | 8 - lib_mips/board.c | 8 - lib_nios/board.c | 5 - lib_nios2/board.c | 5 - lib_ppc/board.c | 92 +------ lib_sh/board.c | 10 - lib_sparc/board.c | 19 -- net/bootp.c | 29 +-- net/eth.c | 76 +++-- net/net.c | 30 +-- net/nfs.c | 10 +- net/tftp.c | 10 +- post/cpu/mpc8xx/ether.c | 4 +- 105 files changed, 1055 insertions(+), 1188 deletions(-) create mode 100644 doc/README.enetaddr

5 43

[U-Boot] show_boot_progess @ ppc not working
by Andre Schwarz 09 Jul '09

09 Jul '09

All, can someone tell me why the board specific function "void show_boot_progress(int arg)" is no longer called (at least on MPC5200). Of course this line is present in the board config : #define CONFIG_SHOW_BOOT_PROGRESS 1 What have I missed ? regards, André MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

6 14

[U-Boot] [PATCH 1/2] at91sam9: add watchdog support
by Jean-Christophe PLAGNIOL-VILLARD 18 Jun '09

18 Jun '09

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- Makefile | 1 + doc/README.at91 | 9 ++++ drivers/serial/atmel_usart.c | 4 +- drivers/watchdog/Makefile | 46 ++++++++++++++++++++ drivers/watchdog/at91sam9_wdt.c | 79 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-at91/at91_wdt.h | 38 ++++++++++++++++ 6 files changed, 176 insertions(+), 1 deletions(-) create mode 100644 drivers/watchdog/Makefile create mode 100644 drivers/watchdog/at91sam9_wdt.c create mode 100644 include/asm-arm/arch-at91/at91_wdt.h diff --git a/Makefile b/Makefile index fcf57f3..3e61417 100644 --- a/Makefile +++ b/Makefile @@ -262,6 +262,7 @@ LIBS += drivers/rtc/librtc.a LIBS += drivers/serial/libserial.a LIBS += drivers/usb/libusb.a LIBS += drivers/video/libvideo.a +LIBS += drivers/watchdog/libwatchdog.a LIBS += common/libcommon.a LIBS += libfdt/libfdt.a LIBS += api/libapi.a diff --git a/doc/README.at91 b/doc/README.at91 index 4e3928a..c883c7c 100644 --- a/doc/README.at91 +++ b/doc/README.at91 @@ -2,6 +2,7 @@ Atmel AT91 Evaluation kits http://atmel.com/dyn/products/tools.asp?family_id=605#1443 +I. Board mapping & boot media ------------------------------------------------------------------------------ AT91SAM9260EK & AT91SAM9XEEK ------------------------------------------------------------------------------ @@ -86,3 +87,11 @@ Environment variables make at91sam9263ek_config - use data flash (spi cs0) (default) make at91sam9263ek_nandflash_config - use nand flash make at91sam9263ek_dataflash_cs0_config - use data flash (spi cs0) + +II. Watchdog support + + The watchdog wan only be activate once so you need to activate in the + bootloader and in the bootstrap if you use it + + The you can activate with + CONFIG_AT91SAM9_WATCHDOG and CONFIG_HW_WATCHDOG diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c index f3b146c..f50552a 100644 --- a/drivers/serial/atmel_usart.c +++ b/drivers/serial/atmel_usart.c @@ -16,6 +16,7 @@ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #include <common.h> +#include <watchdog.h> #include <asm/io.h> #include <asm/arch/clk.h> @@ -87,7 +88,8 @@ void serial_puts(const char *s) int serial_getc(void) { - while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) ; + while (!(usart3_readl(CSR) & USART3_BIT(RXRDY))) + WATCHDOG_RESET(); return usart3_readl(RHR); } diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile new file mode 100644 index 0000000..200968d --- /dev/null +++ b/drivers/watchdog/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)libwatchdog.a + +COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/watchdog/at91sam9_wdt.c b/drivers/watchdog/at91sam9_wdt.c new file mode 100644 index 0000000..5bb8b77 --- /dev/null +++ b/drivers/watchdog/at91sam9_wdt.c @@ -0,0 +1,79 @@ +/* + * [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c] + * + * Watchdog driver for Atmel AT91SAM9x processors. + * + * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * Copyright (C) 2008 Renaud CERRATO r.cerrato(a)til-technologies.fr + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +/* + * The Watchdog Timer Mode Register can be only written to once. If the + * timeout need to be set from U-Boot, be sure that the bootstrap doesn't + * write to this register. Inform Linux to it too + */ + +#include <common.h> +#include <watchdog.h> +#include <asm/arch/hardware.h> +#include <asm/arch/io.h> +#include <asm/arch/at91_wdt.h> + +/* + * AT91SAM9 watchdog runs a 12bit counter @ 256Hz, + * use this to convert a watchdog + * value from/to milliseconds. + */ +#define ms_to_ticks(t) (((t << 8) / 1000) - 1) +#define ticks_to_ms(t) (((t + 1) * 1000) >> 8) + +/* Hardware timeout in seconds */ +#define WDT_HW_TIMEOUT 2 + +/* + * Set the watchdog time interval in 1/256Hz (write-once) + * Counter is 12 bit. + */ +static int at91_wdt_settimeout(unsigned int timeout) +{ + unsigned int reg; + unsigned int mr; + + /* Check if disabled */ + mr = at91_sys_read(AT91_WDT_MR); + if (mr & AT91_WDT_WDDIS) { + printf("sorry, watchdog is disabled\n"); + return -1; + } + + /* + * All counting occurs at SLOW_CLOCK / 128 = 256 Hz + * + * Since WDV is a 12-bit counter, the maximum period is + * 4096 / 256 = 16 seconds. + */ + reg = AT91_WDT_WDRSTEN /* causes watchdog reset */ + /* | AT91_WDT_WDRPROC causes processor reset only */ + | AT91_WDT_WDDBGHLT /* disabled in debug mode */ + | AT91_WDT_WDD /* restart at any time */ + | (timeout & AT91_WDT_WDV); /* timer value */ + at91_sys_write(AT91_WDT_MR, reg); + + return 0; +} + +void hw_watchdog_reset(void) +{ + at91_sys_write(AT91_WDT_CR, AT91_WDT_KEY | AT91_WDT_WDRSTT); +} + +void hw_watchdog_init(void) +{ + /* 16 seconds timer, resets enabled */ + at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000)); +} diff --git a/include/asm-arm/arch-at91/at91_wdt.h b/include/asm-arm/arch-at91/at91_wdt.h new file mode 100644 index 0000000..7e18537 --- /dev/null +++ b/include/asm-arm/arch-at91/at91_wdt.h @@ -0,0 +1,38 @@ +/* + * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h] + * + * Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> + * Copyright (C) 2007 Andrew Victor + * Copyright (C) 2007 Atmel Corporation. + * + * Watchdog Timer (WDT) - System peripherals regsters. + * Based on AT91SAM9261 datasheet revision D. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef AT91_WDT_H +#define AT91_WDT_H + +#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */ +#define AT91_WDT_WDRSTT (1 << 0) /* Restart */ +#define AT91_WDT_KEY (0xa5 << 24) /* KEY Password */ + +#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */ +#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */ +#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */ +#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */ +#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */ +#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */ +#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */ +#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */ +#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */ + +#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */ +#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */ +#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */ + +#endif -- 1.5.6.5

4 9

[U-Boot] [PATCH v3] Freescale NFC NAND driver
by John Rigby 04 Jun '09

04 Jun '09

v3: Fixed problem with CFG vs CONFIG_SYS in board/ads5121/ads5121.c v2: Reworked MPC5121 NAND driver. Attempted to address all the problems listed by Scott Wood. Driver is now board independent. Will still need more work to be SOC independent. Driver for the NAND controller on MPC5121. This driver has been tested on ADS5121 rev4 / MPC5121e rev2 only which has the following configuration: 2K page size 8 bit device width This should work on other boards with MPC5121 rev2 silicon with little or no change to the driver. Various vintages of this controller exist on some iMX parts. Getting it to work on an iMX with the same controller version should be fairly easy. More work if it is an iMX with a different version on the controller. This controller treats 2K pages as 4 512 byte pages and the hw ecc is over the combined 512 byte main area and the first 7 bytes of the spare area. The hw ecc is stored in the last 9 bytes of the spare area. This all means the the spare area can not be written separately from the main. This means unmodified JFFS2 will not work. Signed-off-by: John Rigby <jrigby(a)freescale.com> --- board/ads5121/ads5121.c | 16 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsl_nfc_nand.c | 1105 +++++++++++++++++++++++++++++++++++++++ include/configs/ads5121.h | 38 ++ 4 files changed, 1160 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsl_nfc_nand.c diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 0610928..bd66e5b 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -24,6 +24,7 @@ #include <common.h> #include <mpc512x.h> #include <asm/bitops.h> +#include <asm/io.h> #include <command.h> #include <asm/processor.h> #include <fdt_support.h> @@ -34,6 +35,7 @@ /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ CLOCK_SCCR1_LPC_EN | \ + CLOCK_SCCR1_NFC_EN | \ CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ CLOCK_SCCR1_PSCFIFO_EN | \ CLOCK_SCCR1_DDR_EN | \ @@ -312,3 +314,17 @@ void ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ + +#if defined(CONFIG_NAND_FSL_NFC) +void ads5121_fsl_nfc_board_cs(int chip) +{ + unsigned char *csreg = (unsigned char *)CONFIG_SYS_CPLD_BASE + 0x09; + u8 v; + + v = in_8(csreg); + v |= 0xf; + v &= ~(1<<chip); + + out_8(csreg, v); +} +#endif diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index b0abe6e..b010b55 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -38,6 +38,7 @@ endif COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o +COBJS-$(CONFIG_NAND_FSL_NFC) += fsl_nfc_nand.o endif COBJS := $(COBJS-y) diff --git a/drivers/mtd/nand/fsl_nfc_nand.c b/drivers/mtd/nand/fsl_nfc_nand.c new file mode 100644 index 0000000..67117fe --- /dev/null +++ b/drivers/mtd/nand/fsl_nfc_nand.c @@ -0,0 +1,1105 @@ +/* + * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * + * Based on drivers/mtd/nand/mpc5121_nand.c + * which was based on drivers/mtd/nand/mxc_nd.c + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <common.h> +#include <malloc.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +#include <asm/io.h> +#include <nand.h> + +#define MIN(x, y) ((x < y) ? x : y) + +static struct fsl_nfc_private { + struct mtd_info mtd; + char spare_only; + char status_req; + u16 col_addr; + int writesize; + int sparesize; + int width; + int chipsel; +} *priv; + +#define IS_2K_PAGE_NAND (priv->writesize == 2048) +#define IS_4K_PAGE_NAND (priv->writesize == 4096) +#define IS_LARGE_PAGE_NAND (priv->writesize > 512) + +#define NFC_REG_BASE ((void *)CONFIG_SYS_NAND_BASE) +/* + * FSL NFC registers Definition + */ +#define NFC_BUF_ADDR (NFC_REG_BASE + 0x1E04) +#define NFC_FLASH_ADDR (NFC_REG_BASE + 0x1E06) +#define NFC_FLASH_CMD (NFC_REG_BASE + 0x1E08) +#define NFC_CONFIG (NFC_REG_BASE + 0x1E0A) +#define NFC_ECC_STATUS1 (NFC_REG_BASE + 0x1E0C) +#define NFC_ECC_STATUS2 (NFC_REG_BASE + 0x1E0E) +#define NFC_SPAS (NFC_REG_BASE + 0x1E10) +#define NFC_WRPROT (NFC_REG_BASE + 0x1E12) +#define NFC_NF_WRPRST (NFC_REG_BASE + 0x1E18) +#define NFC_CONFIG1 (NFC_REG_BASE + 0x1E1A) +#define NFC_CONFIG2 (NFC_REG_BASE + 0x1E1C) +#define NFC_UNLOCKSTART_BLKADDR0 (NFC_REG_BASE + 0x1E20) +#define NFC_UNLOCKEND_BLKADDR0 (NFC_REG_BASE + 0x1E22) +#define NFC_UNLOCKSTART_BLKADDR1 (NFC_REG_BASE + 0x1E24) +#define NFC_UNLOCKEND_BLKADDR1 (NFC_REG_BASE + 0x1E26) +#define NFC_UNLOCKSTART_BLKADDR2 (NFC_REG_BASE + 0x1E28) +#define NFC_UNLOCKEND_BLKADDR2 (NFC_REG_BASE + 0x1E2A) +#define NFC_UNLOCKSTART_BLKADDR3 (NFC_REG_BASE + 0x1E2C) +#define NFC_UNLOCKEND_BLKADDR3 (NFC_REG_BASE + 0x1E2E) + +/*! + * Addresses for NFC MAIN RAM BUFFER areas + */ +#define MAIN_AREA(n) (NFC_REG_BASE + (n)*0x200) + +/*! + * Addresses for NFC SPARE BUFFER areas + */ +#define SPARE_LEN 0x40 +#define SPARE_AREA(n) (NFC_REG_BASE + 0x1000 + (n)*SPARE_LEN) + +#define NFC_CMD 0x1 +#define NFC_ADDR 0x2 +#define NFC_INPUT 0x4 +#define NFC_OUTPUT 0x8 +#define NFC_ID 0x10 +#define NFC_STATUS 0x20 + +/* Bit Definitions */ +#define NFC_INT (1 << 15) +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) +#define NFC_BLS_LOCKED 0 +#define NFC_BLS_LOCKED_DEFAULT 1 +#define NFC_BLS_UNLOCKED 2 +#define NFC_WPC_LOCK_TIGHT 1 +#define NFC_WPC_LOCK (1 << 1) +#define NFC_WPC_UNLOCK (1 << 2) +#define NFC_FLASH_ADDR_SHIFT 0 +#define NFC_UNLOCK_END_ADDR_SHIFT 0 + +#define NFC_ECC_MODE_4 1 +/* + * Define delays in microsec for NAND device operations + */ +#define TROP_US_DELAY 2000 + +#if defined(CONFIG_PPC) +#define NFC_WRITEL(r, v) out_be32(r, v) +#define NFC_WRITEW(r, v) out_be16(r, v) +#define NFC_WRITEB(r, v) out_8(r, v) +#define NFC_READL(r) in_be32(r) +#define NFC_READW(r) in_be16(r) +#define NFC_READB(r) in_8(r) +#elif defined(CONFIG_ARM) +#define NFC_WRITEL(r, v) writel(v, r) +#define NFC_WRITEW(r, v) writew(v, r) +#define NFC_WRITEB(r, v) writeb(r, v) +#define NFC_READL(r) readl(r) +#define NFC_READW(r) readw(r) +#define NFC_READB(r) readb(r) +#endif + + +#ifdef CONFIG_MTD_NAND_FSL_NFC_SWECC +static int hardware_ecc; +#else +static int hardware_ecc = 1; +#endif + +/* + * OOB placement block for use with hardware ecc generation + */ +static struct nand_ecclayout nand_hw_eccoob_512 = { + .eccbytes = 9, + .eccpos = { + 7, 8, 9, 10, 11, 12, 13, 14, 15, + }, + .oobfree = { + {0, 5} /* byte 5 is factory bad block marker */ + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_2k = { + .eccbytes = 36, + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_4k = { + .eccbytes = 64, /* actually 72 but only room for 64 */ + .eccpos = { + /* 9 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 23, 24, 25, 26, 27, 28, 29, 30, 31, + 39, 40, 41, 42, 43, 44, 45, 46, 47, + 55, 56, 57, 58, 59, 60, 61, 62, 63, + 71, 72, 73, 74, 75, 76, 77, 78, 79, + 87, 88, 89, 90, 91, 92, 93, 94, 95, + 103, 104, 105, 106, 107, 108, 109, 110, 111, + 119, /* 120, 121, 122, 123, 124, 125, 126, 127, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {16, 7}, + {32, 7}, + {48, 7}, + {64, 7}, + {80, 7}, + {96, 7}, + {112, 7}, + }, +}; + +static struct nand_ecclayout nand_hw_eccoob_4k_218_spare = { + .eccbytes = 64, /* actually 144 but only room for 64 */ + .eccpos = { + /* 18 bytes of ecc for each 512 bytes of data */ + 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, + 33, 34, 35, 36, 37, 38, 39, 40, 41, + 42, 43, 44, 45, 46, 47, 48, 49, 50, + 59, 60, 61, 62, 63, 64, 65, 66, 67, + 68, 69, 70, 71, 72, 73, 74, 75, 76, + 85, 86, 87, 88, 89, 90, 91, 92, 93, + 94, /* 95, 96, 97, 98, 99, 100, 101, 102, + 111, 112, 113, 114, 115, 116, 117, 118, 119, + 120, 121, 122, 123, 124, 125, 126, 127, 128, + 137, 138, 139, 140, 141, 142, 143, 144, 145, + 146, 147, 148, 149, 150, 151, 152, 153, 154, + 163, 164, 165, 166, 167, 168, 169, 170, 171, + 172, 173, 174, 175, 176, 177, 178, 179, 180, + 189, 190, 191, 192, 193, 194, 195, 196, 197, + 198, 199, 200, 201, 202, 203, 204, 205, 206, */ + }, + .oobfree = { + {2, 5}, /* bytes 0 and 1 are factory bad block markers */ + {25, 8}, + {51, 8}, + {77, 8}, + {103, 8}, + {129, 8}, + {155, 8}, + {181, 8}, + }, +}; + +/* + * Functions to transfer data to/from spare erea. + */ +static void copy_from_spare(struct mtd_info *mtd, void *pbuf, int len) +{ + int i, copy_count, copy_size; + + copy_count = mtd->writesize / 512; + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + copy_size = priv->sparesize == 218 ? 26 : 16; + + for (i = 0; i < copy_count - 1 && len > 0; i++) { + memcpy_fromio(pbuf, SPARE_AREA(i), MIN(len, copy_size)); + pbuf += copy_size; + len -= copy_size; + } + if (len > 0) + memcpy_fromio(pbuf, SPARE_AREA(i), len); +} + +static void copy_to_spare(struct mtd_info *mtd, void *pbuf, int len) +{ + int i, copy_count, copy_size; + + copy_count = mtd->writesize / 512; + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + copy_size = priv->sparesize == 218 ? 26 : 16; + + /* + * Each spare area has 16 bytes for 512, 2K and normal 4K nand. + * For 4K nand with large 218 byte spare size, the size is 26 bytes for + * the first 7 buffers and 36 for the last. + */ + for (i = 0; i < copy_count - 1 && len > 0; i++) { + memcpy_toio(SPARE_AREA(i), pbuf, MIN(len, copy_size)); + pbuf += copy_size; + len -= copy_size; + } + if (len > 0) + memcpy_toio(SPARE_AREA(i), pbuf, len); +} + +/*! + * This function polls the NFC to wait for the basic operation to complete by + * checking the INT bit of config2 register. + * + * @max_retries number of retry attempts (separated by 1 us) + */ +static void wait_op_done(int max_retries) +{ + + while (1) { + max_retries--; + if (NFC_READW(NFC_CONFIG2) & NFC_INT) + break; + udelay(1); + } + if (max_retries <= 0) + MTDDEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n", __FUNCTION__); +} + +/*! + * This function issues the specified command to the NAND device and + * waits for completion. + * + * @cmds command for NAND Flash + */ +static void send_cmd(u16 cmd) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_cmd(%#x)\n", cmd); + + NFC_WRITEW(NFC_FLASH_CMD, cmd); + NFC_WRITEW(NFC_CONFIG2, NFC_CMD); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function sends an address (or partial address) to the + * NAND device. The address is used to select the source/destination for + * a NAND command. + * + * @addr address to be written to NFC. + */ +static void send_addr(u16 addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, "send_addr(%#x)\n", addr); + NFC_WRITEW(NFC_FLASH_ADDR, (addr << NFC_FLASH_ADDR_SHIFT)); + + NFC_WRITEW(NFC_CONFIG2, NFC_ADDR); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to initate the transfer + * of data currently in the NFC RAM buffer to the NAND device. + * + * @buf_id Specify Internal RAM Buffer number (0-3) + */ +static void send_prog_page(u8 buf_id) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* Set RBA bits for BUFFER val */ + val &= ~0x7; + val |= buf_id; + NFC_WRITEW(NFC_BUF_ADDR, val); + + NFC_WRITEW(NFC_CONFIG2, NFC_INPUT); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to initated the transfer + * of data from the NAND device into in the NFC ram buffer. + * + * @buf_id Specify Internal RAM Buffer number (0-3) + */ +static void send_read_page(u8 buf_id) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + MTDDEBUG(MTD_DEBUG_LEVEL3, "%s\n", __FUNCTION__); + + /* Set RBA bits for BUFFER val */ + val &= ~0x7; + val |= buf_id; + NFC_WRITEW(NFC_BUF_ADDR, val); + + NFC_WRITEW(NFC_CONFIG2, NFC_OUTPUT); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device ID. + */ +static void send_read_id(void) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + + /* NFC buffer 0 is used for device ID output */ + /* Set RBA bits for BUFFER0 */ + val &= ~0x7; + NFC_WRITEW(NFC_BUF_ADDR, val); + + /* Read ID into main buffer */ + NFC_WRITEW(NFC_CONFIG2, NFC_ID); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + +} + +/*! + * This function requests the NFC to perform a read of the + * NAND device status and returns the current status. + * + * @return device status + */ +static u16 get_dev_status(void) +{ + u32 save; + u16 ret; + u32 val; + /* Issue status request to NAND device */ + + /* save the main area1 first word, later do recovery */ + save = NFC_READL(MAIN_AREA(1)); + NFC_WRITEL(MAIN_AREA(1), 0); + + /* + * NFC buffer 1 is used for device status to prevent + * corruption of read/write buffer on status requests. + */ + + /* Select BUFFER1 */ + val = NFC_READW(NFC_BUF_ADDR); + val &= ~0x7; + val |= 1; + NFC_WRITEW(NFC_BUF_ADDR, val); + + /* Read status into main buffer */ + NFC_WRITEW(NFC_CONFIG2, NFC_STATUS); + + /* Wait for operation to complete */ + wait_op_done(TROP_US_DELAY); + + /* Status is placed in first word of main buffer */ + /* get status, then recovery area 1 data */ + if (NFC_READW(NFC_CONFIG1) & NFC_BIG) + ret = NFC_READB(MAIN_AREA(1)); + else + ret = NFC_READB(MAIN_AREA(1) + 3); + + NFC_WRITEL(MAIN_AREA(1), save); + return ret; +} + +/*! + * This functions is used by upper layer to checks if device is ready + * + * @mtd MTD structure for the NAND Flash + * + * @return 0 if device is busy else 1 + */ +static int fsl_nfc_dev_ready(struct mtd_info *mtd) +{ + return 1; +} + +static void fsl_nfc_enable_hwecc(struct mtd_info *mtd, int mode) +{ + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_ECC_EN)); + return; +} + +/* + * Function to record the ECC corrected/uncorrected errors resulted + * after a page read. This NFC detects and corrects upto to 4 symbols + * of 9-bits each. + */ +static int fsl_nfc_check_ecc_status(struct mtd_info *mtd) +{ + u32 ecc_stat, err; + int no_subpages = 1; + int ret = 0; + u8 ecc_bit_mask, err_limit; + int is_4bit_ecc = NFC_READW(NFC_CONFIG1) & NFC_ECC_MODE_4; + + ecc_bit_mask = (is_4bit_ecc ? 0x7 : 0xf); + err_limit = (is_4bit_ecc ? 0x4 : 0x8); + + no_subpages = mtd->writesize >> 9; + + ecc_stat = NFC_READW(NFC_ECC_STATUS1); + do { + err = ecc_stat & ecc_bit_mask; + if (err > err_limit) + return -1; + else + ret += err; + ecc_stat >>= 4; + } while (--no_subpages); + + return ret; +} + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte(struct mtd_info *mtd) +{ + void *area_buf; + u_char rv; + + /* Check for status request */ + if (priv->status_req) { + rv = get_dev_status() & 0xff; + return rv; + } + + if (priv->spare_only) + area_buf = SPARE_AREA(0); + else + area_buf = MAIN_AREA(0); + + rv = NFC_READB(area_buf + priv->col_addr); + priv->col_addr++; + return rv; +} + +/*! + * This function reads word from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u16 fsl_nfc_read_word(struct mtd_info *mtd) +{ + u16 rv; + void *area_buf; + + /* If we are accessing the spare region */ + if (priv->spare_only) + area_buf = SPARE_AREA(0); + else + area_buf = MAIN_AREA(0); + + /* Update saved column address */ + rv = NFC_READW(area_buf + priv->col_addr); + priv->col_addr += 2; + + return rv; +} + +/*! + * This function reads byte from the NAND Flash + * + * @mtd MTD structure for the NAND Flash + * + * @return data read from the NAND Flash + */ +static u_char fsl_nfc_read_byte16(struct mtd_info *mtd) +{ + /* Check for status request */ + if (priv->status_req) + return (get_dev_status() & 0xff); + + return fsl_nfc_read_word(mtd) & 0xff; +} + +/*! + * This function writes data of length \b len from buffer \b buf to the NAND + * internal RAM buffer's MAIN area 0. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be written to NAND Flash + * @len number of bytes to be written + */ +static void fsl_nfc_write_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_to_spare(mtd, (char *)buf, len); + return; + } else { + priv->col_addr += len; + memcpy_toio(MAIN_AREA(0), (void *)buf, len); + } +} + +/*! + * This function id is used to read the data buffer from the NAND Flash. To + * read the data from NAND Flash first the data output cycle is initiated by + * the NFC, which copies the data to RAMbuffer. This data of length \b len is + * then copied to buffer \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be read from NAND Flash + * @len number of bytes to be read + */ +static void fsl_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + + if (priv->col_addr >= mtd->writesize || priv->spare_only) { + copy_from_spare(mtd, buf, len); + return; + } else { + priv->col_addr += len; + memcpy_fromio((void *)buf, MAIN_AREA(0), len); + } +} + +/*! + * This function is used by the upper layer to verify the data in NAND Flash + * with the data in the \b buf. + * + * @mtd MTD structure for the NAND Flash + * @buf data to be verified + * @len length of the data to be verified + * + * @return -1 if error else 0 + * + */ +static int fsl_nfc_verify_buf(struct mtd_info *mtd, const u_char *buf, + int len) +{ + void *main_buf = MAIN_AREA(0); + /* check for 32-bit alignment? */ + u32 *p = (u32 *) buf; + u32 v = 0; + + for (; len > 0; len -= 4, main_buf += 4) + v = NFC_READL(main_buf); + if (v != *p++) + return -1; + return 0; +} + +static int fsl_nfc_get_hw_config(struct nand_chip *this) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 rcwh; + int rcwh_romloc; + int rcwh_ps; + int width; + int writesize = 0; + int sparesize = 0; + + /* + * Only support 2K for now. + * Remove this when others are tested and debugged. + */ +#if 1 + if (CONFIG_FSL_NFC_WRITE_SIZE != 2048) { + printf("FSL NFC: " + "%d byte write size flash support is untested\n", + CONFIG_FSL_NFC_WRITE_SIZE); + return -1; + } +#endif + rcwh = NFC_READL((void *)&(im->reset.rcwh)); + width = ((rcwh >> 6) & 0x1) ? 2 : 1; + + if (width != CONFIG_FSL_NFC_WIDTH) { + printf("FSL NFC: Device width mismatch, compiled for %d, " + "reset configuration word width is %d\n", + CONFIG_FSL_NFC_WIDTH, width); + return -1; + } + + if (width == 2) { + this->options |= NAND_BUSWIDTH_16; + this->read_byte = fsl_nfc_read_byte16; + } + + /* + * Decode the rcwh_ps and rcwh_romloc + * bits from reset config word + * to determine write size + */ + rcwh_ps = (rcwh >> 7) & 0x1; + rcwh_romloc = (rcwh >> 21) & 0x3; + switch (rcwh_ps << 2 | rcwh_romloc) { + case 0x0: + case 0x1: + writesize = 512; + sparesize = 16; + break; + case 0x2: + case 0x3: + writesize = 4096; + sparesize = 128; + break; + case 0x4: + case 0x5: + writesize = 2048; + sparesize = 64; + break; + case 0x6: + case 0x7: + writesize = 4096; + sparesize = 218; + break; + } + if (CONFIG_FSL_NFC_WRITE_SIZE != writesize) { + printf("FSL NFC: " + "Device write size mismatch, " + "compiled for %d, " + "size from reset configuration word is %d\n", + CONFIG_FSL_NFC_WRITE_SIZE, writesize); + return -1; + } + if (CONFIG_FSL_NFC_SPARE_SIZE != sparesize) { + printf("FSL NFC: " + "Device spare size mismatch, " + "compiled for %d, " + "size from reset configuration word is %d\n", + CONFIG_FSL_NFC_SPARE_SIZE, sparesize); + return -1; + } + + priv->sparesize = sparesize; + priv->writesize = writesize; + priv->width = width; + return 0; +} + +#ifndef CONFIG_FSL_NFC_BOARD_CS_FUNC +static void fsl_nfc_select_chip(u8 cs) +{ + u32 val = NFC_READW(NFC_BUF_ADDR); + + val &= ~0x60; + val |= cs << 5; + NFC_WRITEW(NFC_BUF_ADDR, val); +} +#define CONFIG_FSL_NFC_BOARD_CS_FUNC fsl_nfc_select_chip +#endif + + +/*! + * This function is used by upper layer for select and deselect of the NAND + * chip + * + * @mtd MTD structure for the NAND Flash + * @chip val indicating select or deselect + */ +static void fsl_nfc_select_chip(struct mtd_info *mtd, int chip) +{ + /* + * This is different than the linux version. + * Switching between chips is done via + * board_nand_select_device. + * + * Only valid chip numbers here are + * 0 select + * -1 deselect + */ + if (chip < -1 || chip > 0) { + printf("FSL NFC: " + "ERROR: Illegal chip select (chip = %d)\n", chip); + } + + if (chip < 0) { + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) & ~NFC_CE)); + return; + } + + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_CE)); + + /* + * Turn on appropriate chip. + */ + CONFIG_FSL_NFC_BOARD_CS_FUNC(priv->chipsel); +} + +/* + * Function to perform the address cycles. + */ +static void fsl_nfc_do_addr_cycle(struct mtd_info *mtd, int column, + int page_addr) +{ + struct nand_chip *this = mtd->priv; + u32 page_mask = this->pagemask; + + if (column != -1) { + send_addr(column & 0xff); + /* large page nand needs an extra column addr cycle */ + if (IS_2K_PAGE_NAND) + send_addr((column >> 8) & 0xf); + else if (IS_4K_PAGE_NAND) + send_addr((column >> 8) & 0x1f); + } + if (page_addr != -1) { + do { + send_addr((page_addr & 0xff)); + page_mask >>= 8; + page_addr >>= 8; + } while (page_mask != 0); + } +} + +/* + * Function to read a page from nand device. + */ +static void read_full_page(struct mtd_info *mtd, int page_addr) +{ + send_cmd(NAND_CMD_READ0); + + fsl_nfc_do_addr_cycle(mtd, 0, page_addr); + + if (IS_LARGE_PAGE_NAND) { + send_cmd(NAND_CMD_READSTART); + send_read_page(0); + } else { + send_read_page(0); + } +} + +/*! + * This function is used by the upper layer to write command to NAND Flash for + * different operations to be carried out on NAND Flash + * + * @mtd MTD structure for the NAND Flash + * @command command for NAND Flash + * @column column offset for the page read + * @page_addr page to be read from NAND Flash + */ +static void fsl_nfc_command(struct mtd_info *mtd, unsigned command, + int column, int page_addr) +{ + MTDDEBUG(MTD_DEBUG_LEVEL3, + "fsl_nfc_command (cmd = %#x, col = %#x, page = %#x)\n", + command, column, page_addr); + /* + * Reset command state information + */ + priv->status_req = 0; + + /* Reset column address to 0 */ + priv->col_addr = 0; + + /* + * Command pre-processing step + */ + switch (command) { + case NAND_CMD_STATUS: + priv->status_req = 1; + break; + + case NAND_CMD_READ0: + priv->spare_only = 0; + break; + + case NAND_CMD_READOOB: + priv->col_addr = column; + priv->spare_only = 1; + command = NAND_CMD_READ0; /* only READ0 is valid */ + break; + + case NAND_CMD_SEQIN: + if (column >= mtd->writesize) + priv->spare_only = 1; + else + priv->spare_only = 0; + break; + + case NAND_CMD_PAGEPROG: + if (!priv->spare_only) + send_prog_page(0); + else + return; + break; + + case NAND_CMD_ERASE1: + break; + case NAND_CMD_ERASE2: + break; + } + + /* + * Write out the command to the device. + */ + send_cmd(command); + + fsl_nfc_do_addr_cycle(mtd, column, page_addr); + + /* + * Command post-processing step + */ + switch (command) { + + case NAND_CMD_READOOB: + case NAND_CMD_READ0: + if (IS_LARGE_PAGE_NAND) { + /* send read confirm command */ + send_cmd(NAND_CMD_READSTART); + /* read for each AREA */ + send_read_page(0); + } else + send_read_page(0); + break; + + case NAND_CMD_READID: + send_read_id(); + break; + } +} + +static int fsl_nfc_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + return get_dev_status(); +} + +static int fsl_nfc_read_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page, int sndcmd) +{ + if (sndcmd) { + read_full_page(mtd, page); + sndcmd = 0; + } + + copy_from_spare(mtd, chip->oob_poi, mtd->oobsize); + return sndcmd; +} + +static int fsl_nfc_write_oob(struct mtd_info *mtd, struct nand_chip *chip, + int page) +{ + int status = 0; + int read_oob_col = 0; + + send_cmd(NAND_CMD_READ0); + send_cmd(NAND_CMD_SEQIN); + fsl_nfc_do_addr_cycle(mtd, read_oob_col, page); + + /* copy the oob data */ + copy_to_spare(mtd, chip->oob_poi, mtd->oobsize); + + send_prog_page(0); + + send_cmd(NAND_CMD_PAGEPROG); + + status = fsl_nfc_wait(mtd, chip); + if (status & NAND_STATUS_FAIL) + return -1; + return 0; +} + +static int fsl_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip, + uint8_t *buf) +{ + int stat; + + stat = fsl_nfc_check_ecc_status(mtd); + if (stat == -1) { + mtd->ecc_stats.failed++; + printf("FSL NFC: UnCorrectable RS-ECC Error\n"); + } else { + mtd->ecc_stats.corrected += stat; + if (stat) + printf("%d Symbol Correctable RS-ECC Error\n", stat); + } + + memcpy_fromio((void *)buf, MAIN_AREA(0), mtd->writesize); + copy_from_spare(mtd, chip->oob_poi, mtd->oobsize); + return 0; +} + +static void fsl_nfc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, const uint8_t *buf) +{ + memcpy_toio(MAIN_AREA(0), buf, mtd->writesize); + copy_to_spare(mtd, chip->oob_poi, mtd->oobsize); +} + + +/* + * Generic flash bbt decriptors + */ +static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' }; +static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' }; + +/* + * These are identical to the generic versions except + * for the offsets. + */ +static struct nand_bbt_descr bbt_main_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = bbt_pattern +}; + +static struct nand_bbt_descr bbt_mirror_descr = { + .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE + | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP, + .offs = 0, + .len = 4, + .veroffs = 4, + .maxblocks = 4, + .pattern = mirror_pattern +}; + +void board_nand_select_device(struct nand_chip *nand, int chip) +{ + if (chip >= CONFIG_FSL_NFC_CHIPS) { + printf("FSL NFC: " + "ERROR: Illegal chip select (chip = %d)\n", chip); + return; + } + priv->chipsel = chip; +} + + +int board_nand_init(struct nand_chip *nand) +{ + struct mtd_info *mtd; + + priv = malloc(sizeof(*priv)); + if (!priv) { + printf("FSL NFC: failed to allocate priv structure\n"); + return -1; + } + memset(priv, 0, sizeof(*priv)); + + if (fsl_nfc_get_hw_config(nand) < 0) + return -1; + + mtd = &priv->mtd; + mtd->priv = nand; + + /* 5 us command delay time */ + nand->chip_delay = 5; + + nand->dev_ready = fsl_nfc_dev_ready; + nand->cmdfunc = fsl_nfc_command; + nand->waitfunc = fsl_nfc_wait; + nand->select_chip = fsl_nfc_select_chip; + nand->options = NAND_USE_FLASH_BBT; + if (priv->width == 2) { + nand->options |= NAND_BUSWIDTH_16; + nand->read_byte = fsl_nfc_read_byte16; + } + nand->read_byte = fsl_nfc_read_byte; + nand->read_word = fsl_nfc_read_word; + nand->write_buf = fsl_nfc_write_buf; + nand->read_buf = fsl_nfc_read_buf; + nand->verify_buf = fsl_nfc_verify_buf; + + nand->bbt_td = &bbt_main_descr; + nand->bbt_md = &bbt_mirror_descr; + + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_RST)); + + /* Disable interrupt */ + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_INT_MSK)); + + if (hardware_ecc) { + nand->ecc.read_page = fsl_nfc_read_page; + nand->ecc.write_page = fsl_nfc_write_page; + nand->ecc.read_oob = fsl_nfc_read_oob; + nand->ecc.write_oob = fsl_nfc_write_oob; + if (IS_2K_PAGE_NAND) + nand->ecc.layout = &nand_hw_eccoob_2k; + else if (IS_4K_PAGE_NAND) + if (priv->sparesize == 128) + nand->ecc.layout = &nand_hw_eccoob_4k; + else + nand->ecc.layout = &nand_hw_eccoob_4k_218_spare; + else + nand->ecc.layout = &nand_hw_eccoob_512; + /* propagate ecc.layout to mtd_info */ + mtd->ecclayout = nand->ecc.layout; + nand->ecc.calculate = NULL; + nand->ecc.hwctl = fsl_nfc_enable_hwecc; + nand->ecc.correct = NULL; + nand->ecc.mode = NAND_ECC_HW; + /* RS-ECC is applied for both MAIN+SPARE not MAIN alone */ + nand->ecc.size = 512; + nand->ecc.bytes = 9; + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) | NFC_ECC_EN)); + } else { + nand->ecc.mode = NAND_ECC_SOFT; + NFC_WRITEW(NFC_CONFIG1, (NFC_READW(NFC_CONFIG1) & ~NFC_ECC_EN)); + } + + NFC_WRITEW(NFC_CONFIG1, NFC_READW(NFC_CONFIG1) & ~NFC_SP_EN); + + + /* Reset NAND */ + nand->cmdfunc(mtd, NAND_CMD_RESET, -1, -1); + + /* preset operation */ + /* Unlock the internal RAM Buffer */ + NFC_WRITEW(NFC_CONFIG, NFC_BLS_UNLOCKED); + + /* Blocks to be unlocked */ + NFC_WRITEW(NFC_UNLOCKSTART_BLKADDR0, 0x0); + NFC_WRITEW(NFC_UNLOCKEND_BLKADDR0, 0xffff); + + /* Unlock Block Command for given address range */ + NFC_WRITEW(NFC_WRPROT, NFC_WPC_UNLOCK); + + /* Set sparesize */ + NFC_WRITEW(NFC_SPAS, + (NFC_READW(NFC_SPAS) & 0xff00) | (priv->sparesize/2)); + + /* + * Only use 8bit ecc (aka not 4 bit) if large spare size + */ + if (priv->sparesize == 218) + NFC_WRITEW(NFC_CONFIG1, + (NFC_READW(NFC_CONFIG1) & ~NFC_ECC_MODE_4)); + else + NFC_WRITEW(NFC_CONFIG1, + (NFC_READW(NFC_CONFIG1) | NFC_ECC_MODE_4)); + + return 0; +} diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 8ec5e9d..d967c2e 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -33,6 +33,7 @@ * * 0x0000_0000 - 0x0FFF_FFFF DDR RAM (256 MB) * 0x3000_0000 - 0x3001_FFFF SRAM (128 KB) + * 0x4000_0000 - 0x400F_FFFF NFC (1 MB) * 0x8000_0000 - 0x803F_FFFF IMMR (4 MB) * 0x8200_0000 - 0x8200_001F CPLD (32 B) * 0x8400_0000 - 0x82FF_FFFF PCI I/O space (16 MB) @@ -199,6 +200,43 @@ #undef CONFIG_SYS_FLASH_CHECKSUM /* + * NAND FLASH + * drivers/mtd/nand/mpc5121_mpc.c (rev 2 silicon/rev 4 boards only) + */ +#define CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_FSL_NFC +#ifdef CONFIG_NAND_SPL +#define CONFIG_SYS_NAND_BASE 0xFFF00000 +#else +#define CONFIG_SYS_NAND_BASE 0x40000000 +#endif +#define CONFIG_CMD_NAND 1 +/* + * The flash on ADS5121 board is two flash chips in one package + */ +#define CONFIG_SYS_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE +#define CONFIG_SYS_NAND_SELECT_DEVICE 1 +#define CONFIG_NAND_MPC5121 +/* + * Configuration parameters for MPC5121 NAND driver + */ +#define CONFIG_FSL_NFC_WIDTH 1 +#define CONFIG_FSL_NFC_WRITE_SIZE 2048 +#define CONFIG_FSL_NFC_SPARE_SIZE 64 +#define CONFIG_FSL_NFC_CHIPS 2 + +#ifndef __ASSEMBLY__ +/* + * ADS board as a custom chip select + */ +extern void ads5121_fsl_nfc_board_cs(int); +#define CONFIG_FSL_NFC_BOARD_CS_FUNC ads5121_fsl_nfc_board_cs +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_NAND_FSL_NFC */ + + +/* * CPLD registers area is really only 32 bytes in size, but the smallest possible LP * window is 64KB */ -- 1.5.6.2.255.gbed62

6 8

[U-Boot] [PATCH] Add new Elpida memory configuration for ads5121
by Martha Marx 28 May '09

28 May '09

Rev 3 and earlier stay with Micron memory settings. Rev 4 boards manufactured before Nov-08 #1180 also will use Micron settings. More recent boards use Elpida settings. Signed-off-by: Martha Marx <mmarx(a)silicontkx.com> --- board/ads5121/ads5121.c | 114 +++++++++++++++++++++++++++++++++----------- include/configs/ads5121.h | 41 ++++++++++------ 2 files changed, 110 insertions(+), 45 deletions(-) diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 6c40e94..1983492 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -124,9 +124,15 @@ phys_size_t initdram (int board_type) * fixed sdram init -- the board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ + long int fixed_sdram (void) { + u32 use_micron = 0; volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; + ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00); + char *mac, *end, macaddr[6]; + u32 brddate, macchk; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; u32 msize_log2 = __ilog2 (msize); u32 i; @@ -174,41 +180,91 @@ long int fixed_sdram (void) im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU; im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL; + if (brd_rev >= 0x0400 && (mac = getenv("ethaddr"))) { + for (i=0; i<6; i++) { + macaddr[i] = mac ? + simple_strtoul (mac, &end, 16) : 0; + if (mac) + mac = (*end) ? end+1 : end; + } + brddate = (macaddr[3] << 16) + (macaddr[4] << 8) + macaddr[5]; + macchk = (macaddr[0] << 16) + (macaddr[1] << 8) + macaddr[2]; + debug("brddate = %d\n\t",brddate); + /* Boards made before Nov-08 #1180 use Micron memory; 001e59 is the STx vendor # */ + if (macchk == 0x001e59 && brddate <= 8111180) + use_micron = 1; + } else if (brd_rev < 0x400) { + use_micron = 1; + } + + debug("Using %s Memory settings\n\t", use_micron ? "Micron" : "Elpida"); + /* Initialize MDDRC */ - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG; - im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; - im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1; - im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2; + if (use_micron) { + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_MICRON; + im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_MICRON; + im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_MICRON; + } else { + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA; + im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0; + im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA; + im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA; + } /* Initialize DDR */ for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL; - im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP; - + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + + if (use_micron) { + /* Micron init sequence */ + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP; + udelay(200); + } else { + /* Elpida init sequence - works for Micron too but runs slower */ + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM2; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EM3; + im->mddrc.ddr_command = CONFIG_SYS_DDR_EN_DLL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RES_DLL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_PCHG_ALL; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_DDR_RFSH; + im->mddrc.ddr_command = CONFIG_SYS_ELPIDA_INIT_DEV_OP; + udelay(200); + } + im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_DEFAULT; + im->mddrc.ddr_command = CONFIG_SYS_DDR_OCD_EXIT; + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; + for (i = 0; i < 10; i++) + im->mddrc.ddr_command = CONFIG_SYS_DDR_NOP; /* Start MDDRC */ im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN; - im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN; + + if (use_micron) + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_MICRON_RUN; + else + im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA_RUN; return msize; } diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 8fda3f2..ab06276 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -130,29 +130,38 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ +#define CONFIG_SYS_MDDRC_SYS_CFG_RUN ~(0x10000000) #ifdef CONFIG_ADS5121_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 +#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON 0xF8604A00 +#define CONFIG_SYS_MDDRC_TIME_CFG1_MICRON 0x54EC1168 +#define CONFIG_SYS_MDDRC_TIME_CFG2_MICRON 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON 0xFA804A00 +#define CONFIG_SYS_MDDRC_SYS_CFG_MICRON_RUN 0xEA804A00 +#define CONFIG_SYS_MDDRC_TIME_CFG1_MICRON 0x68EC1168 +#define CONFIG_SYS_MDDRC_TIME_CFG2_MICRON 0x34310864 #endif +#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA 0xFA802b40 +#define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA_RUN 0xEA802b40 +#define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA 0x690e1189 +#define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA 0x35410864 + #define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 +#define CONFIG_SYS_MDDRC_SYS_CFG_CLK_BIT (1 << 29) +#define CONFIG_SYS_MDDRC_SYS_CFG_CKE_BIT (1 << 30) #define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E #define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_ELPIDA_INIT_DEV_OP 0x01000842 +#define CONFIG_SYS_DDR_NOP 0x01380000 +#define CONFIG_SYS_DDR_PCHG_ALL 0x01100400 +#define CONFIG_SYS_DDR_EM2 0x01020000 +#define CONFIG_SYS_DDR_EM3 0x01030000 +#define CONFIG_SYS_DDR_EN_DLL 0x01010000 +#define CONFIG_SYS_DDR_RES_DLL 0x01000932 +#define CONFIG_SYS_DDR_RFSH 0x01080000 +#define CONFIG_SYS_DDR_OCD_DEFAULT 0x01010780 +#define CONFIG_SYS_DDR_OCD_EXIT 0x01010400 /* DDR Priority Manager Configuration */ #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -- 1.5.2.4

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[U-Boot-Users] Add a new command to U-Boot
by Carlos Filipe Silva 20 May '09

20 May '09

Hi all! I have one doubt. How can I add a new command to U-Boot? Do I have to use only the macro U_BOOT_CMD() like files .../common/cmd_* or do I have to do more things, like defines, etc.? And after this is compliled with no error, if I type help in U-Boot's shell, do I see this command like the others? Best regards, Carlos Silva

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[U-Boot] [PATCH] netloop: updates for NetLoop
by Heiko Schocher 15 May '09

15 May '09

Fix some issues introduced from commit: 2f70c49e5b9813635ad73666aa30f304c7fdeda9 suggested by Mike Frysinger. - added some comment for the env_id variable in common/cmd_nvedit.c - moved some variables in fn scope instead of file scope - NetInitLoop now static void Signed-off-by: Heiko Schocher <hs(a)denx.de> --- common/cmd_nvedit.c | 6 ++++++ net/eth.c | 5 ++--- net/net.c | 9 ++++----- 3 files changed, 12 insertions(+), 8 deletions(-) diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index 95eebb5..3caa841 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -75,6 +75,12 @@ DECLARE_GLOBAL_DATA_PTR; static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; #define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) +/* + * This variable is incremented on each do_setenv (), so it can + * be used as an indication, if the environment has changed or not. + * So it is possible to reread an environment variable only if the + * environment was changed ... done so for example in NetInitLoop() + */ static int env_id = 1; int get_env_id (void) diff --git a/net/eth.c b/net/eth.c index 4bbf84b..a494912 100644 --- a/net/eth.c +++ b/net/eth.c @@ -57,9 +57,6 @@ int eth_setenv_enetaddr(char *name, const uchar *enetaddr) #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) -static char *act = NULL; -static int env_changed_id = 0; - /* * CPU and board-specific Ethernet initializations. Aliased function * signals caller to move on @@ -471,6 +468,8 @@ void eth_try_another(int first_restart) #ifdef CONFIG_NET_MULTI void eth_set_current(void) { + static char *act = NULL; + static int env_changed_id = 0; struct eth_device* old_current; int env_id; diff --git a/net/net.c b/net/net.c index a89f6a0..a80c814 100644 --- a/net/net.c +++ b/net/net.c @@ -209,8 +209,6 @@ uchar NetArpWaitPacketBuf[PKTSIZE_ALIGN + PKTALIGN]; ulong NetArpWaitTimerStart; int NetArpWaitTry; -int env_changed_id = 0; - void ArpRequest (void) { int i; @@ -278,15 +276,16 @@ void ArpTimeoutCheck(void) } } -int +static void NetInitLoop(proto_t protocol) { + static int env_changed_id = 0; bd_t *bd = gd->bd; int env_id = get_env_id (); /* update only when the environment has changed */ if (env_changed_id == env_id) - return 0; + return; switch (protocol) { #if defined(CONFIG_CMD_NFS) @@ -347,7 +346,7 @@ NetInitLoop(proto_t protocol) break; } env_changed_id = env_id; - return 0; + return; } /**********************************************************************/ -- 1.6.0.6 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] Using U-boot on the IXP432
by David Milway 02 May '09

02 May '09

Hi, I have been using a board with and IXP432 for about a year now, starting with Redboot but running in big endian mode. I am now looking at using u-boot for network booting but I would like to run it in little endian mode. Before I get stuck into to porting the code I have a few questions. 1) Has anybody else ported the code to the IXP432? 2) Is there any reason that the IXP cpu configuration sets the bigendian flag and should it be possible just to set it to little endian and will the bulk of the code work without modification? Thanks Dave

3 3

[U-Boot] Part 1/0
by Stefan Althoefer 02 May '09

02 May '09

The patch is against "latest" u-boot git-repository Please (still) be patient if style of submission or patches are offending. Signed-off-by: Stefan Althoefer <stefan.althoefer(a)web.de> ----

2 3

[U-Boot] [PATCH 0/6] eSDHC/DR USB switching on MPC837X boards
by Anton Vorontsov 02 May '09

02 May '09

Hi all, Because of pin multiplexing the eSDHC and DR USB are mutually exclusive on MPC837X processors, so we have to support switching between the two devices, and properly fixup the device tree. Patches on the way... -- Anton Vorontsov email: cbouatmailru(a)gmail.com irc://irc.freenode.net/bd2

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