October 2009 - U-Boot

[U-Boot] [PATCH v7 1/2] arm: A320: driver for FTRTC010 real time clock
by Po-Yu Chuang 22 Nov '09

22 Nov '09

This patch adds an FTRTC010 driver for Faraday A320 evaluation board. Signed-off-by: Po-Yu Chuang <ratbert(a)faraday-tech.com> --- drivers/rtc/Makefile | 1 + drivers/rtc/ftrtc010.c | 124 ++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+), 0 deletions(-) create mode 100644 drivers/rtc/ftrtc010.c diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index ea7d899..772a49a 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -40,6 +40,7 @@ COBJS-$(CONFIG_RTC_DS1556) += ds1556.o COBJS-$(CONFIG_RTC_DS164x) += ds164x.o COBJS-$(CONFIG_RTC_DS174x) += ds174x.o COBJS-$(CONFIG_RTC_DS3231) += ds3231.o +COBJS-$(CONFIG_RTC_FTRTC010) += ftrtc010.o COBJS-$(CONFIG_RTC_ISL1208) += isl1208.o COBJS-$(CONFIG_RTC_M41T11) += m41t11.o COBJS-$(CONFIG_RTC_M41T60) += m41t60.o diff --git a/drivers/rtc/ftrtc010.c b/drivers/rtc/ftrtc010.c new file mode 100644 index 0000000..c3c0bc2 --- /dev/null +++ b/drivers/rtc/ftrtc010.c @@ -0,0 +1,124 @@ +/* + * Faraday FTRTC010 Real Time Clock + * + * (C) Copyright 2009 Faraday Technology + * Po-Yu Chuang <ratbert(a)faraday-tech.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include <config.h> +#include <common.h> +#include <rtc.h> +#include <asm/io.h> + +struct ftrtc010 { + unsigned int sec; /* 0x00 */ + unsigned int min; /* 0x04 */ + unsigned int hour; /* 0x08 */ + unsigned int day; /* 0x0c */ + unsigned int alarm_sec; /* 0x10 */ + unsigned int alarm_min; /* 0x14 */ + unsigned int alarm_hour; /* 0x18 */ + unsigned int record; /* 0x1c */ + unsigned int cr; /* 0x20 */ +}; + +/* + * RTC Control Register + */ +#define FTRTC010_CR_ENABLE (1 << 0) +#define FTRTC010_CR_INTERRUPT_SEC (1 << 1) /* per second irq */ +#define FTRTC010_CR_INTERRUPT_MIN (1 << 2) /* per minute irq */ +#define FTRTC010_CR_INTERRUPT_HR (1 << 3) /* per hour irq */ +#define FTRTC010_CR_INTERRUPT_DAY (1 << 4) /* per day irq */ + +static struct ftrtc010 *rtc = (struct ftrtc010 *)CONFIG_FTRTC010_BASE; + +static void ftrtc010_enable (void) +{ + writel (FTRTC010_CR_ENABLE, &rtc->cr); +} + +/* + * return current time in seconds + */ +static unsigned long ftrtc010_time (void) +{ + unsigned long day; + unsigned long hour; + unsigned long minute; + unsigned long second; + unsigned long second2; + + do { + second = readl (&rtc->sec); + day = readl (&rtc->day); + hour = readl (&rtc->hour); + minute = readl (&rtc->min); + second2 = readl (&rtc->sec); + } while (second != second2); + + return day * 24 * 60 * 60 + hour * 60 * 60 + minute * 60 + second; +} + +/* + * Get the current time from the RTC + */ + +int rtc_get (struct rtc_time *tmp) +{ + unsigned long now; + + debug ("%s(): record register: %x\n", + __func__, readl (&rtc->record)); + + now = ftrtc010_time () + readl (&rtc->record); + + to_tm (now, tmp); + + return 0; +} + +/* + * Set the RTC + */ +int rtc_set (struct rtc_time *tmp) +{ + unsigned long new; + unsigned long now; + + debug ("%s(): DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", + __func__, + tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, + tmp->tm_hour, tmp->tm_min, tmp->tm_sec); + + new = mktime (tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_hour, + tmp->tm_min, tmp->tm_sec); + + now = ftrtc010_time (); + + debug ("%s(): write %lx to record register\n", __func__, new - now); + + writel (new - now, &rtc->record); + + return 0; +} + +void rtc_reset (void) +{ + debug ("%s()\n", __func__); + ftrtc010_enable (); +} -- 1.6.3.3

2 1

[U-Boot] [PATCH] MIMC200: set default fbmem value
by Mark Jackson 22 Nov '09

22 Nov '09

This patch adds a default bootargs "fbmem" value to the CONFIG_BOOTARGS string for the MIMC200 board. Signed-off-by: Mark Jackson <mpfj(a)mimc.co.uk> --- include/configs/mimc200.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h index 8f71664..36488b3 100644 --- a/include/configs/mimc200.h +++ b/include/configs/mimc200.h @@ -74,7 +74,7 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTARGS \ - "root=/dev/mtdblock1 rootfstype=jffs2 console=ttyS1" + "root=/dev/mtdblock1 rootfstype=jffs2 fbmem=512k console=ttyS1" #define CONFIG_BOOTCOMMAND \ "fsload boot/uImage; bootm"

2 1

[U-Boot] [PATCH 01/03 v2] Add inverted clock polarity support for Atmel LCD driver
by Dimitar Dimitrov 22 Nov '09

22 Nov '09

This is my second try for Olimex SAM9-L9260/61 board support patches. I deleted the board ethernet initialization and hopefully will add it later in a state that can be accepted. Here follows the first patch. --- Boards utilizing the Atmel LCD driver can now specify that the LCD clock must be inverted by defining the macro CONFIG_ATMEL_LCD_INVCLK. Signed-off-by: Dimitar Dimitrov <dinuxbg(a)gmail.com> --- drivers/video/atmel_lcdfb.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index db86763..64f8e87 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c @@ -112,6 +112,9 @@ void lcd_ctrl_init(void *lcdbase) value |= panel_info.vl_sync; value |= (panel_info.vl_bpix << 5); +#if defined(CONFIG_ATMEL_LCD_INVCLK) + value |= ATMEL_LCDC_INVCLK_INVERTED; +#endif lcdc_writel(panel_info.mmio, ATMEL_LCDC_LCDCON2, value); /* Vertical timing */ -- 1.5.6.1

2 4

[U-Boot] [PATCH] Added preliminary support to EHCI USB FSL controller for platform MPC5121
by Rendine Francesco 22 Nov '09

22 Nov '09

Hi all, I would like to submit you a patch to add a preliminary support to EHCI USB Freescale controller integrated on MPC5121. There is still much job to do..for now, this patch add support for USB0 on UTMI phy. I've personally tested this feature with mass storage and it does work. Could be a base for future development..I'm available to possible improvement of source code with your suggestions. Summary: - introduced ehci_hcd_init and ehci_hcd_stop functions for MPC5121 integrated EHCI USB controller - introduced enable of EHCI USB controller in include/mpc5121ads.h - introduced many defines and struct ehci fields to be able to provvide OTG feature Regards, Francesco Rendine. Signed-off-by: Francesco Rendine <francesco.rendine(a)valueteam.com> diff -Naur u-boot.orig/board/freescale/mpc5121ads/mpc5121ads.c u-boot.usb/board/freescale/mpc5121ads/mpc5121ads.c --- u-boot.orig/board/freescale/mpc5121ads/mpc5121ads.c 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/board/freescale/mpc5121ads/mpc5121ads.c 2009-06-24 18:12:06.000000000 +0200 @@ -54,7 +54,8 @@ #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_DIU_EN | \ CLOCK_SCCR2_I2C_EN | \ CLOCK_SCCR2_MEM_EN | \ - CLOCK_SCCR2_SPDIF_EN) + CLOCK_SCCR2_SPDIF_EN | \ + CLOCK_SCCR2_USB1_EN) #define CSAW_START(start) ((start) & 0xFFFF0000) #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16) diff -Naur u-boot.orig/drivers/usb/host/ehci-fsl.c u-boot.usb/drivers/usb/host/ehci-fsl.c --- u-boot.orig/drivers/usb/host/ehci-fsl.c 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/drivers/usb/host/ehci-fsl.c 2009-06-25 01:14:34.000000000 +0200 @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009, Value Team S.p.A. + * Francesco Rendine, <francesco.rendine(a)valueteam.com> + * * (C) Copyright 2009 Freescale Semiconductor, Inc. * * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB @@ -30,6 +33,7 @@ #include "ehci.h" #include "ehci-core.h" +#ifndef CONFIG_MPC512X /* * Create the appropriate control structures to manage * a new EHCI host controller. @@ -38,34 +42,93 @@ */ int ehci_hcd_init(void) { - struct usb_ehci *ehci; + struct usb_ehci *ehci; - ehci = (struct usb_ehci *)CONFIG_SYS_MPC8xxx_USB_ADDR; - hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength); - hcor = (struct ehci_hcor *)((uint32_t) hccr + - HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + hccr = (struct ehci_hccr *)((uint32_t)ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); - /* Set to Host mode */ - setbits_le32((void *)ehci->usbmode, CM_HOST); + /* Set to Host mode */ + setbits_le32((void *)ehci->usbmode, CM_HOST); - out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB); - out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop1, SNOOP_SIZE_2GB); + out_be32((void *)ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB); - /* Init phy */ - if (!strcmp(getenv("usb_phy_type"), "utmi")) - out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); - else - out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); + /* Init phy */ + if (!strcmp(getenv("usb_phy_type"), "utmi")) + out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI); + else + out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI); - /* Enable interface. */ - setbits_be32((void *)ehci->control, USB_EN); + /* Enable interface. */ + setbits_be32((void *)ehci->control, USB_EN); - out_be32((void *)ehci->prictrl, 0x0000000c); - out_be32((void *)ehci->age_cnt_limit, 0x00000040); - out_be32((void *)ehci->sictrl, 0x00000001); + out_be32((void *)ehci->prictrl, 0x0000000c); + out_be32((void *)ehci->age_cnt_limit, 0x00000040); + out_be32((void *)ehci->sictrl, 0x00000001); + + in_le32((void *)ehci->usbmode); + + return 0; +} + +/* + * Destroy the appropriate control structures corresponding + * the the EHCI host controller. + */ +int ehci_hcd_stop(void) +{ + return 0; +} +#else +/* + * Initialize SOC FSL EHCI Controller + * + * This code is derived from EHCI FSL USB Linux driver for MPC5121 + * + */ +int ehci_hcd_init(void) +{ + struct usb_ehci *ehci; + u32 temp; - in_le32((void *)ehci->usbmode); + /* Hook the memory mapped registers for EHCI-Controller */ + ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR; + hccr = (struct ehci_hccr *)(&ehci->caplength); + hcor = (struct ehci_hcor *)((uint32_t) hccr + + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); + /* Confgure interface for UTMI_WIDE */ + temp = in_be32(&ehci->isiphyctrl); + out_be32(&ehci->isiphyctrl, temp | PHYCTRL_PHYE | PHYCTRL_PXE); + + temp = in_be32(&ehci->usbgenctrl); + out_be32(&ehci->usbgenctrl, temp | GC_PPP | GC_PFP ); + + /* Workaround: disable ULPI phy */ + temp = 0x60000000 | 0x0C << 16 | 0x20 ; + temp = cpu_to_hc32(temp); + out_be32(&ehci->ulpi_viewpoint, temp); + + /* Configure interrupt */ + temp = ehci_readl(&hcor->or_usbintr); + temp |= (INTR_UE | INTR_UEE | INTR_PCE | INTR_SEE | INTR_AAE); + ehci_writel(&hcor->or_usbintr, temp); + + /* Init phy USB0 to UTMI+ */ + temp = ehci_readl(&hcor->or_portsc[0]); + temp &= ~(PORT_PTS_MSK | PORT_PTS_PTW); + temp |= (PORT_PTS_UTMI | PORT_PTS_PTW); + ehci_writel(&hcor->or_portsc[0], temp); + + /* Set to Host mode */ +#ifdef CONFIG_EHCI_DESC_BIG_ENDIAN + setbits_be32(&ehci->usbmode, CM_HOST | ES_BE); +#else + setbits_be32(&ehci->usbmode, CM_HOST); +#endif + return 0; } @@ -75,5 +138,16 @@ */ int ehci_hcd_stop(void) { + u32 temp; + + /* Disable phy USB0 */ + temp = ehci_readl(&hcor->or_portsc[0]); + temp &= ~(PORT_PTS_MSK | PORT_PTS_PTW | PORT_PP | PORT_PR); + ehci_writel(&hcor->or_portsc[0], temp); + + /* Unhook struct */ + hccr = hcor = NULL; + return 0; } +#endif diff -Naur u-boot.orig/drivers/usb/host/ehci.h u-boot.usb/drivers/usb/host/ehci.h --- u-boot.orig/drivers/usb/host/ehci.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/drivers/usb/host/ehci.h 2009-06-24 16:13:40.000000000 +0200 @@ -71,6 +71,11 @@ #define STD_ASS (1 << 15) #define STS_HALT (1 << 12) uint32_t or_usbintr; +#define INTR_UE (1 << 0) /* USB interrupt enable */ +#define INTR_UEE (1 << 1) /* USB error interrupt enable */ +#define INTR_PCE (1 << 2) /* Port change detect enable */ +#define INTR_SEE (1 << 4) /* system error enable */ +#define INTR_AAE (1 << 5) /* Interrupt on async adavance enable */ uint32_t or_frindex; uint32_t or_ctrldssegment; uint32_t or_periodiclistbase; diff -Naur u-boot.orig/include/asm-ppc/immap_512x.h u-boot.usb/include/asm-ppc/immap_512x.h --- u-boot.orig/include/asm-ppc/immap_512x.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/asm-ppc/immap_512x.h 2009-06-24 18:28:29.000000000 +0200 @@ -1228,4 +1228,8 @@ } #endif /* __ASSEMBLY__ */ +#define CONFIG_SYS_MPC512x_USB_OFFSET 0x4000 +#define CONFIG_SYS_MPC512x_USB_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_MPC512x_USB_OFFSET) + #endif /* __IMMAP_512x__ */ diff -Naur u-boot.orig/include/configs/mpc5121ads.h u-boot.usb/include/configs/mpc5121ads.h --- u-boot.orig/include/configs/mpc5121ads.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/configs/mpc5121ads.h 2009-06-25 01:38:29.000000000 +0200 @@ -342,6 +342,21 @@ #define CONFIG_RTC_M41T62 /* use M41T62 rtc via i2 */ #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ +/* USB Support */ +#define CONFIG_USB + +#ifdef CONFIG_USB + #define CONFIG_USB_EHCI +#endif + +#ifdef CONFIG_USB_EHCI + #define CONFIG_USB_EHCI_FSL + #define CONFIG_EHCI_MMIO_BIG_ENDIAN + #define CONFIG_EHCI_DESC_BIG_ENDIAN + #define CONFIG_SYS_USB_EHCI_REGS_BASE 0x80004000 + #define CONFIG_EHCI_IS_TDI +#endif + /* * Environment */ @@ -387,6 +402,16 @@ #define CONFIG_ISO_PARTITION #endif /* defined(CONFIG_CMD_IDE) */ +#if defined(CONFIG_USB) +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_SUPPORT_VFAT +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION +#endif + /* * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set @@ -484,6 +509,7 @@ "rootpath=/opt/eldk/ppc_6xx\n" \ "netdev=eth0\0" \ "consdev=ttyPSC0\0" \ + "usb_phy_type=utmi\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ diff -Naur u-boot.orig/include/usb/ehci-fsl.h u-boot.usb/include/usb/ehci-fsl.h --- u-boot.orig/include/usb/ehci-fsl.h 2009-06-15 19:30:27.000000000 +0200 +++ u-boot.usb/include/usb/ehci-fsl.h 2009-06-24 16:22:15.000000000 +0200 @@ -35,12 +35,16 @@ #define PORT_PTS_ULPI (2 << 30) #define PORT_PTS_SERIAL (3 << 30) #define PORT_PTS_PTW (1 << 28) +#define PORT_PTS_PHCD (1 << 23) +#define PORT_PP (1 << 12) +#define PORT_PR (1 << 8) /* USBMODE Register bits */ #define CM_IDLE (0 << 0) #define CM_RESERVED (1 << 0) #define CM_DEVICE (2 << 0) #define CM_HOST (3 << 0) +#define ES_BE (1 << 2) /* Big Endian Select, default is LE */ #define USBMODE_RESERVED_2 (0 << 2) #define SLOM (1 << 3) #define SDIS (1 << 4) @@ -70,7 +74,74 @@ #define PHY_CLK_VALID (1 << 17) #define FSL_SOC_USB_PORTSC2 0x188 + +/* OTG Status Control Register bits */ +#define FSL_SOC_USB_OTGSC 0x1a4 +#define CTRL_VBUS_DISCHARGE (0x1<<0) +#define CTRL_VBUS_CHARGE (0x1<<1) +#define CTRL_OTG_TERMINATION (0x1<<3) +#define CTRL_DATA_PULSING (0x1<<4) +#define CTRL_ID_PULL_EN (0x1<<5) +#define HA_DATA_PULSE (0x1<<6) +#define HA_BA (0x1<<7) +#define STS_USB_ID (0x1<<8) +#define STS_A_VBUS_VALID (0x1<<9) +#define STS_A_SESSION_VALID (0x1<<10) +#define STS_B_SESSION_VALID (0x1<<11) +#define STS_B_SESSION_END (0x1<<12) +#define STS_1MS_TOGGLE (0x1<<13) +#define STS_DATA_PULSING (0x1<<14) +#define INTSTS_USB_ID (0x1<<16) +#define INTSTS_A_VBUS_VALID (0x1<<17) +#define INTSTS_A_SESSION_VALID (0x1<<18) +#define INTSTS_B_SESSION_VALID (0x1<<19) +#define INTSTS_B_SESSION_END (0x1<<20) +#define INTSTS_1MS (0x1<<21) +#define INTSTS_DATA_PULSING (0x1<<22) +#define INTR_USB_ID_EN (0x1<<24) +#define INTR_A_VBUS_VALID_EN (0x1<<25) +#define INTR_A_SESSION_VALID_EN (0x1<<26) +#define INTR_B_SESSION_VALID_EN (0x1<<27) +#define INTR_B_SESSION_END_EN (0x1<<28) +#define INTR_1MS_TIMER_EN (0x1<<29) +#define INTR_DATA_PULSING_EN (0x1<<30) +#define INTSTS_MASK (0x00ff0000) + +#define INTERRUPT_ENABLE_BITS_MASK \ + (INTR_USB_ID_EN | \ + INTR_1MS_TIMER_EN | \ + INTR_A_VBUS_VALID_EN | \ + INTR_A_SESSION_VALID_EN | \ + INTR_B_SESSION_VALID_EN | \ + INTR_B_SESSION_END_EN | \ + INTR_DATA_PULSING_EN) + +#define INTERRUPT_STATUS_BITS_MASK \ + (INTSTS_USB_ID | \ + INTR_1MS_TIMER_EN | \ + INTSTS_A_VBUS_VALID | \ + INTSTS_A_SESSION_VALID | \ + INTSTS_B_SESSION_VALID | \ + INTSTS_B_SESSION_END | \ + INTSTS_DATA_PULSING) + #define FSL_SOC_USB_USBMODE 0x1a8 + +#define USBGENCTRL 0x200 /* NOTE: big endian */ +#define GC_WU_INT_CLR (1 << 5) /* Wakeup int clear */ +#define GC_ULPI_SEL (1 << 4) /* ULPI i/f select (usb0 only)*/ +#define GC_PPP (1 << 3) /* Port Power Polarity */ +#define GC_PFP (1 << 2) /* Power Fault Polarity */ +#define GC_WU_ULPI_EN (1 << 1) /* Wakeup on ULPI event */ +#define GC_WU_IE (1 << 1) /* Wakeup interrupt enable */ + +#define ISIPHYCTRL 0x204 /* NOTE: big endian */ +#define PHYCTRL_PHYE (1 << 4) /* On-chip UTMI PHY enable */ +#define PHYCTRL_BSENH (1 << 3) /* Bit Stuff Enable High */ +#define PHYCTRL_BSEN (1 << 2) /* Bit Stuff Enable */ +#define PHYCTRL_LSFE (1 << 1) /* Line State Filter Enable */ +#define PHYCTRL_PXE (1 << 0) /* PHY oscillator enable */ + #define FSL_SOC_USB_SNOOP1 0x400 /* NOTE: big-endian */ #define FSL_SOC_USB_SNOOP2 0x404 /* NOTE: big-endian */ #define FSL_SOC_USB_AGECNTTHRSH 0x408 /* NOTE: big-endian */ @@ -86,43 +157,59 @@ #define MPC83XX_SCCR_USB_DRCM_10 0x00200000 #if defined(CONFIG_MPC83XX) -#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC83xx_USB_ADDR #elif defined(CONFIG_MPC85xx) -#define CONFIG_SYS_MPC8xxx_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC85xx_USB_ADDR +#elif defined(CONFIG_MPC512X) +#define CONFIG_SYS_FSL_USB_ADDR CONFIG_SYS_MPC512x_USB_ADDR #endif + /* * USB Registers */ struct usb_ehci { - u8 res1[0x100]; + u32 id; /* 0x000 - Identification register */ + u32 hwgeneral; /* 0x004 - General hardware parameters */ + u32 hwhost; /* 0x008 - Host hardware parameters */ + u32 hwdevice; /* 0x00C - Device hardware parameters */ + u32 hwtxbuf; /* 0x010 - TX buffer hardware parameters */ + u32 hwrxbuf; /* 0x014 - RX buffer hardware parameters */ + u8 res1[0x68]; + u32 gptimer0_ld; /* 0x080 - General Purpose Timer 0 load value */ + u32 gptimer0_ctrl; /* 0x084 - General Purpose Timer 0 control */ + u32 gptimer1_ld; /* 0x088 - General Purpose Timer 1 load value */ + u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */ + u32 sbuscfg; /* 0x090 - System Bus Interface Control */ + u8 res2[0x6C]; u16 caplength; /* 0x100 - Capability Register Length */ u16 hciversion; /* 0x102 - Host Interface Version */ u32 hcsparams; /* 0x104 - Host Structural Parameters */ u32 hccparams; /* 0x108 - Host Capability Parameters */ - u8 res2[0x14]; + u8 res3[0x14]; u32 dciversion; /* 0x120 - Device Interface Version */ u32 dciparams; /* 0x124 - Device Controller Params */ - u8 res3[0x18]; + u8 res4[0x18]; u32 usbcmd; /* 0x140 - USB Command */ u32 usbsts; /* 0x144 - USB Status */ u32 usbintr; /* 0x148 - USB Interrupt Enable */ u32 frindex; /* 0x14C - USB Frame Index */ - u8 res4[0x4]; + u8 res5[0x4]; u32 perlistbase; /* 0x154 - Periodic List Base - USB Device Address */ u32 ep_list_addr; /* 0x158 - Next Asynchronous List - End Point Address */ - u8 res5[0x4]; + u8 res6[0x4]; u32 burstsize; /* 0x160 - Programmable Burst Size */ u32 txfilltuning; /* 0x164 - Host TT Transmit pre-buffer packet tuning */ - u8 res6[0x8]; + u8 res7[0x8]; u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */ - u8 res7[0xc]; + u8 res8[0xc]; u32 config_flag; /* 0x180 - Configured Flag Register */ u32 portsc; /* 0x184 - Port status/control */ - u8 res8[0x20]; + u8 res9[0x1C]; + u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */ u32 usbmode; /* 0x1a8 - USB Device Mode */ u32 epsetupstat; /* 0x1ac - End Point Setup Status */ u32 epprime; /* 0x1b0 - End Point Init Status */ @@ -135,15 +222,18 @@ u32 epctrl3; /* 0x1cc - End Point Control 3 */ u32 epctrl4; /* 0x1d0 - End Point Control 4 */ u32 epctrl5; /* 0x1d4 - End Point Control 5 */ - u8 res9[0x228]; + u8 res10[0x28]; + u32 usbgenctrl; /* 0x200 - USB General Control */ + u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */ + u8 res11[0x1F8]; u32 snoop1; /* 0x400 - Snoop 1 */ u32 snoop2; /* 0x404 - Snoop 2 */ u32 age_cnt_limit; /* 0x408 - Age Count Threshold */ u32 prictrl; /* 0x40c - Priority Control */ u32 sictrl; /* 0x410 - System Interface Control */ - u8 res10[0xEC]; + u8 res12[0xEC]; u32 control; /* 0x500 - Control */ - u8 res11[0xafc]; + u8 res13[0xafc]; }; #endif /* _EHCI_FSL_H */

2 3

[U-Boot] [PATCH] 85xx: Enable the DDR3 SPD support for P2020DS board
by Dave Liu 22 Nov '09

22 Nov '09

* The ELPIDA 2GB unbuffered DDR3 SDRAM DIMMs - EBJ21EE8BAFA-AE-E 600MT/s, 667MT/s and 800MT/s passed on P2020DS * Micron 1GB unbuffered DDR3 SDRAM DIMMs - MT9JSF12872AY-1G4D1 600MT/s, 667MT/s and 800MT/s passed on P2020DS Signed-off-by: Dave Liu <daveliu(a)freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley(a)freescale.com> --- board/freescale/p2020ds/ddr.c | 34 ++++++++++++++++------------------ include/configs/P2020DS.h | 6 ++++-- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index b9c0cb2..aaff6e8 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -51,27 +51,21 @@ typedef struct { * cpo 2-0x1E (30) */ - -/* XXX: these values need to be checked for all interleaving modes. */ -/* XXX: No reliable dual-rank 800 MHz setting has been found. It may - * seem reliable, but errors will appear when memory intensive - * program is run. */ -/* XXX: Single rank at 800 MHz is OK. */ const board_specific_parameters_t board_specific_parameters[][20] = { { /* memory controller 0 */ - /* lo| hi| num| clk| cpo|wrdata|2T */ - /* mhz| mhz|ranks|adjst| | delay| */ - { 0, 333, 2, 6, 7, 3, 0}, - {334, 400, 2, 6, 9, 3, 0}, - {401, 549, 2, 6, 11, 3, 0}, - {550, 680, 2, 1, 10, 5, 0}, - {681, 850, 2, 1, 12, 5, 1}, - { 0, 333, 1, 6, 7, 3, 0}, - {334, 400, 1, 6, 9, 3, 0}, - {401, 549, 1, 6, 11, 3, 0}, - {550, 680, 1, 1, 10, 5, 0}, - {681, 850, 1, 1, 12, 5, 0} + /* lo| hi| num| clk| cpo|wrdata|2T */ + /* mhz| mhz|ranks|adjst| | delay| */ + { 0, 333, 2, 4, 0x1f, 2, 0}, + {334, 400, 2, 4, 0x1f, 2, 0}, + {401, 549, 2, 4, 0x1f, 2, 0}, + {550, 680, 2, 4, 0x1f, 3, 0}, + {681, 850, 2, 4, 0x1f, 4, 0}, + { 0, 333, 1, 4, 0x1f, 2, 0}, + {334, 400, 1, 4, 0x1f, 2, 0}, + {401, 549, 1, 4, 0x1f, 2, 0}, + {550, 680, 1, 4, 0x1f, 3, 0}, + {681, 850, 1, 4, 0x1f, 4, 0} }, }; @@ -127,4 +121,8 @@ void fsl_ddr_board_options(memctl_options_t *popts, * - number of DIMMs installed */ popts->half_strength_driver_enable = 0; + /* + * Disable write leveling + */ + popts->wrlvl_en = 0; } diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index e4119e3..0564242 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -82,8 +82,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* @@ -121,6 +121,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CONFIG_SPD_EEPROM +#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -- 1.5.4

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[U-Boot] [PATCH 2/2] 85xx: add the nfsboot/ramboot to default environment
by Dave Liu 22 Nov '09

22 Nov '09

Give the MPC8569MDS board one default environment var. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/configs/MPC8569MDS.h | 72 ++++++++++++++++++++++++------------------ 1 files changed, 41 insertions(+), 31 deletions(-) diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index b0af5dc..7fd2b56 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -409,46 +409,56 @@ extern unsigned long get_clock_freq(void); * Environment Configuration */ #define CONFIG_HOSTNAME mpc8569mds -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage +#define CONFIG_ROOTPATH /tftpboot +#define CONFIG_BOOTFILE uImage.8569 +#define CONFIG_HAS_ETH0 +#define CONFIG_ETHADDR 00:E0:0C:85:69:01 +#define CONFIG_HAS_ETH1 +#define CONFIG_ETH1ADDR 00:E0:0C:85:69:02 + +#define CONFIG_IPADDR 192.168.1.100 #define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 +#define CONFIG_GATEWAYIP 192.168.1.254 #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ +#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ #define CONFIG_BAUDRATE 115200 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "consoledev=ttyS0\0" \ - "ramdiskaddr=600000\0" \ - "ramdiskfile=your.ramdisk.u-boot\0" \ - "fdtaddr=400000\0" \ - "fdtfile=your.fdt.dtb\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=$serverip:$rootpath " \ - "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - "ramargs=setenv bootargs root=/dev/ram rw " \ - "console=$consoledev,$baudrate $othbootargs\0" \ - -#define CONFIG_NFSBOOTCOMMAND \ - "run nfsargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ - "bootm $loadaddr - $fdtaddr" - -#define CONFIG_RAMBOOTCOMMAND \ - "run ramargs;" \ - "tftp $ramdiskaddr $ramdiskfile;" \ - "tftp $loadaddr $bootfile;" \ - "bootm $loadaddr $ramdiskaddr" - -#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "uboot=u-boot.8569\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=ramdisk.8569\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=dtb.8569\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv bootargs root=/dev/nfs rw " \ + "nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" #endif /* __CONFIG_H */ -- 1.5.4

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[U-Boot] [PATCH 3/3] [OneNAND] Flex-OneNAND boundary settings
by Amul Kumar Saha 19 Nov '09

19 Nov '09

Add command for changing Flex-OneNAND SLC / MLC boundary. Also onenand commands work for Flex-OneNAND. Signed-off-by: Rohit Hagargundgi <h.rohit(a)samsung.com> Signed-off-by: Amul Kumar Saha <amul.saha(a)samsung.com> --- common/cmd_onenand.c | 90 +++++++++++++++++++++++++++++++++------------- include/configs/apollon.h | 2 - 2 files changed, 66 insertions(+), 26 deletions(-) diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 9090940..a34befe 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -69,36 +69,49 @@ static int arg_off_size(int argc, char *argv[], ulong *off, size_t *size) return 0; } +static inline int onenand_blocksize(loff_t ofs) +{ + struct onenand_chip *this = mtd->priv; + int i; + + if (!FLEXONENAND(this)) + return mtd->erasesize; + + i = flexonenand_region(mtd, ofs); + return mtd->eraseregions[i].erasesize; +} + static int onenand_block_read(loff_t from, size_t len, size_t *retlen, u_char *buf, int oob) { struct onenand_chip *this = mtd->priv; - int blocks = (int) len >> this->erase_shift; - int blocksize = (1 << this->erase_shift); + int blocks = (int) onenand_block(this, from + len) + - onenand_block(this, from); + int blocksize; loff_t ofs = from; struct mtd_oob_ops ops = { .retlen = 0, }; int ret; - if (oob) - ops.ooblen = blocksize; - else - ops.len = blocksize; - while (blocks) { + blocksize = onenand_blocksize(ofs); + ret = mtd->block_isbad(mtd, ofs); if (ret) { printk("Bad blocks %d at 0x%x\n", - (u32)(ofs >> this->erase_shift), (u32)ofs); + (u32)onenand_block(this, ofs), (u32)ofs); ofs += blocksize; continue; } - if (oob) + if (oob) { ops.oobbuf = buf; - else + ops.ooblen = blocksize; + } else { ops.datbuf = buf; + ops.len = blocksize; + } ops.retlen = 0; ret = mtd->read_oob(mtd, ofs, &ops); @@ -120,8 +133,7 @@ static int onenand_block_write(loff_t to, size_t len, size_t *retlen, const u_char * buf) { struct onenand_chip *this = mtd->priv; - int blocks = len >> this->erase_shift; - int blocksize = (1 << this->erase_shift); + int blocks, blocksize; loff_t ofs; size_t _retlen = 0; int ret; @@ -135,11 +147,16 @@ static int onenand_block_write(loff_t to, size_t len, } ofs = to; + blocks = (int) onenand_block(this, ofs + len) + - onenand_block(this, ofs); + while (blocks) { + blocksize = onenand_blocksize(ofs); + ret = mtd->block_isbad(mtd, ofs); if (ret) { printk("Bad blocks %d at 0x%x\n", - (u32)(ofs >> this->erase_shift), (u32)ofs); + (u32)onenand_block(this, ofs), (u32)ofs); skip_ofs += blocksize; goto next; } @@ -169,13 +186,15 @@ static int onenand_block_erase(u32 start, u32 size, int force) }; loff_t ofs; int ret; - int blocksize = 1 << this->erase_shift; + int blocksize; for (ofs = start; ofs < (start + size); ofs += blocksize) { + blocksize = onenand_blocksize(ofs); + ret = mtd->block_isbad(mtd, ofs); if (ret && !force) { printf("Skip erase bad block %d at 0x%x\n", - (u32)(ofs >> this->erase_shift), (u32)ofs); + (u32)onenand_block(this, ofs), (u32)ofs); continue; } @@ -186,7 +205,7 @@ static int onenand_block_erase(u32 start, u32 size, int force) ret = mtd->erase(mtd, &instr); if (ret) { printf("erase failed block %d at 0x%x\n", - (u32)(ofs >> this->erase_shift), (u32)ofs); + (u32)onenand_block(this, ofs), (u32)ofs); continue; } } @@ -223,25 +242,28 @@ static int onenand_block_test(u32 start, u32 size) return -1; } - start_block = start >> this->erase_shift; - end_block = (start + size) >> this->erase_shift; + start_block = onenand_block(this, start); + end_block = onenand_block(this, start + size); /* Protect boot-loader from badblock testing */ if (start_block < 2) start_block = 2; - if (end_block > (mtd->size >> this->erase_shift)) - end_block = mtd->size >> this->erase_shift; + if (end_block > onenand_block(this, mtd->size)) + end_block = onenand_block(this, mtd->size); blocks = start_block; ofs = start; while (blocks < end_block) { - printf("\rTesting block %d at 0x%x", (u32)(ofs >> this->erase_shift), (u32)ofs); + printf("\rTesting block %d at 0x%x", + (u32) onenand_block(this, ofs), (u32)ofs); + + blocksize = onenand_blocksize(ofs); ret = mtd->block_isbad(mtd, ofs); if (ret) { printf("Skip erase bad block %d at 0x%x\n", - (u32)(ofs >> this->erase_shift), (u32)ofs); + (u32)onenand_block(this, ofs), (u32)ofs); goto next; } @@ -345,7 +367,6 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) mtd = &onenand_mtd; this = mtd->priv; - blocksize = (1 << this->erase_shift); cmd = argv[1]; @@ -363,9 +384,11 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (strcmp(cmd, "bad") == 0) { /* Currently only one OneNAND device is supported */ printf("\nDevice %d bad blocks:\n", 0); - for (ofs = 0; ofs < mtd->size; ofs += mtd->erasesize) { + for (ofs = 0; ofs < mtd->size; ofs += blocksize) { if (mtd->block_isbad(mtd, ofs)) printf(" %08x\n", (u32)ofs); + + blocksize = onenand_blocksize(ofs); } return 0; @@ -474,6 +497,21 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return ret == 0 ? 1 : 0; } + if (strncmp(cmd, "setboundary", 11) == 0) { + int die, bdry, lock = 0; + + if (argc < 4) + goto usage; + + die = (int) strict_strtoul(argv[2], NULL, 0); + bdry = (int) strict_strtoul(argv[3], NULL, 0); + + if (argc == 5 && strncmp(argv[4], "LOCK", 4) == 0) + lock = 1; + + return flexonenand_set_boundary(mtd, die, bdry, lock); + } + break; } @@ -493,9 +531,11 @@ U_BOOT_CMD( "onenand write[.oob] addr off size\n" " read/write 'size' bytes starting at offset 'off'\n" " to/from memory address 'addr', skipping bad blocks.\n" - "onenand erase [force] [off size] - erase 'size' bytes from\n" + "onenand erase [force] [off size] - erase 'size' bytes from off\n" "onenand test [off size] - test 'size' bytes from\n" " offset 'off' (entire device if not specified)\n" "onenand dump[.oob] off - dump page\n" "onenand markbad off [...] - mark bad block(s) at offset (UNSAFE)" + "onenand setboundary DIE BOUNDARY [LOCK] - \n" + "Change SLC boundary of Flex-OneNAND\n" ); diff --git a/include/configs/apollon.h b/include/configs/apollon.h index ddac5fb..5a97743 100644 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -77,7 +77,7 @@ */ #define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ #define CONFIG_ENV_SIZE_FLEX SZ_256K -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_1M) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_2M) /* bytes reserved for initial data */ #define CONFIG_SYS_GBL_DATA_SIZE 128

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[U-Boot] [PATCH 00/10][v2] Support for LogicPD i.MX27-LITEKIT development board
by Ilya Yanok 19 Nov '09

19 Nov '09

This patch set adds support for LogicPD i.MX27-LITEKIT development board. It contains support for i.MX27 CPU, support for serial console, FEC ethernet controller, NFC NAND controller and SDHC controller. Signed-off-by: Ilya Yanok <yanok(a)emcraft.com>

10 33

[U-Boot] [PATCH] ppc4xx: Initialize magnetic coupler on VOM405 boards
by Matthias Fuchs 17 Nov '09

17 Nov '09

This patch fixes an ugly behavior of the IL712 magnetic coupler as used on VOM405. These parts will remember their last state over a power cycle which might cause unwanted behavior. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- board/esd/vom405/vom405.c | 35 +++++++++++++++++++++++++++++++++++ 1 files changed, 35 insertions(+), 0 deletions(-) diff --git a/board/esd/vom405/vom405.c b/board/esd/vom405/vom405.c index fb48022..de35036 100644 --- a/board/esd/vom405/vom405.c +++ b/board/esd/vom405/vom405.c @@ -26,11 +26,40 @@ #include <asm/io.h> #include <command.h> #include <malloc.h> +#include <sja1000.h> DECLARE_GLOBAL_DATA_PTR; extern void lxt971_no_sleep(void); +/* + * generate a short spike on the CAN tx line + * to bring the couplers in sync + */ +void init_coupler(u32 addr) +{ + struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; + + /* reset */ + out_8(&ctrl->cr, CR_RR); + + /* dominant */ + out_8(&ctrl->btr0, 0x00); /* btr setup is required */ + out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ + out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | + OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); + out_8(&ctrl->cr, 0x00); + + /* delay */ + in_8(&ctrl->cr); + in_8(&ctrl->cr); + in_8(&ctrl->cr); + in_8(&ctrl->cr); + + /* reset */ + out_8(&ctrl->cr, CR_RR); +} + int board_early_init_f (void) { /* @@ -77,6 +106,12 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; + /* + * Init magnetic coupler + */ + if (!getenv("noinitcoupler")) + init_coupler(CAN_BA); + return (0); } -- 1.6.1

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[U-Boot] [PATCH 2/2 V3] ppc4xx: Initialize magnetic couplers in PLU405
by Matthias Fuchs 17 Nov '09

17 Nov '09

This patch fixes an ugly behavior of the IL712 magnetic couplers as used on PLU405. These parts will remember their last state over a power cycle which might cause unwanted behavior. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd.eu> --- V2: - use C struct to access CAN controller registes V3: - move SJA1000 stuff into separate header (see preceding patch) - some renaming board/esd/plu405/plu405.c | 36 ++++++++++++++++++++++++++++++++++++ include/configs/PLU405.h | 3 ++- 2 files changed, 38 insertions(+), 1 deletions(-) diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c index 1841cda..fea7b26 100644 --- a/board/esd/plu405/plu405.c +++ b/board/esd/plu405/plu405.c @@ -26,6 +26,7 @@ #include <asm/io.h> #include <command.h> #include <malloc.h> +#include <sja1000.h> #undef FPGA_DEBUG @@ -45,6 +46,34 @@ const unsigned char fpgadata[] = */ #include "../common/fpga.c" +/* + * generate a short spike on the CAN tx line + * to bring the couplers in sync + */ +void init_coupler(u32 addr) +{ + struct sja1000_basic_s *ctrl = (struct sja1000_basic_s *)addr; + + /* reset */ + out_8(&ctrl->cr, CR_RR); + + /* dominant */ + out_8(&ctrl->btr0, 0x00); /* btr setup is required */ + out_8(&ctrl->btr1, 0x14); /* we use 1Mbit/s */ + out_8(&ctrl->oc, OC_TP1 | OC_TN1 | OC_POL1 | + OC_TP0 | OC_TN0 | OC_POL0 | OC_MODE1); + out_8(&ctrl->cr, 0x00); + + /* delay */ + in_8(&ctrl->cr); + in_8(&ctrl->cr); + in_8(&ctrl->cr); + in_8(&ctrl->cr); + + /* reset */ + out_8(&ctrl->cr, CR_RR); +} + /* Prototypes */ int gunzip(void *, int, unsigned char *, unsigned long *); @@ -198,6 +227,13 @@ int misc_init_r(void) out_8((void *)DUART1_BA + 1, fctr); /* write FCTR */ out_8((void *)DUART1_BA + 3, 0); /* write LCR */ + /* + * Init magnetic couplers + */ + if (!getenv("noinitcoupler")) { + init_coupler(CAN0_BA); + init_coupler(CAN1_BA); + } return 0; } diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index 07fc715..b6740de 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -298,7 +298,8 @@ /* * External Bus Controller (EBC) Setup */ -#define CAN_BA 0xF0000000 /* CAN Base Address */ +#define CAN0_BA 0xF0000000 /* CAN0 Base Address */ +#define CAN1_BA 0xF0000100 /* CAN1 Base Address */ #define DUART0_BA 0xF0000400 /* DUART Base Address */ #define DUART1_BA 0xF0000408 /* DUART Base Address */ #define RTC_BA 0xF0000500 /* RTC Base Address */ -- 1.6.1

2 1