October 2009 - U-Boot

[U-Boot] [PATCH] mkconfig: deny messed up ARCH definition
by Nishanth Menon 02 Nov '09

02 Nov '09

Refuse to setup a platform if the command line ARCH= is not the same as the one required for the board. This prevents any user with prehistoric aliases from messing up thier builds Reported in thread: http://old.nabble.com/-U-Boot--Build-breaks-on-some-OMAP3-configs-to2613272… Signed-off-by: Nishanth Menon <nm(a)ti.com> --- mkconfig | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/mkconfig b/mkconfig index 4c5675b..87ac6d4 100755 --- a/mkconfig +++ b/mkconfig @@ -27,6 +27,11 @@ done [ $# -lt 4 ] && exit 1 [ $# -gt 6 ] && exit 1 +if [ ! -z "$ARCH" -a "$ARCH" != "$2" ]; then + echo "ARCH=$ARCH while ${BOARD_NAME} arch=$2: fail" + exit 1 +fi + echo "Configuring for ${BOARD_NAME} board..." # -- 1.6.0.4

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[U-Boot] Best way of making some drivers common across kirkwood and orion5x SoCs?
by Albert ARIBAUD 02 Nov '09

02 Nov '09

Hi, I am working on adding mainline support for Orion5x family of Marvell SoCs in U-boot, based on the Kirkwood support already present. I believe these are different enough families to justify adding an 'orion5x' SoC along the existing 'kirkwood' one. Several kirkwood drivers could actually be reused almost as-is and should thus be shared between both SoC families. For instance, kirkwood_egiga.c and ehci-kirkwood.c would only differ by the number of ports and kirkwood_i2c.c could be reused as-is. However, these drivers have hard-coded numbers of ports, and 'hard' references to 'kirkwood.h' for their register definitions. Making them cross-SoC would require moving the numbers of ports to some SoC-specific header file, and that this header file *not* be named after a specific SoC. I've searched for a layer between CPU and Core where cross-SoC code could fit, but I haven't seen one, and I don't think one would be needed. Instead, I have thought of replacing the #include "kirkwood.h" with a #include "soc.h", where soc.h would exist in both SoC's header files include/asm-arm/arch-kirkwood and include/asm-arm/arch-orion5x. This soc.h file would either include the specific soc header file (kirkwood.h or orion5x.h) or, better yet, be a symlink to it, or better again, replace it. This could be done in a two-step approach, each step being one commit. 1) introduce "soc.h" by: - 1a) renaming, symlinking or including kirkwood.h into soc.h and changing kirkwood drivers that #include "kirkwood.h" accordingly; - 1b) turning all kirkwood-specific namings in these kirkwood drivers into marvell-non-soc-specific ones (remove "KW_" prefixes and such). (steps 1a and 1b are independent) 2) add orion5x support with its own "soc.h" file. Would this approach be clean enough to be considered for inclusion in mainline? Amicalement, -- Albert.

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[U-Boot] [PATCH] Enable port-mapped access to 16550 UART
by Graeme Russ 02 Nov '09

02 Nov '09

This patch does two things: - Changes default behaviour to use proper memory accessors - Allows port-mapped access (using inb/outb) for the x86 architecture Signed-off-by: Graeme Russ <graeme.russ(a)gmail.com> --- drivers/serial/ns16550.c | 69 ++++++++++++++++++++++++++-------------------- 1 files changed, 39 insertions(+), 30 deletions(-) diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 2fcc8c3..c41ca0d 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -6,6 +6,8 @@ #include <config.h> #include <ns16550.h> +#include <linux/types.h> +#include <asm/io.h> #define UART_LCRVAL UART_LCR_8N1 /* 8 data, 1 stop, no parity */ #define UART_MCRVAL (UART_MCR_DTR | \ @@ -13,28 +15,35 @@ #define UART_FCRVAL (UART_FCR_FIFO_EN | \ UART_FCR_RXSR | \ UART_FCR_TXSR) /* Clear & enable FIFOs */ +#ifdef CONFIG_X86 +#define uart_writeb(x,y) outb(x,(ulong)y) +#define uart_readb(y) inb((ulong)y) +#else +#define uart_writeb(x,y) writeb(x,y) +#define uart_readb(y) readb(y) +#endif void NS16550_init (NS16550_t com_port, int baud_divisor) { - com_port->ier = 0x00; + uart_writeb(0x00, &com_port->ier); #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) - com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ + uart_writeb(0x7, &com_port->mdr1); /* mode select reset TL16C750*/ #endif - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCRVAL; - com_port->mcr = UART_MCRVAL; - com_port->fcr = UART_FCRVAL; - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCRVAL; + uart_writeb(UART_LCR_BKSE | UART_LCRVAL, (ulong)&com_port->lcr); + uart_writeb(0, &com_port->dll); + uart_writeb(0, &com_port->dlm); + uart_writeb(UART_LCRVAL, &com_port->lcr); + uart_writeb(UART_MCRVAL, &com_port->mcr); + uart_writeb(UART_FCRVAL, &com_port->fcr); + uart_writeb(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + uart_writeb(baud_divisor & 0xff, &com_port->dll); + uart_writeb((baud_divisor >> 8) & 0xff, &com_port->dlm); + uart_writeb(UART_LCRVAL, &com_port->lcr); #if defined(CONFIG_OMAP) && !defined(CONFIG_OMAP3_ZOOM2) #if defined(CONFIG_APTIX) - com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */ + uart_writeb(3, &com_port->mdr1); /* /13 mode so Aptix 6MHz can hit 115200 */ #else - com_port->mdr1 = 0; /* /16 is proper to hit 115200 with 48MHz */ + uart_writeb(0, &com_port->mdr1); /* /16 is proper to hit 115200 with 48MHz */ #endif #endif /* CONFIG_OMAP */ } @@ -42,41 +51,41 @@ void NS16550_init (NS16550_t com_port, int baud_divisor) #ifndef CONFIG_NS16550_MIN_FUNCTIONS void NS16550_reinit (NS16550_t com_port, int baud_divisor) { - com_port->ier = 0x00; - com_port->lcr = UART_LCR_BKSE | UART_LCRVAL; - com_port->dll = 0; - com_port->dlm = 0; - com_port->lcr = UART_LCRVAL; - com_port->mcr = UART_MCRVAL; - com_port->fcr = UART_FCRVAL; - com_port->lcr = UART_LCR_BKSE; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; - com_port->lcr = UART_LCRVAL; + uart_writeb(0x00, &com_port->ier); + uart_writeb(UART_LCR_BKSE | UART_LCRVAL, &com_port->lcr); + uart_writeb(0, &com_port->dll); + uart_writeb(0, &com_port->dlm); + uart_writeb(UART_LCRVAL, &com_port->lcr); + uart_writeb(UART_MCRVAL, &com_port->mcr); + uart_writeb(UART_FCRVAL, &com_port->fcr); + uart_writeb(UART_LCR_BKSE, &com_port->lcr); + uart_writeb(baud_divisor & 0xff, &com_port->dll); + uart_writeb((baud_divisor >> 8) & 0xff, &com_port->dlm); + uart_writeb(UART_LCRVAL, &com_port->lcr); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ void NS16550_putc (NS16550_t com_port, char c) { - while ((com_port->lsr & UART_LSR_THRE) == 0); - com_port->thr = c; + while ((uart_readb(&com_port->lsr) & UART_LSR_THRE) == 0); + uart_writeb(c, &com_port->thr); } #ifndef CONFIG_NS16550_MIN_FUNCTIONS char NS16550_getc (NS16550_t com_port) { - while ((com_port->lsr & UART_LSR_DR) == 0) { + while ((uart_readb(&com_port->lsr) & UART_LSR_DR) == 0) { #ifdef CONFIG_USB_TTY extern void usbtty_poll(void); usbtty_poll(); #endif } - return (com_port->rbr); + return uart_readb(&com_port->rbr); } int NS16550_tstc (NS16550_t com_port) { - return ((com_port->lsr & UART_LSR_DR) != 0); + return ((uart_readb(&com_port->lsr) & UART_LSR_DR) != 0); } #endif /* CONFIG_NS16550_MIN_FUNCTIONS */ -- 1.6.4.1.174.g32f4c

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[U-Boot] CPU Sleep in ARM Cortex A8
by akshay ts 02 Nov '09

02 Nov '09

Hi, I want to know what is the instruction for sleeping in ARM Cortex A8. I did execute a WFI instruction seems to be a NOP. void cpu_idle() { unsigned long tmp = 0; asm("b 1f\n\t" ".align 5\n\t" "1:\n\t" "mcr p15, 0, %0, c7, c10, 5\n\t" "mcr p15, 0, %0, c7, c10, 4\n\t" "mcr p15, 0, %0, c7, c0, 4" :: "r" (tmp)); return; } The above function doesnt seem to work. Please let me know exact instructions to follow. Warm Regards, Akshay Keep up with people you care about with Yahoo! India Mail. Learn how. http://in.overview.mail.yahoo.com/connectmore

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[U-Boot] [u-boot] [PATCH][1/2] mx27: Add necessary defines and helper functions to support I2C in i.MX27.
by Javier Martin 02 Nov '09

02 Nov '09

Add proper register definitions, macros and clock functions required for I2C driver to be developed. Signed-off-by: Javier Martin <javier.martin(a)vista-silicon.com> -- diff --git a/cpu/arm926ejs/mx27/generic.c b/cpu/arm926ejs/mx27/generic.c index 808371f..540ef0c 100644 --- a/cpu/arm926ejs/mx27/generic.c +++ b/cpu/arm926ejs/mx27/generic.c @@ -22,11 +22,21 @@ #include <div64.h> #include <netdev.h> #include <asm/io.h> +#include <asm/arch/asm-offsets.h> #include <asm/arch/imx-regs.h> #ifdef CONFIG_MXC_MMC #include <asm/arch/mxcmmc.h> #endif +int imx_get_revision(void) +{ + ulong val; + + val = readl(SYSCTRL_CID); + + return (int)(val >> 28); +} + /* * get the system pll clock in Hz * @@ -152,6 +162,19 @@ ulong imx_get_perclk4(void) return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1); } +ulong imx_get_ipgclk(void) +{ + ulong rate, ipg_pdf; + + if (imx_get_revision() >= CHIP_REV_2_0) + return imx_get_ahbclk(); + else + ipg_pdf = (readl(CSCR) >> 8) & 1; + + rate = imx_get_ahbclk(); + return rate / (ipg_pdf + 1); +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { diff --git a/include/asm-arm/arch-mx27/asm-offsets.h b/include/asm-arm/arch-mx27/asm-offsets.h index 497afe5..cdecef6 100644 --- a/include/asm-arm/arch-mx27/asm-offsets.h +++ b/include/asm-arm/arch-mx27/asm-offsets.h @@ -14,3 +14,5 @@ #define ESDCTL1_ROF 0x08 #define ESDCFG1_ROF 0x0C #define ESDMISC_ROF 0x10 +#define SYSCTRL_CID 0x10027800 +#define CHIP_REV_2_0 0x01 diff --git a/include/asm-arm/arch-mx27/imx-regs.h b/include/asm-arm/arch-mx27/imx-regs.h index d36a6da..2b89b4e 100644 --- a/include/asm-arm/arch-mx27/imx-regs.h +++ b/include/asm-arm/arch-mx27/imx-regs.h @@ -206,6 +206,10 @@ struct iim_regs { }; #endif +#define __REG(x) (*((volatile u32 *)(x))) +#define __REG16(x) (*((volatile u16 *)(x))) +#define __REG8(x) (*((volatile u8 *)(x))) + #define IMX_IO_BASE 0x10000000 #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com

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[U-Boot] Please pull u-boot-i2c.git next
by Heiko Schocher 02 Nov '09

02 Nov '09

Hello Wolfgang, The following changes since commit f2b4bc04d6aed6be712d236dab48ac4c4da22cbf: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash are available in the git repository at: git://git.denx.de/u-boot-i2c.git next Mike Frysinger (2): Blackfin: TWI/I2C: add timeout to transfer Blackfin: TWI/I2C: implement bus speed get/set functions Valentin Yakovenkov (1): new PCA9564 i2c bridge driver drivers/i2c/Makefile | 1 + drivers/i2c/bfin-twi_i2c.c | 74 ++++++++++++++--- drivers/i2c/pca9564_i2c.c | 189 ++++++++++++++++++++++++++++++++++++++++++++ include/pca9564.h | 50 ++++++++++++ 4 files changed, 300 insertions(+), 14 deletions(-) create mode 100644 drivers/i2c/pca9564_i2c.c create mode 100644 include/pca9564.h Thanks bye Heiko -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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[U-Boot] about nand_read_byte() interface
by HeLei 02 Nov '09

02 Nov '09

Hi, all I'm a little confused on NAND read operation. According to NAND character, NAND flash is read page by page, which mean's once you read, at least you should read data with page size (such as 512Bytes) But the nand_read_byte() is implemented as following: static u_char nand_read_byte(struct mtd_info *mtd) { struct nand_chip *this = mtd->priv; return readb(this->IO_ADDR_R); }it seems only one byte is read out. Anybody can tell what's wrong with my understanding? ThanksLeon _________________________________________________________________ 约会说不清地方？来试试微软地图最新msn互动功能！ http://ditu.live.com/?form=TL&swm=1

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[U-Boot] [PATCH] S3C6400/SMDK6400: fix stack_setup in start.S
by "Seunghyeon Rhee (이승현)" 02 Nov '09

02 Nov '09

stack_setup is modified to initialize the stack on the correct address in DRAM accroding to the typical memory configuration described in README and the related CONFIG_* macro definitions. This makes macro CONFIG_MEMORY_UPPER_CODE no longer necessry. This was introduced and used only by this board for some unclear reason. The definition of this macro is removed because it's not referenced elsewhere. Signed-off-by: Seunghyeon Rhee <seunghyeon(a)lpmtec.com> --- cpu/arm1176/start.S | 7 +------ include/configs/smdk6400.h | 2 -- 2 files changed, 1 insertions(+), 8 deletions(-) diff --git a/cpu/arm1176/start.S b/cpu/arm1176/start.S index cb891df..1ecb3b9 100644 --- a/cpu/arm1176/start.S +++ b/cpu/arm1176/start.S @@ -241,16 +241,11 @@ mmu_enable: skip_hw_init: /* Set up the stack */ stack_setup: -#ifdef CONFIG_MEMORY_UPPER_CODE - ldr sp, =(CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE - 0xc) -#else - ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ + ldr r0, =CONFIG_SYS_UBOOT_BASE /* base of copy in DRAM */ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */ sub sp, r0, #12 /* leave 3 words for abort-stack */ -#endif - clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h index f6e1221..f644cd2 100644 --- a/include/configs/smdk6400.h +++ b/include/configs/smdk6400.h @@ -49,8 +49,6 @@ #define CONFIG_ENABLE_MMU #endif -#define CONFIG_MEMORY_UPPER_CODE - #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG #define CONFIG_INITRD_TAG -- 1.6.2.5 -- Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657

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[U-Boot] Pull request: u-boot-sh
by Nobuhiro Iwamatsu 01 Nov '09

01 Nov '09

Dear Wolfgang, Could you pull from the master branch at git://git.denx.de/u-boot-sh.git ? Best regards, Nobuhiro The following changes since commit f2b4bc04d6aed6be712d236dab48ac4c4da22cbf: Wolfgang Denk (1): Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash are available in the git repository at: git://git.denx.de/u-boot-sh.git master Nobuhiro Iwamatsu (3): sh: Remove malloc_bin_reloc from lib_sh, lib_nios2 and lib_nios. sh: Move some defs to convince 'pcrel too far' sh: Update lowlevel_init.S of espt-giga board/espt/lowlevel_init.S | 10 +--- board/renesas/sh7785lcr/lowlevel_init.S | 107 +++++++++++++++---------------- lib_nios/board.c | 2 - lib_nios2/board.c | 2 - lib_sh/board.c | 2 - 5 files changed, 54 insertions(+), 69 deletions(-)

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[U-Boot] [PATCH/RFC] Better I2C support for OMAP3
by Hugo Vincent 31 Oct '09

31 Oct '09

Hi everyone, This patch improves I2C support on OMAP3 platforms, including supporting the second and third I2C controllers (mainline only supports the first controller), and supporting writes where alen=0 (i.e. no register address - this was needed for some I2C devices I needed to drive from u-boot). Tested on Gumstix Overo with several I2C devices, on I2C1 and 3. The multi-bus support is mostly from this patch: http://www.beagleboard.org/gitweb/?p=u-boot-arm.git;a=commit;h=52eddcd07c2e… Best regards, Hugo Vincent Signed-off-by: Hugo Vincent <hugo.vincent(a)gmail.com> diff --git a/board/omap3/common/power.c b/board/omap3/common/power.c index 4908e5b..efc5dd4 100644 --- a/board/omap3/common/power.c +++ b/board/omap3/common/power.c @@ -42,6 +42,7 @@ void power_init_r(void) unsigned char byte; #ifdef CONFIG_DRIVER_OMAP34XX_I2C + i2c_set_bus_num(0); i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); #endif diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 16439ac..6332965 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1324,6 +1324,7 @@ U_BOOT_CMD( #endif ); #endif /* CONFIG_I2C_CMD_TREE */ +#if !defined(CONFIG_I2C_CMD_TREE) U_BOOT_CMD( imd, 4, 1, do_i2c_md, \ "i2c memory display", \ @@ -1378,6 +1379,7 @@ U_BOOT_CMD( " (valid chip values 50..57)\n" ); #endif +#endif /* !defined(CONFIG_I2C_CMD_TREE) */ #if defined(CONFIG_I2C_MUX) diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 6784603..424f172 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -1,7 +1,7 @@ /* * Basic I2C functions * - * Copyright (c) 2004 Texas Instruments + * Copyright (c) 2004, 2009 Texas Instruments * * This package is free software; you can redistribute it and/or * modify it under the terms of the license found in the file @@ -18,6 +18,7 @@ * * Adapted for OMAP2420 I2C, r-woodruff2(a)ti.com * + * Some additions by Hugo Vincent <hugo.vincent(a)gmail.com> June 2009 */ #include <common.h> @@ -25,40 +24,44 @@ #include <asm/arch/i2c.h> #include <asm/io.h> +#ifdef CONFIG_OMAP34XX +#define I2C_NUM_IF 3 +#else +#define I2C_NUM_IF 2 +#endif + static void wait_for_bb (void); static u16 wait_for_pin (void); static void flush_fifo(void); +static i2c_t *i2c = (i2c_t *)I2C_DEFAULT_BASE; + void i2c_init (int speed, int slaveadd) { - u16 scl; - - writew(0x2, I2C_SYSC); /* for ES2 after soft reset */ + writew(0x2, &i2c->sysc); /* for ES2 after soft reset */ udelay(1000); - writew(0x0, I2C_SYSC); /* will probably self clear but */ + writew(0x0, &i2c->sysc); /* will probably self clear but */ - if (readw (I2C_CON) & I2C_CON_EN) { - writew (0, I2C_CON); - udelay (50000); + if (readw (&i2c->con) & I2C_CON_EN) { + writew (0, &i2c->con); + udelay (10000); } - /* 12MHz I2C module clock */ - writew (0, I2C_PSC); - speed = speed/1000; /* 100 or 400 */ - scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ - writew (scl, I2C_SCLL); - writew (scl, I2C_SCLH); + /* Timings from TRM, tested with scope - 100 kHz standard speed */ + writew (23, &i2c->psc); + writew (13, &i2c->scll); + writew (15, &i2c->sclh); /* own address */ - writew (slaveadd, I2C_OA); - writew (I2C_CON_EN, I2C_CON); + writew (slaveadd, &i2c->oa); + writew (I2C_CON_EN, &i2c->con); /* have to enable intrrupts or OMAP i2c module doesn't work */ writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c->ie); udelay (1000); flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -70,19 +77,19 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) wait_for_bb (); /* one byte only */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* no stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c- >con); status = wait_for_pin (); if (status & I2C_STAT_XRDY) { /* Important: have to use byte access */ - writeb (regoffset, I2C_DATA); + writeb (regoffset, &i2c->data); udelay (20000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + if (readw (&i2c->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -91,28 +98,28 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - writew (0, I2C_CON); - while (readw (I2C_STAT) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (0, &i2c->con); + while (readw (&i2c->stat) || (readw (&i2c->con) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); } wait_for_bb (); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* read one byte from slave */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* need stop bit here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + &i2c->con); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - *value = readb (I2C_DATA); + *value = readb (&i2c->data); #else - *value = readw (I2C_DATA); + *value = readw (&i2c->data); #endif udelay (20000); } else { @@ -120,17 +127,17 @@ static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) } if (!i2c_error) { - writew (I2C_CON_EN, I2C_CON); - while (readw (I2C_STAT) - || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c->con); + while (readw (&i2c->stat) + || (readw (&i2c->con) & I2C_CON_MST)) { udelay (10000); - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); } } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); return i2c_error; } @@ -143,12 +150,12 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) wait_for_bb (); /* two bytes */ - writew (2, I2C_CNT); + writew (2, &i2c->cnt); /* set slave address */ - writew (devaddr, I2C_SA); + writew (devaddr, &i2c->sa); /* stop bit needed here */ writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + I2C_CON_STP, &i2c->con); /* wait until state change */ status = wait_for_pin (); @@ -156,24 +163,78 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (status & I2C_STAT_XRDY) { #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) /* send out 1 byte */ - writeb (regoffset, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (regoffset, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); status = wait_for_pin (); if ((status & I2C_STAT_XRDY)) { /* send out next 1 byte */ - writeb (value, I2C_DATA); - writew (I2C_STAT_XRDY, I2C_STAT); + writeb (value, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); } else { i2c_error = 1; } #else /* send out two bytes */ - writew ((value << 8) + regoffset, I2C_DATA); + writew ((value << 8) + regoffset, &i2c->data); #endif /* must have enough delay to allow BB bit to go low */ - udelay (50000); - if (readw (I2C_STAT) & I2C_STAT_NACK) { + udelay (1000); + if (readw (&i2c->stat) & I2C_STAT_NACK) { + i2c_error = 1; + } + } else { + i2c_error = 1; + } + + if (!i2c_error) { + int eout = 200; + + writew (I2C_CON_EN, &i2c->con); + while ((stat = readw (&i2c->stat)) || (readw (&i2c->con) & I2C_CON_MST)) { + udelay (1000); + /* have to read to clear intrrupt */ + writew (0xFFFF, &i2c->stat); + if(--eout == 0) /* better leave with error than hang */ + break; + } + } + flush_fifo(); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); + return i2c_error; +} + +/* Write just one byte (no reg offset) */ +static int i2c_write_byte_raw (u8 devaddr, u8 value) +{ + int i2c_error = 0; + u16 status, stat; + + /* wait until bus not busy */ + wait_for_bb (); + + /* one bytes */ + writew (1, &i2c->cnt); + /* set slave address */ + writew (devaddr, &i2c->sa); + /* stop bit needed here */ + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, &i2c->con); + + /* wait until state change */ + status = wait_for_pin (); + + if (status & I2C_STAT_XRDY) { + /* send out 1 byte */ + writeb (value, &i2c->data); + writew (I2C_STAT_XRDY, &i2c->stat); + + status = wait_for_pin (); + + /* must have enough delay to allow BB bit to go low */ + udelay (1000); + if (readw (&i2c->stat) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -183,18 +244,18 @@ static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) if (!i2c_error) { int eout = 200; - writew (I2C_CON_EN, I2C_CON); - while ((stat = readw (I2C_STAT)) || (readw (I2C_CON) & I2C_CON_MST)) { + writew (I2C_CON_EN, &i2c->con); + while ((stat = readw (&i2c->stat)) || (readw (&i2c->con) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - writew (0xFFFF, I2C_STAT); + writew (0xFFFF, &i2c->stat); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - writew (0xFFFF, I2C_STAT); - writew (0, I2C_CNT); + writew (0xFFFF, &i2c->stat); + writew (0, &i2c->cnt); return i2c_error; } @@ -205,14 +266,14 @@ static void flush_fifo(void) * you get a bus error */ while(1){ - stat = readw(I2C_STAT); + stat = readw(&i2c->stat); if(stat == I2C_STAT_RRDY){ #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) - readb(I2C_DATA); + readb(&i2c->data); #else - readw(I2C_DATA); + readw(&i2c->data); #endif - writew(I2C_STAT_RRDY,I2C_STAT); + writew(I2C_STAT_RRDY,&i2c->stat); udelay(1000); }else break; @@ -223,7 +284,7 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == readw (I2C_OA)) { + if (chip == readw (&i2c->oa)) { return res; } @@ -231,27 +292,27 @@ int i2c_probe (uchar chip) wait_for_bb (); /* try to read one byte */ - writew (1, I2C_CNT); + writew (1, &i2c->cnt); /* set slave address */ - writew (chip, I2C_SA); + writew (chip, &i2c->sa); /* stop bit needed here */ - writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c- >con); /* enough delay for the NACK bit set */ - udelay (50000); + udelay (1000); - if (!(readw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(readw (&i2c->stat) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); - writew(0xFFFF, I2C_STAT); + writew(0xFFFF, &i2c->stat); } else { - writew(0xFFFF, I2C_STAT); /* failue, clear sources*/ - writew (readw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + writew(0xFFFF, &i2c->stat); /* failue, clear sources*/ + writew (readw (&i2c->con) | I2C_CON_STP, &i2c->con); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - writew (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ - writew(0xFFFF, I2C_STAT); + writew (0, &i2c->cnt); /* don't allow any more data in...we don't want it.*/ + writew(0xFFFF, &i2c->stat); return res; } @@ -284,23 +345,34 @@ int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) { int i; - if (alen > 1) { - printf ("I2C read: addr len %d not supported\n", alen); + if (alen > 1 || alen < 0) { + printf ("I2C write: addr len %d not supported\n", alen); return 1; } if (addr + len > 256) { - printf ("I2C read: address out of range\n"); + printf ("I2C write: address out of range\n"); return 1; } - for (i = 0; i < len; i++) { - if (i2c_write_byte (chip, addr + i, buffer[i])) { - printf ("I2C read: I/O error\n"); - i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); - return 1; + if (alen == 1) + for (i = 0; i < len; i++) + { + if (i2c_write_byte (chip, addr + i, buffer[i])) { + printf ("I2C write: I/O error\n"); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + return 1; + } + } + else if (alen == 0) + for (i = 0; i < len; i++) + { + if (i2c_write_byte_raw (chip, buffer[i])) { + printf ("I2C write: I/O error\n"); + i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + return 1; + } } - } return 0; } @@ -310,17 +382,17 @@ static void wait_for_bb (void) int timeout = 10; u16 stat; - writew(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = readw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - writew (stat, I2C_STAT); - udelay (50000); + writew(0xFFFF, &i2c->stat); /* clear current interruts...*/ + while ((stat = readw (&i2c->stat) & I2C_STAT_BB) && timeout--) { + writew (stat, &i2c->stat); + udelay (1000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - readw (I2C_STAT)); + readw (&i2c->stat)); } - writew(0xFFFF, I2C_STAT); /* clear delayed stuff*/ + writew(0xFFFF, &i2c->stat); /* clear delayed stuff*/ } static u16 wait_for_pin (void) @@ -330,7 +402,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = readw (I2C_STAT); + status = readw (&i2c->stat); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -338,8 +410,55 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - readw (I2C_STAT)); - writew(0xFFFF, I2C_STAT); + readw (&i2c->stat)); + writew(0xFFFF, &i2c->stat); } return status; } + +int i2c_set_bus_num(unsigned int bus) +{ + if ((bus < 0) || (bus >= I2C_NUM_IF)) { + printf("Bad bus: %d\n", bus); + return -1; + } + +#ifdef CONFIG_OMAP34XX + if (bus == 2) + i2c = (i2c_t *)I2C_BASE3; + else +#endif + if (bus == 1) + i2c = (i2c_t *)I2C_BASE2; + else + i2c = (i2c_t *)I2C_BASE1; + + return 0; +} + +int i2c_get_bus_num(void) +{ +#ifdef CONFIG_OMAP34XX + if (i2c == (i2c_t *)I2C_BASE3) + return 2; + else +#endif + if (i2c == (i2c_t *)I2C_BASE2) + return 1; + else if (i2c == (i2c_t *)I2C_BASE1) + return 0; + else + return -1; +} + +int i2c_get_bus_speed() +{ + return 100000; +} + +int i2c_set_bus_speed(int speed) +{ + printf("Not yet implemented\n"); + return -1; +} + diff --git a/drivers/mmc/omap3_mmc.c b/drivers/mmc/omap3_mmc.c index e90db7e..234fddf 100644 --- a/drivers/mmc/omap3_mmc.c +++ b/drivers/mmc/omap3_mmc.c @@ -62,6 +62,9 @@ void twl4030_mmc_config(void) { unsigned char data; + i2c_set_bus_num(0); + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + data = DEV_GRP_P1; i2c_write(PWRMGT_ADDR_ID4, VMMC1_DEV_GRP, 1, &data, 1); data = VMMC1_VSEL_30; diff --git a/include/asm-arm/arch-omap3/i2c.h b/include/asm-arm/arch- omap3/i2c.h index 3937f35..9638abc 100644 --- a/include/asm-arm/arch-omap3/i2c.h +++ b/include/asm-arm/arch-omap3/i2c.h @@ -25,21 +25,24 @@ #define I2C_DEFAULT_BASE I2C_BASE1 -#define I2C_REV (I2C_DEFAULT_BASE + 0x00) -#define I2C_IE (I2C_DEFAULT_BASE + 0x04) -#define I2C_STAT (I2C_DEFAULT_BASE + 0x08) -#define I2C_IV (I2C_DEFAULT_BASE + 0x0c) -#define I2C_BUF (I2C_DEFAULT_BASE + 0x14) -#define I2C_CNT (I2C_DEFAULT_BASE + 0x18) -#define I2C_DATA (I2C_DEFAULT_BASE + 0x1c) -#define I2C_SYSC (I2C_DEFAULT_BASE + 0x20) -#define I2C_CON (I2C_DEFAULT_BASE + 0x24) -#define I2C_OA (I2C_DEFAULT_BASE + 0x28) -#define I2C_SA (I2C_DEFAULT_BASE + 0x2c) -#define I2C_PSC (I2C_DEFAULT_BASE + 0x30) -#define I2C_SCLL (I2C_DEFAULT_BASE + 0x34) -#define I2C_SCLH (I2C_DEFAULT_BASE + 0x38) -#define I2C_SYSTEST (I2C_DEFAULT_BASE + 0x3c) +typedef struct i2c { + unsigned int rev; /* 0x00 */ + unsigned int ie; /* 0x04 */ + unsigned int stat; /* 0x08 */ + unsigned int iv; /* 0x0c */ + unsigned int res1; /* 0x10 */ + unsigned int buf; /* 0x14 */ + unsigned int cnt; /* 0x18 */ + unsigned int data; /* 0x1c */ + unsigned int sysc; /* 0x20 */ + unsigned int con; /* 0x24 */ + unsigned int oa; /* 0x28 */ + unsigned int sa; /* 0x2c */ + unsigned int psc; /* 0x30 */ + unsigned int scll; /* 0x34 */ + unsigned int sclh; /* 0x38 */ + unsigned int systest; /* 0x3c */ +} i2c_t; /* I2C masks */ diff --git a/include/configs/omap3_overo.h b/include/configs/ omap3_overo.h index b2c42fa..d8f7a9e 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -103,6 +103,7 @@ "4m(kernel),-(fs)" #define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_I2C_CMD_TREE /* New-style command interface */ #define CONFIG_CMD_MMC /* MMC support */ #define CONFIG_CMD_NAND /* NAND support */ @@ -113,6 +114,7 @@ #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_NO_FLASH #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1

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